diff --git a/xilinx/TODO.txt b/xilinx/TODO.txt new file mode 100644 index 0000000..70a3b65 --- /dev/null +++ b/xilinx/TODO.txt @@ -0,0 +1,10 @@ + +pdp-8 + register file + +caddr + ddr controller + video bitmap + disk interface + +xc2s200-5fg256 diff --git a/xilinx/ps2/_ngo/netlist.lst b/xilinx/ps2/_ngo/netlist.lst new file mode 100644 index 0000000..3bb07d8 --- /dev/null +++ b/xilinx/ps2/_ngo/netlist.lst @@ -0,0 +1,2 @@ +/mwave/work/nt/xess/xilinx/ps2/fpga.ngc 1166710707 +OK diff --git a/xilinx/ps2/_xmsgs/bitgen.xmsgs b/xilinx/ps2/_xmsgs/bitgen.xmsgs new file mode 100644 index 0000000..0d35cb9 --- /dev/null +++ b/xilinx/ps2/_xmsgs/bitgen.xmsgs @@ -0,0 +1,8 @@ + + + + diff --git a/xilinx/ps2/_xmsgs/map.xmsgs b/xilinx/ps2/_xmsgs/map.xmsgs new file mode 100644 index 0000000..900be21 --- /dev/null +++ b/xilinx/ps2/_xmsgs/map.xmsgs @@ -0,0 +1,30 @@ + + + +Logical network clkb has no load. + + +The above warning message base_net_load_rule is repeated 11 more times for the following (max. 5 shown): +vga_hsync_n, +vga_red0, +vga_red1, +vga_red2, +vga_green0 +To see the details of these warning messages, please use the -detail switch. + + +No environment variables are currently set. + + +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. + + +Clock buffer is designated to drive clock loads. BUFG symbol "gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1) has a mix of clock and non-clock loads. The non-clock loads are: +Pin D of gray_cnt_FFd2 + + + diff --git a/xilinx/ps2/_xmsgs/ngdbuild.xmsgs b/xilinx/ps2/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..0d35cb9 --- /dev/null +++ b/xilinx/ps2/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,8 @@ + + + + diff --git a/xilinx/ps2/_xmsgs/par.xmsgs b/xilinx/ps2/_xmsgs/par.xmsgs new file mode 100644 index 0000000..ef7b527 --- /dev/null +++ b/xilinx/ps2/_xmsgs/par.xmsgs @@ -0,0 +1,13 @@ + + + +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". + + +N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. + + diff --git a/xilinx/ps2/_xmsgs/trce.xmsgs b/xilinx/ps2/_xmsgs/trce.xmsgs new file mode 100644 index 0000000..b1a4b30 --- /dev/null +++ b/xilinx/ps2/_xmsgs/trce.xmsgs @@ -0,0 +1,12 @@ + + + +No timing constraints found, doing default enumeration. + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + + diff --git a/xilinx/ps2/_xmsgs/xst.xmsgs b/xilinx/ps2/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..81a512f --- /dev/null +++ b/xilinx/ps2/_xmsgs/xst.xmsgs @@ -0,0 +1,71 @@ + + + +Output <vga_hsync_n> is never assigned. + + +Output <vga_red0> is never assigned. + + +Output <vga_red1> is never assigned. + + +Output <vga_red2> is never assigned. + + +Output <vga_green0> is never assigned. + + +Output <vga_green1> is never assigned. + + +Output <vga_green2> is never assigned. + + +Input <clkb> is never used. + + +Output <vga_blue0> is never assigned. + + +Output <vga_blue1> is never assigned. + + +Output <vga_blue2> is never assigned. + + +Output <vga_vsync_n> is never assigned. + + +Signal <vsync> is never used or assigned. + + +Signal <kb_scancode<7>> is assigned but never used. + + +Signal <kb_bsy> is assigned but never used. + + +Signal <hsync> is never used or assigned. + + +Signal <pixel> is never used or assigned. + + +Signal <data> is never used or assigned. + + +HDL ADVISOR - A 2-bit shift register was found for signal <ps2/ps2_clk_r_1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. + + +HDL ADVISOR - A 3-bit shift register was found for signal <ps2/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + + diff --git a/xilinx/ps2/fpga.bgn b/xilinx/ps2/fpga.bgn new file mode 100644 index 0000000..9a12b3b --- /dev/null +++ b/xilinx/ps2/fpga.bgn @@ -0,0 +1,101 @@ +Release 8.2i - Bitgen I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +Loading device for application Rf_Device from file 'v200.nph' in environment +/opt/Xilinx. + "fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5 +Opened constraints file fpga.pcf. + +Thu Dec 21 09:19:03 2006 + +bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No fpga.ncd + +Summary of Bitgen Options: ++----------------------+----------------------+ +| Option Name | Current Setting | ++----------------------+----------------------+ +| Compress | (Not Specified)* | ++----------------------+----------------------+ +| Readback | (Not Specified)* | ++----------------------+----------------------+ +| DebugBitstream | No** | ++----------------------+----------------------+ +| ConfigRate | 4** | ++----------------------+----------------------+ +| StartupClk | Cclk** | ++----------------------+----------------------+ +| CclkPin | Pullup** | ++----------------------+----------------------+ +| DonePin | Pullup** | ++----------------------+----------------------+ +| M0Pin | Pullup** | ++----------------------+----------------------+ +| M1Pin | Pullup** | ++----------------------+----------------------+ +| M2Pin | Pullup** | ++----------------------+----------------------+ +| ProgPin | Pullup** | ++----------------------+----------------------+ +| TckPin | Pullup** | ++----------------------+----------------------+ +| TdiPin | Pullup** | ++----------------------+----------------------+ +| TdoPin | Pullup | ++----------------------+----------------------+ +| TmsPin | Pullup** | ++----------------------+----------------------+ +| UnusedPin | Pulldown** | ++----------------------+----------------------+ +| GSR_cycle | 6** | ++----------------------+----------------------+ +| GWE_cycle | 6** | ++----------------------+----------------------+ +| GTS_cycle | 5** | ++----------------------+----------------------+ +| LCK_cycle | NoWait** | ++----------------------+----------------------+ +| DONE_cycle | 4** | ++----------------------+----------------------+ +| Persist | No* | ++----------------------+----------------------+ +| DriveDone | No** | ++----------------------+----------------------+ +| DonePipe | No** | ++----------------------+----------------------+ +| Security | None** | ++----------------------+----------------------+ +| UserID | 0xFFFFFFFF** | ++----------------------+----------------------+ +| Gclkdel0 | 11111** | ++----------------------+----------------------+ +| Gclkdel1 | 11111** | ++----------------------+----------------------+ +| Gclkdel2 | 11111** | ++----------------------+----------------------+ +| Gclkdel3 | 11111** | ++----------------------+----------------------+ +| ActiveReconfig | No* | ++----------------------+----------------------+ +| ActivateGclk | No* | ++----------------------+----------------------+ +| PartialMask0 | (Not Specified)* | ++----------------------+----------------------+ +| PartialMask1 | (Not Specified)* | ++----------------------+----------------------+ +| PartialGclk | (Not Specified)* | ++----------------------+----------------------+ +| PartialLeft | (Not Specified)* | ++----------------------+----------------------+ +| PartialRight | (Not Specified)* | ++----------------------+----------------------+ +| IEEE1532 | No* | ++----------------------+----------------------+ +| Binary | No** | ++----------------------+----------------------+ + * Default setting. + ** The specified setting matches the default setting. + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "fpga.bit". +Bitstream generation is complete. diff --git a/xilinx/ps2/fpga.bit b/xilinx/ps2/fpga.bit new file mode 100644 index 0000000..0a3bfb0 Binary files /dev/null and b/xilinx/ps2/fpga.bit differ diff --git a/xilinx/ps2/fpga.bld b/xilinx/ps2/fpga.bld new file mode 100644 index 0000000..3ce5674 --- /dev/null +++ b/xilinx/ps2/fpga.bld @@ -0,0 +1,31 @@ +Release 8.2i ngdbuild I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Command Line: ngdbuild -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise +-dd _ngo -nt timestamp -uc /mwave/work/nt/xess/v/fpga2.ucf -p xc2s200-fg256-5 +fpga.ngc fpga.ngd + +Reading NGO file '/mwave/work/nt/xess/xilinx/ps2/fpga.ngc' ... + +Applying constraints in "/mwave/work/nt/xess/v/fpga2.ucf" to the design... + +Checking timing specifications ... +Checking Partitions ... +Checking expanded design ... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 239836 kilobytes + +Writing NGD file "fpga.ngd" ... + +Writing NGDBUILD log file "fpga.bld"... diff --git a/xilinx/ps2/fpga.cmd_log b/xilinx/ps2/fpga.cmd_log new file mode 100644 index 0000000..af12ce4 --- /dev/null +++ b/xilinx/ps2/fpga.cmd_log @@ -0,0 +1,114 @@ +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -i -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga2.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/ps2/ps2.ise" -intstyle ise -f fpga.ut fpga.ncd diff --git a/xilinx/ps2/fpga.drc b/xilinx/ps2/fpga.drc new file mode 100644 index 0000000..ec074a2 --- /dev/null +++ b/xilinx/ps2/fpga.drc @@ -0,0 +1 @@ +DRC detected 0 errors and 0 warnings. diff --git a/xilinx/ps2/fpga.lso b/xilinx/ps2/fpga.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/xilinx/ps2/fpga.lso @@ -0,0 +1 @@ +work diff --git a/xilinx/ps2/fpga.ncd b/xilinx/ps2/fpga.ncd new file mode 100644 index 0000000..55b220c --- /dev/null +++ b/xilinx/ps2/fpga.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4 +###5592:XlxV32DM 3fff 15c0eNrFWVtz2ziy/ivz4IeZca1DAARvOEmNrFtUkS2PJCf2eQiLFMmsdxLbK2emkrKS334aNxIAIcVTx1s7NRK7v240Gh/QTcg5whg9IsSOlvVfNw83d7fZT+gExT8dYfYPWrMXw/lpvkTBENGTVWDqUV9HrY4cf6lb9sixu+Njxx7bdhzadq5bdmd+bM2PhwibdtCJo4eOP3XsbrzIsUeOPXbssWNPTDtx5iNOfOLEJ0584sQPnXihM546durMR3v+Np+gO/7Y8o/s+DgZYs7/RunpEIF3yl5Mh/M3p5eToBM1ejEYoZi94I8g0kKsBJQogVAlhNon1D6REkiQKgEpZ4KjSAhJhFiAGCKMnCDMBvyD4UPgE6KAnV7O5qN8PVhOx/A1fI3Z6RV8rhN2Wn98+Ck4gZBCzHjGs8Vpzp85X0Vg4zwh3EH5cJxfLN6Nl+b4dvBkvKwlzIeOxvPB9abTZ5OJYZ2dw4Cm0xeXawAMd5hZua/mM5h2eB1A9VvA2eXVxINNNybULkmpFDyswJOJq19bAaaNpZ2PJi5ge1wtlhMXmEISw8Eofzsbv8vfjper2eIcs+GYsOGMC29AmL9J2XBxdjZbr8ejEMTLdcyGy/EAVLDcfboXO1dIUTBfGTJwprw4faUSRQaIwRlio2x2Plvv+Nd1Nl+8y+aD9fB1vljCijP4f3V9PswH6/UyG3Bxt8NsNENsgtkEjsAEztcEztckhA8N4TM7R2yK2RSMUzBOwTgNK8ZzedEek0DqxglREOTYomWLwKbHQoHFQ6j54nQwz+eL6WwY2Cps+yxkMzjIhMEKMZudgwpLI5F47CYTvpTTxZVcTQanj+Nifa9n09fO6nc7Qn88sM8ajAtYy+uVL7SH2MYc8pStMCe5/vuTPG2/U8a3QJRtLERYusREsRZClHUq7bBbQPzvEZsvBqPxqGBng4v8bDG6nI8rIa9nZ+PVenB2UQpVHXzCzor7kJ1DyxPfifhO+TcNYnY+Xr9bLN8gtiBswUsEpozYxWD4ZjwiTDRPdjFa5afzxfBNfjEfDMdn4/N1Y4CXq8F0XAsAouVng9V6vGxafQkRZ+fQJjSwvr4YF1KbjvLZSLpejM50ynDGBTI7zwer1Wx6DjEvoAdqcHy1Hp8DBSISCgUuah26Q346Ox/BdHBkW5hPw0k3Xd8Oh60rNWCZQc77uFq5hS8nPMgbaLcir/PpWb5aXC6H44ajoBqbAADncf16eQlleLG9+3zH2wQKTnhb44t0oJOAT6lBemK0fw96Au/RFk5OeMcOHOAkaDokldMiFzkJPBjyYNiDEQ8WupNOe05Tz6RTz6RTz6RTz6TTkxCx3wlbjt9itoJ7gujEL4CCTSvy95elTWOlTRItoFbCrURaKSy1xF9rehJ4o3XitY451aOmbcxpG3PaxpyGhZaAOkOeapm/4AxZ4/nkxQAZMjZkYsg6fj41/KeG/9TwBxleOKslYmvC1kMo6nVb5bzWGqGrs6+Kz0GgG8CBxQp+y6PyIoAO0djYEl45JnAGp9fQVxfj8UhBvOZnZxeQ4mwto6ytZrHWVSoSmM9OV5D9cobZuxVicBW7OkUVu5rNZ+dX/7gancJ7Hf20Wl9KYbAazsD1ChrrVVXms6qE56f89Oa2urn9ABlw7az41932bb3lv4Q0dHPbQewas+tT+Pwess3HP4pCfPO37fSiMeQX/BsCGMiMP8SokrLmA6ZRyJr7D0UsvvMKbbSQL8S7QGpYw9iCiYaJBYcaDi2YaphacKThyIJjDccCLpV2c5tXvPUYmrAr70/F/cnth08V+7Atvuab28/wQqygdVkqgl20AEGOPQbDYbP0/L7Y/JFDy7wvtnC07x/wi7OiqvIcvh7+LAP4L998/Z/gFSr3GtFhKzpoxa8OTIsOGQ+OJIeM4SEjPWSMDhnjQ8bkkDF9hZHf+PHPz0A+/PZ4mwdwir0+X+62Yg8OmdFhMz5sJnu3UJgPWvFB6+HI4UErPWiNDlrjg9bkoDXds5VIHdnNISOKhPWcVOqpKlDBIS9FEIw5xd56UORFsRcFmnEf9YHYB3qHhz6Q+sDIB8Y+MPGB6atGYptP93n9b45Bq3QRxaABKWbdwfyG5CK4j5Ggj4VYk2tiLxbqPDiomr8fhka9/FECF1QH4m2f4D049eOhWm5585m3+C3v3JGL6MT2GLATAvVCoFcWty2Oe554jyfpeZJ9aWkDri08DxwdObrrT6wUvnBmgh6ijp8J5RMfOHWioV401I/GIeQMxL2BgDg+wBZykXziwaaybdXb7d0236rplaboNT2+VKaCFEOtCgc7chEVxRqIQ9ny/qi/buuP+dbSvtSWhrCtY+LoVNHRAZBG3INUHvZg6gSnoaJAA7xEUOQBceADdZ3CJ4fLZV5XH2rlZ0G6xk0Qq6RNTJ9walma4uNHGWfjx/UwO5ltd4I7CE5Y3IP2jcf98aQ/nuwdH6rG3CJ54ALIBbALEBcIUwFsq6/5thO/FJ2ozvDDRnBgKO0bTWnWkRcYNt2J5U487qHpTi136nGPTPfYco897onpnr4qWiUPDBkZMjZkYsihIVNDjgw5NuTEkFNZM59vPtVbeaioA1gtXMP8VoJdJN9+drxQzwt5vHDPC3u8SM+LcC87f6R7ZQf0fLDrg/s+xPXxzBW6PmHfh7o+tO8TuT5R3yd2feK+T+L6JH2f1PVJuU9lQnlgq6i21cDRXTt2dGKHw7bqWENbpbYa2Wpsq4mtWiebv7YbR0c2gNqGaiKOD+r5oJ4P7vngng/p+QBiJ4ychJHrgB0H7DoQx6E3Reg4hK4DdRyo6xA5DpHrEDsOseuQOA6J65A6Dql6SfEXRqWFE/Wvd/pFwv8mlAitKj4XdStJv6rVhSNh8GIp+JfqdTHb1g/15/x2owUV8OG+2H4ubnHK/vpQ5OXHP+ugE1EnQqfm4odtXd8GhowMGZdC/ufD19tNfpsIZVtXQSuhVlKuf0nXmH3Z4AfMf6Ww3Wi2GpzOx7n+957dDm8AXc7ejvW/CyGczRZamb9dr+fZaj5+B1/cHZrqzjHvdgRizC/X/B9fzsZnGYi70cuff/4+QL/+PMDwIb8Owl9++eX4Z458H+Bj+CLH3wX4y46Uh4bDIHLsG65H0wOj5cRyoBr3qx53IOnv/aw5wke3SeO9wwe4S9UehDdPGwRjhHvoc3dZ3WH6Azc5/Q66yn4/PuMOR/s8vtuhcHzQ8fvf8TzW6RV7PIGavVQcP42KY71/x8qv8vmJvZcHTGwCuMqt2OFkr39vweigqwiHyn0+fK1os8/6XZh9axygPTjeId+mQqQd9IPd7ttvv90XdMN+++1Ls8kmWZShxxWts6TJ4jJDBKMNphnGBUKPtw3KELttcBayo7rJ6op9W9GNx5ewVQIIIllg4RHj/n282IOXe/ANqyBbwPZnCxkGWQ0PUmeoSdltUmUhTYo03gTsKNkI8CipYSA7KpIMwUXmr3WaZJhHzdLyQOA4IzC2CMSjDmWommQ4oPDEWQMhawpcHVHhelukem7EvhaA1Qk8I/F8XYTsf2uY95E2WYiyb6VcWpIRmtHy8QY1Meiv64j9WWCYg7EbBOy7EGyLAzVRDykAYXfwNhBPFJSOB5iQcsHqSaRrU6lnrZ6NehbqWarnRo0LxVMMs2Zo3NQhDdSHSB+ifSjuQ6kDlZK/AjYWPx5VTRZhdpQWwC67qcSiblIqH5F4xGIFN5VY6A0tpSaXFcvVJuJxnPK5+AQJPDlfwSOPnMTsNm0yCvPAdGECISV5KU+EfVMZoW5AKgbEUFZpCUkncmChZ/j2IEeQx5d8LrjJvuRAmrL38OFWkYC0pjF7D7/fvsE5ikRa7bqRWDdcD+7i2My/Sa30YyrTD2QWuJe+iNtlH0cye2JnT7rs5QSPL+Epsos5FskFAcbXA6peDkxQ+TYM3p7PtGHiDJOO/kQuOJILwGrhqbPwmzpV66+8u5eo9cee3aOKgJov9n1KOQGVIqDmpLwEtSNAFmb/yEbPdmSDjZcC+kQKZIJ9DuL9HKSFOqMwdUuCjEMkymnggHEQGu9BqJ6PhsBLQ/zUk9B4WUgPsKArFWbujkKjSQjkWWiss4C8JNTPRwL2kpA8+SwgLwvFARZizQI2zwLSNGB1FpDFA/Hy0DwfD6GXh/TJPBAvD+UBHqjmITR5IJqHUPFALB6otzcEz8dD5OWheDIP1MvD5gAPoeYhMnmgmodI8UAtHvyvdfR8PCReHson8+B/y1cHeMCah8TkQb/7g0TxEFs8pF4e8PPxUHh52DyZh9TLQ32AB6R5KEweUs1DoXhITR7EBbjIoJIsHsLnu+YR+5on70lRJPOP+te8gh8g2g2I2gGw8ETxFsPkhcwhEY9I3pxLmXRc6ztj6L1khvsvmdhLe7T/kpkEinZIHNr/eyhZTnttoAV7DwVgXjkBha18Xwnf1PAtYeOSQvjq8gYG5eVVNDZuwfpaGyoLNq+1pBsnNhyiRqHY7LpRmx1Zm02eb7MD32aHe/c6SX17LW/0cfM3txp5t5rs3erafw+h+7e63VTI27OpgHab2uhqbAK1SUhtX60vLoAIS90Y25fgLppxGIIumthUsKpNRfI2hiGk2NRAvuF7nUWyVxb2PTxW/ITsjiSKGGTf7+AXliAGKWJU6VL/BJymRiWL5HUNPt8eCsUdzE8SJmxQLSapSCztPScJLomJd1XFvlXVP1pVk/gWRZ+6qPbXWOJZUi2W1CRyRU3cunbrQVT8/ouh+Bq5IiJWhEo40HyOowJlm4iBlmot5FqhNcq1RmsNaHGgtZprSGsV/KSv5V8WavmHh0b+PaJRf16QVR7Kv2dQWUc0NWuMyD9U1LIDRLL0Y6xn2DC3H0TKs5KNQCwpbtneEHmEAsV2KtmG2zjR66v42kmpNb52stEaXzuRedayF0SRnDZUZ1boYTehfN1Gtf26hWtvJPc1qs1dLhsVhvIpoy6M7AlI3j4S+bcJ+I3/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a/xilinx/ps2/fpga.pad b/xilinx/ps2/fpga.pad new file mode 100644 index 0000000..9760792 --- /dev/null +++ b/xilinx/ps2/fpga.pad @@ -0,0 +1,286 @@ +Release 8.2i - par I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Thu Dec 21 09:18:51 2006 + + +# NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +INPUT FILE: fpga_map.ncd +OUTPUT FILE: fpga.pad +PART TYPE: xc2s200 +SPEED GRADE: -5 +PACKAGE: fg256 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|DCI Value|IO Register|Signal Integrity| +A1|||GND||||||||||||| +A2||IOB|IO|UNUSED||7|||||||||| +A3||IOB|IO_VREF_0|UNUSED||0|||||||||| +A4||IOB|IO|UNUSED||0|||||||||| +A5||IOB|IO|UNUSED||0|||||||||| +A6||IOB|IO|UNUSED||0|||||||||| +A7||IOB|IO|UNUSED||0|||||||||| +A8||IOB|IO|UNUSED||1|||||||||| +A9||IOB|IO|UNUSED||1|||||||||| +A10||IOB|IO|UNUSED||1|||||||||| +A11||IOB|IO|UNUSED||1|||||||||| +A12||IOB|IO|UNUSED||1|||||||||| +A13||IOB|IO|UNUSED||1|||||||||| +A14||IOB|IO_VREF_1|UNUSED||1|||||||||| +A15|||TDI||||||||||||| +A16|||GND||||||||||||| +B1||IOB|IO_VREF_7|UNUSED||7|||||||||| +B2|||GND||||||||||||| +B3||IOB|IO|UNUSED||0|||||||||| +B4||IOB|IO_VREF_0|UNUSED||0|||||||||| +B5||IOB|IO|UNUSED||0|||||||||| +B6||IOB|IO|UNUSED||0|||||||||| +B7||IOB|IO_VREF_0|UNUSED||0|||||||||| +B8||GCLKIOB|GCK3|UNUSED||0|||||||||| +B9||IOB|IO_VREF_1|UNUSED||1|||||||||| +B10||IOB|IO|UNUSED||1|||||||||| +B11||IOB|IO|UNUSED||1|||||||||| +B12||IOB|IO|UNUSED||1|||||||||| +B13||IOB|IO_CS|UNUSED||1|||||||||| +B14|||TDO||||||||||||| +B15|||GND||||||||||||| +B16||IOB|IO|UNUSED||2|||||||||| +C1||IOB|IO_VREF_7|UNUSED||7|||||||||| +C2||IOB|IO|UNUSED||7|||||||||| +C3|||VCCINT||||||||2.5||||| +C4|||TCK||||||||||||| +C5||IOB|IO|UNUSED||0|||||||||| +C6||IOB|IO_VREF_0|UNUSED||0|||||||||| +C7||IOB|IO|UNUSED||0|||||||||| +C8||IOB|IO|UNUSED||0|||||||||| +C9||GCLKIOB|GCK2|UNUSED||1|||||||||| +C10||IOB|IO|UNUSED||1|||||||||| +C11||IOB|IO_VREF_1|UNUSED||1|||||||||| +C12||IOB|IO|UNUSED||1|||||||||| +C13||IOB|IO_WRITE|UNUSED||1|||||||||| +C14|||VCCINT||||||||2.5||||| +C15||IOB|IO_DOUT_BUSY|UNUSED||2|||||||||| +C16||IOB|IO|UNUSED||2|||||||||| +D1||IOB|IO_VREF_7|UNUSED||7|||||||||| +D2||IOB|IO|UNUSED||7|||||||||| +D3|||TMS||||||||||||| +D4|||VCCINT||||||||2.5||||| +D5||IOB|IO|UNUSED||0|||||||||| +D6||IOB|IO|UNUSED||0|||||||||| +D7||IOB|IO|UNUSED||0|||||||||| +D8||IOB|IO|UNUSED||0|||||||||| +D9||IOB|IO|UNUSED||1|||||||||| +D10||IOB|IO|UNUSED||1|||||||||| +D11||IOB|IO|UNUSED||1|||||||||| +D12||IOB|IO|UNUSED||1|||||||||| +D13|||VCCINT||||||||2.5||||| +D14|fpga_din_d0|IOB|IO_DIN_D0|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE| +D15|||CCLK||||||||||||| +D16||IOB|IO|UNUSED||2|||||||||| +E1|ps2_data|IOB|IO|INPUT|LVTTL|7||||IFD||LOCATED||YES|NONE| +E2||IOB|IO|UNUSED||7|||||||||| +E3|reset_n|IOB|IO|INPUT|LVTTL|7||||NONE||LOCATED||NO|NONE| +E4||IOB|IO|UNUSED||7|||||||||| +E5|||VCCINT||||||||2.5||||| +E6||IOB|IO|UNUSED||0|||||||||| +E7||IOB|IO|UNUSED||0|||||||||| +E8|||VCCO_0|||0|||||any******||||| +E9|||VCCO_1|||1|||||any******||||| +E10||IOB|IO|UNUSED||1|||||||||| +E11||IOB|IO_VREF_1|UNUSED||1|||||||||| +E12|||VCCINT||||||||2.5||||| +E13||IOB|IO_VREF_2|UNUSED||2|||||||||| +E14||IOB|IO|UNUSED||2|||||||||| +E15||IOB|IO|UNUSED||2|||||||||| +E16|fpga_d1|IOB|IO_D1|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE| +F1||IOB|IO|UNUSED||7|||||||||| +F2||IOB|IO|UNUSED||7|||||||||| +F3||IOB|IO|UNUSED||7|||||||||| +F4|ps2_clk|IOB|IO|INPUT|LVTTL|7||||IFD||LOCATED||YES|NONE| +F5||IOB|IO|UNUSED||7|||||||||| +F6|||GND||||||||||||| +F7|||GND||||||||||||| +F8|||VCCO_0|||0|||||any******||||| +F9|||VCCO_1|||1|||||any******||||| +F10|||GND||||||||||||| +F11|||GND||||||||||||| +F12||IOB|IO|UNUSED||2|||||||||| +F13||IOB|IO_VREF_2|UNUSED||2|||||||||| +F14||IOB|IO_VREF_2|UNUSED||2|||||||||| +F15|fpga_d2|IOB|IO_D2|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE| +F16||IOB|IO|UNUSED||2|||||||||| +G1||PCIIOB|IO_IRDY|UNUSED||7|||||||||| +G2||IOB|IO|UNUSED||7|||||||||| +G3||IOB|IO|UNUSED||7|||||||||| +G4||IOB|IO|UNUSED||7|||||||||| +G5||IOB|IO|UNUSED||7|||||||||| +G6|||GND||||||||||||| +G7|||GND||||||||||||| +G8|||GND||||||||||||| +G9|||GND||||||||||||| +G10|||GND||||||||||||| +G11|||GND||||||||||||| +G12||IOB|IO|UNUSED||2|||||||||| +G13||IOB|IO|UNUSED||2|||||||||| +G14||IOB|IO|UNUSED||2|||||||||| +G15||IOB|IO|UNUSED||2|||||||||| +G16|fpga_d3|IOB|IO_D3|OUTPUT|LVTTL|2|12|SLOW|NONE**|||LOCATED||NO|NONE| +H1||IOB|IO|UNUSED||6|||||||||| +H2||IOB|IO|UNUSED||7|||||||||| +H3||IOB|IO_VREF_7|UNUSED||7|||||||||| +H4||IOB|IO|UNUSED||7|||||||||| +H5|||VCCO_7|||7|||||any******||||| +H6|||VCCO_7|||7|||||any******||||| +H7|||GND||||||||||||| +H8|||GND||||||||||||| +H9|||GND||||||||||||| +H10|||GND||||||||||||| +H11|||VCCO_2|||2|||||3.30||||| +H12|||VCCO_2|||2|||||3.30||||| +H13||IOB|IO_VREF_2|UNUSED||2|||||||||| +H14||IOB|IO|UNUSED||2|||||||||| +H15||IOB|IO|UNUSED||2|||||||||| +H16||PCIIOB|IO_IRDY|UNUSED||2|||||||||| +J1||IOB|IO|UNUSED||6|||||||||| +J2||PCIIOB|IO_TRDY|UNUSED||6|||||||||| +J3||IOB|IO_VREF_6|UNUSED||6|||||||||| +J4||IOB|IO|UNUSED||6|||||||||| +J5|||VCCO_6|||6|||||any******||||| +J6|||VCCO_6|||6|||||any******||||| +J7|||GND||||||||||||| +J8|||GND||||||||||||| +J9|||GND||||||||||||| +J10|||GND||||||||||||| +J11|||VCCO_3|||3|||||3.30||||| +J12|||VCCO_3|||3|||||3.30||||| +J13||IOB|IO|UNUSED||2|||||||||| +J14||IOB|IO|UNUSED||3|||||||||| +J15||PCIIOB|IO_TRDY|UNUSED||3|||||||||| +J16|fpga_d4|IOB|IO_D4|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE| +K1||IOB|IO|UNUSED||6|||||||||| +K2||IOB|IO|UNUSED||6|||||||||| +K3||IOB|IO|UNUSED||6|||||||||| +K4||IOB|IO|UNUSED||6|||||||||| +K5||IOB|IO|UNUSED||6|||||||||| +K6|||GND||||||||||||| +K7|||GND||||||||||||| +K8|||GND||||||||||||| +K9|||GND||||||||||||| +K10|||GND||||||||||||| +K11|||GND||||||||||||| +K12||IOB|IO|UNUSED||3|||||||||| +K13||IOB|IO|UNUSED||3|||||||||| +K14||IOB|IO|UNUSED||3|||||||||| +K15||IOB|IO|UNUSED||3|||||||||| +K16||IOB|IO_VREF_3|UNUSED||3|||||||||| +L1||IOB|IO|UNUSED||6|||||||||| +L2||IOB|IO|UNUSED||6|||||||||| +L3||IOB|IO|UNUSED||6|||||||||| +L4||IOB|IO|UNUSED||6|||||||||| +L5||IOB|IO|UNUSED||6|||||||||| +L6|||GND||||||||||||| +L7|||GND||||||||||||| +L8|||VCCO_5|||5|||||any******||||| +L9|||VCCO_4|||4|||||any******||||| +L10|||GND||||||||||||| +L11|||GND||||||||||||| +L12||IOB|IO|UNUSED||3|||||||||| +L13||IOB|IO_VREF_3|UNUSED||3|||||||||| +L14||IOB|IO_VREF_3|UNUSED||3|||||||||| +L15||IOB|IO|UNUSED||3|||||||||| +L16||IOB|IO|UNUSED||3|||||||||| +M1||IOB|IO_VREF_6|UNUSED||6|||||||||| +M2||IOB|IO|UNUSED||6|||||||||| +M3||IOB|IO|UNUSED||6|||||||||| +M4||IOB|IO|UNUSED||6|||||||||| +M5|||VCCINT||||||||2.5||||| +M6||IOB|IO|UNUSED||5|||||||||| +M7||IOB|IO|UNUSED||5|||||||||| +M8|||VCCO_5|||5|||||any******||||| +M9|||VCCO_4|||4|||||any******||||| +M10||IOB|IO|UNUSED||4|||||||||| +M11||IOB|IO|UNUSED||4|||||||||| +M12|||VCCINT||||||||2.5||||| +M13||IOB|IO_VREF_3|UNUSED||3|||||||||| +M14||IOB|IO|UNUSED||3|||||||||| +M15||IOB|IO|UNUSED||3|||||||||| +M16|fpga_d5|IOB|IO_D5|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE| +N1||IOB|IO_VREF_6|UNUSED||6|||||||||| +N2||IOB|IO_VREF_6|UNUSED||6|||||||||| +N3|||M0||||||||||||| +N4|||VCCINT||||||||2.5||||| +N5||IOB|IO|UNUSED||5|||||||||| +N6||IOB|IO|UNUSED||5|||||||||| +N7||IOB|IO|UNUSED||5|||||||||| +N8||GCLKIOB|GCK0|UNUSED||4|||||||||| +N9||IOB|IO|UNUSED||4|||||||||| +N10||IOB|IO|UNUSED||4|||||||||| +N11||IOB|IO|UNUSED||4|||||||||| +N12||IOB|IO|UNUSED||4|||||||||| +N13|||VCCINT||||||||2.5||||| +N14|fpga_d7|IOB|IO_D7|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE| +N15||IOB|IO_INIT|UNUSED||3|||||||||| +N16|fpga_d6|IOB|IO_D6|OUTPUT|LVTTL|3|12|SLOW|NONE**|||LOCATED||NO|NONE| +P1||IOB|IO|UNUSED||6|||||||||| +P2|||M1||||||||||||| +P3|||VCCINT||||||||2.5||||| +P4|||NC||||||||||||| +P5||IOB|IO|UNUSED||5|||||||||| +P6||IOB|IO|UNUSED||5|||||||||| +P7||IOB|IO|UNUSED||5|||||||||| +P8||IOB|IO_VREF_5|UNUSED||5|||||||||| +P9||IOB|IO_VREF_4|UNUSED||4|||||||||| +P10||IOB|IO|UNUSED||4|||||||||| +P11||IOB|IO|UNUSED||4|||||||||| +P12||IOB|IO|UNUSED||4|||||||||| +P13||IOB|IO|UNUSED||4|||||||||| +P14|||VCCINT||||||||2.5||||| +P15|||PROGRAM||||||||||||| +P16||IOB|IO|UNUSED||3|||||||||| +R1||IOB|IO|UNUSED||6|||||||||| +R2|||GND||||||||||||| +R3|||M2||||||||||||| +R4|||NC||||||||||||| +R5||IOB|IO_VREF_5|UNUSED||5|||||||||| +R6||IOB|IO|UNUSED||5|||||||||| +R7||IOB|IO|UNUSED||5|||||||||| +R8|clka|GCLKIOB|GCK1|INPUT|LVTTL|5||||NONE||LOCATED||NO|NONE| +R9||IOB|IO|UNUSED||4|||||||||| +R10||IOB|IO|UNUSED||4|||||||||| +R11||IOB|IO|UNUSED||4|||||||||| +R12||IOB|IO|UNUSED||4|||||||||| +R13||IOB|IO_VREF_4|UNUSED||4|||||||||| +R14|||DONE||||||||||||| +R15|||GND||||||||||||| +R16||IOB|IO|UNUSED||3|||||||||| +T1|||GND||||||||||||| +T2||IOB|IO_VREF_5|UNUSED||5|||||||||| +T3||IOB|IO|UNUSED||5|||||||||| +T4||IOB|IO_VREF_5|UNUSED||5|||||||||| +T5||IOB|IO|UNUSED||5|||||||||| +T6||IOB|IO|UNUSED||5|||||||||| +T7||IOB|IO|UNUSED||5|||||||||| +T8||IOB|IO|UNUSED||5|||||||||| +T9||IOB|IO|UNUSED||4|||||||||| +T10||IOB|IO|UNUSED||4|||||||||| +T11||IOB|IO_VREF_4|UNUSED||4|||||||||| +T12||IOB|IO_VREF_4|UNUSED||4|||||||||| +T13||IOB|IO|UNUSED||4|||||||||| +T14||IOB|IO|UNUSED||4|||||||||| +T15||IOB|IO|UNUSED||3|||||||||| +T16|||GND||||||||||||| + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/xilinx/ps2/fpga.par b/xilinx/ps2/fpga.par new file mode 100644 index 0000000..aac9df7 --- /dev/null +++ b/xilinx/ps2/fpga.par @@ -0,0 +1,200 @@ +Release 8.2i par I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +wide:: Thu Dec 21 09:18:46 2006 + +par -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf + + +Constraints file: fpga.pcf. +Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx. + "fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5 + +Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) +Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts) + +INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par + -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all + internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For + the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a + balance between the fastest runtime and best performance, set the effort level to "med". + +Device speed data version: "PRODUCTION 1.27 2006-05-03". + + +Device Utilization Summary: + + Number of GCLKs 2 out of 4 50% + Number of External GCLKIOBs 1 out of 4 25% + Number of LOCed GCLKIOBs 1 out of 1 100% + + Number of External IOBs 11 out of 176 6% + Number of LOCed IOBs 11 out of 11 100% + + Number of SLICEs 39 out of 2352 1% + + +Overall effort level (-ol): Standard +Placer effort level (-pl): High +Placer cost table entry (-t): 1 +Router effort level (-rl): Standard + + +Starting Placer + +Phase 1.1 +Phase 1.1 (Checksum:98976a) REAL time: 3 secs + +Phase 2.31 +Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs + +Phase 3.23 +Phase 3.23 (Checksum:1c9c37d) REAL time: 3 secs + +Phase 4.3 +Phase 4.3 (Checksum:26259fc) REAL time: 3 secs + +Phase 5.5 +Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs + +Phase 6.8 +. +. +. +. +. +. +Phase 6.8 (Checksum:99cc93) REAL time: 3 secs + +Phase 7.5 +Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs + +Phase 8.18 +Phase 8.18 (Checksum:4c4b3f8) REAL time: 3 secs + +Phase 9.5 +Phase 9.5 (Checksum:55d4a77) REAL time: 3 secs + +Writing design to file fpga.ncd + + +Total REAL time to Placer completion: 3 secs +Total CPU time to Placer completion: 3 secs + +Starting Router + +Phase 1: 225 unrouted; REAL time: 3 secs + +Phase 2: 200 unrouted; REAL time: 4 secs + +Phase 3: 25 unrouted; REAL time: 4 secs + +Phase 4: 25 unrouted; (1488) REAL time: 4 secs + +Phase 5: 25 unrouted; (1) REAL time: 4 secs + +Phase 6: 0 unrouted; (1) REAL time: 4 secs + +Phase 7: 0 unrouted; (1) REAL time: 4 secs + +Phase 8: 0 unrouted; (1) REAL time: 4 secs + +Phase 9: 0 unrouted; (1) REAL time: 4 secs + +Phase 10: 0 unrouted; (1) REAL time: 4 secs + +Phase 11: 0 unrouted; (1) REAL time: 4 secs + +Total REAL time to Router completion: 4 secs +Total CPU time to Router completion: 4 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| gray_cnt_FFd1 | GCLKBUF0| No | 25 | 0.207 | 0.763 | ++---------------------+--------------+------+------+------------+-------------+ +| clka_BUFGP | GCLKBUF1| No | 1 | 0.000 | 0.743 | ++---------------------+--------------+------+------+------------+-------------+ +| ps2/rdy_r | Local| | 2 | 0.000 | 2.188 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + + + The Delay Summary Report + + +The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 + + The AVERAGE CONNECTION DELAY for this design is: 1.482 + The MAXIMUM PIN DELAY IS: 6.039 + The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 3.856 + + Listing Pin Delays by value: (nsec) + + d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00 + --------- --------- --------- --------- --------- --------- + 98 78 17 15 15 0 + +Timing Score: 0 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +------------------------------------------------------------------------------------------------------ + Constraint | Requested | Actual | Logic | Absolute |Number of + | | | Levels | Slack |errors +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net gra | N/A | 8.576ns | 4 | N/A | N/A + y_cnt_FFd1 | | | | | +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net clk | N/A | 6.308ns | 1 | N/A | N/A + a_BUFGP | | | | | +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net ps2 | N/A | 2.969ns | 0 | N/A | N/A + /rdy_r | | | | | +------------------------------------------------------------------------------------------------------ + + +All constraints were met. +INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the + constraint does not cover any paths or that it has no requested value. + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 5 secs +Total CPU time to PAR completion: 5 secs + +Peak Memory Usage: 307 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 0 +Number of info messages: 1 + +Writing design to file fpga.ncd + + + +PAR done! diff --git a/xilinx/ps2/fpga.pcf b/xilinx/ps2/fpga.pcf new file mode 100644 index 0000000..9835c68 --- /dev/null +++ b/xilinx/ps2/fpga.pcf @@ -0,0 +1,18 @@ +//! ************************************************************************** +// Written by: Map I.31 on Thu Dec 21 09:18:43 2006 +//! ************************************************************************** + +SCHEMATIC START; +COMP "reset_n" LOCATE = SITE "E3" LEVEL 1; +COMP "clka" LOCATE = SITE "R8" LEVEL 1; +COMP "fpga_d1" LOCATE = SITE "E16" LEVEL 1; +COMP "fpga_din_d0" LOCATE = SITE "D14" LEVEL 1; +COMP "fpga_d2" LOCATE = SITE "F15" LEVEL 1; +COMP "fpga_d3" LOCATE = SITE "G16" LEVEL 1; +COMP "fpga_d4" LOCATE = SITE "J16" LEVEL 1; +COMP "fpga_d5" LOCATE = SITE "M16" LEVEL 1; +COMP "fpga_d6" LOCATE = SITE "N16" LEVEL 1; +COMP "fpga_d7" LOCATE = SITE "N14" LEVEL 1; +COMP "ps2_data" LOCATE = SITE "E1" LEVEL 1; +COMP "ps2_clk" LOCATE = SITE "F4" LEVEL 1; +SCHEMATIC END; diff --git a/xilinx/ps2/fpga.prj b/xilinx/ps2/fpga.prj new file mode 100644 index 0000000..bf251c7 --- /dev/null +++ b/xilinx/ps2/fpga.prj @@ -0,0 +1,2 @@ +verilog work "../../v/ps2.v" +verilog work "../../v/fpga2.v" diff --git a/xilinx/ps2/fpga.stx b/xilinx/ps2/fpga.stx new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/ps2/fpga.syr b/xilinx/ps2/fpga.syr new file mode 100644 index 0000000..40d629f --- /dev/null +++ b/xilinx/ps2/fpga.syr @@ -0,0 +1,524 @@ +Release 8.2i - xst I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to ./xst/projnav.tmp +CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s + +--> +Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s + +--> +Reading design: fpga.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpga.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "fpga" +Output Format : NGC +Target Device : xc2s200-5-fg256 + +---- Source Options +Top Module Name : fpga +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : YES +Resource Sharing : YES +Multiplier Style : lut +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100 +Add Generic Clock Buffer(BUFG) : 4 +Register Duplication : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +RTL Output : Yes +Global Optimization : AllClockNets +Write Timing Constraints : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : fpga.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../v/ps2.v" in library work +Compiling verilog file "../../v/fpga2.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"fpga.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library with parameters. + PS2_FREQ = "00000000000000000000000000001010" + KEY_RELEASE = "11110000" + FREQ = "00000000000000000110000110101000" + TIMEOUT = "00000000000000000000100111000100" + +Building hierarchy successfully finished. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + +Analyzing module in library . + FREQ = 32'sb00000000000000000110000110101000 + PS2_FREQ = 32'sb00000000000000000000000000001010 + TIMEOUT = 32'sb00000000000000000000100111000100 + KEY_RELEASE = 8'b11110000 +Module is correct for synthesis. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "../../v/ps2.v". + Found 14-bit adder for signal <$addsub0000> created at line 93. + Found 4-bit adder for signal <$addsub0001> created at line 103. + Found 4-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit 4-to-1 multiplexer for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Summary: + inferred 36 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 5 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/fpga2.v". +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1780 - Signal is never used or assigned. +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:1780 - Signal is never used or assigned. +WARNING:Xst:1780 - Signal is never used or assigned. +WARNING:Xst:1780 - Signal is never used or assigned. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 4 | + | Inputs | 0 | + | Outputs | 2 | + | Clock | clka (rising_edge) | + | Reset | reset_n (negative) | + | Reset type | asynchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 2 + 14-bit adder : 1 + 4-bit adder : 1 +# Registers : 8 + 1-bit register : 4 + 10-bit register : 1 + 14-bit register : 1 + 4-bit register : 1 + 5-bit register : 1 +# Multiplexers : 2 + 1-bit 4-to-1 multiplexer : 1 + 4-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 11 | 11 + 10 | 10 +------------------- +Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx. + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# FSMs : 1 +# Adders/Subtractors : 2 + 14-bit adder : 1 + 4-bit adder : 1 +# Registers : 39 + Flip-Flops : 39 +# Multiplexers : 2 + 1-bit 4-to-1 multiplexer : 1 + 4-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 1. + +Final Macro Processing ... + +Processing Unit : +INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 39 + Flip-Flops : 39 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : fpga.ngr +Top Level Output File Name : fpga +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 24 + +Cell Usage : +# BELS : 85 +# GND : 1 +# INV : 4 +# LUT1 : 13 +# LUT2 : 16 +# LUT3 : 2 +# LUT3_L : 1 +# LUT4 : 14 +# LUT4_D : 3 +# LUT4_L : 2 +# MUXCY : 13 +# MUXF5 : 2 +# VCC : 1 +# XORCY : 13 +# FlipFlops/Latches : 39 +# FDC : 24 +# FDCE : 10 +# FDP : 5 +# Clock Buffers : 2 +# BUFG : 1 +# BUFGP : 1 +# IO Buffers : 11 +# IBUF : 3 +# OBUF : 8 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200fg256-5 + + Number of Slices: 34 out of 2352 1% + Number of Slice Flip Flops: 39 out of 4704 0% + Number of 4 input LUTs: 55 out of 4704 1% + Number of IOs: 24 + Number of bonded IOBs: 12 out of 180 6% + Number of GCLKs: 2 out of 4 50% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +ps2/rdy_r | NONE(rdy) | 1 | +clka | BUFGP | 2 | +gray_cnt_FFd11 | BUFG | 36 | +-----------------------------------+------------------------+-------+ +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +-------------------------------------+------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-------------------------------------+------------------------+-------+ +ps2/rst_n_inv(ps2/rst_n_inv1_INV_0:O)| NONE(rdy) | 39 | +-------------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: 10.147ns (Maximum Frequency: 98.551MHz) + Minimum input arrival time before clock: 2.827ns + Maximum output required time after clock: 8.329ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'ps2/rdy_r' + Clock period: 5.188ns (frequency: 192.753MHz) + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Delay: 5.188ns (Levels of Logic = 1) + Source: rdy (FF) + Destination: rdy (FF) + Source Clock: ps2/rdy_r rising + Destination Clock: ps2/rdy_r rising + + Data Path: rdy to rdy + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 2 1.292 1.340 rdy (rdy) + INV:I->O 1 0.653 1.150 _not00011_INV_0 (_not0001) + FDC:D 0.753 rdy + ---------------------------------------- + Total 5.188ns (2.698ns logic, 2.490ns route) + (52.0% logic, 48.0% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'clka' + Clock period: 9.821ns (frequency: 101.823MHz) + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Delay: 9.821ns (Levels of Logic = 2) + Source: gray_cnt_FFd1 (FF) + Destination: gray_cnt_FFd2 (FF) + Source Clock: clka rising + Destination Clock: clka rising + + Data Path: gray_cnt_FFd1 to gray_cnt_FFd2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 1 1.292 1.150 gray_cnt_FFd1 (gray_cnt_FFd11) + BUFG:I->O 37 0.773 4.050 gray_cnt_FFd1_BUFG (gray_cnt_FFd1) + INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In) + FDC:D 0.753 gray_cnt_FFd2 + ---------------------------------------- + Total 9.821ns (3.471ns logic, 6.350ns route) + (35.3% logic, 64.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'gray_cnt_FFd11' + Clock period: 10.147ns (frequency: 98.551MHz) + Total number of paths / destination ports: 389 / 44 +------------------------------------------------------------------------- +Delay: 10.147ns (Levels of Logic = 4) + Source: ps2/timer_r_7 (FF) + Destination: ps2/bitcnt_r_1 (FF) + Source Clock: gray_cnt_FFd11 rising + Destination Clock: gray_cnt_FFd11 rising + + Data Path: ps2/timer_r_7 to ps2/bitcnt_r_1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 2 1.292 1.340 ps2/timer_r_7 (ps2/timer_r_7) + LUT4:I0->O 1 0.653 1.150 ps2/_cmp_eq00018 (ps2/_cmp_eq0001_map32) + LUT4:I0->O 6 0.653 1.850 ps2/_cmp_eq000156 (ps2/_cmp_eq0001) + LUT4_D:I3->O 1 0.653 1.150 ps2/bitcnt_x<1>111 (ps2/N3) + LUT4:I1->O 1 0.653 0.000 ps2/bitcnt_x<1>1 (ps2/bitcnt_x<1>) + FDC:D 0.753 ps2/bitcnt_r_1 + ---------------------------------------- + Total 10.147ns (4.657ns logic, 5.490ns route) + (45.9% logic, 54.1% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd11' + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Offset: 2.827ns (Levels of Logic = 1) + Source: ps2_clk (PAD) + Destination: ps2/ps2_clk_r_0 (FF) + Destination Clock: gray_cnt_FFd11 rising + + Data Path: ps2_clk to ps2/ps2_clk_r_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.924 1.150 ps2_clk_IBUF (ps2_clk_IBUF) + FDP:D 0.753 ps2/ps2_clk_r_0 + ---------------------------------------- + Total 2.827ns (1.677ns logic, 1.150ns route) + (59.3% logic, 40.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'gray_cnt_FFd11' + Total number of paths / destination ports: 7 / 7 +------------------------------------------------------------------------- +Offset: 8.329ns (Levels of Logic = 1) + Source: ps2/sc_r_6 (FF) + Destination: fpga_din_d0 (PAD) + Source Clock: gray_cnt_FFd11 rising + + Data Path: ps2/sc_r_6 to fpga_din_d0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDCE:C->Q 3 1.292 1.480 ps2/sc_r_6 (ps2/sc_r_6) + OBUF:I->O 5.557 fpga_din_d0_OBUF (fpga_din_d0) + ---------------------------------------- + Total 8.329ns (6.849ns logic, 1.480ns route) + (82.2% logic, 17.8% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'ps2/rdy_r' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 8.189ns (Levels of Logic = 1) + Source: rdy (FF) + Destination: fpga_d1 (PAD) + Source Clock: ps2/rdy_r rising + + Data Path: rdy to fpga_d1 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 2 1.292 1.340 rdy (rdy) + OBUF:I->O 5.557 fpga_d1_OBUF (fpga_d1) + ---------------------------------------- + Total 8.189ns (6.849ns logic, 1.340ns route) + (83.6% logic, 16.4% route) + +========================================================================= +CPU : 7.48 / 7.59 s | Elapsed : 8.00 / 8.00 s + +--> + + +Total memory usage is 239200 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 18 ( 0 filtered) +Number of infos : 3 ( 0 filtered) + diff --git a/xilinx/ps2/fpga.twr b/xilinx/ps2/fpga.twr new file mode 100644 index 0000000..54789d8 --- /dev/null +++ b/xilinx/ps2/fpga.twr @@ -0,0 +1,48 @@ +-------------------------------------------------------------------------------- +Release 8.2i Trace +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +trce -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise -e 3 -l 3 -s 5 +-xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf + +Design file: fpga.ncd +Physical constraint file: fpga.pcf +Device,speed: xc2s200,-5 (PRODUCTION 1.27 2006-05-03) +Report level: error report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:2698 - No timing constraints found, doing default enumeration. +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. + + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Clock to Setup on destination clock clka +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +clka | 6.308| | | | +---------------+---------+---------+---------+---------+ + + +Analysis completed Thu Dec 21 09:18:57 2006 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 194 MB + + + diff --git a/xilinx/ps2/fpga.twx b/xilinx/ps2/fpga.twx new file mode 100644 index 0000000..7d0482a --- /dev/null +++ b/xilinx/ps2/fpga.twx @@ -0,0 +1,279 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 8.2i Trace Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.trce -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise -e 3 -l 3 -s 5 +-xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga2.ucf + +fpga.ncdfpga.pcfxc2s200-5PRODUCTION 1.27 2006-05-03INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.clkaclka6.308Thu Dec 21 09:18:57 2006TraceTrace Settings + +Peak Memory Usage: 194 MB + diff --git a/xilinx/ps2/fpga.unroutes b/xilinx/ps2/fpga.unroutes new file mode 100644 index 0000000..52236c2 --- /dev/null +++ b/xilinx/ps2/fpga.unroutes @@ -0,0 +1,7 @@ +Release 8.2i - par I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Thu Dec 21 09:18:52 2006 + +There are 0 unrouted networks: + diff --git a/xilinx/ps2/fpga.ut b/xilinx/ps2/fpga.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/xilinx/ps2/fpga.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/xilinx/ps2/fpga.xpi b/xilinx/ps2/fpga.xpi new file mode 100644 index 0000000..d043f7f --- /dev/null +++ b/xilinx/ps2/fpga.xpi @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=OFF diff --git a/xilinx/ps2/fpga.xst b/xilinx/ps2/fpga.xst new file mode 100644 index 0000000..5752522 --- /dev/null +++ b/xilinx/ps2/fpga.xst @@ -0,0 +1,54 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn fpga.prj +-ifmt mixed +-ofn fpga +-ofmt NGC +-p xc2s200-5-fg256 +-top fpga +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso fpga.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xilinx/ps2/fpga_last_par.ncd b/xilinx/ps2/fpga_last_par.ncd new file mode 100644 index 0000000..f2ad455 --- /dev/null +++ b/xilinx/ps2/fpga_last_par.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4 +###5592:XlxV32DM 3fff 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\ No newline at end of file diff --git a/xilinx/ps2/fpga_map.mrp b/xilinx/ps2/fpga_map.mrp new file mode 100644 index 0000000..638265e --- /dev/null +++ b/xilinx/ps2/fpga_map.mrp @@ -0,0 +1,169 @@ +Release 8.2i Map I.31 +Xilinx Mapping Report File for Design 'fpga' + +Design Information +------------------ +Command Line : map -ise /mwave/work/nt/xess/xilinx/ps2/ps2.ise -intstyle ise +-p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd +fpga.pcf +Target Device : xc2s200 +Target Package : fg256 +Target Speed : -5 +Mapper Version : spartan2 -- $Revision: 1.34.32.1 $ +Mapped Date : Thu Dec 21 09:18:40 2006 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 3 +Logic Utilization: + Number of Slice Flip Flops: 37 out of 4,704 1% + Number of 4 input LUTs: 39 out of 4,704 1% +Logic Distribution: + Number of occupied Slices: 39 out of 2,352 1% + Number of Slices containing only related logic: 39 out of 39 100% + Number of Slices containing unrelated logic: 0 out of 39 0% + *See NOTES below for an explanation of the effects of unrelated logic +Total Number 4 input LUTs: 52 out of 4,704 1% + Number used as logic: 39 + Number used as a route-thru: 13 + Number of bonded IOBs: 11 out of 176 6% + IOB Flip Flops: 2 + Number of GCLKs: 2 out of 4 50% + Number of GCLKIOBs: 1 out of 4 25% + +Total equivalent gate count for design: 630 +Additional JTAG gate count for IOBs: 576 +Peak Memory Usage: 356 MB + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Modular Design Summary +Section 11 - Timing Report +Section 12 - Configuration String Information + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:LIT:243 - Logical network clkb has no load. +WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 11 + more times for the following (max. 5 shown): + vga_hsync_n, + vga_red0, + vga_red1, + vga_red2, + vga_green0 + To see the details of these warning messages, please use the -detail switch. +WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol + "gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1) has a mix of clock and + non-clock loads. The non-clock loads are: + Pin D of gray_cnt_FFd2 + +Section 3 - Informational +------------------------- +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs in the + schematic. + +Section 4 - Removed Logic Summary +--------------------------------- + 2 block(s) optimized away + +Section 5 - Removed Logic +------------------------- + +Optimized Block(s): +TYPE BLOCK +GND XST_GND +VCC XST_VCC + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Strength | Rate | | | Delay | ++------------------------------------------------------------------------------------------------------------------------+ +| clka | GCLKIOB | INPUT | LVTTL | | | | | | +| fpga_d1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d3 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d4 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d5 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d6 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d7 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_din_d0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| ps2_clk | IOB | INPUT | LVTTL | | | INFF | | IFD | +| ps2_data | IOB | INPUT | LVTTL | | | INFF | | IFD | +| reset_n | IOB | INPUT | LVTTL | | | | | | ++------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Modular Design Summary +----------------------------------- +Modular Design not used for this design. + +Section 11 - Timing Report +-------------------------- +No timing report for this architecture. + +Section 12 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings diff --git a/xilinx/ps2/fpga_map.ncd b/xilinx/ps2/fpga_map.ncd new file mode 100644 index 0000000..d4cab61 --- /dev/null +++ b/xilinx/ps2/fpga_map.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4 +###5388:XlxV32DM 3fff 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file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. +2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. +3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. + +INPUT FILE: fpga_map.ncd +OUTPUT FILE: fpga_pad.txt +PART TYPE: xc2s200 +SPEED GRADE: -5 +PACKAGE: fg256 + +Pinout by Pin Number: + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|DCI Value|IO Register|Signal Integrity| ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|A1 | | |GND | | | | | | | | | | | | | +|A2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|A3 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|A4 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A8 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A11 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A13 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A14 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|A15 | | |TDI | | | | | | | | | | | | | +|A16 | | |GND | | | | | | | | | | | | | +|B1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|B2 | | |GND | | | | | | | | | | | | | +|B3 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|B4 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|B5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|B6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|B7 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|B8 | |GCLKIOB |GCK3 |UNUSED | |0 | | | | | | | | | | +|B9 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|B10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|B11 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|B12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|B13 | |IOB |IO_CS |UNUSED | |1 | | | | | | | | | | +|B14 | | |TDO | | | | | | | | | | | | | +|B15 | | |GND | | | | | | | | | | | | | +|B16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|C1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|C2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|C3 | | |VCCINT | | | | | | | |2.5 | | | | | +|C4 | | |TCK | | | | | | | | | | | | | +|C5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|C6 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|C7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|C8 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|C9 | |GCLKIOB |GCK2 |UNUSED | |1 | | | | | | | | | | +|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|C11 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|C12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|C13 | |IOB |IO_WRITE |UNUSED | |1 | | | | | | | | | | +|C14 | | |VCCINT | | | | | | | |2.5 | | | | | +|C15 | |IOB |IO_DOUT_BUSY|UNUSED | |2 | | | | | | | | | | +|C16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|D1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|D2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|D3 | | |TMS | | | | | | | | | | | | | +|D4 | | |VCCINT | | | | | | | |2.5 | | | | | +|D5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D8 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D9 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D11 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D13 | | |VCCINT | | | | | | | |2.5 | | | | | +|D14 |fpga_din_d0|IOB |IO_DIN_D0 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|D15 | | |CCLK | | | | | | | | | | | | | +|D16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|E1 |ps2_data |IOB |IO |INPUT |LVTTL |7 | | | |IFD | |LOCATED | |YES |NONE | +|E2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|E3 |reset_n |IOB |IO |INPUT |LVTTL |7 | | | |NONE | |LOCATED | |NO |NONE | +|E4 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|E5 | | |VCCINT | | | | | | | |2.5 | | | | | +|E6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|E7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|E8 | | |VCCO_0 | | |0 | | | | |any******| | | | | +|E9 | | |VCCO_1 | | |1 | | | | |any******| | | | | +|E10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|E11 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|E12 | | |VCCINT | | | | | | | |2.5 | | | | | +|E13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|E14 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|E15 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|E16 |fpga_d1 |IOB |IO_D1 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|F1 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F3 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F4 |ps2_clk |IOB |IO |INPUT |LVTTL |7 | | | |IFD | |LOCATED | |YES |NONE | +|F5 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F6 | | |GND | | | | | | | | | | | | | +|F7 | | |GND | | | | | | | | | | | | | +|F8 | | |VCCO_0 | | |0 | | | | |any******| | | | | +|F9 | | |VCCO_1 | | |1 | | | | |any******| | | | | +|F10 | | |GND | | | | | | | | | | | | | +|F11 | | |GND | | | | | | | | | | | | | +|F12 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|F13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|F14 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|F15 |fpga_d2 |IOB |IO_D2 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|F16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G1 | |PCIIOB |IO_IRDY |UNUSED | |7 | | | | | | | | | | +|G2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G3 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G4 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G5 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G6 | | |GND | | | | | | | | | | | | | +|G7 | | |GND | | | | | | | | | | | | | +|G8 | | |GND | | | | | | | | | | | | | +|G9 | | |GND | | | | | | | | | | | | | +|G10 | | |GND | | | | | | | | | | | | | +|G11 | | |GND | | | | | | | | | | | | | +|G12 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G13 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G14 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G15 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G16 |fpga_d3 |IOB |IO_D3 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|H1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|H2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|H3 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|H4 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|H5 | | |VCCO_7 | | |7 | | | | |any******| | | | | +|H6 | | |VCCO_7 | | |7 | | | | |any******| | | | | +|H7 | | |GND | | | | | | | | | | | | | +|H8 | | |GND | | | | | | | | | | | | | +|H9 | | |GND | | | | | | | | | | | | | +|H10 | | |GND | | | | | | | | | | | | | +|H11 | | |VCCO_2 | | |2 | | | | |3.30 | | | | | +|H12 | | |VCCO_2 | | |2 | | | | |3.30 | | | | | +|H13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|H14 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|H15 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|H16 | |PCIIOB |IO_IRDY |UNUSED | |2 | | | | | | | | | | +|J1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|J2 | |PCIIOB |IO_TRDY |UNUSED | |6 | | | | | | | | | | +|J3 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | | +|J4 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|J5 | | |VCCO_6 | | |6 | | | | |any******| | | | | +|J6 | | |VCCO_6 | | |6 | | | | |any******| | | | | +|J7 | | |GND | | | | | | | | | | | | | +|J8 | | |GND | | | | | | | | | | | | | +|J9 | | |GND | | | | | | | | | | | | | +|J10 | | |GND | | | | | | | | | | | | | +|J11 | | |VCCO_3 | | |3 | | | | |3.30 | | | | | +|J12 | | |VCCO_3 | | |3 | | | | |3.30 | | | | | +|J13 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|J14 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|J15 | |PCIIOB |IO_TRDY |UNUSED | |3 | | | | | | | | | | +|J16 |fpga_d4 |IOB |IO_D4 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|K1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|K2 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|K3 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|K4 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|K5 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|K6 | | |GND | | | | | | | | | | | | | +|K7 | | |GND | | | | | | | | | | | | | +|K8 | | |GND | | | | | | | | | | | | | +|K9 | | |GND | | | | | | | | | | | | | +|K10 | | |GND | | | | | | | | | | | | | +|K11 | | |GND | | | | | | | | | | | | | +|K12 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K13 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K14 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K16 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|L1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L2 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L3 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L4 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L5 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L6 | | |GND | | | | | | | | | | | | | +|L7 | | |GND | | | | | | | | | | | | | +|L8 | | |VCCO_5 | | |5 | | | | |any******| | | | | +|L9 | | |VCCO_4 | | |4 | | | | |any******| | | | | +|L10 | | |GND | | | | | | | | | | | | | +|L11 | | |GND | | | | | | | | | | | | | +|L12 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|L13 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|L14 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|L15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|L16 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|M1 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | | +|M2 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|M3 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|M4 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|M5 | | |VCCINT | | | | | | | |2.5 | | | | | +|M6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|M7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|M8 | | |VCCO_5 | | |5 | | | | |any******| | | | | +|M9 | | |VCCO_4 | | |4 | | | | |any******| | | | | +|M10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|M11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|M12 | | |VCCINT | | | | | | | |2.5 | | | | | +|M13 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|M14 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|M15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|M16 |fpga_d5 |IOB |IO_D5 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|N1 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | | +|N2 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | | +|N3 | | |M0 | | | | | | | | | | | | | +|N4 | | |VCCINT | | | | | | | |2.5 | | | | | +|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|N6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|N7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|N8 | |GCLKIOB |GCK0 |UNUSED | |4 | | | | | | | | | | +|N9 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N12 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N13 | | |VCCINT | | | | | | | |2.5 | | | | | +|N14 |fpga_d7 |IOB |IO_D7 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|N15 | |IOB |IO_INIT |UNUSED | |3 | | | | | | | | | | +|N16 |fpga_d6 |IOB |IO_D6 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|P1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|P2 | | |M1 | | | | | | | | | | | | | +|P3 | | |VCCINT | | | | | | | |2.5 | | | | | +|P4 | | |NC | | | | | | | | | | | | | +|P5 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|P6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|P8 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | | +|P9 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|P10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P12 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P13 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P14 | | |VCCINT | | | | | | | |2.5 | | | | | +|P15 | | |PROGRAM | | | | | | | | | | | | | +|P16 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|R1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|R2 | | |GND | | | | | | | | | | | | | +|R3 | | |M2 | | | | | | | | | | | | | +|R4 | | |NC | | | | | | | | | | | | | +|R5 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | | +|R6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|R7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|R8 |clka |GCLKIOB |GCK1 |INPUT |LVTTL |5 | | | |NONE | |LOCATED | |NO |NONE | +|R9 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R12 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R13 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|R14 | | |DONE | | | | | | | | | | | | | +|R15 | | |GND | | | | | | | | | | | | | +|R16 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|T1 | | |GND | | | | | | | | | | | | | +|T2 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | | +|T3 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T4 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | | +|T5 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T8 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T9 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T11 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|T12 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|T13 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T14 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|T16 | | |GND | | | | | | | | | | | | | ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/xilinx/ps2/fpga_summary.html b/xilinx/ps2/fpga_summary.html new file mode 100644 index 0000000..1159bec --- /dev/null +++ b/xilinx/ps2/fpga_summary.html @@ -0,0 +1,165 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PS2 Project Status
Project File:ps2.iseCurrent State:Programming File Generated
Module Name:fpga
  • Errors:
No Errors
Target Device:xc2s200-5fg256
  • Warnings:
21 Warnings
Product Version:ISE 8.2i
  • Updated:
Wed Dec 27 10:45:57 2006
+ 
+ + +
PS2 Partition Summary
No partition information was found.
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops374,7041% 
Number of 4 input LUTs394,7041% 
Logic Distribution     
    Number of occupied Slices392,3521% 
    Number of Slices containing only related logic3939100% 
    Number of Slices containing unrelated logic0390% 
Total Number 4 input LUTs524,7041% 
        Number used as logic39   
        Number used as a route-thru13   
Number of bonded IOBs111766% 
        IOB Flip Flops2   
Number of GCLKs2450% 
Number of GCLKIOBs1425% 
Total equivalent gate count for design630   
Additional JTAG gate count for IOBs576   
+ 
+ + + + + + + + + + + + + + + + + + + +
Performance Summary
Final Timing Score:0Pinout Data:Pinout Report
Routing Results:All Signals Completely RoutedClock Data:Clock Report
Timing Constraints:All Constraints Met  
+ 
+ + + + + + + + + +
Detailed Reports
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentThu Dec 21 09:18:27 2006018 Warnings3 Infos
Translation ReportCurrentThu Dec 21 09:18:36 2006000
Map ReportCurrentThu Dec 21 09:18:44 200603 Warnings2 Infos
Place and Route ReportCurrentThu Dec 21 09:18:52 2006002 Infos
Static Timing ReportCurrentThu Dec 21 09:18:57 2006002 Infos
Bitgen ReportCurrentThu Dec 21 09:19:06 2006000
+ 
+ + + +
Secondary Reports
Report NameStatusGenerated
Xplorer Report  
+ \ No newline at end of file diff --git a/xilinx/ps2/fpga_usage.xml b/xilinx/ps2/fpga_usage.xml new file mode 100644 index 0000000..e009208 --- /dev/null +++ b/xilinx/ps2/fpga_usage.xml @@ -0,0 +1,412 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/ps2/fpga_vhdl.prj b/xilinx/ps2/fpga_vhdl.prj new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/ps2/ps2.ise b/xilinx/ps2/ps2.ise new file mode 100644 index 0000000..4a35f1f Binary files /dev/null and b/xilinx/ps2/ps2.ise differ diff --git a/xilinx/ps2/ps2.ise_ISE_Backup b/xilinx/ps2/ps2.ise_ISE_Backup new file mode 100644 index 0000000..4a35f1f Binary files /dev/null and b/xilinx/ps2/ps2.ise_ISE_Backup differ diff --git a/xilinx/ps2/ps2.ntrc_log b/xilinx/ps2/ps2.ntrc_log new file mode 100644 index 0000000..b92f78e --- /dev/null +++ b/xilinx/ps2/ps2.ntrc_log @@ -0,0 +1,19 @@ +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- diff --git a/xilinx/ps2/xst/work/hdllib.ref b/xilinx/ps2/xst/work/hdllib.ref new file mode 100644 index 0000000..682b6b1 --- /dev/null +++ b/xilinx/ps2/xst/work/hdllib.ref @@ -0,0 +1,2 @@ +MO fpga NULL ../../v/fpga2.v vlg22/fpga.bin 1166710699 +MO ps2 NULL ../../v/ps2.v vlg61/ps2.bin 1166710699 diff --git a/xilinx/ps2/xst/work/vlg22/fpga.bin b/xilinx/ps2/xst/work/vlg22/fpga.bin new file mode 100644 index 0000000..a72341a Binary files /dev/null and b/xilinx/ps2/xst/work/vlg22/fpga.bin differ diff --git a/xilinx/ps2/xst/work/vlg61/ps2.bin b/xilinx/ps2/xst/work/vlg61/ps2.bin new file mode 100644 index 0000000..6dd29aa Binary files /dev/null and b/xilinx/ps2/xst/work/vlg61/ps2.bin differ diff --git a/xilinx/scancode/_xmsgs/xst.xmsgs b/xilinx/scancode/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..636a3c2 --- /dev/null +++ b/xilinx/scancode/_xmsgs/xst.xmsgs @@ -0,0 +1,89 @@ + + + +Found 7-bit latch for signal <sc>. + + +Found 8-bit latch for signal <ascii>. + + +Input <ps2_clk> is never used. + + +Input <ps2_data> is never used. + + +Output <vga_hsync_n> is never assigned. + + +Output <vga_red0> is never assigned. + + +Output <vga_red1> is never assigned. + + +Output <vga_red2> is never assigned. + + +Output <vga_green0> is never assigned. + + +Output <vga_green1> is never assigned. + + +Output <vga_green2> is never assigned. + + +Input <clkb> is never used. + + +Output <vga_blue0> is never assigned. + + +Output <vga_blue1> is never assigned. + + +Output <vga_blue2> is never assigned. + + +Output <vga_vsync_n> is never assigned. + + +Signal <vsync> is never used or assigned. + + +Signal <kb_ascii_rdy> is assigned but never used. + + +Signal <hsync> is never used or assigned. + + +Signal <kb_release> is assigned but never used. + + +Signal <pixel> is never used or assigned. + + +FF/Latch <strobe_out> is unconnected in block <scancode_convert>. + + +FF/Latch <key_up> is unconnected in block <scancode_convert>. + + +FF/Latch <scancode_convert/strobe_out> is unconnected in block <fpga>. + + +FF/Latch <scancode_convert/key_up> is unconnected in block <fpga>. + + +HDL ADVISOR - A 2-bit shift register was found for signal <gray_cnt_FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + + diff --git a/xilinx/scancode/fpga.cmd_log b/xilinx/scancode/fpga.cmd_log new file mode 100644 index 0000000..dc5569a --- /dev/null +++ b/xilinx/scancode/fpga.cmd_log @@ -0,0 +1,10 @@ +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/scancode/scancode.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr diff --git a/xilinx/scancode/fpga.lso b/xilinx/scancode/fpga.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/xilinx/scancode/fpga.lso @@ -0,0 +1 @@ +work diff --git a/xilinx/scancode/fpga.ngc b/xilinx/scancode/fpga.ngc new file mode 100644 index 0000000..aacc0f9 --- /dev/null +++ b/xilinx/scancode/fpga.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4e 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4642ho0e4m50;9lg<<722wx=5a11394>{tn;0;6?uQf39>g152z\e5>;4:00h56*>038e7>h688097p}:9;296~X2127h97;;;%336?3?3g;;=7>4}r74>5<4sW?<70m;:468947c20o0(<>=:4:8j466281v8850;6xZ00<5j>19?5210f9=c=:;;315n5+11091==i99;1>6srb2f94?4=83:p(<><:`g8m`6<5j81945+1109a6=i99;1<6s|e383>6}Ym;16?7k?;01<,8:96h=4n022>4=z{l;1<7=t^d38977;9;%336?c43g;;=7<4}r326?6=:r7>6984=b09b1=#9981=5=z{8;;6=4={<1903=:k;0m>6*>038254=i99;1=6s|11d94?4|5;0?:63l2;d2?!77:3;:=6`>0081?xu4k3:18v3=:ed8966ih4=2f9g<=zuk9n;7>5b;294~\4m3;p>=4r$020>6>f3E;;57ot$530>6>f3-9o>7:<8:&0bco4n2d0>5=#<::1<6sf4583>>o3=3:17d=n:188k`7=83.oi7kn;ofg>2=6=50z&2465;h;e>5<5<3290;w)??3;12?l?b2900e4h50;9je3<722eh57>5;|q742<72?qU8=94=2g5>16<5=8=69>8;<1gg?`c3493>7=m;<1f3?5f3ty84:4?:3y]7=1<5:nh69:4}r32a?6=:r78hn4k2:?0<4<>m2wx=?=50;0x96bd2m>01>6>:8d8yv7503:1?v3;4m>0?963>2e8`=>{t;1:1<7;t=2g5>6`<5=8=6>66;<1;6?23349n;7:;;<1;5?e>3ty8i;4?:3y>7`0=m9168?854218yv5b=3:1>vP070=;>i0(<>=:2g7?k7793:0q~=j3;296~X4l=168?8536c8 4652:o?7c??1;38yv5b:3:1>vP070=;>30(<>=:2g7?k779380q~=j1;296~X4l?168?8536:8 4652:o?7c??1;18yv5b83:1>vP070=;>=0(<>=:2g7?k7793>0q~=kf;296~X4l1168?853648 4652:o?7c??1;78yv5cm3:1>vP070=;>?0(<>=:2g7?k7793<0q~=kd;296~X4lh168?853668 4652:o?7c??1;58yv5?>3:1>v3<838f0>;6:m0j:6*>0380<0=i99;1<6s|39694?4|5:296h<4=00g><`<,8:96>6:;o335?752z?0<7i46e:&247<40<1e==?52:p7c6=838p19<9:506?85b?3oi7)??2;1fb>h6880;7p}7}:<;<18?=4=2g4>`?<,8:96>ki;o335?752z?763<3:;16?h95e69'554=;ll0b<>>:39~w6cd2909w0:=6;615>;4m>0n:6*>0380ac=i99;1?6s|3d`94?4|5=8=697=jf:l244<33ty8il4?:3y>070=<8l01>k8:d68 4652:om7c??1;78yv5b13:1>v3;27875`=:;l=1i?5+11097``5<5s4>9:7:>d:?0a28=}ABA5{GHYqvLM \ No newline at end of file diff --git a/xilinx/scancode/fpga.prj b/xilinx/scancode/fpga.prj new file mode 100644 index 0000000..708126e --- /dev/null +++ b/xilinx/scancode/fpga.prj @@ -0,0 +1,2 @@ +verilog work "../../v/scancode.v" +verilog work "../../v/fpga3.v" diff --git a/xilinx/scancode/fpga.stx b/xilinx/scancode/fpga.stx new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/scancode/fpga.syr b/xilinx/scancode/fpga.syr new file mode 100644 index 0000000..856593a --- /dev/null +++ b/xilinx/scancode/fpga.syr @@ -0,0 +1,539 @@ +Release 8.2i - xst I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to ./xst/projnav.tmp +CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s + +--> +Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 0.00 s + +--> +Reading design: fpga.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpga.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "fpga" +Output Format : NGC +Target Device : xc2s200-5-fg256 + +---- Source Options +Top Module Name : fpga +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : YES +Resource Sharing : YES +Multiplier Style : lut +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100 +Add Generic Clock Buffer(BUFG) : 4 +Register Duplication : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +RTL Output : Yes +Global Optimization : AllClockNets +Write Timing Constraints : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : fpga.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../v/scancode.v" in library work +Compiling verilog include file "../../v/scancode_rom.v" +Module compiled +Compiling verilog file "../../v/fpga3.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"fpga.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library with parameters. + C_KEYRELEASE = "001000" + C_IDLE = "000010" + C_HOLD = "100000" + C_INIT = "000001" + C_KEYPRESS = "000100" + C_RELEASE = "010000" + +Analyzing hierarchy for module in library . + +Building hierarchy successfully finished. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + +Analyzing module in library . + C_INIT = 6'b000001 + C_IDLE = 6'b000010 + C_KEYPRESS = 6'b000100 + C_KEYRELEASE = 6'b001000 + C_RELEASE = 6'b010000 + C_HOLD = 6'b100000 +"../../v/scancode.v" line 129: Found Full Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "../../v/scancode_rom.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/scancode.v". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 13 | + | Inputs | 7 | + | Outputs | 6 | + | Clock | clock (rising_edge) | + | Reset | reset_n (negative) | + | Reset type | asynchronous | + | Reset State | 000001 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- +WARNING:Xst:737 - Found 7-bit latch for signal . +WARNING:Xst:737 - Found 8-bit latch for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 8-bit subtractor for signal <$addsub0000> created at line 184. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 6 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/fpga3.v". +WARNING:Xst:647 - Input is never used. +WARNING:Xst:647 - Input is never used. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:647 - Input is never used. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1306 - Output is never assigned. +WARNING:Xst:1780 - Signal is never used or assigned. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:1780 - Signal is never used or assigned. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:1780 - Signal is never used or assigned. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 4 | + | Inputs | 0 | + | Outputs | 2 | + | Clock | clka (rising_edge) | + | Reset | reset_n (negative) | + | Reset type | asynchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 3-bit up counter for signal . + Found 1-bit register for signal . + Found 8-bit up counter for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 2 Counter(s). + inferred 1 D-type flip-flop(s). +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 1 + 8-bit subtractor : 1 +# Counters : 2 + 3-bit up counter : 1 + 8-bit up counter : 1 +# Registers : 7 + 1-bit register : 7 +# Latches : 2 + 7-bit latch : 1 + 8-bit latch : 1 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 11 | 11 + 10 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with sequential encoding. +-------------------- + State | Encoding +-------------------- + 000001 | 000 + 000010 | 001 + 010000 | 010 + 001000 | 011 + 000100 | 100 + 100000 | 101 +-------------------- +Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx. +WARNING:Xst:1291 - FF/Latch is unconnected in block . +WARNING:Xst:1291 - FF/Latch is unconnected in block . + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# FSMs : 2 +# Adders/Subtractors : 1 + 8-bit subtractor : 1 +# Counters : 2 + 3-bit up counter : 1 + 8-bit up counter : 1 +# Registers : 12 + Flip-Flops : 12 +# Latches : 2 + 7-bit latch : 1 + 8-bit latch : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Mapping all equations... +WARNING:Xst:1291 - FF/Latch is unconnected in block . +WARNING:Xst:1291 - FF/Latch is unconnected in block . +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 4. + +Final Macro Processing ... + +Processing Unit : +INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 21 + Flip-Flops : 21 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : fpga.ngr +Top Level Output File Name : fpga +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 24 + +Cell Usage : +# BELS : 191 +# GND : 1 +# INV : 5 +# LUT1 : 7 +# LUT2 : 13 +# LUT3 : 22 +# LUT3_D : 1 +# LUT3_L : 2 +# LUT4 : 106 +# LUT4_D : 4 +# LUT4_L : 1 +# MUXCY : 7 +# MUXF5 : 14 +# VCC : 1 +# XORCY : 7 +# FlipFlops/Latches : 36 +# FDC : 5 +# FDCE : 12 +# FDE : 1 +# FDP : 3 +# LD : 8 +# LDE : 7 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 9 +# IBUF : 1 +# OBUF : 8 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200fg256-5 + + Number of Slices: 88 out of 2352 3% + Number of Slice Flip Flops: 28 out of 4704 0% + Number of 4 input LUTs: 161 out of 4704 3% + Number of IOs: 24 + Number of bonded IOBs: 10 out of 180 5% + IOB Flip Flops: 8 + Number of GCLKs: 1 out of 4 25% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +----------------------------------------------------------------+----------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +----------------------------------------------------------------+----------------------------------+-------+ +gray_cnt_FFd1 | NONE(kb_scancode_2) | 19 | +clka | BUFGP | 2 | +scancode_convert/strobe_out_set(scancode_convert/state_Out11:O) | NONE(*)(scancode_convert/ascii_0)| 8 | +scancode_convert/_cmp_eq0005(scancode_convert/state_FFd1-In21:O)| NONE(*)(scancode_convert/sc_3) | 7 | +----------------------------------------------------------------+----------------------------------+-------+ +(*) These 2 clock signal(s) are generated by combinatorial logic, +and XST is not able to identify which are the primary clock signals. +Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +-------------------------------------+------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +-------------------------------------+------------------------+-------+ +clk8_Aset_inv(clk8_Aset_inv1_INV_0:O)| NONE(kb_scancode_2) | 20 | +-------------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: 11.005ns (Maximum Frequency: 90.868MHz) + Minimum input arrival time before clock: 3.150ns + Maximum output required time after clock: 8.128ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'gray_cnt_FFd1' + Clock period: 11.005ns (frequency: 90.868MHz) + Total number of paths / destination ports: 260 / 31 +------------------------------------------------------------------------- +Delay: 11.005ns (Levels of Logic = 4) + Source: kb_scancode_2 (FF) + Destination: scancode_convert/state_FFd3 (FF) + Source Clock: gray_cnt_FFd1 rising + Destination Clock: gray_cnt_FFd1 rising + + Data Path: kb_scancode_2 to scancode_convert/state_FFd3 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDCE:C->Q 8 1.292 2.050 kb_scancode_2 (kb_scancode_2) + LUT4_D:I1->O 2 0.653 1.340 scancode_convert/_cmp_eq000211 (scancode_convert/N21) + LUT4:I0->O 3 0.653 1.480 scancode_convert/_cmp_eq0000 (scancode_convert/_cmp_eq0000) + MUXF5:S->O 1 0.981 1.150 scancode_convert/state_FFd3-In_SW0_SW0 (N1336) + LUT4:I1->O 1 0.653 0.000 scancode_convert/state_FFd3-In (scancode_convert/state_FFd3-In) + FDC:D 0.753 scancode_convert/state_FFd3 + ---------------------------------------- + Total 11.005ns (4.985ns logic, 6.020ns route) + (45.3% logic, 54.7% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'clka' + Clock period: 7.048ns (frequency: 141.884MHz) + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Delay: 7.048ns (Levels of Logic = 1) + Source: gray_cnt_FFd1 (FF) + Destination: gray_cnt_FFd2 (FF) + Source Clock: clka rising + Destination Clock: clka rising + + Data Path: gray_cnt_FFd1 to gray_cnt_FFd2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 20 1.292 3.200 gray_cnt_FFd1 (gray_cnt_FFd1) + INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In) + FDC:D 0.753 gray_cnt_FFd2 + ---------------------------------------- + Total 7.048ns (2.698ns logic, 4.350ns route) + (38.3% logic, 61.7% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd1' + Total number of paths / destination ports: 1 / 1 +------------------------------------------------------------------------- +Offset: 3.150ns (Levels of Logic = 1) + Source: reset_n (PAD) + Destination: kb_rdy (FF) + Destination Clock: gray_cnt_FFd1 rising + + Data Path: reset_n to kb_rdy + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 2 0.924 1.340 reset_n_IBUF (reset_n_IBUF) + FDE:CE 0.886 kb_rdy + ---------------------------------------- + Total 3.150ns (1.810ns logic, 1.340ns route) + (57.5% logic, 42.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'scancode_convert/strobe_out_set' + Total number of paths / destination ports: 8 / 8 +------------------------------------------------------------------------- +Offset: 8.128ns (Levels of Logic = 1) + Source: scancode_convert/ascii_7 (LATCH) + Destination: fpga_din_d0 (PAD) + Source Clock: scancode_convert/strobe_out_set falling + + Data Path: scancode_convert/ascii_7 to fpga_din_d0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + LD:G->Q 1 1.421 1.150 scancode_convert/ascii_7 (scancode_convert/ascii_7) + OBUF:I->O 5.557 fpga_din_d0_OBUF (fpga_din_d0) + ---------------------------------------- + Total 8.128ns (6.978ns logic, 1.150ns route) + (85.9% logic, 14.1% route) + +========================================================================= +CPU : 13.09 / 13.20 s | Elapsed : 14.00 / 14.00 s + +--> + + +Total memory usage is 245536 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 25 ( 0 filtered) +Number of infos : 2 ( 0 filtered) + diff --git a/xilinx/scancode/fpga.xst b/xilinx/scancode/fpga.xst new file mode 100644 index 0000000..5752522 --- /dev/null +++ b/xilinx/scancode/fpga.xst @@ -0,0 +1,54 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn fpga.prj +-ifmt mixed +-ofn fpga +-ofmt NGC +-p xc2s200-5-fg256 +-top fpga +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso fpga.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xilinx/scancode/fpga_summary.html b/xilinx/scancode/fpga_summary.html new file mode 100644 index 0000000..ae037df --- /dev/null +++ b/xilinx/scancode/fpga_summary.html @@ -0,0 +1,82 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SCANCODE Project Status
Project File:scancode.iseCurrent State:Synthesized
Module Name:fpga
  • Errors:
No Errors
Target Device:xc2s200-5fg256
  • Warnings:
25 Warnings
Product Version:ISE 8.2i
  • Updated:
Wed Dec 27 11:41:43 2006
+ 
+ + +
SCANCODE Partition Summary
No partition information was found.
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary (estimated values)
Logic UtilizationUsedAvailableUtilization
Number of Slices8823523%
Number of Slice Flip Flops2847040%
Number of 4 input LUTs16147043%
Number of bonded IOBs101805%
Number of GCLKs1425%
+ + 
+ + + + + + + + + +
Detailed Reports
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 27 11:41:42 2006025 Warnings2 Infos
Translation Report     
Map Report     
Place and Route Report     
Static Timing Report     
Bitgen Report     
+ 
+ + + +
Secondary Reports
Report NameStatusGenerated
Xplorer Report  
+ \ No newline at end of file diff --git a/xilinx/scancode/fpga_vhdl.prj b/xilinx/scancode/fpga_vhdl.prj new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/scancode/scancode.ise b/xilinx/scancode/scancode.ise new file mode 100644 index 0000000..3a4be83 Binary files /dev/null and b/xilinx/scancode/scancode.ise differ diff --git a/xilinx/scancode/scancode.ise_ISE_Backup b/xilinx/scancode/scancode.ise_ISE_Backup new file mode 100644 index 0000000..3a4be83 Binary files /dev/null and b/xilinx/scancode/scancode.ise_ISE_Backup differ diff --git a/xilinx/scancode/xst/work/hdllib.ref b/xilinx/scancode/xst/work/hdllib.ref new file mode 100644 index 0000000..3b0c382 --- /dev/null +++ b/xilinx/scancode/xst/work/hdllib.ref @@ -0,0 +1,4 @@ +MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167237688 +MO scancode_convert NULL ../../v/scancode.v vlg3C/scancode__convert.bin 1167237688 +MO fpga NULL ../../v/fpga3.v vlg22/fpga.bin 1167237688 +MO test NULL ../../v/scancode.v vlg34/test.bin 1167237381 diff --git a/xilinx/scancode/xst/work/vlg22/fpga.bin b/xilinx/scancode/xst/work/vlg22/fpga.bin new file mode 100644 index 0000000..d2e238a Binary files /dev/null and b/xilinx/scancode/xst/work/vlg22/fpga.bin differ diff --git a/xilinx/scancode/xst/work/vlg34/test.bin b/xilinx/scancode/xst/work/vlg34/test.bin new file mode 100644 index 0000000..120583f Binary files /dev/null and b/xilinx/scancode/xst/work/vlg34/test.bin differ diff --git a/xilinx/scancode/xst/work/vlg39/scancode__rom.bin b/xilinx/scancode/xst/work/vlg39/scancode__rom.bin new file mode 100644 index 0000000..4c4dc71 Binary files /dev/null and b/xilinx/scancode/xst/work/vlg39/scancode__rom.bin differ diff --git a/xilinx/scancode/xst/work/vlg3C/scancode__convert.bin b/xilinx/scancode/xst/work/vlg3C/scancode__convert.bin new file mode 100644 index 0000000..88932f2 Binary files /dev/null and b/xilinx/scancode/xst/work/vlg3C/scancode__convert.bin differ diff --git a/xilinx/scancode2/_xmsgs/xst.xmsgs b/xilinx/scancode2/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..eb7cf2d --- /dev/null +++ b/xilinx/scancode2/_xmsgs/xst.xmsgs @@ -0,0 +1,38 @@ + + + +"../../v/scancode2.v" line 63: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 69: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 75: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 80: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 87: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 92: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 93: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 101: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 109: Unsupported Event Control Statement. + + +"../../v/scancode2.v" line 110: Unsupported Event Control Statement. + + + diff --git a/xilinx/scancode2/fpga.cmd_log b/xilinx/scancode2/fpga.cmd_log new file mode 100644 index 0000000..af6dd89 --- /dev/null +++ b/xilinx/scancode2/fpga.cmd_log @@ -0,0 +1 @@ +xst -ise "/mwave/work/nt/xess/xilinx/scancode2/scancode2.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr diff --git a/xilinx/scancode2/fpga.lso b/xilinx/scancode2/fpga.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/xilinx/scancode2/fpga.lso @@ -0,0 +1 @@ +work diff --git a/xilinx/scancode2/fpga.prj b/xilinx/scancode2/fpga.prj new file mode 100644 index 0000000..8dadb84 --- /dev/null +++ b/xilinx/scancode2/fpga.prj @@ -0,0 +1,2 @@ +verilog work "../../v/scancode2.v" +verilog work "../../v/fpga3.v" diff --git a/xilinx/scancode2/fpga.syr b/xilinx/scancode2/fpga.syr new file mode 100644 index 0000000..e4b0584 --- /dev/null +++ b/xilinx/scancode2/fpga.syr @@ -0,0 +1,152 @@ +Release 8.2i - xst I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to ./xst/projnav.tmp +CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s + +--> +Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.09 s | Elapsed : 0.00 / 0.00 s + +--> +Reading design: fpga.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpga.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "fpga" +Output Format : NGC +Target Device : xc2s200-5-fg256 + +---- Source Options +Top Module Name : fpga +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : YES +Resource Sharing : YES +Multiplier Style : lut +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100 +Add Generic Clock Buffer(BUFG) : 4 +Register Duplication : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +RTL Output : Yes +Global Optimization : AllClockNets +Write Timing Constraints : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : fpga.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../v/scancode2.v" in library work +Compiling verilog include file "../../v/scancode_rom.v" +Module compiled +Module compiled +Compiling verilog file "../../v/fpga3.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"fpga.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Building hierarchy successfully finished. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + +Analyzing module in library . +ERROR:Xst:850 - "../../v/scancode2.v" line 63: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 69: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 75: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 80: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 87: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 92: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 93: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 101: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 109: Unsupported Event Control Statement. +ERROR:Xst:850 - "../../v/scancode2.v" line 110: Unsupported Event Control Statement. + +Found 10 error(s). Aborting synthesis. +--> + + +Total memory usage is 216028 kilobytes + +Number of errors : 10 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/xilinx/scancode2/fpga.xst b/xilinx/scancode2/fpga.xst new file mode 100644 index 0000000..5752522 --- /dev/null +++ b/xilinx/scancode2/fpga.xst @@ -0,0 +1,54 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn fpga.prj +-ifmt mixed +-ofn fpga +-ofmt NGC +-p xc2s200-5-fg256 +-top fpga +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso fpga.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xilinx/scancode2/fpga_summary.html b/xilinx/scancode2/fpga_summary.html new file mode 100644 index 0000000..3fe30d2 --- /dev/null +++ b/xilinx/scancode2/fpga_summary.html @@ -0,0 +1,53 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SCANCODE2 Project Status
Project File:scancode2.iseCurrent State:Synthesized
Module Name:fpga
  • Errors:
10 Errors
Target Device:xc2s200-5fg256
  • Warnings:
No Warnings
Product Version:ISE 8.2i
  • Updated:
Wed Dec 27 11:33:33 2006
+ 
+ + +
SCANCODE2 Partition Summary
No partition information was found.
+ + + 
+ + + + + + + + + +
Detailed Reports
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentWed Dec 27 11:33:31 200610 Errors00
Translation Report     
Map Report     
Place and Route Report     
Static Timing Report     
Bitgen Report     
+ 
+ + + +
Secondary Reports
Report NameStatusGenerated
Xplorer Report  
+ \ No newline at end of file diff --git a/xilinx/scancode2/fpga_vhdl.prj b/xilinx/scancode2/fpga_vhdl.prj new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/scancode2/scancode2.ise b/xilinx/scancode2/scancode2.ise new file mode 100644 index 0000000..7a917de Binary files /dev/null and b/xilinx/scancode2/scancode2.ise differ diff --git a/xilinx/scancode2/scancode2.ise_ISE_Backup b/xilinx/scancode2/scancode2.ise_ISE_Backup new file mode 100644 index 0000000..7a917de Binary files /dev/null and b/xilinx/scancode2/scancode2.ise_ISE_Backup differ diff --git a/xilinx/scancode2/xst/work/hdllib.ref b/xilinx/scancode2/xst/work/hdllib.ref new file mode 100644 index 0000000..b6dc48f --- /dev/null +++ b/xilinx/scancode2/xst/work/hdllib.ref @@ -0,0 +1,4 @@ +MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167237210 +MO scancode_convert NULL ../../v/scancode2.v vlg3C/scancode__convert.bin 1167237210 +MO fpga NULL ../../v/fpga3.v vlg22/fpga.bin 1167237210 +MO test NULL ../../v/scancode2.v vlg34/test.bin 1167237210 diff --git a/xilinx/scancode2/xst/work/vlg22/fpga.bin b/xilinx/scancode2/xst/work/vlg22/fpga.bin new file mode 100644 index 0000000..be15cb3 Binary files /dev/null and b/xilinx/scancode2/xst/work/vlg22/fpga.bin differ diff --git a/xilinx/scancode2/xst/work/vlg34/test.bin b/xilinx/scancode2/xst/work/vlg34/test.bin new file mode 100644 index 0000000..9afc57e Binary files /dev/null and b/xilinx/scancode2/xst/work/vlg34/test.bin differ diff --git a/xilinx/scancode2/xst/work/vlg39/scancode__rom.bin b/xilinx/scancode2/xst/work/vlg39/scancode__rom.bin new file mode 100644 index 0000000..3308d70 Binary files /dev/null and b/xilinx/scancode2/xst/work/vlg39/scancode__rom.bin differ diff --git a/xilinx/scancode2/xst/work/vlg3C/scancode__convert.bin b/xilinx/scancode2/xst/work/vlg3C/scancode__convert.bin new file mode 100644 index 0000000..32ca8d4 Binary files /dev/null and b/xilinx/scancode2/xst/work/vlg3C/scancode__convert.bin differ diff --git a/xilinx/vga/__ISE_repository_vga.ise_.lock b/xilinx/vga/__ISE_repository_vga.ise_.lock new file mode 100644 index 0000000..a407a06 Binary files /dev/null and b/xilinx/vga/__ISE_repository_vga.ise_.lock differ diff --git a/xilinx/vga/_ngo/netlist.lst b/xilinx/vga/_ngo/netlist.lst new file mode 100644 index 0000000..5c279cc --- /dev/null +++ b/xilinx/vga/_ngo/netlist.lst @@ -0,0 +1,2 @@ +/mwave/work/nt/xess/xilinx/vga/fpga.ngc 1167708110 +OK diff --git a/xilinx/vga/_xmsgs/bitgen.xmsgs b/xilinx/vga/_xmsgs/bitgen.xmsgs new file mode 100644 index 0000000..f8f4393 --- /dev/null +++ b/xilinx/vga/_xmsgs/bitgen.xmsgs @@ -0,0 +1,11 @@ + + + +Gated clock. Clock net vga/crt/_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. + + + diff --git a/xilinx/vga/_xmsgs/map.xmsgs b/xilinx/vga/_xmsgs/map.xmsgs new file mode 100644 index 0000000..59d1227 --- /dev/null +++ b/xilinx/vga/_xmsgs/map.xmsgs @@ -0,0 +1,45 @@ + + + +No environment variables are currently set. + + +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic. + + +Clock buffer is designated to drive clock loads. BUFG symbol "gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1) has a mix of clock and non-clock loads. The non-clock loads are: +Pin D of gray_cnt_FFd2 + + +Clock buffer is designated to drive clock loads. BUFG symbol "vga/crtclk_BUFG" (output signal=vga/crtclk) has a mix of clock and non-clock loads. The non-clock loads are: +Pin D of vga/crtclk + + +The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing. + vga/crt/Madd_ram_addr_Madd_cy<7> + vga/crt/Madd_ram_addr_Madd_cy<8> + + +The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing. + vga/Madd_ram_addr_video_Madd_cy<7> + vga/Madd_ram_addr_video_Madd_cy<8> + + +The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing. + vga/vgacore/Mcount_hcnt_cy<0> + vga/vgacore/Mcount_hcnt_cy<1> + + +The following adjacent carry multiplexers occupy different slice components. The resulting carry chain will have suboptimal timing. + vga/vgacore/Mcount_vcnt_cy<0> + vga/vgacore/Mcount_vcnt_cy<1> + + +Gated clock. Clock net vga/crt/_or0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. + + + diff --git a/xilinx/vga/_xmsgs/netgen.xmsgs b/xilinx/vga/_xmsgs/netgen.xmsgs new file mode 100644 index 0000000..2bf02be --- /dev/null +++ b/xilinx/vga/_xmsgs/netgen.xmsgs @@ -0,0 +1,11 @@ + + + +The generated Verilog netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM simulation library for correct compilation and simulation. + + + diff --git a/xilinx/vga/_xmsgs/ngdbuild.xmsgs b/xilinx/vga/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..db7765f --- /dev/null +++ b/xilinx/vga/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,29 @@ + + + +On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem8", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. + + +On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem11", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. + + +On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem21", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. + + +On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem31", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. + + +On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem41", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. + + +On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem51", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. + + +On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem61", the following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be used. + + + diff --git a/xilinx/vga/_xmsgs/par.xmsgs b/xilinx/vga/_xmsgs/par.xmsgs new file mode 100644 index 0000000..ef7b527 --- /dev/null +++ b/xilinx/vga/_xmsgs/par.xmsgs @@ -0,0 +1,13 @@ + + + +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". + + +N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. + + diff --git a/xilinx/vga/_xmsgs/trce.xmsgs b/xilinx/vga/_xmsgs/trce.xmsgs new file mode 100644 index 0000000..b1a4b30 --- /dev/null +++ b/xilinx/vga/_xmsgs/trce.xmsgs @@ -0,0 +1,12 @@ + + + +No timing constraints found, doing default enumeration. + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + + diff --git a/xilinx/vga/_xmsgs/xst.xmsgs b/xilinx/vga/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..8ce0f2e --- /dev/null +++ b/xilinx/vga/_xmsgs/xst.xmsgs @@ -0,0 +1,89 @@ + + + +Signal <keyrel_r> is assigned but never used. + + +Signal <keyrel_x> is used but never assigned. Tied to value 0. + + +Signal <printable> is assigned but never used. + + +Signal <clr_offset> is assigned but never used. + + +Found 1-bit latch for signal <ram_wclk>. + + +HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. + + +Signal <rom_addr_char<7>> is assigned but never used. + + +Signal <resetVGA> is assigned but never used. + + +Signal <done> is assigned but never used. + + +Signal <kb_bsy> is assigned but never used. + + +Signal <hloc<2:0>> is assigned but never used. + + +Signal <vloc<9>> is assigned but never used. + + +HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + + +FF/Latch <rom_addr_char_7> is unconnected in block <vga>. + + +The FF/Latch <pixelData_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <pixelData_1> <pixelData_2> <pixelData_3> <pixelData_4> <pixelData_5> <pixelData_6> <pixelData_7> <pixelData_8> + + +FF/Latch <enable> is unconnected in block <vgacore>. + + +FF/Latch <done> is unconnected in block <crt>. + + +Unit <vgacore>: instances <Mcompar__cmp_lt0000>, <Mcompar__cmp_ge0001> of unit <LPM_COMPARE_1> and unit <LPM_COMPARE_6> are dual, second instance is removed + + +FF/Latch <inst_Mram_mem71> is unconnected in block <vga>. + + +FF/Latch <vga/crt_data_7> is unconnected in block <fpga>. + + +FF/Latch <vga/crt/ram_data_7> is unconnected in block <fpga>. + + +FF/Latch <vga/crt/done> is unconnected in block <fpga>. + + +FF/Latch <vga/vgacore/enable> is unconnected in block <fpga>. + + +FF/Latch <vga/scancode_convert/ascii_7> is unconnected in block <fpga>. + + +HDL ADVISOR - A 2-bit shift register was found for signal <vga/ps2/ps2_clk_r_1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. + + +HDL ADVISOR - A 3-bit shift register was found for signal <vga/ps2/sc_r_7> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + + diff --git a/xilinx/vga/fpga.bgn b/xilinx/vga/fpga.bgn new file mode 100644 index 0000000..868f66c --- /dev/null +++ b/xilinx/vga/fpga.bgn @@ -0,0 +1,104 @@ +Release 8.2i - Bitgen I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +Loading device for application Rf_Device from file 'v200.nph' in environment +/opt/Xilinx. + "fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5 +Opened constraints file fpga.pcf. + +Mon Jan 1 22:22:58 2007 + +bitgen -intstyle ise -w -g DebugBitstream:No -g Binary:no -g Gclkdel0:11111 -g Gclkdel1:11111 -g Gclkdel2:11111 -g Gclkdel3:11111 -g ConfigRate:4 -g CclkPin:PullUp -g M0Pin:PullUp -g M1Pin:PullUp -g M2Pin:PullUp -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GSR_cycle:6 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:No -g DriveDone:No fpga.ncd + +Summary of Bitgen Options: ++----------------------+----------------------+ +| Option Name | Current Setting | ++----------------------+----------------------+ +| Compress | (Not Specified)* | ++----------------------+----------------------+ +| Readback | (Not Specified)* | ++----------------------+----------------------+ +| DebugBitstream | No** | ++----------------------+----------------------+ +| ConfigRate | 4** | ++----------------------+----------------------+ +| StartupClk | Cclk** | ++----------------------+----------------------+ +| CclkPin | Pullup** | ++----------------------+----------------------+ +| DonePin | Pullup** | ++----------------------+----------------------+ +| M0Pin | Pullup** | ++----------------------+----------------------+ +| M1Pin | Pullup** | ++----------------------+----------------------+ +| M2Pin | Pullup** | ++----------------------+----------------------+ +| ProgPin | Pullup** | ++----------------------+----------------------+ +| TckPin | Pullup** | ++----------------------+----------------------+ +| TdiPin | Pullup** | ++----------------------+----------------------+ +| TdoPin | Pullup | ++----------------------+----------------------+ +| TmsPin | Pullup** | ++----------------------+----------------------+ +| UnusedPin | Pulldown** | ++----------------------+----------------------+ +| GSR_cycle | 6** | ++----------------------+----------------------+ +| GWE_cycle | 6** | ++----------------------+----------------------+ +| GTS_cycle | 5** | ++----------------------+----------------------+ +| LCK_cycle | NoWait** | ++----------------------+----------------------+ +| DONE_cycle | 4** | ++----------------------+----------------------+ +| Persist | No* | ++----------------------+----------------------+ +| DriveDone | No** | ++----------------------+----------------------+ +| DonePipe | No** | ++----------------------+----------------------+ +| Security | None** | ++----------------------+----------------------+ +| UserID | 0xFFFFFFFF** | ++----------------------+----------------------+ +| Gclkdel0 | 11111** | ++----------------------+----------------------+ +| Gclkdel1 | 11111** | ++----------------------+----------------------+ +| Gclkdel2 | 11111** | ++----------------------+----------------------+ +| Gclkdel3 | 11111** | ++----------------------+----------------------+ +| ActiveReconfig | No* | ++----------------------+----------------------+ +| ActivateGclk | No* | ++----------------------+----------------------+ +| PartialMask0 | (Not Specified)* | ++----------------------+----------------------+ +| PartialMask1 | (Not Specified)* | ++----------------------+----------------------+ +| PartialGclk | (Not Specified)* | ++----------------------+----------------------+ +| PartialLeft | (Not Specified)* | ++----------------------+----------------------+ +| PartialRight | (Not Specified)* | ++----------------------+----------------------+ +| IEEE1532 | No* | ++----------------------+----------------------+ +| Binary | No** | ++----------------------+----------------------+ + * Default setting. + ** The specified setting matches the default setting. + +Running DRC. +WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced + by a combinatorial pin. This is not good design practice. Use the CE pin to + control the loading of data into the flip-flop. +DRC detected 0 errors and 1 warnings. +Creating bit map... +Saving bit stream in "fpga.bit". +Bitstream generation is complete. diff --git a/xilinx/vga/fpga.bit b/xilinx/vga/fpga.bit new file mode 100644 index 0000000..3905beb Binary files /dev/null and b/xilinx/vga/fpga.bit differ diff --git a/xilinx/vga/fpga.bld b/xilinx/vga/fpga.bld new file mode 100644 index 0000000..d072ea1 --- /dev/null +++ b/xilinx/vga/fpga.bld @@ -0,0 +1,66 @@ +Release 8.2i ngdbuild I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Command Line: ngdbuild -ise /mwave/work/nt/xess/xilinx/vga/vga.ise -intstyle ise +-dd _ngo -nt timestamp -uc /mwave/work/nt/xess/v/fpga.ucf -p xc2s200-fg256-5 +fpga.ngc fpga.ngd + +Reading NGO file '/mwave/work/nt/xess/xilinx/vga/fpga.ngc' ... + +Applying constraints in "/mwave/work/nt/xess/v/fpga.ucf" to the design... + +Checking timing specifications ... +Checking Partitions ... +Checking expanded design ... +INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem8", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem11", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem21", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem31", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem41", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem51", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. +INFO:NgdBuild:526 - On the RAMB4_S1_S1 symbol "vga/inst_Mram_mem61", the + following properties are undefined: INIT_00, INIT_01, INIT_02, INIT_03, + INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, + INIT_0C, INIT_0D, INIT_0E, INIT_0F. A default value of all zeroes will be + used. + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 242404 kilobytes + +Writing NGD file "fpga.ngd" ... + +Writing NGDBUILD log file "fpga.bld"... diff --git a/xilinx/vga/fpga.cmd_log b/xilinx/vga/fpga.cmd_log new file mode 100644 index 0000000..cfa5d61 --- /dev/null +++ b/xilinx/vga/fpga.cmd_log @@ -0,0 +1,516 @@ +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +netgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim fpga.ngc fpga_synthesis.v +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +netgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -s 5 -pcf fpga.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim fpga.ncd fpga_timesim.v +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd +xst -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -ifn fpga.xst -ofn fpga.syr +ngdbuild -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -dd _ngo -nt timestamp -uc "/mwave/work/nt/xess/v/fpga.ucf" -p xc2s200-fg256-5 "fpga.ngc" fpga.ngd +map -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd fpga.pcf +par -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -w -intstyle ise -ol std -t 1 fpga_map.ncd fpga.ncd fpga.pcf +trce -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -e 3 -l 3 -s 5 -xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf +bitgen -ise "/mwave/work/nt/xess/xilinx/vga/vga.ise" -intstyle ise -f fpga.ut fpga.ncd diff --git a/xilinx/vga/fpga.drc b/xilinx/vga/fpga.drc new file mode 100644 index 0000000..dc0a21b --- /dev/null +++ b/xilinx/vga/fpga.drc @@ -0,0 +1,4 @@ +WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced + by a combinatorial pin. This is not good design practice. Use the CE pin to + control the loading of data into the flip-flop. +DRC detected 0 errors and 1 warnings. diff --git a/xilinx/vga/fpga.lso b/xilinx/vga/fpga.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/xilinx/vga/fpga.lso @@ -0,0 +1 @@ +work diff --git a/xilinx/vga/fpga.ncd b/xilinx/vga/fpga.ncd new file mode 100644 index 0000000..6f8c79c --- /dev/null +++ b/xilinx/vga/fpga.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4 +###5252:XlxV32DM 3ff5 146ceNqVW21v2zgS/iv9sF/PEV9ESuVhAUu2VaOJlXWcNvkkOHFS9G6bFmlvsYfrj78hh7I5I2mTBWKSM89wXimKtJFfHuT9/4Rwv2wf/vj8/fPXp7dvxEzYN79I94/8wZ3V51W3FVktstlVxmiR0oLhguGS4ZLhiuGK4ZrhmuGG0ZbJAy0OJ9q7Q8kUVZTUVFhTNKdoTlFDUUNRS1HmZEHRckCeIhasQoJVSLAKCVYhwSokWIUEq4hgFQA6Z/PNkD4FJ2gFAplqk4bCakCmujRFNUVziuYUZYaYl5ailqIFRcsBeQpJsgJJViDJCiRZgSQrkGQFkuwRkqxgkj1CkhVE1kydZOqkGdJE3jLcMpwkS9KKSlpRSWsmac0krZmsWSCWopaiJUXLFFU1ybliNVOsRorVRLGaKFYTxWqiWE0Ue6gUPlSJe3JAptKSWZPMmmTWJLMmc4bnDDcMNwy3DLcMLxheMLyk4akBmUorVgvFaqdYbRTLluL6NF0KjDTUGTsgU+GCouWAPAlrv+YySp7c0riEElgOyFSaLgHNloBmS0CzJaDZEtCspJqVVLOSalZSzUqqazUgU2mVUW0qY7hgOMsVLblmJdeh5BmjCc6yQ5eEpkXXtMqBTIVZ5KToOS16IFNUUlRSVFGUBJGzJOYsiTlLYs6SmLMk5iyJOUtazpKGNMFzhucMNzQcS8liQKapIEk2NI2GptHQNBqaRkPTaFiaDEuTYWkyLE2GrTXD0mZY2gxLm2FpMyxtJqSN0JbJWxqtpdEWAzIVLlNdlr0GLXutWZYry3JjWW4sy41lubEsN5blxrLcWJYbi0uK0QS3DCe5svS4YWnqbM2EyY5XsNgLFnvBYi9Y7AWLvWCxFyz2gsVesNgLFltBz8oFja2omXBBURJqyU5DJTuxliz0koVeslBLut3KjDygkt7KJL07IXm0Jdl1SAr6GpX0YC/pwV7So7tkR3cZj+qHE20GpEhIS1FL0fRRk+zEKdmJM9IipRXD0/pKRfY8qahr9BQj6SlG0mMLkifLmnmm6VlYauaZpmfdSBN9xBlNk6qp5/RVjORJV85s5/Tc7WnNcM1wy/CC0jIb0ul8SRYIfWMjKRLSUNQOyJNqw9JuWNoNC9WwUA29p0eayFuGM/s0dMNCNyx0+pZFUiSkpqgZkKmwpailKHmQ2Dsr0iKlBcMFwyXDJcMVwxXDNcM1w3OG5ww3DDcMtwy3DC8YXlBcsvxIlh/J8iNZfiQprK2HpEhITVE7IFNhUskCI72PNL0AaXS7B/HgTKgjFg6HGaGONg1m9wRKIkrVKIIpgmmCpa+zWFBKpqilqE30WuKPJf5Y4o8l/oSDTIKlFgtc4AnJUEvR1J+iplPDUqJkIqsIlRPKJP4FKsEswaj99DJV4qNOyRQVFBUUlRSVFFUUzQdkKmwoaamwpWiZhFfW1KykAZGElqTgJUlvSQpekmSXJNklSXZJkl2SZJfhEEioBKNR+LKU7qypz99X16vsNEy4Kg4v5wth3ZnvMtMPbByIIg5UHge6l9G9jIkD2UMy13FgVBzY46CHbBkHRdYPeqjo9ZRxoLKsH8RZSkR/lDQmDApz586284tKd9uszk6ESAmZEioldErkKWHqTDj4E9KJDD6+l/BR8NHwyeFj4GPhU8CnFA5gCaISRKUfg6gEUQmiEkQliEoQlSCqlFMzkFMgr4RwWrhcOCOcFa4QrpRuDugctMxBy1znbr5YbOcGuyz2UEHss34gIiJjr2KvY5/H3sTexr6IfYmGKiSraKiKhqreUNUbqqKhKhqqoqEqGqqioSoaqqKhqoSgq/O2fg/pPusHEPKANx9jVilzuZl3l+3H5ZYyq8jUJ+b2ajfvmm17vVkwdtWz1Yn9cXnkZq66Xp8vut182yyhqd+BqRv43Bauevj9+5tspiAjfvi2n98do7ITwHwSqQbIKcgh0kdaMiQNdwQ7RlcwLAk8R8jvGOsWuNB3fkPJKN9vCPLE6upldCmZf5y8Wm4fkO2nLpbn89v7E71erRJ0vYEJjye6vd4BIxEHy1H86nwNZqvbjNGidxYZtfiwoFNqNqWGKYIyLq5vViO85j5lraihVQ4SjGWA9Ug48w11ZrW6YfQtMdKQ6Q1Mp4zNYsUZdApETxk37XbFGQ34Xc8X3Yf18mP3Ybm9Wrcb6eqlcvXaD94r37xdb9a7n765eXvefnx7Pt/V77p2C06/hb+r203dzXe77du5H/78ySbdvmqSPMCkv2HkJP86/Sqblg/jkSkOVrL2zTy0Venq9uJivdstF8CANWpdvV3OgQTk65dvYX94wOHxMdtH2j8Wh2QMqzrO8gv8Lg5DaYSDV6Bb/O0UusVawQe8hSYLLTyZvs2wi5TETmGnscuDvAytCq0OLfJNaG1oi9CW3lTlh1UwVQXlFZqqRKQkdgo7jV1QWQVTVTBVBVMV8oOpKpiqgqnKm2p9VG2Iqg1RtRhVi1G1GFWLUbUYVYtRtSGqNkTVhqjaOfJNaG1oi9AGUz6qNkTVhqhajKrFqFqMqsWoWoyqxajaEFUbompDVG2F/GAqRNWGqFofFez2vqmEW0m3gq11BSeBFTw/KzhPrGDiKl9vhGukawBsAGwAbPTB+RV0dtx+M6STnTeyYGUduXdHDmymNhCwhEHVeVvNz7vztlnXGSVhL1xrt4aXnnKwLqVbb4CEBQnHgLA4Vyu/AKv2BtfgW9jVPT+synfr5h1bs/BM5S9PHK718Pgmu9CI6pHH4dH93Y0rMXL794288il9ePUMnOAz9vPnz9L50oXXqA1DSBnywstzH4b43kTcn7Hd+jfjztv5YrnYu4v5ZXfRLq7Pl4cw3q0vlnB0uLi8C2Tc/5W72H/L3UZkGtbvRtg8tLByN7KEg7Nvu2/7+393cJXayM7CpSq+CN1GyUJhp7HLsTPYlaErM9/BkRg7GzqhsMuxQ6YU2CFTGuwiVmAXdIIa7FCLwgkKMY1aNDJzlMyRmeOEPGKoOsd5BilT3mMXow5MGzt1jx3BUJnF6QUyMS8KE6IKdL5EqsTASpxQRiw4obMMO4GdxE5hp7HLsTPYWewK7FCLQC0CtQjUginXArVg5rVALVgALVCLQC0StWBVtEQtErVI1IKl0lgqjaXSWCqNpdJYKq1Qi0ItWDitUAvWT2P9tMYJWEatcYLGCRonYG21RrMazWo0q1FLjvOw4DrHeVh3naMk1l0btGdQxKCIQdW4JrTBCRYlcTFoi6otbM8b1cnjc4GkimSDpO5J5TZa730T15BnGM8wkQFPns1saMu70J4kS7n3zUmyhIXnNsvdx3b7XrhWudYf52Bf0L7JQgvu+jbDLlISO4Wdxi4P8jK0KrQ6tMg3obWhLUJbGnc5r98vF8qF7xXc5eIKbzvd5fm8Xl4sN7vHhHl9NW+WD4EBPncX86vdcvt4pOFysltv4PjdM3a3l8s9Us2iWy9Q9HJx0e9e8JoMnPWmm19drZsN6LyECHvm8ma33MBuGDRBvjw/nH7hAN1V680CzMFb78j2Zvw2nIp+qOujaJ6w0YPOXxtj5IS/XXkl7+EmFPzaNBfdVXu9rZePngtksh8Dw+dx9257Dejz1x9f/fFQZLNm5m+pJ46SM7jX+KgZa5bBDfLIlLqY4VVmFkpOEX9X8B5z3kwkxqXlxqW1s4oajywwnsqVYubvZ3LAmolUDl4FPJjIosEgcywYj/Bgeh4JRpnZarZIGDrzjHSemSW32xHuTEzwZaLWYHkE58yyVCif4V2UcWh2gOdvfWl2IotmG5nNUK6ZUUcgif6OTGKOPJIrUwxiKIYxlAOhMlZuyBMjPJlWGBZRvD3N/CF+CqnEfgyZz/BLsmIc9Jed0XnVDL/zKsZBf3MpxyG/s/qH+4Sdvscxo+yZmALkFKCmAD0F5FOA4c5W485WU85WU85WU85WU85WU85WR2cJkH7bVUwAsOomITENyWlITUN6GsqnoWFU1VRU1XRU1XRU1XRU1XRU1XRU1XRU1SmqPIWSbxjtOJ/u7AQRk4icRNQkoieRfBIx6b5qs8H+G1mzbIwpxphyjKnGmHqMmY8xzRjTDl1vhnLNmOvNmOvNmOvNmOvNmOvNmOvNmOsNc10Msy7Gsi76rKeT1XCyGpusxkqmxkqm+pINzDRDuWbMTDNmphkz0zAzehiNjtEkb2Kb8zcxcsAXw3jHI1RGgHCCkgMWy60ZemNGjiPIbIZyDZOzQ312TJ8d6rNj+oqhvmKs9sXYwimGRoqxihZ9Rd1vym2XH7Tze3xoK+mustKFW94ZnIlPQ3EXh+Gs1fPrkwic/e6PQ/+bBKEaG6lV0Q/EcSSPI3Uc6d5e+KniSPgfKfY9Md8cHVmtbk7D295Y06trjsaao7HmaKzRvUr/m8VxDBlOxk0/9suqH/vfJ5Jxz+9WZ/64dhzLZKyScW+3axL5JpFvEnkYayjPVridcrsabqC745XUXwwfAx0vavGmyDhwdQ2/RCL7g9fqb2xwnX2kvO3uQBgXsNAS+upyuVxElr+gri8uwcX1DrXsyM12118pgwPn6+oKvN+ulfu4nPsGltzHK+FupLupxMHdrM/Xm5t/3CyqN3DmfnO1u8bB/Kper0HmN+NuDnfd+nAH/Zeu+vx0+Pz0CXzx1MX+X1+fPzw8+/9W7Fmfn04sdyvdLRi8/U27+9//vd+H1n/P3Fw+JuMz34KChLP2Xe4eP8ncaPf47dPehrY7wLKPg64N32MiJXu2JGzVsxVh656tCTvv2Tlhm55tCNv2bBvYd5H6/NQd/DaTUAGP0l/232ZPn74c3Kfn/X+7+6cf3Wp1EA+U9Ns/YYS00DkSFhyhj9/4fNs/F+7b5z8ffv9n8at1377LDlJ76Aez+DtrJDuf6yJQh/2P/cNxhHKHIx0ErXt++P7wo3u67wdx/new+mP/JCGUPz7tzy72h0P3vP/SQf/c/fH58PC1FhD80wHujS8IwBVqSkLCczuNyWwajNn5C/fUS+5Fgb9QoV9SEQXgyZuSQIGHF/DpFG3/IkWASTUFdoF3/99/iuxXKV+Uyl8jZF4jZH+V+SuEuucfr1BWvMZi+avUfy30+39+hDyol8XyV0mZV0nZV0kVr5J6Ocg/vz6HIF8jJl606cXMq6Tsq6SKV0mVsMF5oU0WHwkYCLk/DdVdMoZ9PyHyA6HMAyX9V/aU0e8h2YkfWdEJkRX9oHcHRsmw98wPwbP/A5cs9kg=###3548:XlxV32DM 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c98eNq1WkuP3LgR/jM+jEcX8aE3DGgWm2AXyGYD7ywQ5GBDT2Au3gBBggSj4W8PH6IkUiySGnf7MN1dXV+x+FWxqqj28pffn7/++vnrL3/6peZvlx8/PTywJ/Qo/uLHJ/oxeeCv/ANJGP/E/3HB+rX8Skofnwj/ZiFjs0TZY1JfWWLayMclwwG8wCmHnsjjyR8pFcLDGh8XWlwwmhxtWhtfyBBjaXVA4hOJX+G0ioGzHa/3tMkOm5rfaavdbQnfNIncYhm0SN00McvWkhXRpphly7FlHVTpJI61bCWY9E/HIWBkw7c7fczOBTrEGNFH47A5VwpzcyjSXLubs2kPJfqeQI9WXmw+6UTvYUvHiFw/Jmc006dEw/F8Af6EA7EwiLZKhXUUtlgU7zDHzNITzQQzqTAS1VdO3XCTSYKu4JniMhj6xEGldVy3tCZ50JpNwNpJ0BWgcj2cte2JbS6LzHlmpi2XCeRakBeaX0PD3Wp8l6EEKusXt8WMghtMYDd6T8D8MnwNf3EZuAYixmNmx1G3ynD6M6iWHPO/vUI+syrpgfz8MnpNRv/hsRrS1o/YhZMLd6FA+T4CE+XuJYSMEskiEXY6pxdwaincxUGEdqhqmeMEiwoWs6LlLBqBYDEzWodgxQNtJstLQKO/D5FQCQh1Y8eIC/Z1/B2WNqq9Rzp5OHcJgdQXnDA6cTX0qHkgcXVT42gS7Mczu6uSsMtAMdmC3cWh1fHx749Bk/S2WB+JV6t5XWu3Om6WOT1royDYbhOn27I/s1v74LNzl48r1i07V2udEcVVYNxsaSF1by5jMafU9d1O94ro42rrbN4sIYcyoIZKT7ViEXchHIafB9kpAGKBK1TQ6cDgMV+En2o8qa5bSFj4IRI7jy/nKhDY/KEMCLLxGKuu+hEuYvS5anAjdsOxNxJIg8R5EZUPQDSTXdCAWeL2BuQvDQ7wHn3vFUan6qPrAm3eIrcpmpLr9g7POnTrjfGKwRXfV2PNRm2Nt3SKAAYeKJiX6vGiQXvoK6/jdUaRa9B1hAtQ5x/htpR8j6HWbcjXvZg5amxx9Nc0cnzYeuVJDC9CVg0Iz4oW5vBcdu9yXRitk9vXpTblU0v21FkDtKYOzoLqct7EeVBvHUzhy5yqpPtU+xieRo+Q9ebn4Z+eTwYKa5/mefggMiPEh9FRs9lHQPcbdpT2lg0kQvucDkUYtQZu8GhS+MGWXghMpC2JRKYshLr0jOLg+I0BSOvzDww6EOAqR7OA08eJUemh2aOnzkfq0VAE+xY7TA3exdrgYm1oMWYykIf0Vq/cieTIuQhNXUu9TiaRTh6pCxpMogzugffu5dhMFtQBmiLpoXRMHtYEStQQm/nU2K4HmovKbmt2Admwb2lgZibBY5AcjoHH+WOIMp9a+Ggmus56tseMxzNgCBMRQmiddjuVELyV8B74kslv3VBJKsAEWx9kiVir9d1XA+b7PcI7RDOgKLPQbYTB43LLriCZsxP0fqTxoykwQ/n/68IlUOABKgN+zfVF9TgVA9nLzj0KI5+iryucnpICZe/4RHKrHalHc+1WJahyah3Yq8o855k5qnzpVzx2Iu/C6uIBnOF1BF4QGH95xMG0Tczrwjq/5KB2TFtmjuINRipUvZlRTEtQ5RRMr6pJP/KqqpWxV2cNERSERAUBsHF0fEGuBpW6xWhBriP1BMnxglyRZQLg/gLLhf/26+fnp69Pz8+fa5pW+d/Rsol/MMX8lrAstMLi5ee//vz8NU3r9Dv/1coQupUhfCtD5FaG6K0MZbcylN/KUHErQ+WtDFW3MtTdylB/K0PDrQyNtzI03crQ/N2G3tr2n3mRo6Zt/0txVv+5zmr0+hsmpMbdWOOqqBHBZBrzuhhH8vqNor5GDX8Zatp8oKiqKSqaN45ALkTR/IY7rkN4FI7ysZEIWz4NbvlMm1G4x2U+97hD/Ejwstt8QDN3kObNN9z1Nc2qapgn1HzAXSfF/M0g4M0HkmG+XN7855lQXGOxQJ3h0b/IXKNh5FjaqTc0VavxN309poN4wxfCgiKeN2Jh7r1Q/UYyov3Bzf9IhmoyleJNKt/8ROjU/IOitMavmNAazXP91q9754703Kmpf32hlNfH+ieaTs2/CeV7SZvmhZLJIaTIIcTpSfjHKLqALaSEujSdwtwlLM/CYR5cwskFT12auUvoXKhz2XQIKc5dwtIldMIHl3By8Zm6hGfmexVNnkZ1/srTqKgxKUXO8aToOh5C0djq5oXgWb1Kw80Lrkr5SmU4+GfphfgsYtb8gatcvXZSLyGUiFe+nLAj/Ehf5Sq4IzxdacXXnRvlAM9sbr+SeEJEXjVvfVnyylhnRyA9AAnN+BnqtYVReFSunq0ekk5ZHPt1B52yTGlqu5Qpy/ysaoOTwyVFHToCCwWkdFQujQitFlC6kfD2L0oKseTrJ7Er7mjzhfMn5DQ7yKuu+cL55PKyzHc53wDX70qpnyq5oJX713wSEu6gXGPevxMiZZR08jvhOXmV6grHJdy95ov48yZqQS7TghcrOy2q8g5pgQUh5EhlvsYgSxWVE+50MOZTMF4o0kGRjjuDkvVrUHg0HUEpK7wSxp0RpHzhuxNkSYtEySWRQmKSVYJkVfcgqwLJQhfJKkGyBi9ZnTw9kqzKJKvUZFWarNIiqwPJukfBwT1IFr5IVgeSNQbIqjRZvUlWp8nqNVmdRdYAktXfg6wRJItcJGsAyZoCZJWarNEka9BkjZqswSJrAska7kHWDJJFL5IFNpJsDpBVaLJmkyxd4PGsybIKvNy9m6zxHn0fgWRl18iSnjjJytMAWbnuiMggS1okSq7I4hKTLAySNd2DLAKSlV8kC4NkoQBZmSaLmGRhTRbRZGGTLHkVEBNlcZoo71GzKAYmSiLywTNRdj0wURKdSLga3jdREnCiJN6JUlLnnign70RZlnSdEPmuuIN8QqxKY9KUcsekKeT7pLmyKSZDvE6NQkFOjWWHdowxhZIds06hRE+hckdy0iT6O2SdLQqdre4uhSiDzha9WogoWLVDhajXZyszzxbVZyvTZ4saZKlLqZusO4zlwwyO5XS4RJZy3E1W4SWLklGRJZw5kKUsEiWXZAmJSRY4lvOTfgeywLFcXwejyYLH8jKWrMokq9RkVZoscyxXzyvcZGW3J2tMwbGc6ut8h2PIUo67yeq8ZA3joMgSzhzIUhaJkkuyhMTMLJgs9D1k/R8eAiyH###2848:XlxV32DM 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Z2blsvykQN7F1V/hrFy44ypcFRRUX7jwEAnYKyZv3zM96bMHT5q8HE2W1RQ0VYdZCk9Z4lTQVC/Gc71BU+GYJdCZWXCMrlwjVe4kRFO2zmzKZH3mZuZgcrFf09PEyl+Vp7jxG5nTmdXjxdlXlhyzUNCRkiQYnyz4qpKeyYtFk48vx7vNuC308aMXbcvIoyzOH8+J4BMfgtRV1X6k2zVk2oayWZ35ukZTe2vYo89GgBSllfkGHVl6DYfGw7q19AZNo6BZ2NC2H2cjGipqVB1uuwkqckjFIfi2X8oNkPP0QWkdB+x7ERhPpwpyyMkhJ67xyq6CHLJ0+ynqaredi3l1Tr5urw9XfW6nnR8O6FGjR40NNTbU2DT42ZRtghoFV0Ib3AkFVGV74YkMGhc9cbETF7t+VGU3hZlzSv5xyF5FpX6uJMXBSsiTPDxJv5McO5FQIMdOTa27OtfJhvFOtpNkO8mxU4PeK21O0uYkW05y4yQlTlLiJBNO8t4k3U3S3STLTXLaJJVNUtkkg03y1SRNTdLUZKk7S91JOJng0Kn75fzlb/tdjbqoRIlJgRSOH22S1eT7pBol+o+2gmvL/buf7d0mQ7k5L+hP1cJTuWt/j1MnwNCEopmWO/US89srd2bp5JGOjCfJIpARBolgEPZlRCkTFK0093aPY2DFth04LdqFbMwKRL35xHJiObDYeEIyESoQnmRTDnxaqUE+AYQnFZ4qWCwmKJCaIgX6BPp4LJ53XTx1MR6HxdHnZDzMIh1YDvzUoo2CZWlYGhbGHMu7Mlp9Mk1MMCaaEhamE5lOZDoLyOCDFQkKlsXCTkDegW/NBr41GwI8wWO5sFxsQWILEiJpn8y5Fnx9VVtqNw1fQRPgCyyeQvQr7xC3M3gCNBJ3sB8vLJeUMKpJtnsuYblu8N2+T6xtnUgvLznwMc89kXYSnRzH9j/J7uP3c0y3olp+Y6AjqDYB+bGBWWyUnc+SFDT9+YFZLPd0yoz1gwQJN52U0+1++Xn9Ja+P+np9/jo1xOvrI2Dw+gi137+kDQGCoFHjdfxp1KMJYHFkh+9XjPBEhEYgiIBOIPCAQSCIgEEgiIBJIIgAYb4vwgdOlXGqdONmpEO+yKBAXkFkDoRTjREBMIgRETCIEQHQSM8RsMNHBDSiRgJ0okYEdKJGAHSihgcMokYADKJGAAyiRgBMokYEDMJHImpEwCRqRMAkakTAIGpEQCdqJEAjakTAIGpEwCBqRMAgakTAIEYkwLSfc3yCRSRGbDCIER6wz4k7Ruyo0fGjsX+B3nEDKY2P++3GE/fhx0MfhxTHWHfZ/wPaG7I8###6472:XlxV32DM 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10a8eNqNW0va5aYO3BJgjKGzjrsAjPEws4zyZe/Xv6XCpg706c6guyIdWwi9ELKx5vpT9qOc1x8bzY3XcBw/uCbBmzv2N2Z+pp/2yD/49Mb9YLsf8Y2/0bM7tvt591Ov/70d9efvJZ/u52+8fzOC8X5vz+VP6Hi/L6e/ob4f+Bsd8q3bad/yeXfeesur4C2McZNvgqMRecN6lrc8Wzn3ER3ygc78TIf8aTvjW37nTLz1r/KuYYwhL/BWRB6XTPoTOuRz2eQfnOqRbrmTYKZDflfG/EzH+pbTbD948bo/q1l+MK+XMeQv2RwjDPlmOGWRryRTRrjZfzX7CDd/mODrNff6ttPUGwfBebfrzZ+Ffwk2jfwJ9C2IPtieQS+1t3fYC+imiv2Bbo96vOmxCub9AH0Pul+0HtDPYCWeZIlHaxF5eT+hH1v690GechzhXn+onb+A31qxT4P4Qvwcf5if6RwPZvYH+n///b2e2/HL/Er//r349Munv/5ZfPzl/vrf4rdftiz/Lm6JS74sf5M3yF4CY+ew8g9LiGoJcWIJUSTj54F+GLEE0NkSrBFLYPlAT0Y0ncrEEmLz7LElRLEE7NwR1NOIH54EOvPDk4GZn+mrEctLSZ4fFo0UWSIF0xenO7uIPpm/OrJk4oe8oQo/6wuWuSid+WGZ0UkmZf6P9xE/7//HfrdIdG4jOt63VrFs5p/Jx/zJa+Yke/3GD7wXG9+RDf6A39tqO32Dn+msP/HU+vLUrfNU9+Op/vovu012+ooR/r3yvUoNwvjQN6VQ6wi3nTY1jXDSHLDu6nn6fF/755kg8jDG85Y6xlcO6ywD67NOdgY1QslnGuEnh47xk0PHODrJobvtLfGKTNuf0KEfWOqyivxLMbdl8Hp4/77RWd+gn05qHuDDWT/C0IczYqmtBlLM9FbzTPiZjvXns+FDa6Ybsz5m+uH1AEO+3ZnzjnyoUdMduL/SIf9arR1hrGeGYZ/IBLzelgmzZMI0q4myZsI8yYRO/SFMMqHTTMj+iEzoNBPWSSZETZwnmTD369/qpcpX5Mbz2hlA6cwP/cdk1hE/01tmdMaP7IPpzf+iZhbWN9Gb/ybRf8vM+jym8/uYXyL1+YrUax+p9ztSL0tGTm6eoNXaZTdDjNMxS1J1JUyHZKAzP9OTl5XiNN08uQr+Si+9pj/Wt+jO1TG+IplEuqg7NcOmRb4OP+uTSPisT/A3ei6yvsNWqiGkGv9Gh+fYTegf6ze6n8sYX+wS2YxGOsLIbJebnu/9BGY61jfjh/wzfqZf+99HOvX8fFCkKxrpyiTSaQ2a4iTSeY10fhLp/DnUd4t0XiNdnkQ6nOb9JNKVPtItoY+MHOlAZ37oG5j5eX+ZH88rUSqRD30QvVUuE9wqH8XsXx90fT7842O/iM7+1E67VTM/2Us77VbbRW7wo7JZNHMzP+uP+e9IHM0rEi+T0+22aJ/ESZ8jaKQrWr0zbp5vbBhh7BRqgFh7T4iUM/H+S3/rTdf3ZSuKZdxOD/E0I9xqAN0pfn6L3PEMI4ydhqXx74HrnTce+c9c8+/4QW99zVj3EYb+/KJ9k0X7Hl5qBH5/jIeasNANDKOKfhnz82bPhz3wfrZIVyXS8f62SFc10oVJpNMzEOu7RbqgkY71gUgXJNLFWU1XJZLEWU1HNW10gpmf9cH8LVM40d/MvrFfzC+eal+eantPTbenrkuOVB0DQ3PAblXNEH9aNEaRJLhRYAzNY2exU6zJ61/uzc87UUy/E5Cv7WTs5f2whCiWEGeng9jnTLbEaNQSteO5296SvRFLbpEsquXTeqE/tgTww5Oc0dMB8ZtS7whVl97zwL8Z8mTmx+krap+K9J20RluT6p/4P+Rj/on8bC/XaW6oz6ynhSVZN+QnfTC/X9Eh1hsXsgeWh/nFk9zjScvZe9J5edKy2CvnJfVpozsdekmATZJsO6MfqZ3rO/7mSb6ng5/pMfSaTJPevHHy/jjzNKeeps+7DlH9OTirp03uFmxWT5vFbO27gP7haU48jdfTPM2pp6mlWY2BvB9XEBXLt72ngP/w5CnMjz5dEctnfV36HXoK+Pl9zM/6ZX3BMl2VmoTpWO/FtY74mQ5cjXriRH+g43mmqifRfn/jhz6us3EZ2SOqXdCZn/eT+dl+gLE/zbOD5lSi8/OZXyLB8ooERx8J6h0JzJVTKcYDw3LXQzUV+xh4+Zkd4ev3XZ+AceP3/d0DcKSODSy35Xw6B7F8UW9poz27arN47eh+o/M5Sy3tqlaG+phiI5Y7w8bIChm3atyNccTdzNFXx5AvZvJUxbgF/0Zv1bjrz6HAkc7Be6FIdGq1XbT6Jszyfuh3U8vOYtmMm70U8jzF3+y5RWKv1fukIxthj36SCXQqI876FEUzCe8XMlHpa76PTOZV37Oa00smFE/3j6evru84LrenX9XzTvfhwHgy7oeD6ztGJvd3AcCb13OT5nzGiHnW9XcFwMmNawYftVr6Qt9VM3mT5+20k7zeUzukSTtA+67rneDn7oPmQ8yY/tx9jPmZ/rEftJ52TnNyS7hPLHXRmmOfdNSi1iz7xFJLlpyH32+LntPhKVoz7ZN5is3162FL3fWciI52XIWf7Y33h/kZ26T85uS+SBqtFx1svqvbqWO2m9Zx6/iZ3u6WFGM9Wx7TWV7mf+4OpYO2TzpuoLe7hwludxWK8b6rBh7SZ/KBn+2D5ZNItL4ikelrjnyf48OS6yq9PF/7XnMyY7xTrzbT/X+mDgyeH6rcyjQcRNOMn3Ma3UIrznTu5ue3jkYe492Qp096z7sXT2H+5mmaE7Dede1PNx6TSJN5mYJJvEkfIWLScNLRWjQn7mESqbzt5kF2LzUF77er6slWPZn4j9pHgm/8s/3wmBL4Yh/M//Q1JPPwemf2C/7Wd8gyJcH7hd9HmrIA/8xewS+eFl4ds9rn/HrfMl6ehlu2oL3IJfYztoxbjjf9LSPwdQ4Zztxe5w77J/SsfQCpvV6a97pT3+ndTp5Znh9Prb61mlyizMQxfu6bxxh9is32MTeX1lv/LT3TObed+zzpU3GYzDDP6MDQzwz7dHY5IWQpw7/RWx9gghGZWo1l+kjD9KzVb04UKYJOSk36KAtmRCd9mKjzQfz+1wzp/t4P7gN5zIhOJgM3zIiWSaQO1DvPegtL/JgfwKQe8+P0c3g9vTC/RrqqdOY3u94y534SD/zs/8yfecaV+Jv/gZ/0hdOri/1kIPhZ3hl/KBopab+Sdg+CrV3NBn6mw54v9d3PCduhnfOaRnSOH8yfsp5pdp2qIH72Z+ZnfTI/2wv7i0T67RXpSx/pjzvSX6c7b3Xm0/SW4DGTShiTeGeVcyTjeup9dBVPZYwaApJehoWZ034+JdD8iWJ8TfCRKbxmEqI/HeMxP9Mz3YVAP8gEkOcKJd3XDsBMz6af/2B+prdq3fc5HjhT9Qz5vOm/zrh+JRailoXTyDd6O634vsYF/kbPdHri/WV5Wb/f6LBHO8GH1jyHTsMzbmeEIp7MGPoNq5xW2D+gP1/HOEaRB32y5+sW7cgS/fnaRejMz/RMHd1EM9qs75n+sR7GwdEMOWGsN4W+2wPcIqVi3FXx5OSM/lQOfaYEznTLnCe31LvO4LO+Xt8Q5Pc3Bthv0Ff9BiBPuh+H0Uph0j1JOl+WJ3eri37DwPHw9Q3BM8Md4yuS5z6Sb3efLi35aKcLmmYP9N2aYkwmtZpM+1iu9NP2V4noRpjfN3v/5XfbCGeaScV3NTwZdmbRBMv7zMiqJicd16QzsHkyA3s43Uncda19x3XVGdg8O13rDGyenc7JkpNXy2d+ojdPmeDmeYrXMvFU0HXSz+l3bszP+8/86LO1SMP2srf5Ef/+Toon33Y6PQMjc/Mk6ozeKgP9OoPlYTrv74e9INJ4ySTf6O0MNMF4P7A/NZOV39O9fh3C/Lw+5n++gZA+94c/Md33ffIZxt1960vH/vczeutzK4Y9mfB7erNP4pdImF6RMPZ9wv3uE25Pn7DWfp4iaQ3KGJEFmjradzS9ZvHFK+PMp1czjmwtcmkkDRqJ+X1THLTGIfx8VzXGmKlt80yK3akzyGX8tQy+MGV5Z/JbrYEYtz5VGeNMUwbo47XTpU7vhwlmeWfyr74/0wCzvczsZy/9d3rAyCz8hetHJtAZ4TyZQtkwY0z70zKR7zPRRybzksl4P58ZZ82EZpJJS/81yUcmLu+aJL88MUymBFATWJ1ZvA7oQfpgNY/wU+21c/RzTv8/yk3phQ==###4584:XlxV32DM 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11d0eNqNW0u65iiu3BIvY1y9jrsADHjYsx7V13u/HEvBMWGc1Tn5MzJkG6SQENh5XZc9a7r6n5jb8fMLfKS237+53v8ebUtLPtX7d/ct//zWrcbbrl3X035La3xEub6dytt6/y0aE0z/w/f7xPEKT3w1c/xcj+f5ZPIKH06e7y+zK64/2BWz/eDzrPKkIuNhzOP9Gj/GcxR5Xq72vr/NMp6r2XTz7A/lfTP+5oPw237ZJ3/o/HH/Y7/Sk++jOFfxAr/Fds+b/QF+b+ovvf9+mfbkz2bt0785mmtl/xUf2AOf7TpW8+F4f9njeS9/q/2eLnfbsz+ZV/0H212ywLAPedYfjw/8f//77+1K51/mr+Pvf/tw/BXCv/7jQ/rL/ev/fNj/cpv/23u/+9xHdj/JH9Zp5CUTj9vRhvnxJGP9CiPy+RJPAENpwCPyl2SCDcLnTZR/ZvE043LW8id82ZqfuCv9/k32yv8LPyqPKplxj8ykFNdkfF2X22o+X9gUjRzhkAVXK5nCGPNtsbUVxvy+MObzhbOZlTrwJZnMPDKZM7UYydRXvJXvZejOdL7/qBRJK0X+qDRJ4sHjGZUqaaVK60rXy+ZSr+D736bKsWM+NF/Ol5c98YjHUaQSMUY8gaPXlSBLJWPeO9WfF/2xfW3zSsP2GG9JspK84kU8xvuFMT5gzg/meXxsL5WsPCqZmytZuCtZ9LkLRpSwSawHVmWkUC9dU+M9077Y3DCvsfWyxvZFdlvhrDV6O2ZPdWXH/4XHGgxPp481rzhVUvzIJCeZxPMfmZQlk9LXmp2vpb9GJumacpiPTHKaSe4jk9ycSUcW5b7mS3xOc+YAYyV68VBiNOfK/hU/sj9OrZS3Ln9x1+smGTNfz/ajx9CVhf0NPZz2mnpc2IPHSsT2yLTdaeUjex4P2w//usus4j0qkfJsz/74su/Pqyu9YLxxu8rKnnme3++eQHtY0lsuYp8PO+Ub7JnH+HuTdefjWVQPp9yPedYL20ulqo9KZaZKZdtdqUzvudx6DYVSgN05d8sjM1WJEUrXkfkolYIxZlKdzIQxPPWFoeTT2qkSuiaVLFVVntHM2bSSlrmSwj4WqsRkz9hdinW+jNkfL/+oksphygqPNc6ZusLIFFSqlz9Q6YJUupQ/KmWYK+Wr0moPyHoYlbpoD0r6GJW+tCnzXitFmFeK10oT5t3VmbUnMOueADwqbTq0sqZ55WOe9cD2j93RufIH643tR0+bjVvGg3g8/zwkPl/zAS+Z3n4z3bc502vPdOcP30u71ogsSqxprhmMR+YFykTFKczKy4d6Is2ecM7YFYZyhyc0EmfTmdJ4GY9znDIrBThRd5y+dgdamTCel1KjKlWvt5WU3malvzKlqXK+dgdNMu3lD2RqlEizv0emx7mn2bJJq/lkt1Y27F/+J3vTpNK1ba6ksK9mrqQve33eVVqRXpH8SXzW3TB2m8BZD8JePPRnpCd42ZM+2f41/w8923zFVbxf9/uwHystXS+ZfD0y+Zx3F/Zes73P8ZSZcbfnAmWaYigHykqJdiNpHgnuP7pNzKTITBjz9fBkzboPpPF+YTzvC3dl5BUeJ5ylnSuM+ftNlGWyKtPPSsZ4GWPfjBrMeJzj4IQUa1KZ96VffKJ9Lsb7qlRJK9XXOYae8PJ8wUeju6+0rlTdK+dKH+D7Zig8/fmqVEkrVfuoVIl2X3pu8Jov8Uejcw2Nj8G5BvFmr1qI5h4M9hx/tj8TVTLWi46vN7fbar6onOawYWX/eyIv55Rsf5T1OSfsX/Mn+7uSHKZXkk0qyXVMlaT0QmJ7U5A3PWjrjs7iBymVMQt+8afyZc33tVBK8Qduu+DoJLAvbOSVy88u7saXHNDYL16Pns8mjnvZE/+7jZyP3oGrLklGhcj+2LFd1QNDth+Jqi0I++ug6yVQtgcqSKBsXQfqzE1OaA8ReHDtroz+lAofnE5EFbEnrdCbDGzDwHQtfvFFu1Yvwmd75sdaia6XsDcyvrOuMc8HuB0yny8eXe+XPfgQ5Xk9n/3SX1lwL592ZW/UHiezEij3yKg8d9n2jtT+m1J9v3j3DZcXide2xpB001rOuPSqI5GV/R9jSL5LbImNmyNtgnalGlnmfZG3QPsp4zNBcI9sWl0/1h6VuKXrgXG9v2RN6fvhtLJnPm6aQopbE/+eds2z/9ke99/U//7j+eBxf+C+UZT7+TX/ij/Zi5J8V5LXlL8mJSX3t08+I6E3rRRIWLgdCbrLcdn14jVhO52eCQ175pHAIckBIGMk8Lat8UhAPSBkjASsXuxfWBPSJDlgEzeF38p4zc1wvfPN/+SbxG8r2C8LDtsalyLxRaVgHLPYoxK87q89UWxrnDbB3XHSa31hI/dlnJPuji7dBRHeY7N/wuOkMK7x2GV9YOR3uHRpJn8E+FMrI9uPXjMIlkBuv3p3dgrk0fV+/Ord4VWbxTGQDOuFm7asVQ+EGau+XdVjTMLjo4Vy7Su8BSmzvTNc4uqae+rbe9V7ET3/E2/TrH/Goa3yIT7yoUxuPO98sD7vRVuMIitbaYL3bY17fbqeKynjw4g9Vs7X/bVFOtoa90IgbxAuPY+V+A7MPM7TAs7byJ75cd4W17hFnDKoEGg+Ef7QToDtx94oyP0kEPtDz34KxN71vP/qOeswUZ+hP8aot0eeDyOAneoh1zXORRsiK1ty6M3p4cM/8b3tCPLva3w1wTEJFjekR0M0d67W3IKMPx91iIPxUhUC7A3HEkOAY3NNGAGspx4I8/1VoHipzLiV+X6M9/QP91eB+7bGEHS/LDwFD8w8BG2NfpRC9syPV3VYqQnXjAN5/XwIx4paGf+JH5v9gFetsz+QMD1b1v5yMy9KOR4Js/2p4Yn6rQQSBMN64UgJFdcFPqW5wANvSQp6Ote4RSngSBjGSKDeHy/xrgUdCcQYO4w5ofKjwM/n+PnOJ+Oz13igIekbAuwxl7hGwWhwGDu9HxZ4FEB0iuNwp6ztfRaMhiB4BFJeaPD9mIfe92uNkS/AyDc0XMy//EP24ujzocf9TwXc6rSgv0QNNzAKtm3S5zH2Gm/n17howcUbZ8bQ1270esJR9XWca4wGu6q9uKE8CnhaHz0EzW9saOBPbGAZZ90QHVk2oC+sh7ZH1U8nCB/6GuELO7ww1c8bGY/DVn3VPg5bFf8jj08RvN6P8DjMLHI4MY7z9TVKTPOGl/lAG2L2L9tLoOrjjGg+emh3oILPrkiEcXKQLm05nb55JGxqw3epS9x70DCfoegW04ijkAHbJo7BFtPoScKL1xa87PMW1tAZFPhxCh/0lJswz5dxdjL+8eb3A483qx94vIkl3FeEyT8vf+X5DOllry3VfMb08yY3aGXytFQWF35iffxEuxb5cgTrUfCCa9ANCvFHlqgZjw2JyLdvSKqmz82fEWV2xuP+aY3xZctYFoykazhkPapZ01nr0dE0nbX+uSIY9Y5xiXT9Jc+Hmvvz79+xjBA2ej9Ej3HQ8WH8fby3f7K/9F2QYHzrmYqtT745wV98bxwmvmn5iPoO5dIv07K2eczXOPMh2fLkbREM3js58h7xUDy+Nc36JZGOL0TBGJ/the7G48BGMDakhnjXZv5Ks//6/fPz/sy7PPM2ip5w/1hUX3g+8Vsgvtj21MsV1f+6/u1BMPiUZz6lmc9t5n1Wf+v4rcYD46+q17Fvhh51n8n8Vmb+zBIvxDdp/BBfXA8+6/Xgc9UvywrWf40vxq/fU8F/u8Yf/nP6fMzfK8b1RusJnu/U/3i+Vb2AR/yHfinfTtQL1adrs35TnPXL9aDo/DG+rlf3jA/uj/hAP4/4pSeP/Br5H+z55M9iT3r++Xx+Rbw8vtVX/+H5Zfa/b7P/cT14XA8+h5mHPsAX/UoH9T5p/H3S/yvgZn4nvteT6f6hzfcPND4fZ57Xl4D8/o1PnPSBegT9pJnHeMHzeuO0K4E+en3Zn7z54nX+qC+Yf0rzermZmTdh5qF/8LzeGuJLEn8h/+G/kf8aP/BJ8TinovUJ6wevP4hP1vqH+JyqZ/i3j++P6wfiD/+hfoz6TesH189K9XWHnuFffR78w/1CTnN+o/7AP/A//GNVT7h+d3P9a8hnrF86/y/9Yn3D9X09l+OjYx0v9EcGeiN77l/Ynus32/f5yPst5dneVhk//q8Q9zNnFPvxBTTZ8/0+7fWLbtZjX7/+aP+6P9kH7afwxTXrGfyX/Qm97TM/vuh+P/+P9tzPHfp9Lfpb7tcw34T4kf1XvGBfrejR53W/53U8o78me54P21+76Fl35696wDyPf9PttjFzfznemxHP+gY+9Iv7vr5uf4oP2w+s5/Jcj5hnfR0ar/FFP/WzL57y40gzz/0w86z/Q/t5jIf7YeZZH5jPuD/1wzxftkc+j/Hz9ZTvbM964n76lT+0HpQd/xNC9qu8f33tT8me6x/bs7+gZ2DsT/GFCffjzPN+lvevzPN42B754dvI16nfr0l4zjfYM8/58dp/034B9iVo/0b7AeZZPxgPnsf7BR4P25/af2F8vJ941WeyR3y3j/0G83L9/wMTVSOz###4152:XlxV32DM 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116ceNqNW0u25KgO3BI/Y1y9jrcAwHjYsx716b0/MqWgTCS+WTW5FUcyHyECCZRXSiaa/q+Z87z6v1wE13LWF4Y8b2e7Y2ebeeHNreXZvZu7ymnMSv/YWnjhkK7y7pf02972F3bG2Bc+a0sv7Itgc7Z4l7M+t8/6wCmL/IiC43bJvLNge8h4rqTyt/an/Gk8e7jeEzO1He9+imCWc//VyPizfZv12lrb3v/xrd3nc5jLrPTLLvqxipz1//vv7+0q5pf55f/924fjlw/5r398SL/cX//zYf9l3b/e+hyi9hvETtYIPtWu0o793Y51+9RO7O1En3MW/0rhirLO4i+bW+PQmn+P97i2FW5ecGgyDsbeiz2OusZnUnv5NTZpNU/X52mjTNSFaZ6b8f/65I3PR9GuokxluEYTPFy1reV9qd+ubq1OlfRZXrLg6K93v7tOtZtStpa6RjvENZ8wXJnx2QTD9VsWF4Ordrvbd79qWpbv6nIw7aCKIFSwBXWNw2wr3NxMTZeOB67E9mbM9mA8XCOs8UWuwbhVwXAVbLnNN2mvCU6pLeXOzfKaW73LT9fqJHezvORZjvadb+e9/y0JvgLZU3EzehSQvU8zy3k9YxaM+bM/5iD4SII33Vr4fqOtFuss9yT3RIVbEOySUmWd5cHM8hplPoPKk87XqH9Hsafx13vctQr2SXCpou+9+ptSW0zqb2G2v8uz/VOb7QeM+fF+Czo/jA98sT/YqxbB8G/WP7IeDUXGy/of+4v086Z+ma59ZS+W9yMkv/WsUn0TXDaldpJzf6wP/rBZ5bQeLombgx9Z/wgiT/7aVvqH2jOea/0P+5B+n4e57wvwo3e6X2k+rA/+9Fb0mC++6aei+96s+YTlcdPvFX/0T/LxvVvz0dB3a322B+ujf2OlXeYzlvN4Ox9Pct6PLOfx8PnEfOlPDWUzhb6B5DhfSJ/96UOfzlPmi6z+02eTV/q8nz/09XyDPvMxf8/6Qfcb4gPm07HfqsQXrM/zZf2S5lCW+f5DruPLOJcu3Y/YfyTn/cr64MvO+211nnD/rC+hor+FxCYuQ2LEcUHWL1yCXVxjtwtuTnmLMOJEhLgj5Edc9kV+VgqJ6zrumUPicJ/nOc3z6PM8ejys8YTvOcp7fYust3nAPSN6YxdMWuIoof62GbfCrWgqkDTVIjz8OQsuOG8Rz36RAycr+4nx5ii+IXyZlR23WyqWZju6bkfns3VzKtb5TPzuAVdNKed+Yu8naz+uzP2knsKEVwoTmw3vUM+KSXOWzYuUwZ6Ce1JvV/Ia7f6TPstDtO+lRXYfvehjyfD9pSHFWeX7YiXkYDlwrdfxkz7kTeWnF9xnfb1TkWr8+68X14xtjesm+p3g3/jowcQdf5P7at92NkXwR/9G8GtxVjhmWa/oZb0YX876u70Zb6fdpNsH3Gyc1of84zoFB73NYIz2oq5nj2EE65b6Ji9B+h/ZOdnnPAW7vMY83g9M/sb42m1+r5tTebblPr5v8tP2w+0lj0qthFOz531+bG8XraZeervE/ppk/5gkFNSSyEd7QeQjRasyv3Ebpbib7VyNJxvBIwUjf41GcDeqX+3nUAVj/LyeuxOM9lOS8Yz1p/GyvVk/eJn/OPrIHuxfrC9UuXeqPECVRMnHmypfF2TZvJc6afRyNMG7X+PqZOfjopMxhgKqZIytAtyPHcEaXX2TH2l2rRqk/+o1OitCTbg4ZRz1e1fW+IrSH05Dxp1xpqVn+7nDvLdGj5aXuGQZr/75wJvOB9QGqm1Rtvo3eSHXzk3sj/G3OG+985L5wD5Yr31E3/P3T3K4IuuzHP2PaJ3WD+37MPsPMI4+4L7Vj7t/sHzgrLclpI+tF46r3Y/WoU/yauat/LH+u673A+b5Mub1YNz9sZC/TriPd6JuxqDu3cxUDtyp8bzrM97DTK3sbynOVMr7dTN0FJA/ukxHAfnLHuejgPfjUWcq5vUyQagXR8XHfNJ8VAiVpt/RbTDXKrp1TuyI6LYdgqtb4x5yLvo5bv1Ys3rQuHQ90E9xq3byfbx1Nd7SxC/GeHcd3wNOy/GWez/zERPc64QZ421Vs5dom673Em9m9jfGldaL8bG0R71lJ+1aZbOdLsJ9nPsmvF/yGlsnfmTsGvtOgBMvFplnirgV/ll+unlejBHizPM8bw88Pm8PLzzNyVyz5GMjfA1hjcHBTzhq+DZeWKyE53pR9Ts8NmtsNVzE9z3dkfHZWX/Lc//ALAeHP+mz3IZ5/DbJWvZ8tclLzHxmMEY4t+l8GO8aTkOf8YVwG/aj9emHabifQYyz2muEl1nsD3nnuEnO9mX9JzzSBcJof7woxVnuWE7+sR+qH9fYND1TMH/CmxM80gGyH9oLeY2dm9tjnKl9th/7y4f/uDmGYAx/SZpu7mmdnj3KnWC2P9rn9fjwryh4FAMoRoz5TZ6VOxEDwD8gh72vIDEq4x6jTDHEpv5d6no/fMjJnz7wgz3GetP+4PZ5vRnXU9rb9TqGMfippAes/IcY6KP/NvbPEsPeNz6Zr0u+yHdavw/7erXnAx78+4AH/z7gwccPuOl+AT/yeQOMF0bmw13tdYv5Jnl2s7yoP44YQ68HcNbyeWGof/an8ND/eHGAf+O8oPUI4Hsz9td0XliNPccLMNkL1yOQ2zj37zP1T3y9wT46f+ZzT3I+z3H9g/aZrzfNIWAf5tud5Mx3JQhG/8xHOc72Y76pdc5ZeD8eer2DnIT3E68n+C2ZkVNM/sRyg++Vn4HHeUfyD/4mfT4/eb0lVmz32D0+5BrHnQdck3MI6yjtXPd2jlUO4I18h3bSptfX7QHn+XxkXNOc0zG+3Hwd+B5nfRWLbcgB5lzl8q/5bj7vmj0iC9gOvXh/wGCy2JQ53Hzb8U1+cXZL/Vdks3aNW54vAhlHuqjk/mKds2nWP+hiM2a9uCzjonuyNJg75nGRPOmzfNhHsdFsHivN8q2o/R/0P9aP9MUTbuV+Pev8KTse7VyaLbc1PtvK49w9m99WWWcPId7M7YIwS7TSrn/CGvnhdi1SJPhNPi6eA11EK66RdhbhttxZ/j7PmUm2Ps/tPc90ZwCvDxTpAY9bODBCfbile5CfdOvzgfNqHq+34IDySL592cLLMw7vfUaFjynjBVVeTjc5LxijQmjcoRKuSfDvl2t9Ib/0Bb/o7g6Cz4C7vHau5MA2i/xJH3Kjz0SoMEEFoo8yvlEhoPEqY7zMP+HxkqvnKSomkP+nwBUYTe/WpeKuOK3k0Yo8tj8qPqzmc4wx3mDWGBVoI17x0p/Rir9qpfg5tAec5orBQ4uOzaH+EcSeeL59wqPCjLDTChJUiF3az6WVSzGIv2B9WW6Py/+ED9Nd7bb+sP+em+YnWqHpBecs9oF/sr8y5vE9YVQ0YfwOFVbf5Oono4LLnBK3HkZOuyAYFVCdhaywqxblawVSTDI/2CcawazPcqd+APs0zK+oX6g98H3Vyp2oRfUsx/wgZ32W99N5+2l9MD/wQ8877d3+3+TAsD9j2MNrBS9j0+b1ybFpmNbyyv6P6/GADdkf9tmD2jdrpZr2x/JC9jP2VCIwcs/nT610lmd5xoc5pZ9DrktsOWVf/6G8BpGXIrg5Pc3VH8DXsal/kRzREcYflB8RVTBffvDnpnxplM8ID750a1yi/ljFyrow9sqHhxee6faQZdjUP6vMf/gD4X7c5zsf4cc9wN/ku1ZIwz7Dnuo/V0S0RfZW+WZm+x5ptl9uM58/YfD5Ex4Vvw8Y9mRsyb55l357nFHu/AHM8tSk7Aj7E/Y0eLNUewKz3EeR442vGc1jUeGqeFS4khz27l+eK7ybOT5hfuX98bFfHvoHhj4qhBmj/1HBzPxO/ML2/iZPebb/x/4lf2OM/VjqHJ8B9wNqjr+If3k+jHl/AA8+fdg/4H/WZ/lG9u3xXpjOH8Wj4lkrHH2d9Yc/Hc3d5az/IdcfZz31j+9bVL4i3ONof6+wtfpjwFEDofHuMbJsjXfx9vdF7pzKNXspVewYTn0zp3iVMcfTPoidBp98kQPvVivNCRfF1WuFMn6os8v4PuxB8Qn7I2NU2CPeQUX+iJ++yHcj/YC/067+Ukd+sVxvU2f/e5Jb3Y/gJ16fpvP5XYMz461ShTzZx2l7qNjGehWt+P4mR/yO9YF/jV/MUT7GcuZ/xtbI9+B/2IsrzM+s8aVbV8CXOFe8A6PiGOPn9vDjU7R3qxQ3fyJHPveErcb5w785v6P1Zv/68HfC3R+meIcx52Pwb+Bv8s6zP/o/x2OMbcKzcpt+IdHSn8mj/gJv5HuEbdQKed0/wUt87I3evxOf7P5UXsF70qzPcsQr27hfVjnew77Izyh4/Hhb8wO0v1/6i5C2xrDHE8Z+esLFSb4x3puof96/nL9AHl5X97f9C/xNnqLmO4e0x7jH63IeFPmFA48P/oFfxDJG/5l+jA+M8QCP/P7/kyji6Q==###4496:XlxV32DM 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1178eNqNW0mW5LYOvBInUVT5HP8AJEUtvfOqn+/+WQmESggpK91e1IMDpDiAmHNzq5v/etv7Mf/V4PI3nd3evumwue1KL5vwM16T0Gtz5ZtOdSwvPB31++/WRvr+G/Mbeuzff460HtsT7bzQPrz+vKWPIOu5fT8L7bZnuqyyHteP9ES7feTvv3sd4/vvWMd6pT/hqxvldb7+Rd7oYwjd4+Fe30/7a0O5CXwUoasTshfhz1HW13W+rQjt54Je59uc/z6Prcr4eXkv2mfBQ5SDHlnwpQi95327jh9KY/zoh7+Od+MI1/GbExr4Ui0OealN5K2rPA0n9EG46yKfwOf3Xvtc4pBx5YivYypC52rxmPReFcf4Esd2Hd+K0IFwjAfeyrFc8R6EBr4TPr+Xr3hPcp6tueN6vpN40bns9YrHIDTwVeUB8+N+Mb/vcr/n/rLFF3eY8aEeBs/V4mu2uNf3s0W5VxeE7kXoSHgajMt9Qr5w/5AvVyyO+wde6rFe73frQuN+y7D4vF+DuyL7gXxi/5DP1Vkc+weO88P8GI/5V8IxHnjPqi+i6Le9Cz3XJfccLB6K6BPgro9ovl+Gkf84LL4mi3ulvxmv4+df0avV4hgPvAeRp63JviB/O84tiPwBh/wBX8boRt85oY8idEsW793isQwj34vqWcjn1K8Gr9niIal9gP5S+cX9+mJxyC/w+aDTdX0Yj/V5tT/AMR449o/1Yf+nfsgWx/6B1yHvBfYB7wf2oQWL4/0AZ3uN8c0JHfHeFMd44LAvo7n9al/CVGXfNO4fOO4fuHe6Lz2flsV+4XzYHs7z3a4428e9W/vYwqjGPg6hYR+n/XzRNR7tik+9LefW5b4w/6Lyctpf3U+Motd31ce5CB30voEnp/MpvnTZB76/BaHxfcan/jD4OlSfq30o+v3TPnSLV8I3lS8Xj9c570HoWISGP9i63B/fd9bz79sUnYv/CH7GQU/HoD7RdZH5k7M4xrM8HV7s4aLuE7+HuqjeV7vA+532SeyrF5r5Wxc87aJ/7/yynhaez5v9UeaP+l7yJuaN75NxHg9/01W1X6TPpvy/5Hz3qt+IH/vN7lnfMB71fWQv73Lq5xc9lGZ86lvZvtdzI/6m+hP+L+tLxkFjP9ui/rm+5xuu+ts19feJP+l95eXoT/aMcZx/cYfae7nf4mV+xmsQfFnUfhP/Vu36mL/XEcz5kL1mPEbZ31C7x/tlfOo/8du8vgvyJxhfNqGP/ExP+QnX8799j/C1ynv1r9dx9/fO963xHfOvm/jLXvUx8/N5Mj/uawnP/nKvGh+p/DL/5mT+uOA+LD/WU+qzPw99CZz5o9qXbRN7yfw3fUL88zK9vqtd9ZqJ1xif8Yw395NsvM/xGOOgy+aW636m8k5P+Lv7Az/e3/BiL9neYv9TytbrewU/46HLfZ36m98n4f/++/d8+cuX+0r+z98xbV9+/PVPTOUr/PW/mNavXtKfGKKb/9VDZOBHOarx/nHuJBiMKhzzW1mdiu2Jjl3oc3yVw4IxAI3LZnyvNricKqBfHzNorIfplm3wF8ezMapDhY/wQsasbuoMafA3nU+58/aGLpps8CKUTENYNqfOItFJg8szeHD6iJvsP6mxwnkwDeM3jerrb6rDnM8nfCpTe354bPr/p1Cax+g3ST5MJ1GckHEYZXyoE5vzszwx7qtNXsxr8Nf98XoY5/Xw+fF4pjEe9AzW49P87/A9Pe9/OmHtur93OM7nlHfCpw6N5j6JDt2eH8/H58+0H/b9RlU25/krHcm44P4+4b3b5A9w7I+/x/iizg7mZ3ofdn68r+DOZGAzyRl1LnOQ91uSTf7AGchZ6NVZ/NDkGeTr3XmDhr7E+2PaB1HikI+liX6DvDlK7rB883qY5vmqOgNlcUG8k119fw2eiQ6q76C/md6UZv2ZdN1Yb4jPNN7jlp7p016pc8t0dzb4ZP3N58X0osE3nAnoy57G+C94Kiq36twyPSVwv+p3Xh/k7dBxTGdK7rwbD3mtGkzB/nzCR7bJobXI+wDO74VxFA/akPFMz/dlkiPzXBYNcren/TCO+4pN5mWa/Rmms0bd8FeY3hMl31SeT/vB+umNfwD+2/gs9I/8iH5zQe3RBxzJItz/dOYlSb5p8BFs8eOGkz5EMnzp0x2U5Iq8V/9Ms75gmr/H84dF5CXUZ5r1xe18P+Asn5A/0IzP91ye5PcdXqqV39yp2JVsMo/9OSQ3kQxkfbmrfCHZxf4o7h/4rv4W5DVlW+w5nC3mTP/EFHvYX58xmSn2sD+eEhVzyB76ZIslbM/2SsUMsmel2GIF67vp8CZT7Mg2+YLv43zZn92CTUbf9FGxyVy+b59sMvfmrw97vxxPJU2WnsUqvc8zeZBssZPlo2WSD0reDZIPtoeFkrGsT/ZExVTC5wMyOOubPdliK+OHo2IsxxPJFlsHBe94Pyimdi7GVovzeJ9tMZb99T3YYuzNXyec452QbbF2JPs+90zFWvLXMd9ZrKR4KND7Zn+90ftmfHpJttib7fvG/Z36hXDc3zs8kH5gfxzFj/P7hFdncY4XDho/9YvBfT9+xXOyOOcLVhrP8QD0D/TbLV7oVv8xvhSLczxyDFtMbqQfsf6zGSHbYi1wyF8jHPv70b/WH83DFivZH8rOFiPZX0RxEeOxv7O4MWyxb+oXWwzMFufxB43HfCj2AUexbw8W99UWA1m/t271P5KXOT/P9xPfajGS+Dl+Yn74Y3koTvtZo7yvEN7wk//F/HnY5DOfN+PsH57J6Tf3AX+Px4Of/UHm79nGH2zP2V9jfs7nsT3k+JT5Ob/I7yUux7jGy8zP8fSN31l+fq+MY75Di+pzsnaNfxjn+P4TP+uT3gVHfMT6EuNL0HiL+N99D/yc72V7wfLK/JwfZH+2DJv/YnvLOOcHQa+I/8ifZhz5Ruwf+Qnsl/Fd5Rjnw/ycf2D+XGyx4ubvQN+oPrjxE876Y6XmSPaXGL/pnzM/J++b/VnGvRYToQ9Yf93wU1+qvqJ4i3GMh37h+RiXYkn+cl9RaiU5m1rJGv7ENVak56cY4NlIL0x7pts40+39iU7ZppFAn2mjD3j3cJfUTBHtqEflRhcbxsgxrJdjWJ+OIfTTK9Dqz1Cr8ExXza7UIF7DjdZWBZQimY7JbptpbLtVewygt2KtO9MzOnw4hvJzDN4t5hz8PAcf61CvwaH0WCwt82yX47TTpDlNitVrRXZo0JOqHuP2TOdikxFMj2C3x/SRrHMjy6zXSqGLZqH7+ioV+rjEir6k0rRkUNAXgbqlmrQsIf4nHK4m+lrQ97BGffpDTD2eKtNILZ19ThraTlVqSpVx2FQ76Ep9mKNLnZ9TpZvOyzhoCCPTW7d9D3Bl0C8FV4b7IHo5+w5+xbdg50cql/mx/rOvof/OD9zR/Dwf+ihAo+8C833CHZ1Paei31lcRbF/POoN2uTdxHXyxrh3ja6bUWtNXoHKJ1G/Q0hLTQZXUWVojeh82NIrJ6thBoQT6rNAHhlQL+goZR9/bOxyuLvBCoUOnUIhxpFKAd+pDQ6rkDMXoPvZsU2k79YXmeku1GdceofB5Ps7ikfFqU4HoazxTgYH6Xp3FW7f31SiUbdTXi77CM5VHeMsW37Ltw0JfJfqG+b2u1fYls75YhsX5vcRA4wP1TVfbN8045r+kAtZr33YMtm87Eu4JX4rFp5G0feHF9oWjj/zsC6e+8+g4VWFxT6kOV21og/G4f8Y9pVICpaqnzTWparYXlVLZPB59/Gff/LCpHrw/pHpypt99VJtKDHiP6poflOo8qE8qF5tKZTz133HQZyqe7PVebd8t69tcb6WMdtVf0C/QXyPZPimkstF3vGs/FOQffsQp//y7omR/V3R06puutm9679R3XW3fNeu3TqUE1k+e9FOjvv+tW/3D9mT5oJ820k89Wf1zkP6BvQBe++/45izO/oAfv+uf+EH/eNI/B72Pnd8HlULWYeWrJgo9uy2lpGL72pGqhXyxP5md7ZtHaRD+283eE87+HkqVufw3/Cx1qnyiVLpU3R/h+N1g6YLf+NFXGOT9sT8Bfwp968yPvtFld+2Jf1X/cH4vP/Hjd5PbkPUwP6+f+ZF6WPOzP3PDNdWE1AXWM3bp42T83frBf6Y2NdXA/tIW3qRClX/78Vdf/5if4x/mv50P8SOVlNTPZX+X5Yv526ry1LV1RnMW635Ar+nvP9R+Ef9N/oif/XWWH8Q7SIWyP4f4I/z8Di09tWJgf8wPeQ5F30N6TlUBD86mjvg+GEd8W8Ozv3j6ZSjJEj+f9zt+xEdsjxa0wlCrJ/h5PuZnfcT+Osd/7K+/O/9L/Gfvl+wl46DP/bD8Es7xI9tbxvl8zt9BjDf2kvCgrRppk5Q/aLxnxm/yQ/wsr2wvL7/T2J/sPeOh0PoKrY9wtBqUZvFTP6m9XBfbmgD+m34i/qT+xPm9/Lx+lI6Yn/H/Awk2aM4=###4496:XlxV32DM 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116ceNqNW0va5LYK3ZJeluU/67gLkGV5mFlG/WXvV2U4SnHs6upM/tAc64EAAaLc6Y96jv9cd96N/+py9Be9u3O7/tbj9ec8otBx7e7115frn0/Gl3zId5uLr/FaFdrtQjPf78c1Uu0uveityXxpFZr5WG/U+VcndN7tekLr8i/puAZcotAxy/jR9/qEb75f68td/m5dcCUKzfyUhY/xwC/tDBdO+VsUurXTv+NzlX/H+KHS+lQeWH/v13LP7PslgbWd7v37HM71+s4LbpyTSCrKh2O4fP3VgRjfSzfz52LH//ffv5fzCD/uJ/76O6btJwX/1z8xlZ/w1/9iWn9C+BVDrL4d7RqnDc0a/3UvtPtAn0XOKTihZZ445kkyT97NNEf8FX2Mse7luARzNH8p8JJl4Baf6dwEn7eLvNFtF3zN7ry+D7KwbZOFfeMfXei+u+ORbnajrfT8bmC+9+tAXDmvA1i78IsXmvFr6ZdC+fXcn/B5lfUOM1qe8L2KAW3XboY8CI+DqipfxrP8GS8Hmf5TmNzMQS5DX5ZYXZqfXX6hR6HX+kxjmZsTsTKNY9rrM+2L2D2OhenDPenjMrbRZRthW8w+hi6+NuJj3c5+mXQorlwasgmd6jNdc4/X1nah11Nc7ELfg2b+3sVF4PvhgmT8Lkvn9Xxa3/hfccmqIXDR3/hHFvrYxUXHJvuB6fN6bnQReloY0U7Hw9Hw+Gnr6d2VMH0GGa9t418e6D3JeH4X+jb+ruPVZ7o3O94neuhmfaI3nS/tQt/kF1VeH+jD2fk+0ZiP6cDzR9nfklXfqtXPYxE6BKEZz3TX81w2tz7RReevu8uP+w863/JM83qYZvs5up3/Gz+n369v7zpffKaPQudBNOTlgupjFhrn85Wf+2LOj+jUhR6bq0/67nW9ixM6sz1Uy2d9xfdzfPJHRUOu3al8yV8U3EjjKB7tHeetrvimr8HOz/rqlcb87G8j8Vkfsb8xeX7Uh2r50B+cL8tzqI3VD8Lf9J/wchXlcRWtchXF1ZmryJf4isHSuIoOUZW1ydDlVNMMslSmoWrVPdM+kGiCqFbW8Xk+piupLtOn0lO1aL5AR1ErrYeOYk101NkedQpW1TA+VI3Xk501pa5XSdjc9jifyi+kZzzzh2tLdDVc8y2Lqg7xb/InPMY/kuyP9ztcQXpyRcBvRceL86o0+Nv8hMd4a30+r1Wv6uF68xN+06t2JJ3tCX+bn/BiKuswlSWLrSynMZWzpZepLK+UZUvip4Z2XH4oOk299B4APQ/vC78V6wdv42sq3YtE0kzP1DTY1Bz0rplE3IU+Nw1hk3wfdD5kAjNVb5I5fOMXSv2XoikpUkunKXM83RMfqfDWhb8GTVm9pMDf+C4rX1PnI8i4wyFfoXxekOLKhcO0rzJuiEIPzfOiXDKuzza1xfoPL3jQmO8Tzan/kux4n/jDnW/v8/vtjO/ru62X+GP1/v37lCSVn6WDVVL/IdftiR5yX59LGyrvbksX2A/OB+cP/nRmWf59hMfpXV7MXx2chdCsP3weWN9IHNqf8EemW97nZzqoHDC/D6LvU7+VxviwjyGg9id819ReVf9WzZSR14CGM2U+UmI4a6Sw47IQ+3fW/vE98jKUylqWOIv5GB+luS3Y0hy+P/OIPB/o1mU8fM/zbVTqY9ppJYHnL5v4Rx6PacyPOJLXD7pvIh+mTy1NQn6lCZ1GgnzhFL/t5yElPcsHnZezPfGPrnwtTfL5TX+uNPOPKvvD+oAvRSpPw3+Lv96FTlXs6Wx6eSrd4zO9V71M9f4CjfvrGz8Fm2dA39/kdf09nNA+6/rV3xxamt2L+i8ab/hJE2zBn9eola4g9FGEZnmghDMIqVVlyz+Jz+cVi+hbdUK7YEvNgfg9q/3q/n3VSprun/kn9Ff5mH/yi9Cfvq/0PetzSrK+cXj+yV72IDTyrpNK9UN+ci7u2V7PRHySD76HfNhfeK3Mzu/JH43xDJ/9XVf9wv44HjqK5Rd6CkDJeeSfF818VGo/8av7PR80+K/aryk56v6QbLC/d8Rfi32KwNME7Gdtlj/iBMNfND6d9qf3F/hdk50ZD2kyAf645sx9tun+F423xjmbeOLMQuN75g9tWX+3/v5lfyMeNPyuyRHkP5M1lT/HK13l08pzvIPxwcd5xihPKNCfXITmeKr23++/0P57s/Hc4mRe8Mf6zP5csftjfm96nsrnePPUeAjj52yfmqrG//h+6ZYP/Znypaci+GdeP/hY/+TT/n2z+2f5jGjWv/Nd0jgV8aTKb66P8oHSZ95ySLxm+Zn5lI+MOLO86wfnQ9CvU+XC/NYtv6t+53gmtUfRxyI0yzeQfDnfzJXqbhRPDHtu7/4xaT6I+3FFvqr341ktvznL53jpSL+/v1r9/f2F+xXrW4rNR3fVP7yUcb7asuVjfbifTrqf1mL94/7FPyZn9Zfj/VqsfyxqbzPfgD2qfnI+cjrBg8/5UiT753wwJ2s/sVj7HwHBZvw75cOlWv3i/Z+a37H9Tv+byP6C+hWN36DfiN9csfaF9U37Iv2P3a7Pqz4if2J9Bh8vvYzflG6H5QO/av7a6ghFHvAoPo3R1if8LT4nPOoXm8qD492644leX2oJv6s8vddiG+HDIi/DTYtrjOf1MZ7zD5YP89lfoNjcg6xn0/sEL9EoFg/Hsj7hb/IjPNe/OL/a1L7HweUnPIqXM18i/G1+wmfEp1p/4XwH60kF8YnFO6/+tNrWFOCZD3p4yUXiDytP5iN/Lp/yEeJzfsvj3/gkL87nPdUb2Z/z+Iy/1ScoX+H5GM/y5Hid6zEcr8/6RxN7ZnxeDr13hM94lg/jY7D1Qo53g8bjbVUc4Vk/GM989BGkbOtfGI/zBeazPKvG3+DzfcHrYXzWThrU0zjfwHwto3XJ4pnP9Ty2B+bf6qcUrzMfrVSpIz7WuG595vP+b3itXwLP8UJd5C/4jL/Jl/Bcj+V84fY94bn+y/XatCBvFvl+4sPfMv52HxF++nPNtzgf4/NlPNfTOZ84km19YzyfF+NnfT88x1s3Pts72SPnYzzfLR7S9eK8OR678T/sNyW9byif4vcXxt/kQ3imOd+Cvo688TFevOuDxfP7BceTrL+MTx36p51vlI9hvtez8BOe9Znxi9aTEC9xPZL5HE+BHus93vONWW/U+xL3MeOZf7tfNV/zm3NP9TwftVOyarxEeI6nGM/xAtc7wcd4nK8xn+vtsKfZGkv1MrY3xvtm7zfOB2/3JeFv9x/Vo+BPwed6CPtbxk9/1J/rJTd+sq3CbO/MR/NAXzR+o/fqW/xL+CmfD/UijhcYL4/15cf9HPJWP+In21q8xV8xvVos0SLTmrZAKr37Z/qotqXrE43QES1hI/VJf8JfnG1pallDE6VRikapnfHV2RaolG59NqavZUPpG60FmkrMUo9ejfgepYjZN5OpVBRsqShrSxaeYjZdH55ikqY+s88FpWL9PjrLx1MO+As/9TT71LNQCxdavPD93u1TFI83WxDLMx4tVXuklsUy92P0i/HTNasp3ORN/NBsq8hs4e0yHvNnS2Knlt/+vB7GH9nqN+sT75fxk6/j8Xl8lF+38sna4sz6iv2Az3jsBzTjmQ/7xPkyfTtfWi/rK+NZ3xOehtQfsL3z+TMe64/a98X2xutnPOsD27O40m240qqutDf6lcZwpfHVIghXuXjtTq22O3hOXe3SPvHh2ribGS1aPF9T0wF+vqqpK9g0m5v8JvR0FTRfJVfVuh0fr9KzhU/56M6syke368rdsNl2wy6Oum3p1dopje/PoqqF71V1Zrc4raef+gqoVQTGoxsaLX+MZ/nf8NQNz/v9hv+vq2eeh5FHT1ZfGH8bn/AwpYjzJH1B1wT4Nzzxk8p3duOTvJjPNOuTd/qLrO1ZX1GlPZ2Mz3if9IdZs4pk8Ye+MuVFvyc8y4/x7pAq7pitPekj82e3eX22V+aLq6lvruYMH1zN/CGJdmf6bFUNjfPoHmX8nLr/GR8PFNO02dSdNXVejydT96TakaKWHGxUt1FUt3WrGnuxrgwNK9NVFeuqjmzXv9H6eb9OoyLwIZ+Yp+qa/RwfTBV4Ph/Gh0SunvBMw/RSUdMj11Y/uMJP+MVZmuWF70tXV0p4RDW8PuB5f4x//Uj1/ZZnfYC+btptz/i+63ja3cz42/oIPxvI2rM+MR8/XWRXOOVD/JGFWFfXP7g6/Z7xXV3Tdgif8bf9EV5czT5czY6oxiaIvl0/fCix4qg23Sp+czYk/kjP3+TlZzpQlAFVLlFFXeg3VkSnD7+xQkDnC0UR2Yq+0q2zZxtQV0oAebz5VqyuJAR7C6BXZLqSILfCvMXxq1L8xidQ1Eauitc7e6HAr+SKi3VlLC/8sGOun6O+wgmq/nwTvYy0Xqj6WrSXkfF0voxn/fqG5/O8nS/JA7cy9IPPg/WH8bwexut+/w82dO0G###4624:XlxV32DM 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10e4eNqNW0uW5aYS3BI/IdRehxeAEBp69kY+3rspZQZPGdLt65pUR0dKQJLkD9Vy+MWNnz2c2zl+1s3HO16Yzz7/4CMKTt2HHxx3539+L0Xw6gSvyu/tvH7AVyfYVV/N+xS7ctYf3Jo/fuC2n8cPrlXw4QTzfEIXjOf94bdr/Co8j1cXv17zLIJZPnZffnBfzv4m74Loq3pZD8vz+ll+CbKetIk8rxe8zGrol+R5PJZ3Oj4w75dbBbeu8yP5x/xJ/p9//srOl1/uV/z7r5i2X2mtf/wvpvIr/PFnTOuvEP6OIdZURO8hyb6UVUaIH3BIsi7so4yzjXGKjBPOYMbxNf4MlGMtVVSXm2vXVJfzmvz6CXfB5+auKS674OQEf+NjPfcL74J5/HToVtV3fIb39/sm+Bvfvozf9Kgs8R0f1b6fceoi/+n9u/KLf8dRTdPlD7iJvN8FP+YfaP6Eu7PzZZyznf9jPaqP4t7lMb/yYb+3IBg870ftli/JrjcXXY/7oI9EvOpvGOD+9r4G+eWDPOuX5OWo1XHUVhy1ZI+aH0fNxzXWFkXVtdPRyO84BKuaqFuxqSnDdIp/x3jfODqvOBTaOno/TL/Ed3w0OgqEFzINxjFZU+H5eOJX4kuxPOu3ZmtKrM9Cpgb9hPw+HlxRru/yrD+Wf+iX5iumtA9T2mBKzppSubx2inUOHdTrpXevB36npWPotYsVTy+Z3/HpJLDg/YzHVpr3p129drPvO4OcKsbYSpxKx6ZCXsd1Kx/p1Ndsed8sz+MV9iq0nlqtqbA+C/M0/5W8Yit2v3i9vD8sD1OaXonlNSq1TfVJ+vomfzqLWZ+8vyzP83vIk72yvr7Jy1FptwSnd3tUwuV1S6xVc/G2uCtnKpLJuaCnEA4f+Bufk51qaITJVBMFHE+mynwmU+Xxcvr9+3FU8HzPZ7w/fwTBM0AvM8F6XQ/zY6v6fStYv8wP00/3qMTyPcl84BVZfiZA6V1fPB7L+03ej/mzPng8lhdTO4ap7Wpq7bCmdlxeeRsBPrxP5XTi5RhvtBTGkUxhoa3J5WEKyWx1tVvN/Dil6c4f/VwpQK4mQNL4nsbfKBfLT1M345/Zzq+GXi7Va7m1Z8Eoj+dR7O/zYZ73Y8xv063e3/jier/zLL/6LmV+dvlN/liVb1rOk/yu6yvKszzm3/sc30YpdU3gX+TNfFm+qr5nrUL7weth+aXI/Psm8+X9WrzgraG9YeV5/Sxf1/PCob7bI/NR2wqf9pd5Ocr9/1EjVm+PcrqO8ihaapOh4ZWGVy3GKxFuxzDmm9dgPBSZfod7tV6pZRvwTi2r59HmMrtaU3nMfxVcP2B41bKKV2bM83nMTxOIj+Nn1dfyjpO6kk2jAmNe72P9VKayPjJFRZ5vqJRA0vxLtq6Q92vMx7gy3q9MCSDP1xMvpnoOU13UVheKOv5MP7ZafirLZevhFE/Q5Jfgw3dZFfHr2d3vcEyHxCn/jo8ieIn9SnvbdHRi1WvvV3mQ1crrInK9ioOBPHDZZZ7ALD/mddzXw/LM50X+2+d3PCrBa70hCh452XZ/Ho6mF50PYVjDGZVPXU6zl3UP/UtgjbLOGAUvQXD56UDeeB+6vz+P/VryO4/9ClX0xPjIdn9KUj2t6oDVerN/x8iB1qbjEx5S/j7/rPrA/KCvtbzzo9Iv9+eXcpj9q8uhTRixN8Y+Ccb+8fNnFgz+yP2af/igX8bQ5yfcVb+YP+x5VT6q/WO9jGuT33ie5zecQ5McVscjvDRZ37QXwi6IfrD/UfUz+9RB5TVw+/2QQC5F/VnKsd3lGR9BcN5VPhzXv/bNXf36th/qJ9zV/z79Ieuqglme+VAEjzBueLxvdb/neXzGa5fxkZjged9xD/N73uv8oD/wSOAxHvCDd6I/3FsU1SfuKR77Qfxe7fN9ObL4QU0I1V6C3sswz+9nnJPMF/t7arSGfRYv7R/YO9o5wN/4WTjAP+p5hT0AQ//Q58hQ/X/hUxU87Zv8O+bn0zue7S/Fh7YfEP++8TGj6a5xDPvx0ym5siuZf94kQ2dcoY9d5Pl9s/ArgqFP+LvZJC+CXZf9w/MHspkCLPFpi+flB1OS+NSKYN4vvH8v2D/az2R5V8QfTX/nDsMv6k+x3mHveoEmmPmcLc/6OlWfn56vnd5frL3HJhj3rlsVf4Dz5oP6E80qo2Lwp8qDf5zXdmx3nv3BQTz7m6T+D4XxWJ/hQ3rw17TmPa6uH/eFD3+q/j45weyPD+I5HmB90B/Hm1P3H/PjeIX9g30ink/7JZ6fr1/4Uiy/aTzqu5P74DrPa5dLK8ufGh/AczzfsmDY95koX1D9g+/N5otZ88P5POUzReM9zjfnU10LZzyPfHzy1c6P+dYtv7te7P5o3jj1Z3mvecrUf5P1gF/Uv0z/UzQ/Vj4RvyeZD/xTV/3CPzHfquVn9abrq8Hqh3nguT+U747qOBi+2vl7Z+fP/Kn1AviqjRK830Hv+ntrlof+wT/qMeSn0/6l3pn21QXP+VO9AnucvLPr94XWT/yIht7Mrwu+xa9g4pfqc+5/szzXW8NrrWL3KGssj/gGHuexxnO/2//IesS+qjai1H7G/m13+9mK2lMUvTV93zh17q3exfu3gnpYzuvM91CvqH9/5CsaT9h/I361auMX52v+S/w6go1PzO/Z8ku38eMINn7w+Af5f6wP8QPrQ/zI3caHo9n4wP5pJf/E9Vj94l/hX8BzPVmd9a/sH46Hf9X5R+n6IX4NO89v5yPT+eF6HfOH/Y883pzfLdjz++gn0PrwPNaH52f8oH7ISjz8O87Hqf5q5oe6vzgfVePjPB9aP+/hPR9D/Q2e5fdF+1dBuoEs36Lg2NzyJh+S1tfKs3yssl+or/i8In/HhQHLYzwfNP8h+U/zg/yp33HNft28fldDIB71CvpfLuJ7PdxlWX6MI43+VeVIvmt8B8/yj/WRPM+X6xGuv4BRL/F8WB711eynUL3B/PySJmn8UH0AM8/zYfnH/lM/ZdP4mbz0ybieYh79wKh6bqfYp9N48Y1n/aP+RX+K662kGPU7y2N9q/YJH/I8PsmjvxE7vlu18QDjgWd55lm/3E/heMX84zyrP2naD+F6CP4EPMtjP+bzJM/ng+W5/8T9DujzcLb/Mftp5D9Ynt/P8Rb9Udg311PcP2V53m+Wx/g9S33E9RLzSePrtkn99OiPEM/+nOW5/8r5QtSL5GnP3K8lPkXBn/wj8+7o+d7v5nzjwa99vWMen3nup3M+wv05lmee/e2i9QT2m+s58NM+SJ71wfIP/0H3Uzgvqb3Xg5Cf/TWS5/exfHK6r+p/uV5knu+zeH3Mw990L/ke54Pgd3+WN3nu17L8p/wC8vN+pn+ox+K8l3uV5/shlmf7ZPnH/RfVu3z/xfJ8/8HyzLM98XnmeprPE9fTuB9ck82Xp/40D8Z8Wf6hv0/yqs9HPU48CoB5P8fvJ77W09wPcr3NPO//AF7PwWs9jvmBZ3nmef3z/lTzUa7XOV9l+Xl/q/12rmdwHwye5XGfPPv9JA/7+ST/8GckD7w56Sdwv4F5vG+um/Np4peuPPwX9SvYH7E83gfM9RzzOC9Lefd/zEftd1Sv/Rbul9B9P8t/8q/zewHkd03ex/Um7j/xPpZ/5C8kPz8sytovo/sS5rlewHi5v98HPPhi81POd5mv1d6/cr8f93dJ+y0s/+n+D/Iz39UPprjf8+CR/ypuWetxjVfMc/xieb7P435QbHqtr/6O++l8P8/ysCfUc9zP5nyG5ZG/wb9xPxvxbNazJM884ptvNl/hfAj89TVQcD9fAyX5GijTXwa4JckfdPlY4Z2HF1rv3vATPkO32iVcmo1WTbu74DHeUmw0AV41msxsvNqviYa6bPdLv/ZYupWf0YT4Fqw1bFFORwr4BuzQbBh/f6G3VQu+AfvCd72919OM9eFrqZGNm2g0sjqtHoXf8fXHIvpmnt83zqo31vKF34KN1r3Y/WN7YD4nu7+rZk+RqpGg2TbzAV81xXlrYa2929PC+uD5MWZ7Y5yzta9hr8t9fsA3ezY8vtVEdsi4BFtt8fpw2qEfxqw/ZBc4H0mzhZnNEX9Wup3D/BpVhx/wStUi9jvuMi/WD7//G7+Sfuop+x3r7HIbfX3C2A/GsJ/ZzSJ9wVtnZ7/GAj6y1V/d9H31fb7Ms70y5vk85ldofPV3edFuid7+zz++wddM6b/xR7bdlvm1XNGvVZzt5jA+qBuE50PXbJ/8NfO92efn11xBulHwr8APvttuVaWvnSC/ateX+Zhtt7FqdrDF9/EZp2S/boA9IH5UxJd/AQewzDc=###4540:XlxV32DM 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11a4eNqNW0uy5LgNvBJ/oqj2OXwAkqKWs/Nqwnc3q4DUE1LSPPemIyPBD0AQAKF6y7Ee818N++e/oyyCQxXc/FGecO2C93hsX1z27/9jc97Nf4ff6we78oxXJzg2wRjvN+euOG3HuM4PnIaMz+27jbnp4b5yyR2f8X7I/rbNje96xBflWxNcl13W6YJztTzjVfEEX9z7vl/1KUXw6gS3JBjjD+Uxfu12/p7t/MxXWn8J1h5B7VudYLZXIt6NvX/t1Y7vxC4I3p1i4v2wfMoyH/jdyXmB98PyB/E8/9SvXXn2t67n58rxnXewP1bLp6T+11z82GvKiz85wWy/IwkP+8Rs+Z142APzA2P+MUQf8EcWfPLqP0scTe3zxaUIZr4Wy+8632huv84fnPh/G5bH/sD3Mr76lTi+em1VcCuC92z5Eiw/93tc+Y77onwPlm/Z8nGM5crHIhi8S3I/QxzwB7GHXuQ9CAaP+wd+DRLXMP/0ivU6fyb9R7b6uST/n+dTRrnaf9H9g49d9Xnhl2J53+X/LR7hay9dvxfBOP8Yj6z+t8u+Bbsgcfk8n2H1K6R/zcQnWQd86oJP+2TLZ+Ij6eeT1Y/5ucF05UPWfej83qmfkP9gPPzntG843HX8mgVj/NKtf7lu/Wsh/5sBM135lewzb5jRf0tiz4+i3/NS+4cyjid+D5bfk5x3jYfc0yF4L4Lhf/APrxj+gfE9it4YP73CPfF7sHzvgnM8vnoP5bciuHRr31itfXOyfCB+xt9u19/bdf1YLY/4D57z9TJs/tsov+6UXzm/9GzzC+I/8jfyJ/I31yuxWB75FfEd+QHxfcZnE7/3X+J76Zbn+Lgk679rtvcb/nXG52rjW6f45ouNb/N+bP8Un+Af8L8Q7P2dCb085QfMj/yA+dl/Ct1fjj8+0f0LgjF/1vuJ+ZlPyfJY78wf6r/IH65aHvEFfKD7ObroD/vc6lGu59Q+eTnzs5Evh8SjEGYF/SC/7cLnLv7G8qlq/FWe5VH/+iH+zPUs81HjMer9mnS/cV6dB37a7ZunAtYjed7fTZ7qc77vbC+W5/cF13v8frm9R2i/b++d6ReP9ewWhU9B61+S5/lZnnnf5D2TNH5Fep9xPcw88PBSP7zNB5715XiH8VH9Hfafgbtf5wfP68EeexV/5nqVed/2csW3+8P8csYxibMaD6fjfPcXg/hfbYJZnvfP8ozDoXFH65rbeLxPdP3u5D5GL/viegT8mzyvz/J8HlxP834Rj2MbUqdoPZG9xDWul7tH3H6W5/lZHjhUtTvlI+b5/FjfW72t8skf8SmfwX6+aZ5g+Zfzhzzs64bcF67Xmef7NRfxmtcf63HmjyzHeZ4HnRfza1U5nAfV28zfzpPObxmy3raKvZPWG7sGYq53ZziSODOEZ3mej+XzIvrgPnI+Lk3vaX+W5/vM8kn9OS9Hf6rHm/qz349H+XqIPyBes/ym7420aD4j+Vt+JvmxyjnMYw1P74Ebv0v+BMZ6s27/v/jb/lTf1Ysf8nvi1HeR8SzP87P8fK+3qzy/F3oTfNaBJI/7BZ7l3/ITy2/p+T3CfNZ+w9v6bzz6j9wPZJ77lTVL/oW/cb/tVk+QPOdvfu9g/BhSX9z6VcQjvwJvWp8s7YUnf2Z5xEPkM+4ncb5k+UXfU+C5H4T7MfNSe+rnbEXuA8azPPO4Py5ofHm5X+ARzxb0k6hfw/xajuUaj6fXyfyL7Iv5mUfET6vsj+XhX9CH+ymIl7mqXaifMgrlG5KHvkt/7re0YusVlj/jl96f8BbflK9Jxp/3izDHt6TvXe/FLtzvYB4Y+f8W34j/73//yi74P+5P/PuvmLY/ff/Xf2Iqf8K//h3T+mcJf8cl1uDGV3ykMwxGCS/POEYx24p2m7aloOZvfNAyCGGMMdpgaLOIGuGixjBq5KlGjtVr9dOSWG/T7DWj0SPG6cNa57bH+Yo3fKsvakKe+HkaRi3GrjypGX/U9NEZPf3U08cadZ75nPbqlQbLPOk6jzfzpDlPmjFB9+uTjEM0nLHaPeEeRL56uWWMs+4L1RVjdM/RXZR9LnOfTfe523MNLv4dYwyx9jLkAm7u+/RdtqENjPnGesCz8JYjaILnw3C/jgdeNrc+8b0K5vGQR+Aqw+UnjEZFbYJHlv0dm8wHjPXgSqPM1PYgz3wpKPSnqp/1gtzQtkhjBfZY6jNGIn/DaGSvTTDPz/tnjPWCs+cDPK+WOZ/pwhJh+vN6t/UPKXxKl/Ng/Ha+wH3Y82F9Mz4EObUH7bckwUX14fNAo35xej7kT/hQhPHYD9bHhzSsz/tFI3Y49Tfy90r7mxPE6/w+qz0xP/lrTTS/l/Pbh8rTfbyd3y/yvJ/b/SN7SKjIM1QkCRVlM5Gixk9knPXaqrF0TVrhHNpgeMEVGXfRjgRjjXF4ETKejp9MRUcYqQwd2aydJfAxHeaL4NIO7YQ8y89IKjls144CyXfVf164R/mbfUheDL1ecscy/ikH5Z9Os8EyT7nOc/xTDsJ+Nr1IS3vGKCVgf8ah2pzDOLunHLT97LP2p9Li0IdLkzJ23iv9ocLyjPEwSekZT/l2beTiIeez/lDjF34U2whnXJ39oYeoWS9q7v+kJt77btXv9S/47H/qewrbBGY+ahjEe4/lmV+HVYsxwpRVs/2omcL+5L2Hfvea6eI7bns0V794L8Ub9d5a7Txx2bWv8oJ1/zhWxkUx+v+Mcaz4fYfsc/8Ji4v13vENi3OjaDyepXGh0phwww8pmpa+hCM1It/wWSoTRuOravi54Tzsh1fCBQ/Knw+xzTQO9EMtDhSOGHG/WJ75bD+0bPrwn+97qfOIX7U+K0E+bLD81oTvWezL8rfzIXk56HFxyBafHHuGw359Csx01e9Pg+NnnpEe40CRPiiictTf35X8grV/hT4p46DHd0ZpxXg5/MavxR7/DWfrDl81o7uay+q5Tj3XT7Wg34HS+T7X/T7j+b6Q7z9BsuoNaz9mHmZ9wsXp+1/7X+gHbPp7it/40fXFFZ8xsht+nyF2+Lz/u9ih2fdV/r6vykzn2sivwyWpTwWXzS3fQMW8fmjem2C/6b3X91dTg6GeY+z1wzfqOzhMOmS+GYe8/mJwe8K8Hu8HH8rnZV7kfSLjz/oenQ6tf4OOP+t7xaifeb++2PET+WtjMkMf/aHFPNhh+CQYfEyWX5zleX437Pyffu2VL4rBe7UH6vuoHzZQ39ch87fteT0+H5ZnftGyFjiuKjfkPJgfWT+wd/U3kp+Od1zXY32Zh7/O2R/xb/tn/wfG+5H9iXkejw87h5NCh/0haD7DflieeeTL+d5Kj/snHo3R0x7kbzf+xX64b3xf+D6yPOav6m/sj8yf8Qb++RaPlJdA9+kQ+kMiXcjU6uwz1m2fXlLVp9QcnK62rmqroLbhs3jjT9u5Zwxd2dYxiG3WrncdttSk673qqs37ZdGzJtyKtQ1jj+a02rpr0sNd4/UYn76k9mL7gW/5GeOj7Rt2+DGvxu55NcY1V8D+sNeNV4y7yPKogc7eiO5v1npVxxveR3yskPlZ/oa1Nj7nx69+1F+SFic4D8aYby3oJVrs9ccFZ+9H9etJ7VVFf8zHeFWM8awf/Kkvz7glyuWEXaXcqEWhj+pPtB5jPi++H7/x+CgE+/dhYzEw7ME8PsactYHOD/umamuLqLVD8urPND/GtyD8MbTlpDww1v+Nb/oj17MXy/eX7U2Y/YUx6zuyzaW/8pSLeX98HxhjP7AX24/5ozzv743Hm/J1fxzPCPN5M96drSUYr/j4itqM4lXS+I9aku3TivCoZTmeZY1fZy+a4lkhnuNV14+Ib/yolud8FoKtNVlf1NrgOV4cmtuhP9+3TLU8+9tK6zf9IwiM74rPt4Dqd74VFIO/5aOOH/8/+wtq+cv5GPutbN9k+S1b/sCPVNQ+GH/6R7U8xoPnfIH9oNbneiOpf2F9zhfwP4zneLvSW4nj6eLsW4nrkaA85ud4h1rz1J/uM95qb/6HP4p44323PPJvTs/2jnr/fr4FWnnmgX/qMRufmV/0vM78QP7APNcLUT9h4Nsh+9uNp3oG9RnqPb5PXA+yPNd/fN+kVv985q5aqvts2xLh25ZIse6q+gyF4hr7uXTWUlz6IN6WTlu2pRIw8z7YUonlmd80dEOV0PR3I/rZ0Wsbb+x61Izx+yI9OsZL0ciCZzq7KrUVmEcoPUMh2Qtt0/MqO5uKNkpFvJ9VI9/ls2Oxz2D9+wodz/bC/AiVHb+P+SkdV/NZklIp63vj9VmIUmWvtrRiHqkkLKIPy7N/3eTJP1keVyMX6GPtFbO9yizP/sXyt/VJHv6cO0KxPe8zdHX7dAJmPlLoue2P+Jm6stGPzpt5/J5q01DGGPYBfrM3eAk1n1/C7OgKrCbUxCV+fgEVY63a4cNUcBVMxXgP1lXeMFep+NT1G9+77dDs2bo6/nQIPONAWa8OmzU3qpoSV200nvfTqEO5DuooFcsX4lH1nvvbtOP0caX/AfOO/zU=###4492:XlxV32DM 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1174eNqNW02y5CwOvBJ/xrjnHHMAjGH57WY1MXcfqqT0s7KoeN2bF9mSQQghCaRyzqU83Jj/unPZzX+5CL5Ol164OMHeue2FQx7hhfdzkua/rQo+neCq46XT1ef3k/jGow3//N51+30cQr+aC+/xunzvThdX9CsLPg+hA5dD5GV69CO+cKuyXuYPQeQZTejM30sfT37WF+QrX/hrkfH7puMTP8/P/KfqbzvcvtqPqt93/4Wfxyd+yOO77Bfv59yPNz0c7ljyEx0Y89ddsOuK+y/yEX9Ldj+T2h/sA3Tom/mr6qtHGZ/5P+Yn/g/6ofI1kW8uqD/n27tgyJc3sYeWxV6Yn+m9Wvu57UXPK9OncGKvjezLreVnftetPIXkBx3zMT/khz0zP9s784Oeu9gz+4uT7IX5a7L7df5mX8T/v//9k13c/rg/6b//xHT88fFf/4mp/An/+ndM+58a/xt9dLFGPZj7uB3Ve6J+OP/C/hDFzmHj39DPrPhc49hHeh9EJ7hXNTyle10I6LVZw2f+D/mJn+lbGtcTx103vMtfpg/8f9PxiF8Unaeioyg6bofRtA8vTVevAQLjbM6uU8bZfzbsqGaYfQ6zx3poHLpSP97bP8TuuuJSe3v/jYKvIPgsa/7a1O6VXs4uy3fr8ZgOuwduGkfOY03/kJ/4RQ3loYZzbbd16+dbf03+QjDg0QRHPy3mL+gp6wGH4tybPGoS/mPrb0H3LziGvkkAlfEYs7xBNwbz/0bPzW4E46vbjeb1zP83Gy2KPn7s1pe4stszybhNv6vBYhmn/oxzFDPMNofZ4vSKYu7Yd8Sj8/yCdTluW+OYrXoYn6SeD5ytumQZ52MZ9hTnuYw8TzF2VZcRtp5VK0s8p6niLXtZ4S3o7nrBsIJNx/+NPrJdFuOzr5bZ5jKbLDN4u13hnAcsxRjrPCDvpWynOMLp8YxjZTztyz8zyJnqjGeggCfoVR0r0UuyGfL0mO8TeDSJiDjAWxDsNSIjIv5G9xTBGTfFkH9Xi2k6P8uTouCz6HpIX4yPIhj6Yhxd300gLDp+1Pmx9ZohpCSmcWeov9Cb15MTJMNlfBUxMWTIPP+M/G/5pmfcV3gf4hC3JPysPx6PMeuTMfYX9sP29Bt9D9a+2N6K3tAQkNmesxOMG+TZrsvYexJ808meDicYdLY3RGLQ2d5uB44bJtlL6IIhPzxePSUj3NU14IbM+sjVrp/toTnBuAHX7XrL04LIz/pgepDl/GT4iu+MluhsT8wPjw/M62X7Yn5f7fnn/QL9Gz/Tb//T1/bNdHHF1yND39aZztyWd8wplxpyEQzHMfPrJL7/7+ij2ow86ZUUmek8MLscwDUeQR32BUdu5fuNfh/MtMalWsP8kDfYGwTzFzJkUXR/Zug2p0zhFfLu1Bp6QGqa/Br3bAMY46zjxXONcQCncv2PnONHzpSWqVTWp4I7MB33U9IS42q5a2CcuctYPX18o3tdN66ujKM6Ujim9zqSm+vYVN/FrS370COHleynzHx8wUFdKCRjPC87/emy9ku/r/p9sJIW4s86Hlwcj3cQ/UN+ms81Kx/PN3S8O8QSP4/P/KJp/8zmrKZDe2dz07gRTe73FPVGLc9js8DwVj5Nx7/AOLTfcEwazU77fSpqNN16Y6bPRPZ6qoJxqFaVU3Xv6Bf1/WOqLj/HZ5yK8CNasH54vI/xq4yHaMB4rt+MP6PF9Xz/RHY4bXFbYUS/0jVaE65Zr6df5Ec2WMIaz2tmfcrLGNkh3rMYD80Ovq0v1vX+Ipr/Roc9fcODnBTjg5zUvK42817G+iIMeaAvxj1QtkHrv/nTGl/Vfs/y8Xgf+qXzA3w79S/nyxc5L8zP9O7I9ZE+Q7WulPlzsa6S7fUMgpGNsj5wcQWdz6vPgkFnfwNXvTnBbK8tCcb3vJ+F5ufzHKudn/3RQesXVx0ewT2k1QND0KwedrArRl2DcdWsN2xr3Jx9N2Z8vzsnmywAp273nbHvq+AfH+vc91WylbsXO0pDnr+yYHescXNe7NivcajCX+M4VzgXwVcRLHKmn9AZt25D5zZDZ3w9ucJ1Rj0a09VXU0pSeqh31rCmo3RI3zd9YZtZTn0e9bKtMc83j0aVtOPv6Fey8/uk43sNpZu+ISUt7RCGq5jnaonv0s8XvFVbauT1wxXnb5j0yThl+/DBuGmou0MD65/0wZjtgfFM8sx8jPNv8+vFscQ1jk3z/0tdPeGWbenyG75dAuFNS0sPV2nk29VVlm/2rPoGncdDqfzh+qsp1ev3eAhhe0EWDzqfx0Lz83k8OtHpPHSis71UHQ8uj/dzr5YO+ziLyM/rDdedWqQVP59/5hdX9ij1xWxLRzG8PFlNek9DaNm0JI2WAMYoWWKfmO6L3UeR41UJ80GvI65ZQXJ83WCn+3fJPqbAhxxIv4meMz2W6eMgZAn77YPOFYZOe1/jjXwkY69VHthIoMckjJeL3XNg2OjdLjK0nNFsenZQ+gm8aTpznyH6PmAvdn1cI3w62x7AeKgPuB8LOR3V6xfKy4yjo3TUUTr6C70qhn4j+UzgR7prH7+LPcPMf19/2p0+W3qx+8P6PvRmDlt3l+q/39fLah5XVX8Y7y7DwifQfPgedLYX+DTQ2R57sD6L6ZXorK/CdDpfqdj1X8W2U+DxGm9uR7Z0pOOg83nG+D+P69ZH7t3GBLZX36wv4vW1Susje8vVxrQP+y9k/862i/B6Qb8fi4mf6ff1sKznY3oK9rrO+mJ7Z34en/l5/Wzv7P/Y3j/80xf+e/wv/vDS4g3bW9Lv7+Ij8YN+P28Q/8K+DT/Lx/wS6/ZnzLVvymXG3BIrcp/QtKijMTT2L7hbv8y4d2v3PD7aoKbcaYUvahNjXLLN1Xg+dOfgnDG/S6uc4NXOsWtKkG2Vw+8zJQjv9ERfGLCUbZOpITrj5rQ0Htc47tro4TSEEIbJ+2rTeODRrYtomob6qC9ku1xrMB5jXHtiVhdDGCb7DR/Bzs/6QTnC+zW+r12VrmGKY7Bp9cf4vF7CPa07+o6spvMLHS4bpsP6Rr3yDmnE75w1tdREPtADdQSzPgu5fNYHXjYQcmaIHfbF1M7H+md+OQrPhpvcV+WdI4392XgUN8Fn/oI11Zv2V1f4bizS8RhDz1tcYzQWldIfLyePhh+/b8tOtaD1YG1VOU+pjtQveKbcWuZb41IRAtbYawqCDiDGOF+BGsaA8QJ5r/sLtno4n3roqxe97sQFYz93bYCc83/Bmiqo3IwdUg2v8qBy4uT73+iF1sUYnVF2ne3ZKJZWL3oImdhvpAw9r3FwtmOLcXZWLsYtrOS8nnLmVUi+0Ceg+wG5cJ4YD6/7ov7hA2sfz75JmZtxurTyFOTlkXHf5UX3cAP7n6VzcrS/obck+DilcZVxDPL95QSLnh7lcH/k5Ut0EH7oqcVh9PKBs/gl+B3Gp6YasEvGdwe+0zjIWP1xiGuMX4BsmtrKOsdznddqnaP2JO0HmkpF7cv6gpFn+HONr1PkQEWHMdY1whqf2a6LcQqLdW7usc66rCycdZjWxeld89P/Ms53f9QaD213wHkFxn7+Rj+aXRfjsFynf67TptwhvDLJu9N012dbpNglr3FY2c0WnvNcq/iG5zTM07T4j3EZV82/Ep5DGesVLml8Z+zQqFzlXDK+K7RtjU/t34JfYOwdGp8ffmJ7VHJ8C6t85SwXro5enmsvuQpua5wvwZtWUhm3U3DJa9yL5BX3FYXwUGyuIFt6ruNY7efVL4lT7S2m2+slduvdWOF8Cv8MrMcKDy/86H9jPMc7TcUd69QK8W/0Gajsur9gq4ftoYcrr84P9hNX3+6v9qyMM77aap78nKcs/W6W7zAP8sH2BSMfRAfGB77Uj8nl4AMjjrqu7VqEk/ZPoj2LMeKoadfaXk8AWa+2w+rzfLc5+ViLnlAUUJpG7tpwEyG6Rl4UfBhvp3wf2hpnPcE/bU0WF/2JC24+uaz57wIIyVs1c/lGL9nSb/nqer4GebY1/4d+iF92ojwa/EZbWrbz13vn1SPGQ/Doa3wW/y4OWI94PDo2bWn7em94jK+LyaYCmg7Hoa9TLqx/bDaodbl1rcASP1IG0Jmf6Qhxd6tyoN9kVdtRyfwl01WY1jf0SAD3rE1W2inJ9Jyp45T50bGK1nqSN2uHKzotmf9D/8QvG1kfr3fbWF1pTr1K4UkE/X1Dn1A+6NqviCeqD0x65PEKPTmInK8r5qUuhuScxvaKwdPHDLQWapPuzKKGnqGywnc/lVtjmNA3vCf7e11PRdqdirTMnwr93rrY3+eiGx0+pCf7+8lR9Gd+dxHW/n4W+P6ZYaLu9Ga79ZHFg46Cyk2noi3w43WoPee/9BaN+YeOB3rXgs7dbR9swSlTwQn7czkUha2+mR6o4ABTDHrkmF51fhxJ5r+bhLUviPfj/p0f9REBe6WHvObn+Zh/6O/P7yaXh738H45M6+A=###4572:XlxV32DM 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11c4eNqNm0uW9CgOhbfEyxj+WkcvgJeHNetRndp7E5bkgJuKjM7Zl2AbCSEkQRhjzJXG9fpr2TSz8JVNMUp7PJid6S+2zC6apLX767IvHs64u71d7sWmGq+28/PCZ+X3N+qP7c6M+x8pm+PF3RGXaqLWLlwzva8co97cTHhxK6O8uFdiX0b7rT+2pzr6PT6jjx/b5X0iz+Xo+6Kfp7/T+398/9O/k7yJxjtC76t8rty4yLf3x/Zzjvx+f+DvAx95uJVHGOnWf9fbL56v4On92L9w+8HyYf8QSF8yvmb2+cP2R3+D3v/oa4B+hz4+7I/6Ho7sQebv33//juZof8wf/8/fPuQ/vsW//utD+uP++o8P5x/n/vHOl7PZ216PcN3yt8Pe9hqjzke0ZH+JmL7T1++c23eO+Z3DlxgtjbNd97hNtPc4u9fZW+JqrlPjMxPPWVU58TjnQk8aH0WTY6xyBFWOYdOqr1LtueoHOXjia9C4kI9O+v3EtuzjRvbqfFyrHMcmR5hyBF9So+dcuG47HZ705z9xY/1b+g6ybzAuZKeMM5r3OIPZ9X3OcZ6+HImeE32fbI/O6WwN9ZdxCSdLcmC76PuMV9X6y3xJO/bH9mTIPorXOSTinohJD3bq4SA99E0L1vl/5kwkX6Z7PG6H0o0Y2M0um3wbjL/CrRDDGyK02zx7LO3Y/0d7og3yrDrLhlrl+UgsDjAaYmtoA4yFvicOak7YzbMzLdz5intiWD6Ut3neWAt9D/sP3njjYIcM/XOhfuLQsb/ooxcOCGC8PvN4Ejto6I/jxf6V9ScbAupLApLZ22v9C2+48j7sj9/H/mRo7m1o125o9ja0844r7heNiyei8E7PhoQskZFPFLkh+3LdO3WoxL0SV45EfnwP2kVQUTTy3BE2RSFfkfuzovF7cxZJcbyTIstEG7MbinB3tHDEUOZzu6F1NrQP3C82VEeGijx3/NvQZbw4fmxHeWPYFyKO15V9IeJ8zUDckCcjJkPyyw6TvBZZZEPP5UbPtYvsonzgQyLm7TthfifQd6LdPhPnZ+LLXCnQmkJQgNwpkGofeKrjHparOl+RhhWPq2lcWCxx6Pj9FjkQZAeP/ROrd98AjmUjdE3bCKf/pQAi8PI6OGCIOk87ogCC/SzynHYyi+PKGldHZiQbIbIsw1xIDuTp3za5kePQ9BAXPRyXNt9iVo++O8sbaX6QKydW9mR7ALadeNyLffpl4GbHrQ/P+w1yMZQ4+KqzDdT/5P4k5/n2w3Y36+v2wzPSlAl5HHohBR/5d5aME3m43S+ESJF24Iyn9ek5bsXxBgr8+L0PXMvuVwb/X/ygZ38cPzCOB1kMWDZ0ZNQXshiw7FvIxlF/CXBQXxLwiB9FeV3c/Si+z4Y9YCJDSIsfPYuWcdhBz7VGz5WTxzV0loV4Rp1lf/7ErpEflnEjh8SVjE2O/JajVXXdDk5o2X9dnhJY8VfIg9dRPOk55DmqWy0v/dyP+3GrvyTyD9/aXRr3Ntq8zkcjvrg/iVkWMZuWV12FPiNi5kKvcVXnyv1lmMjB7cNCPoI2zPreNdOe/rXbvbhXPkEFmRK4sNTJcZ5O5zCGp7CK/CPySKRvY6kQIfq+BvG39rn9k2LYDjzMRzC7oNg/sCKOxM/LfPP+ju8rJ41H9iHsHwrJN+PoovY3pJ9UWT/QH/WL/WmilgJNK9qyOVlcsacm5pt1rhyOxM6rFFjEHE7nGsAegV2BZQMcVHtc6kPp1MScyyat2goXcY06j3OcbIU3n2nE1bq+tc/JiCSPzins1oV8pN3aSMylfJSSGsSxmJ2Dgjk8CraqznFwMGF5FplFjG/tooYZWneNRexPbEFsZHGSuxqW6lOK2pYWIj0mahCnKGIji1MUMYVFzG/t4jQfX+F0X7OJcZq3E+270Zbbic5MaeZSeRVkJmFlHTiy5RjBHDrPRexXQZBdoP7JU39kz7lcTcy86Up7lr2b26c99vX92N/w+9tBdoX9rSX5R9D7o36wPyn6Vf2KpOgcPpS/zkBZr3x5cLlDRtoSSGp2SbG/bRTdSrvhtOjw7HB4ZlIidhy9vbcbYjEZqcfP8EUdD7ZLvV9Y0tQS9PY5jrJqEvtHSYs6aR715WSbz3p/fD/2l2jfN/o/6gu/h/2fclUjPaA+sZ23q2cJf+LH84E82E6W5t6eqXptHwqu04Kl3P86G3HxOs/0sVAYxu2uk/lkrm58aW+1N9qfKNlBHoaiiFx1LomP1cy1eK6lOFODKmYcdk2i5+5POUTWWU7bsuOkufWtKPKtXU73Mud0yLHtYiGXoIkZ3mLaBOVM9/IbpXEQNvi52nam9yzFF5uNFtVnx8/x6VWtfFr5gSNPk0wzsnXUP1a2IuDM/QvZNI9zKY70oJXcLO9rT/JRaR+UnArZR4pZHR+202fO5TP62VGgx85Aa7VZCo1T/MAc+ners0n0vtf2o7Eb2jCXzNn6U5v9GZ143t6vNUT323vyuxST9szVmnv3ie9kKTUq4nier9PrfPD8WaosfGSxB+Qed/v/wWZfDznsGrNl15hoQrx1dMSyu42yJ8v4Pkn2XCYvi/3DxfbbOAuA/tIeGp+CQX9ZPwfrF/uj/rF/b3tyifIGNvTMxT3s/2P80J8sZUn+u9fiWlkYgzc3WQhX/MCR+LS0+X1iUTOygWlCtk5bOHVdOEnzI87Qc+JHQia/YT+xpAXbd5bcdqjqilyhk88UVovURn4wlwrOg+/aAE931raSD/CM9dqaqyJ3vlOz5a5nX04g1CNqOQGoQSrrZHS56yyhnW9cMOScM1gK9r+1C4uVIM/xbGIh97iLieOXE4yciEkNS247nDabMzUfawovBT1J2ZEbR8Sn44IdsETMNeh8ll0s5Dq02Vxz00sTQwp4T27KuaoEwsjVQO4JLAUWz64W+XC7q0KWzU9c9S1GWi5OQMTCEd7B1WeZDakSi/Z/sGjv5HIXsFQGQtjFEP7W7lAsYO80Me3iquLx2x6f016Gy9t7lrg/Dc3jyayLuiRSEvUgywa7D9evw43atIhnfaquMrtV5172jUpYQidsF7VP6x1af2yXyofsGMhS4Nk8e1oC72rVRRR7XuPls1Aa1K3OkialuKdBwt/aJQ3CtEj4Mkr+kJa4vzo1nm70GRFj+M71Jp0vLU1Ja9iuHmGbCPsgr00J038wr005CkGWtTgC1HjD/9cua/OJv4GTFlakNW1wWtoQ2542VAnSss49gq0DBwNBKvCppQ1pSRvapQ3Tc/ZhA3tIHtbFsSxyh1gY+YCgDDlqSVhaztO66uA77+piNHNS237+Dxyp9PsYCfD7Qq3O7wu0OtsBsSdwLJqYS0g9shZcTdu2FAy9bnyZuVTY4X1g44ld4FPiDxwC3zsFnhsB7WN8uoycDbHcH0Q2jdTaPVU6kcfgCnu63plFWkPyWrR9zhp6j+XnLn6P3d6zhtxJc8wzUt4LP4ELPVVn+cykovFM8eN6KwR58LnLIz5wK5o6+qqOqskx96/IZcT7ufMk9h94uqx9nMDiErO5qsq8D8rtFWQ5ht1us6T1PKhpi7gmMrrn/KAMs50fALvYt6qmLFIvUdaXdlm0H3lAMAqc1Chtjam76qsCFJf5jHR84Ok7jvUYAbnEPcZGfoLPAsEosym7WMinFnPnJeZO+xpNU8z0nk0xynwMuaqUNXaZ2HCihyyz1/hsdrA1yAb4rV1m1/JpXjdQJfnS7qCKgiw7166mJWZvaqIY6ChpOf0jfp/+7TwTvrFlWMD+IA4cmyNbjt5k2MieeRfDvdP+5rWdScSQcCZf9NnE/KOd77kcXWcZtnE690G19PcJyM7H2MXC8YiYcmKF/X3S1LCmNFnPwPg9TwbWdqb3LClDM5pVDPlhhwxXfnDSdQ483MhxDvJc8Zt6kM+4i49sVatYUoZmNauQa06S4MnvpM4PbLnI0tkFIgfDcYRUKoGf3ynwMJGPerXf2BoQG1m1iriWEMdvVhHZ2sQq4nrEntecoWkZWDSwiDobddTZgpHTZ5aYv/ffLpVKMH1wxmWdznMbOtiDDo1Fy41rYq0QP575S7th7cnpKLLMyi7mkjOMqBoni/lU+viQsn3gwpXBcnBlEtiwB07uMcqN5a5s4w1Prp8If2vvcY8WkT3nMFv0mNec4tT2aVGDZHhyZdhFncvz20+a5R/MaplBStHYMcvaFLELr2VsFzVIO/bH9hj3HAN5hgeKmpacYxy/ZZhymiEZpZxeIM84ovJN8VNljv3DoXOCVAq5NcgdgG3RxGzvfbzs5fs8xcy+yD1nuWnhi/zikMML5qfE9qX95Iv6z74a6P1yE6Qb+WEQXwyH/kV+wSgem38wMDIFvzje5yaII8b+Ut7/cXOE+/+QH8ZLalxSsqIeCsvvE+Qznn+wJ1Ec8hF2NSL3tqsFuYxdTTTMsVZgu7YxdY4zJDypY2d6z5LSFKf+LpFTkqdgzIVTKdwiV/59tVwPRR58f+YTx7bfr5FZk/s139plEYr6kLNT1FmWlKeo92UsG5GooZ9s1B84lTH+B9S0pio=###4464:XlxV32DM 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f64=83;pD?;>;|l2f65=83;pD?;>;|l2f62=83;pD?;>;|l2f63=83;pD?;>;|l2f60=83;pD?;>;|l2f61=83;pD?;>;|l2f6>=83;pD?;>;|l2f6?=83;pD?;>;|l2f6g=83;pD?;>;|l2f6d=83;pD?;>;|l2f6e=83;pD?;>;|l2f6b=83;pD?;>;|l2f6c=83;pD?;>;|l2f6`=83;pD?;>;|l2f16=83;pD?;>;|l2f17=83;pD?;>;|l2f14=83;pD?;>;|l2f15=83;pD?;>;|l2f12=83;pD?;>;|l2f13=83;pD?;>;|l2f10=83;pD?;>;|l2f11=83;pD?;>;|l2f1>=83;pD?;>;|l2f1?=83;pD?;>;|l2f1g=83;pD?;>;|l2f1d=83;pD?;>;|l2f1e=83;pD?;>;|l2f1b=83;pD?;>;|l2f1c=83;pD?;>;|l2f1`=83;pD?;>;|l2f06=83;pD?;>;|l2f07=83;pD?;>;|l2f04=83;pD?;>;|l2f05=83;pD?;>;|l2f02=83;pD?;>;|l2f03=83;pD?;>;|l2f00=83;pD?;>;|l2f01=83;pD?;>;|l2f0>=83;pD?;>;|l2f0?=83;pD?;>;|l2f0g=83;pD?;>;|l2f0d=83;pD?;>;|l2f0e=83;pD?;>;|l2f0b=83;pD?;>;|l2f0c=83;pD?;>;|l2f0`=83;pD?;>;|l2f36=83;pD?;>;|l2f37=83;pD?;>;|l2f34=83;pD?;>;|l2f35=83;pD?;>;|l2f32=83;pD?;>;|l2f33=83;pD?;>;|l2f30=83;pD?;>;|l2f31=83;pD?;>;|l2f3>=83;pD?;>;|l2f3?=83;pD?;>;|l2f3g=83;pD?;>;|l2f3d=83;pD?;>;|l2f3e=83;pD?;>;|l2f3b=83;pD?;>;|l2f3c=83;pD?;>;|l2f3`=83;pD?;>;|l2f26=83;pD?;>;|l2f27=83;pD?;>;|l2f24=83;pD?;>;|l2f25=83;pD?;>;|l2f22=83;pD?;>;|l2f23=83;pD?;>;|l2f20=83;pD?;>;|l2f21=83;pD?;>;|l2f2>=83;pD?;>;|l2f2?=83;pD?;>;|l2f2g=83;pD?;>;|l2f2d=83;pD?;>;|l2f2e=83;pD?;>;|l2f2b=83;pD?;>;|l2f2c=83;pD?;>;|l2f2`=83;pD?;>;|l2f=6=83;pD?;>;|l2f=7=83;pD?;>;|l2f=4=83;pD?;>;|l2f=5=83;pD?;>;|l2f=2=83;pD?;>;|l2f=3=83;pD?;>;|l2f=0=83;pD?;>;|l2f=1=83;pD?;>;|l2f=>=83;pD?;>;|l2f=?=83;pD?;>;|l2f=g=83;pD?;>;|l2f=d=83;pD?;>;|l2f=e=83;pD?;>;|l2f=b=83;pD?;>;|l2f=c=83;pD?;>;|l2f=`=83;pD?;>;|l2f<6=83;pD?;>;|l2f<7=83;pD?;>;|l2f<4=83;pD?;>;|l2f<5=83;pD?;>;|l2f<2=83;pD?;>;|l2f<3=83;pD?;>;|l2f<0=83;pD?;>;|l2f<1=83;pD?;>;|l2f<>=83;pD?;>;|l2f;|l2f;|l2f;|l2f;|l2f;|l2f;|l2f<`=83;pD?;>;|l2fd6=83;pD?;>;|l2fd7=83;pD?;>;|l2fd4=83;pD?;>;|l2fd5=83;pD?;>;|l2fd2=83;pD?;>;|l2fd3=83;pD?;>;|l2fd0=83;pD?;>;|l2fd1=83;pD?;>;|l2fd>=83;pD?;>;|l2fd?=83;pD?;>;|l2fdg=83;pD?;>;|l2fdd=83;pD?;>;|l2fde=83;pD?;>;|l2fdb=83;pD?;>;|l2fdc=83;pD?;>;|l2fd`=83;pD?;>;|l2fg6=83;pD?;>;|l2fg7=83;pD?;>;|l2fg4=83;pD?;>;|l2fg5=83;pD?;>;|l2fg2=83;pD?;>;|l2fg3=83;pD?;>;|l2fg0=83;pD?;>;|l2fg1=83;pD?;>;|l2fg>=83;pD?;>;|l2fg?=83;pD?;>;|l2fgg=83;pD?;>;|l2fgd=83;pD?;>;|l2fge=83;pD?;>;|l2fgb=83;pD?;>;|l2fgc=83;pD?;>;|l2fg`=83;pD?;>;|l2ff6=83;pD?;>;|l2ff7=83;pD?;>;|l2ff4=83;pD?;>;|l2ff5=83;pD?;>;|l2ff2=83;pD?;>;|l2ff3=83;pD?;>;|l2ff0=83;pD?;>;|l2ff1=83;pD?;>;|l2ff>=83;pD?;>;|l2ff?=83;pD?;>;|l2ffg=83;pD?;>;|l2ffd=83;pD?;>;|l2ffe=83;pD?;>;|l2ffb=83;pD?;>;|l2ffc=83;pD?;>;|l2ff`=83;pD?;>;|l2fa6=83;pD?;>;|l2fa7=83;pD?;>;|l2fa4=83;pD?;>;|l2fa5=83;pD?;>;|l2fa2=83;pD?;>;|l2fa3=83;pD?;>;|l2fa0=83;pD?;>;|l2fa1=83;pD?;>;|l2fa>=83;pD?;>;|l2fa?=83;pD?;>;|l2fag=83;pD?;>;|l2fad=83;pD?;>;|l2fae=83;pD?;>;|l2fab=83;pD?;>;|l2fac=83;pD?;>;|l2fa`=83;pD?;>;|l2f`6=83;pD?;>;|l2f`7=83;pD?;>;|l2f`4=83;pD?;>;|l2f`5=83;pD?;>;|l2f`2=83;pD?;>;|l2f`3=83;pD?;>;|l2f`0=83;pD?;>;|l2f`1=83;pD?;>;|l2f`>=83;pD?;>;|l2f`?=83;pD?;>;|l2f`g=83;pD?;>;|l2f`d=83;pD?;>;|l2f`e=83;pD?;>;|l2f`b=83;pD?;>;|l2f`c=83;pD?;>;|l2f``=83;pD?;>;|l2fc6=83;pD?;>;|l2fc7=83;pD?;>;|l2fc4=83;pD?;>;|l2fc5=83;pD?;>;|l2fc2=83;pD?;>;|l2fc3=83;pD?;>;|l2fc0=83;pD?;>;|l2fc1=83;pD?;>;|l2fc>=83;pD?;>;|l2fc?=83;pD?;>;|l2fcg=83;pD?;>;|l2fcd=83;pD?;>;|l2fce=83;pD?;>;|l2fcb=83;pD?;>;|l2fcc=83;pD?;>;|l2fc`=83;pD?;>;|l2g56=83;pD?;>;|l2g57=83;pD?;>;|l2g54=83;pD?;>;|l2g55=83;pD?;>;|l2g52=83;pD?;>;|l2g53=83;pD?;>;|l2g50=83;pD?;>;|l2g51=83;pD?;>;|l2g5>=83;pD?;>;|l2g5?=83;pD?;>;|l2g5g=83;pD?;>;|l2g5d=83;pD?;>;|l2g5e=83;pD?;>;|l2g5b=83;pD?;>;|l2g5c=83;pD?;>;|l2g5`=83;pD?;>;|l2g46=83;pD?;>;|l2g47=83;pD?;>;|l2g44=83;pD?;>;|l2g45=83;pD?;>;|l2g42=83;pD?;>;|l2g43=83;pD?;>;|l2g40=83;pD?;>;|l2g41=83;pD?;>;|l2g4>=83;pD?;>;|l2g4?=83;pD?;>;|l2g4g=83;pD?;>;|l2g4d=83;pD?;>;|l2g4e=83;pD?;>;|l2g4b=83;pD?;>;|l2g4c=83;pD?;>;|l2g4`=83;pD?;>;|l2g76=83;pD?;>;|l2g77=83;pD?;>;|l2g74=83;pD?;>;|l2g75=83;pD?;>;|l2g72=83;pD?;>;|l2g73=83;pD?;>;|l2g70=83;pD?;>;|l2g71=83;pD?;>;|l2g7>=83;pD?;>;|l2g7?=83;pD?;>;|l2g7g=83;pD?;>;|l2g7d=83;pD?;>;|l2g7e=83;pD?;>;|l2g7b=83;pD?;>;|l2g7c=83;pD?;>;|l2g7`=83;pD?;>;|l2g66=83;pD?;>;|l2g67=83;pD?;>;|l2g64=83;pD?;>;|l2g65=83;pD?;>;|l2g62=83;pD?;>;|l2g63=83;pD?;>;|l2g60=83;pD?;>;|l2g61=83;pD?;>;|l2g6>=83;pD?;>;|l2g6?=83;pD?;>;|l2g6g=83;pD?;>;|l2g6d=83;pD?;>;|l2g6e=83;pD?;>;|l2g6b=83;pD?;>;|l2g6c=83;pD?;>;|l2g6`=83;pD?;>;|l2g16=83;pD?;>;|l2g17=83;pD?;>;|l2g14=83;pD?;>;|l2g15=83;pD?;>;|l2g12=83;pD?;>;|l2g13=83;pD?;>;|l2g10=83;pD?;>;|l2g11=83;pD?;>;|l2g1>=83;pD?;>;|l2g1?=83;pD?;>;|l2g1g=83;pD?;>;|l2g1d=83;pD?;>;|l2g1e=83;pD?;>;|l2g1b=83;pD?;>;|l2g1c=83;pD?;>;|l2g1`=83;pD?;>;|l2g06=83;pD?;>;|l2g07=83;pD?;>;|l2g04=83;pD?;>;|l2g05=83;pD?;>;|l2g02=83;pD?;>;|l2g03=83;pD?;>;|l2g00=83;pD?;>;|l2g01=83;pD?;>;|l2g0>=83;pD?;>;|l2g0?=83;pD?;>;|l2g0g=83;pD?;>;|l2g0d=83;pD?;>;|l2g0e=83;pD?;>;|l2g0b=83;pD?;>;|l2g0c=83;pD?;>;|l2g0`=83;pD?;>;|l2g36=83;pD?;>;|l2g37=83;pD?;>;|l2g34=83;pD?;>;|l2g35=83;pD?;>;|l2g32=83;pD?;>;|l2g33=83;pD?;>;|l2g30=83;pD?;>;|l2g31=83;pD?;>;|l2g3>=83;pD?;>;|l2g3?=83;pD?;>;|l2g3g=83;pD?;>;|l2g3d=83;pD?;>;|l2g3e=83;pD?;>;|l2g3b=83;pD?;>;|l2g3c=83;pD?;>;|l2g3`=83;pD?;>;|l2g26=83;pD?;>;|l2g27=83;pD?;>;|l2g24=83;pD?;>;|l2g25=83;pD?;>;|l2g22=83;pD?;>;|l2g23=83;pD?;>;|l2g20=83;pD?;>;|l2g21=83;pD?;>;|l2g2>=83;pD?;>;|l2g2?=83;pD?;>;|l2g2g=83;pD?;>;|l2g2d=83;pD?;>;|l2g2e=83;pD?;>;|l2g2b=83;pD?;>;|l2g2c=83;pD?;>;|l2g2`=83;pD?;>;|l2g=6=83;pD?;>;|l2g=7=83;pD?;>;|l2g=4=83;pD?;>;|l2g=5=83;pD?;>;|l2g=2=83;pD?;>;|l2g=3=83;pD?;>;|l2g=0=83;pD?;>;|l2g=1=83;pD?;>;|l2g=>=83;pD?;>;|l2g=?=83;pD?;>;|l2g=g=83;pD?;>;|l2g=d=83;pD?;>;|l2g=e=83;pD?;>;|l2g=b=83;pD?;>;|l2g=c=83;pD?;>;|l2g=`=83;pD?;>;|l2g<6=83;pD?;>;|l2g<7=83;pD?;>;|l2g<4=83;pD?;>;|l2g<5=83;pD?;>;|l2g<2=83;pD?;>;|l2g<3=83;pD?;>;|l2g<0=83;pD?;>;|l2g<1=83;pD?;>;|l2g<>=83;pD?;>;|l2g;|l2g;|l2g;|l2g;|l2g;|l2g;|l2g<`=83;pD?;>;|l2gd6=83;pD?;>;|l2gd7=83;pD?;>;|l2gd4=83;pD?;>;|l2gd5=83;pD?;>;|l2gd2=83;pD?;>;|l2gd3=83;pD?;>;|l2gd0=83;pD?;>;|l2gd1=83;pD?;>;|l2gd>=83;pD?;>;|l2gd?=83;pD?;>;|l2gdg=83;pD?;>;|l2gdd=83;pD?;>;|l2gde=83;pD?;>;|l2gdb=83;pD?;>;|l2gdc=83;pD?;>;|l2gd`=83;pD?;>;|l2gg6=83;pD?;>;|l2gg7=83;pD?;>;|l2gg4=83;pD?;>;|l2gg5=83;pD?;>;|l2gg2=83;pD?;>;|l2gg3=83;pD?;>;|l2gg0=83;pD?;>;|l2gg1=83;pD?;>;|l2gg>=83;pD?;>;|l2gg?=83;pD?;>;|l2ggg=83;pD?;>;|l2ggd=83;pD?;>;|l2gge=83;pD?;>;|l2ggb=83;pD?;>;|l2ggc=83;pD?;>;|l2gg`=83;pD?;>;|l2gf6=83;pD?;>;|l2gf7=83;pD?;>;|l2gf4=83;pD?;>;|l2gf5=83;pD?;>;|l2gf2=83;pD?;>;|l2gf3=83;pD?;>;|l2gf0=83;pD?;>;|l2gf1=83;pD?;>;|l2gf>=83;pD?;>;|l2gf?=83;pD?;>;|l2gfg=83;pD?;>;|l2gfd=83;pD?;>;|l2gfe=83;pD?;>;|l2gfb=83;pD?;>;|l2gfc=83;pD?;>;|l2gf`=83;pD?;>;|l2ga6=83;pD?;>;|l2ga7=83;pD?;>;|l2ga4=83;pD?;>;|l2ga5=83;pD?;>;|l2ga2=83;pD?;>;|l2ga3=83;pD?;>;|l2ga0=83;pD?;>;|l2ga1=83;pD?;>;|l2ga>=83;pD?;>;|l2ga?=83;pD?;>;|l2gag=83;pD?;>;|l2gad=83;pD?;>;|l2gae=83;pD?;>;|l2gab=83;pD?;>;|l2gac=83;pD?;>;|l2ga`=83;pD?;>;|l2g`6=83;pD?;>;|l2g`7=83;pD?;>;|l2g`4=83;pD?;>;|l2g`5=83;pD?;>;|l2g`2=83;pD?;>;|l2g`3=83;pD?;>;|l2g`0=83;pD?;>;|l2g`1=83;pD?;>;|l2g`>=83;pD?;>;|l2g`?=83;pD?;>;|l2g`g=83;pD?;>;|l2g`d=83;pD?;>;|l2g`e=83;pD?;>;|l2g`b=83;pD?;>;|l2g`c=83;pD?;>;|l2g``=83;pD?;>;|l2gc6=83;pD?;>;|l2gc7=83;pD?;>;|l2gc4=83;pD?;>;|l2gc5=83;pD?;>;|l2gc2=83;pD?;>;|l2gc3=83;pD?;>;|l2gc0=83;pD?;>;|l2gc1=83;pD?;>;|l2gc>=83;pD?;>;|l2gc?=83;pD?;>;|l2gcg=83;pD?;>;|l2gcd=83;pD?;>;|l2gce=83;pD?;>;|l2gcb=83;pD?;>;|l2gcc=83;pD?;>;|l2gc`=83;pD?;>;|l2`56=83;pD?;>;|l2`57=83;pD?;>;|l2`54=83;pD?;>;|l2`55=83;pD?;>;|l2`52=83;pD?;>;|l2`53=83;pD?;>;|l2`50=83;pD?;>;|l2`51=83;pD?;>;|l2`5>=83;pD?;>;|l2`5?=83;pD?;>;|l2`5g=83;pD?;>;|l2`5d=83;pD?;>;|l2`5e=83;pD?;>;|l2`5b=83;pD?;>;|l2`5c=83;pD?;>;|l2`5`=83;pD?;>;|l2`46=83;pD?;>;|l2`47=83;pD?;>;|l2`44=83;pD?;>;|l2`45=83;pD?;>;|l2`42=83;pD?;>;|l2`43=83;pD?;>;|l2`40=83;pD?;>;|l2`41=83;pD?;>;|l2`4>=83;pD?;>;|l2`4?=83;pD?;>;|l2`4g=83;pD?;>;|l2`4d=83;pD?;>;|l2`4e=83;pD?;>;|l2`4b=83;pD?;>;|l2`4c=83;pD?;>;|l2`4`=83;pD?;>;|l2`76=83;pD?;>;|l2`77=83;pD?;>;|l2`74=83;pD?;>;|l2`75=83;pD?;>;|l2`72=83;pD?;>;|l2`73=83;pD?;>;|l2`70=83;pD?;>;|l2`71=83;pD?;>;|l2`7>=83;pD?;>;|l2`7?=83;pD?;>;|l2`7g=83;pD?;>;|l2`7d=83;pD?;>;|l2`7e=83;pD?;>;|l2`7b=83;pD?;>;|l2`7c=83;pD?;>;|l2`7`=83;pD?;>;|l2`66=83;pD?;>;|l2`67=83;pD?;>;|l2`64=83;pD?;>;|l2`65=83;pD?;>;|l2`62=83;pD?;>;|l2`63=83;pD?;>;|l2`60=83;pD?;>;|l2`61=83;pD?;>;|l2`6>=83;pD?;>;|l2`6?=83;pD?;>;|l2`6g=83;pD?;>;|l2`6d=83;pD?;>;|l2`6e=83;pD?;>;|l2`6b=83;pD?;>;|l2`6c=83;pD?;>;|l2`6`=83;pD?;>;|l2`16=83;pD?;>;|l2`17=83;pD?;>;|l2`14=83;pD?;>;|l2`15=83;pD?;>;|l2`12=83;pD?;>;|l2`13=83;pD?;>;|l2`10=83;pD?;>;|l2`11=83;pD?;>;|l2`1>=83;pD?;>;|l2`1?=83;pD?;>;|l2`1g=83;pD?;>;|l2`1d=83;pD?;>;|l2`1e=83;pD?;>;|l2`1b=83;pD?;>;|l2`1c=83;pD?;>;|l2`1`=83;pD?;>;|l2`06=83;pD?;>;|l2`07=83;pD?;>;|l2`04=83;pD?;>;|l2`05=83;pD?;>;|l2`02=83;pD?;>;|l2`03=83;pD?;>;|l2`00=83;pD?;>;|l2`01=83;pD?;>;|l2`0>=83;pD?;>;|l2`0?=83;pD?;>;|l2`0g=83;pD?;>;|l2`0d=83;pD?;>;|l2`0e=83;pD?;>;|l2`0b=83;pD?;>;|l2`0c=83;pD?;>;|l2`0`=83;pD?;>;|l2`36=83;pD?;>;|l2`37=83;pD?;>;|l2`34=83;pD?;>;|l2`35=83;pD?;>;|l2`32=83;pD?;>;|l2`33=83;pD?;>;|l2`30=83;pD?;>;|l2`31=83;pD?;>;|l2`3>=83;pD?;>;|l2`3?=83;pD?;>;|l2`3g=83;pD?;>;|l2`3d=83;pD?;>;|l2`3e=83;pD?;>;|l2`3b=83;pD?;>;|l2`3c=83;pD?;>;|l2`3`=83;pD?;>;|l2`26=83;pD?;>;|l2`27=83;pD?;>;|l2`24=83;pD?;>;|l2`25=83;pD?;>;|l2`22=83;pD?;>;|l2`23=83;pD?;>;|l2`20=83;pD?;>;|l2`21=83;pD?;>;|l2`2>=83;pD?;>;|l2`2?=83;pD?;>;|l2`2g=83;pD?;>;|l2`2d=83;pD?;>;|l2`2e=83;pD?;>;|l2`2b=83;pD?;>;|l2`2c=83;pD?;>;|l2`2`=83;pD?;>;|l2`=6=83;pD?;>;|l2`=7=83;pD?;>;|l2`=4=83;pD?;>;|l2`=5=83;pD?;>;|l2`=2=83;pD?;>;|l2`=3=83;pD?;>;|l2`=0=83;pD?;>;|l2`=1=83;pD?;>;|l2`=>=83;pD?;>;|l2`=?=83;pD?;>;|l2`=g=83;pD?;>;|l2`=d=83;pD?;>;|l2`=e=83;pD?;>;|l2`=b=83;pD?;>;|l2`=c=83;pD?;>;|l2`=`=83;pD?;>;|l2`<6=83;pD?;>;|l2`<7=83;pD?;>;|l2`<4=83;pD?;>;|l2`<5=83;pD?;>;|l2`<2=83;pD?;>;|l2`<3=83;pD?;>;|l2`<0=83;pD?;>;|l2`<1=83;pD?;>;|l2`<>=83;pD?;>;|l2`;|l2`;|l2`;|l2`;|l2`;|l2`;|l2`<`=83;pD?;>;|l2`d6=83;pD?;>;|l2`d7=83;pD?;>;|l2`d4=83;pD?;>;|l2`d5=83;pD?;>;|l2`d2=83;pD?;>;|l2`d3=83;pD?;>;|l2`d0=83;pD?;>;|l2`d1=83;pD?;>;|l2`d>=83;pD?;>;|l2`d?=83;pD?;>;|l2`dg=83;pD?;>;|l2`dd=83;pD?;>;|l2`de=83;pD?;>;|l2`db=83;pD?;>;|l2`dc=83;pD?;>;|l2`d`=83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| Local| | 9 | 0.715 | 2.527 | ++---------------------+--------------+------+------+------------+-------------+ +| vga/crt/_or0000 | Local| | 2 | 0.000 | 0.700 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + + + The Delay Summary Report + + +The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 + + The AVERAGE CONNECTION DELAY for this design is: 2.379 + The MAXIMUM PIN DELAY IS: 7.048 + The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 6.411 + + Listing Pin Delays by value: (nsec) + + d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 8.00 d >= 8.00 + --------- --------- --------- --------- --------- --------- + 574 826 763 511 459 0 + +Timing Score: 0 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +------------------------------------------------------------------------------------------------------ + Constraint | Requested | Actual | Logic | Absolute |Number of + | | | Levels | Slack |errors +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net gra | N/A | 11.183ns | 5 | N/A | N/A + y_cnt_FFd1 | | | | | +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net vga | N/A | 8.284ns | 4 | N/A | N/A + /crtclk | | | | | +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net clk | N/A | 7.120ns | 1 | N/A | N/A + a_BUFGP | | | | | +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net vga | N/A | 10.431ns | 0 | N/A | N/A + /crt/ram_wclk | | | | | +------------------------------------------------------------------------------------------------------ + Autotimespec constraint for clock net vga | N/A | 9.916ns | 4 | N/A | N/A + /vgacore/hblank | | | | | +------------------------------------------------------------------------------------------------------ + + +All constraints were met. +INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the + constraint does not cover any paths or that it has no requested value. + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 22 secs +Total CPU time to PAR completion: 20 secs + +Peak Memory Usage: 323 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 0 +Number of info messages: 1 + +Writing design to file fpga.ncd + + + +PAR done! diff --git a/xilinx/vga/fpga.pcf b/xilinx/vga/fpga.pcf new file mode 100644 index 0000000..704ebae --- /dev/null +++ b/xilinx/vga/fpga.pcf @@ -0,0 +1,29 @@ +//! ************************************************************************** +// Written by: Map I.31 on Mon Jan 01 22:22:14 2007 +//! ************************************************************************** + +SCHEMATIC START; +COMP "ps2_clk" LOCATE = SITE "F4" LEVEL 1; +COMP "fpga_d1" LOCATE = SITE "E16" LEVEL 1; +COMP "fpga_d2" LOCATE = SITE "F15" LEVEL 1; +COMP "fpga_d3" LOCATE = SITE "G16" LEVEL 1; +COMP "fpga_d4" LOCATE = SITE "J16" LEVEL 1; +COMP "fpga_d5" LOCATE = SITE "M16" LEVEL 1; +COMP "fpga_d6" LOCATE = SITE "N16" LEVEL 1; +COMP "fpga_d7" LOCATE = SITE "N14" LEVEL 1; +COMP "ps2_data" LOCATE = SITE "E1" LEVEL 1; +COMP "fpga_din_d0" LOCATE = SITE "D14" LEVEL 1; +COMP "vga_blue0" LOCATE = SITE "H4" LEVEL 1; +COMP "vga_blue1" LOCATE = SITE "K3" LEVEL 1; +COMP "vga_vsync_n" LOCATE = SITE "K1" LEVEL 1; +COMP "vga_blue2" LOCATE = SITE "L5" LEVEL 1; +COMP "vga_hsync_n" LOCATE = SITE "K4" LEVEL 1; +COMP "clka" LOCATE = SITE "R8" LEVEL 1; +COMP "vga_red0" LOCATE = SITE "J1" LEVEL 1; +COMP "vga_red1" LOCATE = SITE "M1" LEVEL 1; +COMP "vga_red2" LOCATE = SITE "T2" LEVEL 1; +COMP "reset_n" LOCATE = SITE "E3" LEVEL 1; +COMP "vga_green0" LOCATE = SITE "H2" LEVEL 1; +COMP "vga_green1" LOCATE = SITE "K5" LEVEL 1; +COMP "vga_green2" LOCATE = SITE "R1" LEVEL 1; +SCHEMATIC END; diff --git a/xilinx/vga/fpga.prj b/xilinx/vga/fpga.prj new file mode 100644 index 0000000..03140ef --- /dev/null +++ b/xilinx/vga/fpga.prj @@ -0,0 +1,2 @@ +verilog work "../../v/vga.v" +verilog work "../../v/fpga.v" diff --git a/xilinx/vga/fpga.stx b/xilinx/vga/fpga.stx new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/vga/fpga.syr b/xilinx/vga/fpga.syr new file mode 100644 index 0000000..0abf6e4 --- /dev/null +++ b/xilinx/vga/fpga.syr @@ -0,0 +1,967 @@ +Release 8.2i - xst I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to ./xst/projnav.tmp +CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 2.00 s + +--> +Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.08 s | Elapsed : 0.00 / 2.00 s + +--> +Reading design: fpga.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "fpga.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "fpga" +Output Format : NGC +Target Device : xc2s200-5-fg256 + +---- Source Options +Top Module Name : fpga +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +FSM Style : lut +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : YES +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : YES +Resource Sharing : YES +Multiplier Style : lut +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100 +Add Generic Clock Buffer(BUFG) : 4 +Register Duplication : YES +Slice Packing : YES +Pack IO Registers into IOBs : auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : NO +RTL Output : Yes +Global Optimization : AllClockNets +Write Timing Constraints : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : maintain +Slice Utilization Ratio : 100 +Slice Utilization Ratio Delta : 5 + +---- Other Options +lso : fpga.lso +Read Cores : YES +cross_clock_analysis : NO +verilog2001 : YES +safe_implementation : No +Optimize Instantiated Primitives : NO +tristate2logic : Yes +use_clock_enable : Yes +use_sync_set : Yes +use_sync_reset : Yes + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling verilog file "../../v/vga.v" in library work +Compiling verilog include file "../../v/vgacore.v" +Compiling verilog include file "../../v/crt.v" +Module compiled +Compiling verilog include file "../../v/video_ram.v" +Module compiled +Compiling verilog include file "../../v/char_rom.v" +Module compiled +Compiling verilog include file "../../v/ps2.v" +Module compiled +Compiling verilog include file "../../v/scancode.v" +Compiling verilog include file "../../v/scancode_rom.v" +Module compiled +Module compiled +Module compiled +Compiling verilog file "../../v/fpga.v" in library work +Module compiled +Module compiled +No errors in compilation +Analysis of file <"fpga.prj"> succeeded. + + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library . + +Analyzing hierarchy for module in library with parameters. + V_SIZE = "00000000000000000000000111100000" + H_SIZE = "00000000000000000000001010000000" + +Analyzing hierarchy for module in library with parameters. + PS2_FREQ = "00000000000000000000000000001010" + KEY_RELEASE = "11110000" + FREQ = "00000000000000000110000110101000" + TIMEOUT = "00000000000000000000100111000100" + +Analyzing hierarchy for module in library with parameters. + C_INIT = "000" + C_HOLD = "101" + C_RELEASE = "100" + C_KEYRELEASE = "011" + C_KEYPRESS = "010" + C_IDLE = "001" + +Analyzing hierarchy for module in library with parameters. + T_RESET = "0000" + T_WRITE = "0101" + T_SCROLL = "1000" + T_CLEARALL = "0001" + LINES = "011001" + COLS = "1010000" + T_CLEARLAST_DONE = "1100" + T_CLEARLAST = "1001" + T_CLEARALL_NEXT = "0010" + T_IDLE = "0011" + T_CLEARLAST_WRITE = "1010" + T_CLEARLAST_NEXT = "1011" + T_PREWRITE = "0100" + T_POSTWRITE = "0110" + T_NEWLINE = "0111" + +Analyzing hierarchy for module in library . + +Building hierarchy successfully finished. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing top module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + H_SIZE = 32'sb00000000000000000000001010000000 + V_SIZE = 32'sb00000000000000000000000111100000 +Module is correct for synthesis. + +Analyzing module in library . + FREQ = 32'sb00000000000000000110000110101000 + PS2_FREQ = 32'sb00000000000000000000000000001010 + TIMEOUT = 32'sb00000000000000000000100111000100 + KEY_RELEASE = 8'b11110000 +Module is correct for synthesis. + +Analyzing module in library . + C_INIT = 3'b000 + C_IDLE = 3'b001 + C_KEYPRESS = 3'b010 + C_KEYRELEASE = 3'b011 + C_RELEASE = 3'b100 + C_HOLD = 3'b101 +"../../v/scancode.v" line 151: Found Full Case directive in module . +Module is correct for synthesis. + +Analyzing module in library . +Module is correct for synthesis. + +Analyzing module in library . + T_RESET = 4'b0000 + T_CLEARALL = 4'b0001 + T_CLEARALL_NEXT = 4'b0010 + T_IDLE = 4'b0011 + T_PREWRITE = 4'b0100 + T_WRITE = 4'b0101 + T_POSTWRITE = 4'b0110 + T_NEWLINE = 4'b0111 + T_SCROLL = 4'b1000 + T_CLEARLAST = 4'b1001 + T_CLEARLAST_WRITE = 4'b1010 + T_CLEARLAST_NEXT = 4'b1011 + T_CLEARLAST_DONE = 4'b1100 + COLS = 7'b1010000 + LINES = 6'b011001 +"../../v/crt.v" line 220: Found Full Case directive in module . +Module is correct for synthesis. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "../../v/char_rom.v". + Found 1024x8-bit ROM for signal . + Summary: + inferred 1 ROM(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/video_ram.v". + Found 2049x8-bit dual-port block RAM for signal . + ----------------------------------------------------------------------- + | ram_style | Auto | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 2049-word x 8-bit | | + | mode | write-first | | + | clkA | connected to signal | rise | + | weA | connected to signal | low | + | addrA | connected to signal | | + | diA | connected to signal | | + ----------------------------------------------------------------------- + | Port B | + | aspect ratio | 2049-word x 8-bit | | + | clkB | connected to signal | rise | + | addrB | connected to signal | | + | doB | connected to signal | | + ----------------------------------------------------------------------- + Found 12-bit register for signal . + Summary: + inferred 1 RAM(s). + inferred 12 D-type flip-flop(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/vgacore.v". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 10-bit comparator greatequal for signal <$cmp_ge0000> created at line 131. + Found 11-bit comparator greatequal for signal <$cmp_ge0001> created at line 145. + Found 11-bit comparator greatequal for signal <$cmp_ge0002> created at line 109. + Found 10-bit comparator greatequal for signal <$cmp_ge0003> created at line 123. + Found 11-bit comparator less for signal <$cmp_lt0000> created at line 137. + Found 10-bit comparator less for signal <$cmp_lt0001> created at line 131. + Found 11-bit comparator less for signal <$cmp_lt0002> created at line 79. + Found 10-bit comparator less for signal <$cmp_lt0003> created at line 95. + Found 11-bit comparator less for signal <$cmp_lt0004> created at line 109. + Found 10-bit comparator less for signal <$cmp_lt0005> created at line 123. + Found 11-bit up counter for signal . + Found 10-bit up counter for signal . + Summary: + inferred 2 Counter(s). + inferred 4 D-type flip-flop(s). + inferred 10 Comparator(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/ps2.v". +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:653 - Signal is used but never assigned. Tied to value 0. + Found 14-bit adder for signal <$addsub0000> created at line 93. + Found 4-bit adder for signal <$addsub0001> created at line 103. + Found 4-bit register for signal . + Found 4-bit 4-to-1 multiplexer for signal . + Found 1-bit register for signal . + Found 5-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 14-bit register for signal . + Summary: + inferred 35 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 4 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/crt.v". +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 13 | + | Transitions | 24 | + | Inputs | 8 | + | Outputs | 13 | + | Clock | clock (rising_edge) | + | Reset | reset_n (negative) | + | Reset type | asynchronous | + | Reset State | 0000 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4x1-bit ROM for signal . +WARNING:Xst:737 - Found 1-bit latch for signal . +INFO:Xst:2371 - HDL ADVISOR - Logic functions respectively driving the data and gate enable inputs of this latch share common terms. This situation will potentially lead to setup/hold violations and, as a result, to simulation problems. This situation may come from an incomplete case statement (all selector values are not covered). You should carefully review if it was in your intentions to describe such a latch. + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 12-bit adder for signal . + Found 12-bit adder for signal <$addsub0000>. + Found 12-bit adder for signal <$addsub0001> created at line 102. + Found 8-bit adder for signal <$addsub0002>. + Found 7-bit up counter for signal . + Found 6-bit up counter for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 3-bit up counter for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 ROM(s). + inferred 3 Counter(s). + inferred 22 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/scancode_rom.v". +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/scancode.v". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 6 | + | Transitions | 14 | + | Inputs | 8 | + | Outputs | 5 | + | Clock | clock (rising_edge) | + | Reset | reset_n (negative) | + | Reset type | asynchronous | + | Reset State | 000 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 4x1-bit ROM for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit subtractor for signal <$addsub0000> created at line 135. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit up counter for signal . + Found 1-bit register for signal . + Found 7-bit register for signal . + Found 1-bit register for signal . + Summary: + inferred 1 Finite State Machine(s). + inferred 1 ROM(s). + inferred 1 Counter(s). + inferred 21 D-type flip-flop(s). + inferred 1 Adder/Subtractor(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/vga.v". +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. +WARNING:Xst:646 - Signal > is assigned but never used. + Found 7-bit comparator equal for signal <$cmp_eq0001> created at line 159. + Found 6-bit comparator equal for signal <$cmp_eq0002> created at line 159. + Found 8-bit 4-to-1 multiplexer for signal <$mux0002>. + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit up counter for signal . + Found 8-bit register for signal . + Found 9-bit register for signal . + Found 12-bit adder for signal . + Found 8-bit register for signal . + Found 12-bit adder for signal . + Summary: + inferred 1 Counter(s). + inferred 36 D-type flip-flop(s). + inferred 2 Adder/Subtractor(s). + inferred 2 Comparator(s). + inferred 8 Multiplexer(s). +Unit synthesized. + + +Synthesizing Unit . + Related source file is "../../v/fpga.v". + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 4 | + | Inputs | 0 | + | Outputs | 2 | + | Clock | clka (rising_edge) | + | Reset | reset_n (negative) | + | Reset type | asynchronous | + | Reset State | 00 | + | Encoding | automatic | + | Implementation | LUT | + ----------------------------------------------------------------------- + Summary: + inferred 1 Finite State Machine(s). +Unit synthesized. + +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 1 + 2049x8-bit dual-port block RAM : 1 +# ROMs : 3 + 1024x8-bit ROM : 1 + 4x1-bit ROM : 2 +# Adders/Subtractors : 9 + 12-bit adder : 5 + 14-bit adder : 1 + 4-bit adder : 1 + 8-bit adder : 1 + 8-bit subtractor : 1 +# Counters : 7 + 10-bit up counter : 1 + 11-bit up counter : 1 + 3-bit up counter : 3 + 6-bit up counter : 1 + 7-bit up counter : 1 +# Registers : 30 + 1-bit register : 17 + 10-bit register : 1 + 12-bit register : 2 + 14-bit register : 1 + 4-bit register : 1 + 5-bit register : 1 + 7-bit register : 1 + 8-bit register : 5 + 9-bit register : 1 +# Latches : 1 + 1-bit latch : 1 +# Comparators : 12 + 10-bit comparator greatequal : 2 + 10-bit comparator less : 3 + 11-bit comparator greatequal : 2 + 11-bit comparator less : 3 + 6-bit comparator equal : 1 + 7-bit comparator equal : 1 +# Multiplexers : 2 + 4-bit 4-to-1 multiplexer : 1 + 8-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + 00 | 00 + 01 | 01 + 11 | 11 + 10 | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------- + State | Encoding +------------------- + 000 | 000001 + 001 | 000010 + 010 | 010000 + 011 | 001000 + 100 | 000100 + 101 | 100000 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +------------------------ + State | Encoding +------------------------ + 0000 | 0000000000001 + 0001 | 0000000000010 + 0010 | 0000000000100 + 0011 | 0000000001000 + 0100 | 0000000010000 + 0101 | 0000000100000 + 0110 | 0000001000000 + 0111 | 0000010000000 + 1000 | 0000100000000 + 1001 | 0001000000000 + 1010 | 0010000000000 + 1011 | 0100000000000 + 1100 | 1000000000000 +------------------------ +Loading device for application Rf_Device from file 'v200.nph' in environment /opt/Xilinx. +WARNING:Xst:1291 - FF/Latch is unconnected in block . +INFO:Xst:2261 - The FF/Latch in Unit is equivalent to the following 8 FFs/Latches, which will be removed : +WARNING:Xst:1291 - FF/Latch is unconnected in block . +WARNING:Xst:1291 - FF/Latch is unconnected in block . + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# FSMs : 3 +# RAMs : 1 + 2049x8-bit dual-port block RAM : 1 +# ROMs : 3 + 1024x8-bit ROM : 1 + 4x1-bit ROM : 2 +# Adders/Subtractors : 8 + 12-bit adder : 4 + 14-bit adder : 1 + 4-bit adder : 1 + 8-bit adder : 1 + 8-bit subtractor : 1 +# Counters : 7 + 10-bit up counter : 1 + 11-bit up counter : 1 + 3-bit up counter : 3 + 6-bit up counter : 1 + 7-bit up counter : 1 +# Registers : 130 + Flip-Flops : 130 +# Latches : 1 + 1-bit latch : 1 +# Comparators : 12 + 10-bit comparator greatequal : 2 + 10-bit comparator less : 3 + 11-bit comparator greatequal : 2 + 11-bit comparator less : 3 + 6-bit comparator equal : 1 + 7-bit comparator equal : 1 +# Multiplexers : 9 + 1-bit 4-to-1 multiplexer : 8 + 4-bit 4-to-1 multiplexer : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +WARNING:Xst:1988 - Unit : instances , of unit and unit are dual, second instance is removed +WARNING:Xst:1291 - FF/Latch is unconnected in block . + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Mapping all equations... +WARNING:Xst:1291 - FF/Latch is unconnected in block . +WARNING:Xst:1291 - FF/Latch is unconnected in block . +WARNING:Xst:1291 - FF/Latch is unconnected in block . +WARNING:Xst:1291 - FF/Latch is unconnected in block . +WARNING:Xst:1291 - FF/Latch is unconnected in block . +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block fpga, actual ratio is 17. +FlipFlop vga/rom_addr_char_0 has been replicated 1 time(s) +FlipFlop vga/rom_addr_char_1 has been replicated 1 time(s) +FlipFlop vga/scancode_convert/sc_0 has been replicated 1 time(s) +FlipFlop vga/scancode_convert/sc_1 has been replicated 1 time(s) +FlipFlop vga/vgacore/vcnt_0 has been replicated 1 time(s) +FlipFlop vga/vgacore/vcnt_1 has been replicated 1 time(s) +FlipFlop vga/vgacore/vcnt_2 has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : +INFO:Xst:2387 - HDL ADVISOR - A 2-bit shift register was found for signal and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +INFO:Xst:2387 - HDL ADVISOR - A 3-bit shift register was found for signal and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally. +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 175 + Flip-Flops : 175 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : fpga.ngr +Top Level Output File Name : fpga +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : NO + +Design Statistics +# IOs : 23 + +Cell Usage : +# BELS : 978 +# GND : 1 +# INV : 15 +# LUT1 : 27 +# LUT2 : 71 +# LUT2_D : 1 +# LUT2_L : 1 +# LUT3 : 186 +# LUT3_D : 3 +# LUT3_L : 6 +# LUT4 : 376 +# LUT4_D : 9 +# LUT4_L : 30 +# MULT_AND : 10 +# MUXCY : 60 +# MUXF5 : 100 +# MUXF6 : 26 +# VCC : 1 +# XORCY : 55 +# FlipFlops/Latches : 176 +# FD : 29 +# FDC : 67 +# FDC_1 : 14 +# FDCE : 38 +# FDE : 16 +# FDP : 10 +# FDR : 1 +# LD : 1 +# RAMS : 7 +# RAMB4_S1_S1 : 7 +# Clock Buffers : 3 +# BUFG : 2 +# BUFGP : 1 +# IO Buffers : 22 +# IBUF : 3 +# OBUF : 19 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 2s200fg256-5 + + Number of Slices: 387 out of 2352 16% + Number of Slice Flip Flops: 176 out of 4704 3% + Number of 4 input LUTs: 725 out of 4704 15% + Number of IOs: 23 + Number of bonded IOBs: 23 out of 180 12% + Number of BRAMs: 7 out of 14 50% + Number of GCLKs: 3 out of 4 75% + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+---------------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+---------------------------------+-------+ +clka | BUFGP | 2 | +gray_cnt_FFd11 | BUFG | 102 | +vga/pclk_2 | NONE(vga/rom_addr_char_2) | 9 | +vga/crt/ram_wclk | NONE(vga/video_ram/ram_addr_w_9)| 19 | +vga/charload | NONE(vga/inst_Mram_mem31) | 7 | +vga/crtclk1 | BUFG | 37 | +vga/crt/_or0000(vga/crt/_or00001:O)| NONE(*)(vga/crt/ram_wclk) | 1 | +vga/vgacore/hblank | NONE(vga/vgacore/vcnt_4) | 13 | +-----------------------------------+---------------------------------+-------+ +(*) This 1 clock signal(s) are generated by combinatorial logic, +and XST is not able to identify which are the primary clock signals. +Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +------------------------------------------------------+------------------------+-------+ +Control Signal | Buffer(FF name) | Load | +------------------------------------------------------+------------------------+-------+ +gray_cnt_Rst_inv(gray_cnt_Rst_inv1_INV_0:O) | NONE(gray_cnt_FFd1) | 65 | +gray_cnt_Rst_inv1_INV_0_1(gray_cnt_Rst_inv1_INV_0_1:O)| NONE(vga/vgacore/hsync)| 64 | +------------------------------------------------------+------------------------+-------+ + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: 13.678ns (Maximum Frequency: 73.110MHz) + Minimum input arrival time before clock: 2.827ns + Maximum output required time after clock: 18.188ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'clka' + Clock period: 13.121ns (frequency: 76.214MHz) + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Delay: 13.121ns (Levels of Logic = 2) + Source: gray_cnt_FFd1 (FF) + Destination: gray_cnt_FFd2 (FF) + Source Clock: clka rising + Destination Clock: clka rising + + Data Path: gray_cnt_FFd1 to gray_cnt_FFd2 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 1 1.292 1.150 gray_cnt_FFd1 (gray_cnt_FFd11) + BUFG:I->O 103 0.773 7.350 gray_cnt_FFd1_BUFG (gray_cnt_FFd1) + INV:I->O 1 0.653 1.150 gray_cnt_FFd2-In1_INV_0 (gray_cnt_FFd2-In) + FDC:D 0.753 gray_cnt_FFd2 + ---------------------------------------- + Total 13.121ns (3.471ns logic, 9.650ns route) + (26.5% logic, 73.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'gray_cnt_FFd11' + Clock period: 13.025ns (frequency: 76.775MHz) + Total number of paths / destination ports: 2095 / 138 +------------------------------------------------------------------------- +Delay: 13.025ns (Levels of Logic = 6) + Source: vga/scancode_convert/ctrl (FF) + Destination: vga/scancode_convert/ascii_4 (FF) + Source Clock: gray_cnt_FFd11 rising + Destination Clock: gray_cnt_FFd11 rising + + Data Path: vga/scancode_convert/ctrl to vga/scancode_convert/ascii_4 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDCE:C->Q 5 1.292 1.740 vga/scancode_convert/ctrl (vga/scancode_convert/ctrl) + LUT3:I0->O 20 0.653 3.200 vga/scancode_convert/raise1 (vga/scancode_convert/raise) + LUT3:I1->O 1 0.653 1.150 vga/scancode_convert/scancode_rom/data<3>81 (vga/scancode_convert/scancode_rom/N43) + LUT4_L:I1->LO 1 0.653 0.100 vga/scancode_convert/scancode_rom/data<4>145 (vga/scancode_convert/scancode_rom/data<4>1_map1650) + LUT4:I2->O 1 0.653 1.150 vga/scancode_convert/scancode_rom/data<4>182 (vga/scancode_convert/scancode_rom/data<4>1_map1654) + LUT4:I1->O 1 0.653 0.000 vga/scancode_convert/scancode_rom/data<4>1673_F (N3329) + MUXF5:I0->O 1 0.375 0.000 vga/scancode_convert/scancode_rom/data<4>1673 (vga/scancode_convert/rom_data<4>) + FDE:D 0.753 vga/scancode_convert/ascii_4 + ---------------------------------------- + Total 13.025ns (5.685ns logic, 7.340ns route) + (43.6% logic, 56.4% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'vga/crt/ram_wclk' + Clock period: 4.587ns (frequency: 218.007MHz) + Total number of paths / destination ports: 84 / 84 +------------------------------------------------------------------------- +Delay: 4.587ns (Levels of Logic = 0) + Source: vga/video_ram/ram_addr_w_11 (FF) + Destination: vga/inst_Mram_mem8 (RAM) + Source Clock: vga/crt/ram_wclk rising + Destination Clock: vga/crt/ram_wclk rising + + Data Path: vga/video_ram/ram_addr_w_11 to vga/inst_Mram_mem8 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 7 1.292 1.950 vga/video_ram/ram_addr_w_11 (vga/video_ram/ram_addr_w_11) + RAMB4_S1_S1:ADDRA11 1.345 vga/inst_Mram_mem61 + ---------------------------------------- + Total 4.587ns (2.637ns logic, 1.950ns route) + (57.5% logic, 42.5% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'vga/crtclk1' + Clock period: 11.607ns (frequency: 86.155MHz) + Total number of paths / destination ports: 703 / 50 +------------------------------------------------------------------------- +Delay: 11.607ns (Levels of Logic = 4) + Source: vga/crt/cursor_h_0 (FF) + Destination: vga/crt/cursor_h_0 (FF) + Source Clock: vga/crtclk1 rising + Destination Clock: vga/crtclk1 rising + + Data Path: vga/crt/cursor_h_0 to vga/crt/cursor_h_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDCE:C->Q 10 1.292 2.200 vga/crt/cursor_h_0 (vga/crt/cursor_h_0) + LUT4_L:I1->LO 1 0.653 0.100 vga/crt/eol_SW1 (N3311) + LUT4:I0->O 16 0.653 2.800 vga/crt/eol (vga/crt/eol) + LUT4_D:I3->O 6 0.653 1.850 vga/crt/_and000019 (vga/crt/_and0000_map1131) + LUT4:I1->O 1 0.653 0.000 vga/crt/cursor_h_Eqn_51 (vga/crt/cursor_h_Eqn_5) + FDCE:D 0.753 vga/crt/cursor_h_5 + ---------------------------------------- + Total 11.607ns (4.657ns logic, 6.950ns route) + (40.1% logic, 59.9% route) + +========================================================================= +Timing constraint: Default period analysis for Clock 'vga/vgacore/hblank' + Clock period: 13.678ns (frequency: 73.110MHz) + Total number of paths / destination ports: 566 / 13 +------------------------------------------------------------------------- +Delay: 13.678ns (Levels of Logic = 13) + Source: vga/vgacore/vcnt_1 (FF) + Destination: vga/vgacore/vcnt_9 (FF) + Source Clock: vga/vgacore/hblank falling + Destination Clock: vga/vgacore/hblank falling + + Data Path: vga/vgacore/vcnt_1 to vga/vgacore/vcnt_9 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC_1:C->Q 87 1.292 6.550 vga/vgacore/vcnt_1 (vga/vgacore/vcnt_1) + LUT4_D:I1->LO 1 0.653 0.100 vga/vgacore/vcnt_Eqn_911 (N3480) + LUT4:I1->O 2 0.653 1.340 vga/vgacore/vcnt_Eqn_bis_021 (vga/vgacore/vcnt_Eqn_bis_0) + LUT2:I1->O 2 0.653 0.000 vga/vgacore/Mcount_vcnt_lut<0> (vga/vgacore/Result<0>1) + MUXCY:S->O 1 0.784 0.000 vga/vgacore/Mcount_vcnt_cy<0> (vga/vgacore/Mcount_vcnt_cy<0>) + MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<1> (vga/vgacore/Mcount_vcnt_cy<1>) + MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<2> (vga/vgacore/Mcount_vcnt_cy<2>) + MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<3> (vga/vgacore/Mcount_vcnt_cy<3>) + MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<4> (vga/vgacore/Mcount_vcnt_cy<4>) + MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<5> (vga/vgacore/Mcount_vcnt_cy<5>) + MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<6> (vga/vgacore/Mcount_vcnt_cy<6>) + MUXCY:CI->O 1 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<7> (vga/vgacore/Mcount_vcnt_cy<7>) + MUXCY:CI->O 0 0.050 0.000 vga/vgacore/Mcount_vcnt_cy<8> (vga/vgacore/Mcount_vcnt_cy<8>) + XORCY:CI->O 1 0.500 0.000 vga/vgacore/Mcount_vcnt_xor<9> (vga/vgacore/Result<9>1) + FDC_1:D 0.753 vga/vgacore/vcnt_9 + ---------------------------------------- + Total 13.678ns (5.688ns logic, 7.990ns route) + (41.6% logic, 58.4% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'gray_cnt_FFd11' + Total number of paths / destination ports: 2 / 2 +------------------------------------------------------------------------- +Offset: 2.827ns (Levels of Logic = 1) + Source: ps2_clk (PAD) + Destination: vga/ps2/ps2_clk_r_0 (FF) + Destination Clock: gray_cnt_FFd11 rising + + Data Path: ps2_clk to vga/ps2/ps2_clk_r_0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.924 1.150 ps2_clk_IBUF (ps2_clk_IBUF) + FDP:D 0.753 vga/ps2/ps2_clk_r_0 + ---------------------------------------- + Total 2.827ns (1.677ns logic, 1.150ns route) + (59.3% logic, 40.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'gray_cnt_FFd11' + Total number of paths / destination ports: 28 / 19 +------------------------------------------------------------------------- +Offset: 12.522ns (Levels of Logic = 2) + Source: vga/vgacore/hblank (FF) + Destination: vga_red0 (PAD) + Source Clock: gray_cnt_FFd11 rising + + Data Path: vga/vgacore/hblank to vga_red0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC:C->Q 17 1.292 2.900 vga/vgacore/hblank (vga/vgacore/hblank) + LUT3:I2->O 9 0.653 2.120 vga/pixel<8>27 (pixel<8>) + OBUF:I->O 5.557 vga_red1_OBUF (vga_red1) + ---------------------------------------- + Total 12.522ns (7.502ns logic, 5.020ns route) + (59.9% logic, 40.1% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'vga/vgacore/hblank' + Total number of paths / destination ports: 108 / 9 +------------------------------------------------------------------------- +Offset: 18.188ns (Levels of Logic = 4) + Source: vga/vgacore/vcnt_2_1 (FF) + Destination: vga_red0 (PAD) + Source Clock: vga/vgacore/hblank falling + + Data Path: vga/vgacore/vcnt_2_1 to vga_red0 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDC_1:C->Q 84 1.292 6.400 vga/vgacore/vcnt_2_1 (vga/vgacore/vcnt_2_1) + LUT3:I1->O 1 0.653 0.000 vga/pixel<8>191 (N3439) + MUXF5:I1->O 1 0.363 1.150 vga/pixel<8>19_f5 (vga/pixel<8>_map785) + LUT3:I0->O 9 0.653 2.120 vga/pixel<8>27 (pixel<8>) + OBUF:I->O 5.557 vga_red1_OBUF (vga_red1) + ---------------------------------------- + Total 18.188ns (8.518ns logic, 9.670ns route) + (46.8% logic, 53.2% route) + +========================================================================= +CPU : 30.25 / 30.36 s | Elapsed : 31.00 / 33.00 s + +--> + + +Total memory usage is 262956 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 21 ( 0 filtered) +Number of infos : 6 ( 0 filtered) + diff --git a/xilinx/vga/fpga.twr b/xilinx/vga/fpga.twr new file mode 100644 index 0000000..1e047c9 --- /dev/null +++ b/xilinx/vga/fpga.twr @@ -0,0 +1,48 @@ +-------------------------------------------------------------------------------- +Release 8.2i Trace +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +trce -ise /mwave/work/nt/xess/xilinx/vga/vga.ise -intstyle ise -e 3 -l 3 -s 5 +-xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf + +Design file: fpga.ncd +Physical constraint file: fpga.pcf +Device,speed: xc2s200,-5 (PRODUCTION 1.27 2006-05-03) +Report level: error report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:2698 - No timing constraints found, doing default enumeration. +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. + + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Clock to Setup on destination clock clka +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +clka | 7.120| | | | +---------------+---------+---------+---------+---------+ + + +Analysis completed Mon Jan 1 22:22:52 2007 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 203 MB + + + diff --git a/xilinx/vga/fpga.twx b/xilinx/vga/fpga.twx new file mode 100644 index 0000000..bac9527 --- /dev/null +++ b/xilinx/vga/fpga.twx @@ -0,0 +1,279 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 8.2i Trace Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.trce -ise /mwave/work/nt/xess/xilinx/vga/vga.ise -intstyle ise -e 3 -l 3 -s 5 +-xml fpga fpga.ncd -o fpga.twr fpga.pcf -ucf /mwave/work/nt/xess/v/fpga.ucf + +fpga.ncdfpga.pcfxc2s200-5PRODUCTION 1.27 2006-05-03INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.clkaclka7.120Mon Jan 1 22:22:52 2007TraceTrace Settings + +Peak Memory Usage: 203 MB + diff --git a/xilinx/vga/fpga.unroutes b/xilinx/vga/fpga.unroutes new file mode 100644 index 0000000..7062bfb --- /dev/null +++ b/xilinx/vga/fpga.unroutes @@ -0,0 +1,7 @@ +Release 8.2i - par I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Mon Jan 1 22:22:44 2007 + +There are 0 unrouted networks: + diff --git a/xilinx/vga/fpga.ut b/xilinx/vga/fpga.ut new file mode 100644 index 0000000..009a4e6 --- /dev/null +++ b/xilinx/vga/fpga.ut @@ -0,0 +1,29 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g Gclkdel0:11111 +-g Gclkdel1:11111 +-g Gclkdel2:11111 +-g Gclkdel3:11111 +-g ConfigRate:4 +-g CclkPin:PullUp +-g M0Pin:PullUp +-g M1Pin:PullUp +-g M2Pin:PullUp +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GSR_cycle:6 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:No +-g DriveDone:No diff --git a/xilinx/vga/fpga.xpi b/xilinx/vga/fpga.xpi new file mode 100644 index 0000000..d043f7f --- /dev/null +++ b/xilinx/vga/fpga.xpi @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=OFF diff --git a/xilinx/vga/fpga.xst b/xilinx/vga/fpga.xst new file mode 100644 index 0000000..5752522 --- /dev/null +++ b/xilinx/vga/fpga.xst @@ -0,0 +1,54 @@ +set -tmpdir "./xst/projnav.tmp" +set -xsthdpdir "./xst" +run +-ifn fpga.prj +-ifmt mixed +-ofn fpga +-ofmt NGC +-p xc2s200-5-fg256 +-top fpga +-opt_mode Speed +-opt_level 1 +-iuc NO +-lso fpga.lso +-keep_hierarchy NO +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case maintain +-slice_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style lut +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract YES +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-mux_extract YES +-resource_sharing YES +-mult_style lut +-iobuf YES +-max_fanout 100 +-bufg 4 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-tristate2logic Yes +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/xilinx/vga/fpga_last_par.ncd b/xilinx/vga/fpga_last_par.ncd new file mode 100644 index 0000000..d6aad7d --- /dev/null +++ b/xilinx/vga/fpga_last_par.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4 +###5268:XlxV32DM 3ff9 147ceNqVW21v2zgS/iv9sF/PEd+l6rCA5RfVaGJlHadNPglOnBS926ZF2lvs4frjb8ihLM5I2mSBmuQzz5DzRtGig/7yIO3/hCh/2T388fn7569Pb9+ImXBvfpHlP8xDebY4r9qdyBZCzK6yFMshFilWjFeMd4zPGS6GOJ0vM8p7THjmr8eEZ/5L5r9k/kvmv9SM14w3jHdDTPRZ/B4TnuVDsXiVj/fYY5IusRAkXYgJLxgvGC8ZLxnvGO8oT9MpWLoEC1+w8AULH3HKKxafYvH59Ihjj22aLUGzJVm2JMuGZN5K5q1E7449VpRWgk5XbHklGVZMn69nGW8Z7xjvqHs6TYZcMDanbDGAvSnFMqfYPlO47Y89VpSmmVEsMypkJmOY8IrxfH3NeM14w3jDeMt4y3jHeMd4kky1MAOYJsdSls0tBrC3pFkhNCuExgf62GNJ1elxpdlxpfF5TKarAUy1aVk1K6tmZdWsrJqVVbOyalZWzcqqWVk1K6tmZdWsrJqVVbOyaiwrw4Qn54Gmdda+zinMaS6LAeyXNqzOhtXZsO9hwORhN7TuhtXdsOfV0DobWmfD6mpYXQ2rq2F1NayuhtXVsLoaVlfD6mpYXQ2rq2F1NayuhtXVsLoaVldDH2dDn19Dy2xomQ0tc4C9sl2QxFr2dWyxbIm6GsB0Nk2rZWm1LK2WpdWytFqWVsvSallaLUsr4jRYTb3XlDWUtZRliSBpdAty6AXY++XY9nMsT47F7Vicjn2vOuqpo0+9o7sjwN52ju/Lxx6TycWCHKgFOwUK9rZd4Nt0Mt0MYLq4pWxOWbYUyTC+dveQHAiS3RoiPs0GbChMTUn6TivhHTMtR8T9bEGq62FG1ckNQLJX1IjJ/LRCkr0keqyGmOhrhi3T5+s7xjvKkxuPx5LqkxuNx8w/me4wKcmZgTBlNWU1ZQ1lDWUthQVVTjeQVIt0AyHsg1AsSYolSbEkKbrxAUuqTveEYjlTLGeK7QlFb4ERE95S82oA09A1ZTVlDWUNZUmcmmZR0yxqep/xmISp2dbULOuaZV2zrGt6eY9YJO5I6p2ksyXzhiZds6QjTldXdHVFWU1ZNtdQ1lDWUbYYwN5Nw8469ibmsWX6jvGO8pLNp2kwbO8Z/AXi2GMGiwHsJ7MXjIgJrxivGc6HmMwvGM/sS7Y+3QOWBW9Z8JYFT1+IEIoEasqyucRVx1LjWCocq6NjoToWqsNQjz0ewl47Z6vleOofe6wGsA+U3tok/miSQDGAp7mKKiNM2VRZ02NX07cCTZUNfdUxdK6hcw11w1A3DA3BUEOW3nkttWvxeUtgQZSJGwgTZakpqylrKGsom1NI7ZJ4LY3I4W0vgamTjsbraLyO3gQdPqEJLAgrswFMlCW1K6mTJHxHw3c0opxGlNOIEKaspKwawFRZU1ZTNqdsTtmCsgVhSXJympycJienyYnP7/0Jpk7F1/oEigFMlRWFOVXOKVtQtiCspHZJQAUNqKABFfRAQiiK8qxenL+vrtdZP0ykKg4v50vhyjPfZbYbuDgQeRwoEwe609Gdjo0D2VHS6DiwKg7cadBRroiDPOsGHZV36xRxoLKsG8RZSkR/lLQ2DHJ7V57t5heVbnfZIuuBSIFMgUqBToFJgV1kooR/QpYig4/vJXwUfDR8DHwsfBx8cvgUogRagqoEVenHoCpBVYKqBFUJqhJUJagqVaoZ6CnQV0KUWpRGlFaUTpS5KAtZzoGdwypzWGWuTTlfLndzi10We6gg9lk3EJGRsVex17E3sbexd7HPY1+goQphFQ1V0VDVGao6Q1U0VEVDVTRURUNVNFRFQ1U0VBUQdHXeLN5Dus+6AYQ8kM3HhFUqXG3n7WXzcbWjwioKdS/cXe3nbb1rrrdLJq46serFH1cnaVZW15vzZbuf7+oVNIt3YOoGPrd5WT38/v1NNlOQET98281vT1G5CWI+yVQDpg9yyHSRFoxJwx3hTtHljEsCN0j5E2PTgBT61h8oGZX7A0H2onaxii4l80+T16vdA4r91OXqfH573+PNep2wmy1MeOxxc70HQaIOlqP61fkGzFa3GcOicxYFC/FhSacs2JQFTBFUcHF9sx6R1fepaE0NrQ1oMJEF0SORzLfUmfX6huFbYqQm02uYTgXb5ZoL6BSIngpumt2aC2rwezFfth82q4/th9XuatNsZblYqXKx8YP3yjdvN9vN/qdvbt6eNx/fns/3i3dtswOn38K/q9vtop3v97u3cz/8+ZNNun3VJHmESX/DSK//uvVVNq0fxiNTStjJ2jfz0FZFuWguLjb7/WoJAtijrlzsVnOAwHz98i2cDw84PD1mh4j9Y3FMxrCr4yy/we/iMJRGlPAVWC7/dgrL5UbBB7yFJgstPJm+zbCLSGKnsNPYmaAvQ6tCq0OLchtaF9o8tIU3VflhFUxVYfEKTVUiIomdwk5jF5asgqkqmKqCqQrlwVQVTFXBVOVNNT6qJkTVhKgajKrBqBqMqsGoGoyqwaiaEFUTompCVM0c5Ta0LrR5aIMpH1UTompCVA1G1WBUDUbVYFQNRtVgVE2IqglRNSGqpkJ5MBWiakJUjY8KTnvfVKJcy3INR+sa3gTW8Pys4X1iDRPXZrMVZS3LGsgayBrIWh9Lv4POTsdvhjg5eaMIdtZJeneSwGHqAoAtDEudN9X8vD1v6s0ioxDOwo0uN/Clp0rYl7LcbAHChoTXgLA512u/AavmBvfgWzjVvTzsyneb+h3bs/BMmZcnDvd6eHyTU2hk6ZHH4bH8uwdXYuT27xt55VP68OoZOMFn7OfPn0XpSxe+Rl0YQspQFr48D2GI35vI+3fscvObLc+b+XK1PJQX88v2ollen6+OYbzfXKzg1eHi8i7AeP6r8uLwzZRbkWnYv1vhTGhh525lAS/Ovm2/He7/3cIVZStbB9eR+EVYbpXMFXYaO4Odxa4IXZH5Dl6JsXOhEwo7gx0KpcAOhdJiF7kcu7AmLIMdrqJwgkJO4yoahQY1DQoNTjCRw6UNzrOIbHGPXYw6CF3s1D12hMPFHE7PUYh5UZgQlaPzBaICAytwQhG54ITOMuwEdhI7hZ3GzmBnsXPY5djhKgJXEbiKwFUw5VrgKph5LXAVLIAWuIrAVSSuglXREleRuIrEVbBUGkulsVQaS6WxVBpLpRWuonAVLJxWOEHhBKyf1jgBy6g1TtA4QaMhjfM0ztM4z6AmllgbdNCgCpZYW1za4tIWJ1jUtBgK7gJtc9jtqpWn3Y5QRVgj1B1U5Vabg2/izvAC5wUuCuB5cpkLbXEX2l6zkAff9JoFbKdyu9p/bHbvRdmosvEvafC0a99koYUYfJthF5HETmGnsTNBX4ZWhVaHFuU2tC60eWgLW17OF+9XS1WGXwvKy+UV3mHay/P5YnWx2u4fE+H11bxePQQB+NxezK/2q93jCcOVY7/Zwkt1J9jfXq4OiOplu1mi6uXyojuT4MsvSDbbdn51tam3sOYlRNgJVzf71RbOuLAS5MvLwzstvBa31Wa7BHPwXXYSezP+cE1VPywWJ1WTiNGD1l8GY+REvlv7Rd7D/Sb4ta0v2qvmerdYPXopwOSUBYHP4/7d7hrY568/vvqXPpHN6pm/e/YSWczgtuKjZqJZBvfCk1BqPcMLyiyUnDL+BuA95rKZSIxLx41Lp2YVNR5FYDzVy93M37rkQDQTqZ7KNA8mimgwKBwLxjM8mE5GglF2tp4tU0HOBAYTK7gEXEkWt7PkYjsinYkJuUxMWTnDGyaT0OyAzN/l0uxEEc02CuuhXj0j4VhIor/5knCijOTKGp4JlMyyVMkOlGxM11AmRmSSxOCGsbou1hGhGBPKMaEaE+oxoRkT2jGhG7peD/XqMdfrMdfrMdfrMdfrMdfrMdfrMddr5no+zHo+lvW8y3ryUMLzHK+xM3+bmmIqcRhj5jP8tTIfJ/2tc3ReNcMfH/Nx0l8hi3HKfxn687jn+h/U7Kh4JqYIOUWoKUJPEWaKsNzZatzZasrZasrZasrZasrZasrZ6uQsIdKfHfMJArbYJCWmKTlNqWlKT1NmmhpGVU1FVU1HVU1HVU1HVU1HVU1HVU1HVfVRmZRKfup143L6ZUwYMcnISUZNMnqSMZOMTQ80lw0OtCiiB1onFGNCOSZUQzP1UK8eM1OPmanHzNTMjBhGI2I0yTexk/ybGCXgi2Wy0ytURojwBiUHIvo6Ai96A2/UyOsICuuhXs309HA9PbaeHq6nx9Yzw/XMWO1NV/vB5HqoV49N9pkpf1PlbvVBl/7ACG0ly6usKMMt7wzeifuhuIvD8K7VyRe9Crz73Z+G/i8NBNUuonXeDcRpJE8jdRrpzl74A8QJ+D89HDow354cWa9v+uFtZ6zulqtPxuqTsfpkrNbdkv4vEacxZDgZ193Yb6tu7P/qkIw7ebs+89/9p7FMxioZd3bbOtGvE/060YexhvLsRLlX5X4BN9D96UrqL4aPAceLWrwpMglcXcPfF1H8wa/qb2xwnX2kst3+SAQXsNESfHW5Wi2jyF9QNxeX4OJmj6vsyc12310pgwPnm+oKvN9tVPlxNfcNbLmPV6K8keVNJY7lzeZ8s735x82yegPv3G+u9tc4mF8tNhvQ+c2WN8e7dnO8g/5LW31+On5++gS+eHRx+NfX5w8Pz/6/JXaiz0+9qLyV5S0YvP1Nl/e///twCK3/9bi+fEzGZ76FBRLJxnemfPwkjdXl47dPBxfa9gjbPg7aJvw6iUh2YknEqhMrItadWBOx6cSGiG0ntkTsOrEL4ruIPj+1R3/MJCjwUfvL4dvs6dOXY/np+fDf9v7pR7teH8UDhf74J4KQFjpHwoYj+PSLz7fDc15++/znw+//zH915bfvsoXUHrvBLP71NMLW5zoP6Hj4cXg4jVDveMJB0ZXPD98ffrRP990gzv8OVn8cniSE8senw9nF4Xhsnw9fWuif2z8+Hx++LgQE/3SEe+MLCvA+PqUh4bmd5mQ2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Wch0OXFYfa2Xwj+Et4YD+qwESFFazW/QkGWwcOg87Fubb1AtCrqFA2083jiIhooaBQkFaaOwk0jpy0HwnUH7zsS41NlRWscB+9oE5tOpgvaVCpBTZz7rPnxHljtPBerqgHP1tS1c14a1PwnLgeWHAwbUGFBjRY0VNVYLfr5RvkCLgprQOndCEVW5RyeqUouLgbjYiIvNPqHym8LCe0r58ZKtRaV9nCTFgSbkQR4epN9Bjh1IKJJjh6XWVZ17eZ3eyXaQbAc5dljQe6XNQdocZMtBbhykxEFKHGTCQd4bpLtBuhtkuUFOG6SyQSobZLBBvhqkqUGaGmx1Y6sbCWcjODTqfnn/StO/A2cuKlFCLjY0EqT7R5tktfU5uTjyq+3EtQ/ljO82mcqk6JLvum5f+ancKx8SmFNnQLeEYpk2e71tYHnlyiyNPNKQ8SBZRDJCJxF0wr7M6NwIit6U/B7HgcY2tuRwz82nv4AZEPWeFUvFUrB4PZ3PE8sJj7+bG2gE+QxQnp2ndjzFI5sBrSlc3ga0z8DiUSIfnaf8mjkfDUujj78VGFCegqVgSTyVsEQsEQtzPvZ3ZaR9Npr8BDPVQqZayNx5GlALy1Egk3fpOlBLpk/mqYiFiSV40sDSsXSOIHMEGZHET+bUDRf5au1m4StaAnwB5TmJfj9C3MrgGVBJ3NF/qqAuGYa7lnlItMDqibv7d40rn6xZpJfJ3vhYGulNINq+eZeXHwlsX5f8eMyL6sGV8eDTUPmNgVs86MuPDXTTDVT71YFbMhb3DQEabgYJxtYmb4RDf1502PD2fLArLB8+ATrDJ6iDhg8JLTlDEC1qvF5/KvVoBngcWeH7FSMCEaESCBKgEQgCoBMIEqATCBJgEAgSQJhnx+1xqhOn4ssGBhoRIQFkiJ2gs7d3sIiAToxIgE6MiIBKek6AFT4SoBI1MqARNRKgETUioBE1AqATNSKgEzUioBM1ImAQNRKgEz4yUSMBBlEjAQZRIwE6USMBGlEjAypRIwE6USMBOlEjATpRIwE6MSID/Occr2CRiBELdGJEAKz3xBUjVtRo+JH+zFB/YzpwAymNt+PtxgP3CQZeDimOsW7Jm8fFwNdA9AvS9n2Q8R61avDIdqFX+KhlrFe/zzw8itQtvSNENKDzyOXkY/mBY7fzTd2M2ooALt6NMQFWFGpQnyyxM4aFvGg/TygQjRUXVhDhGxNGHYl0zYCdYvmxe4npRx1jf48xGGNAnQErmkaoN6gj1I3z6Iyhv9PY1u+Q7ftm9vM/3b64xVfbnjk1mVvWq90nZ9irVqTy99BieSHrHW+iU6Lib559hNLKR63+Bpd32vvkcuJQpuM9XGM4TVHHGu58E3QLkn77Gf4HrKKpeg==###6396:XlxV32DM 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10f8eNqNW0uW5SYM3RI/Y9xZRxaAsRlmllGf7D0uS5dnrqGrelJ9j/Qw6I+AvV7/bD7S19/NnMf99zzWr7/nXuuTvibjzfUvG6Gv1ZxfGPSarP3C+L2vZn3S93T99Ov3TujbWtNzfGtquf/uiqNdnuPlQ/CxHPELx9PUe3ziZzpwOk14jof18Xwxv2Wt9v4uzfe///5Zqg+/zK/t9z8+2F9h+etfH8wv99ff3tdfLvrf3vvkM2a2nfX+VirHds9s6VcK+pb7L+V0nDe+13X9W28F1ZLO+/eMrT/kO3mM8X1j/4y9PfMIY77BiOwYb0HmH7yMtxqZ34Xu/5jzUsn171jG2FnBOdd1hLEek6ob4U3nG+ylzAH+zLeGEd5I8218J/NbNxlvN8bd6iC8RcFuM9sI43v+FE9gDP3DEoHhacDwhJk9pSTzZbyl3vJf+kmqDzvGLA/GPJ/X+PLnMtgxZntnbDfhN8GuQ6zzccGmEU5B52dtp4/t/Bmd5c/+2iKZk/WzPlskzL2+X5E0ayRNk0icJRKzv7VI7jSSsz0r/XBq77Qe0K/Ida9fIt3yiHS+i3R2vyKd86vPp8bYax3pKbn9NMcII+Zi5fz7sx73iqITz5qNf017iCEZSL7Y02lO8MPxCUMyH0857wiyFPl98TreBO+L4KCewRjfWzSyMYZ8YFmv79N6GG+bYJdVHoTxvUv4ZYTXRS0ljXFcNHNE60f4E1nHGJada5/jX54U1JPCxJOKetI58aSinpQnnqTyxO/DqpkNnhT6mujlSUE9idbTPKmIJ/Hveb38feYXT4wPT7R9zfHlieGqOvLpzvsXlz7ukcohMfyMEkMZL2oZWzZxhF0Uy8v7GC9O+auOR/iaz81fdpHMC8PzThtH+MoptyR2K/y+SkzH/GMWvGxiGdUeWao2md93dFjmDCeqDhfNKZcb7Lc890NznVgaxgdmOsaf8TMdMbzVAGppq5eaDBiWwvo/vObwUpchLprDl2pGeFGc7amuI/MtV/E2omP+oDM/01/z1/HsIfOHvE8tgWcY+mB7aZ54qiemiSfH3pMh3xYJokaCMIkkiLxuEolO0Wea7Y60BkyzmiJKJGT9srzyKfRrNfuIv9U0Wfck9D3oC3TmZzr8CzUfz4fpGO9Ks/aZqZs8iY7vAbP/M/0Mar9Wvs/8Z1B57Cof4n/Jj/glEq+fSOxrF4mveui3X7zx+bKYfqRNPM9oTmMMzzuXmkfYr7B88dwZNrobY9wk5ca4SX6C4Vn+kGpzr5pJski2zfcwywjnBZ40xtBUieLJjDFfozUK5gf8Hb15tnom1vPytKQ1Rxx7ajFac6Sxp1//c09P5khxFWD++X3Is0WapJEmTiJV0kgVxjXHVWN1u5fTSCZ98RMd8gN2TuWvmZrp0N8ab8d78UP/5RA688N+Shb9Mj/bF/Ofq/qPRkbmf/kf8bfIliTTveRN9Bb5JjhpJFmtZrKku886ppdF56v+y/w8X+Zv9u3Unsjemj8onfmjzufc+kgLOvSxHlppEf/M/8HfKikjldTLn4jeKrMJxvdRyXF8YXqrNHLdnvGLMx3ozI/KDZj5o9HumpX4zPynZj67aiYkftYv80umSY9Mc/Q1f7j7jNHnlPqVJeobHIvU3Iez4VljO+2QMoak2u5cJRs32R3Dky/+IU5exgvad5piI307xq0mzmPcauQJxvxbTUnzj2o5+6aeQPijaekYM/5YyhhvhjrKWlNg946aIvgZ7ufLOCyCQxB5MsZ8U6A+4A/pbD+oWbmmDk4yDcu7ZaosmSqp54eDdtf5HH6vZUrXZ8pXpnWSaVneLVM7ranTJNNn9Tx0P9KZRvPdo3ZPtA/O/EvQPa9GPuYPSf1vF/tg/iMJhv29+HVPfjmIG/Gz/TA/5rud4v+sz1l8AP9rvsQvkWp7RKq9j1TLHalWnxGz3SF9QOweyyY1GmNY6p6Fn3HrK05wor4QItURZXzUmOhbMcb3Wt/KaJ9rs+En9HY2VfqaCxiWBk0gJ6CPhxyLvh1jlidjXi9jRA4XZDzGWF8MfZ81/pCeqG8H3DIV7f54/ciJa1VLJoycyjXMZXx2RG8nLmHMz3SeH2rKFsl5voRRsyHzMUbNF6v2gQmvi3iiL5LZGH/k32dC4O/oWB8id9PXoieCE/orkpba8b8icdBIPOnTmqB7pkl3JQXNBDS/lkmKZpIwyUSlz0SvTBaeJx75E8kW00cye0cy77MposnL72X3qpq3UltWxo+zsm2ENyeRA9Uh47YbcdSXUZypj7N50bx1fV8lpDHeI0kefbYsmkKH/4gS2Ri3yGYo0inG+HlVuo5/AamZ9OwwbSJPxp+zzL5PC7zPdhdJalrIM27WjOh76C3z0LNLV+T7rG/GvJ7X+kgfwEZrpO/oQSN3LNI3Zbyb3vJf89ezXGvH+KsNUWWbso0w2wNjlm+e9DGL9g33SXdl1ZqN9dH6pE76qC97RZ9Xa0bIIx59HzdozcnyapFG5f2yV/RxnZwF8/g8nkSS/XFic85uiSAS6O4h7iJJG2RljD81UL8vBYYmdquSV0uvRs8Wv6Fj5dDctX0ZWjrmy7hFLniyYuzLv6O3HJWpplCcC1kOPE3v9+TUjz/DqJ5nmGsGmwV/Sy9UM+AWzaa7ldJ7CtNbDZL6s1PgPY0j6UWsfxqfI19M/YkT8E4nGNf3+khC9vDCeiupGokcjHm+bG8tUhTNbGUSKbSm2CcnLnuwQ320SKE1xT458QlaU+yTE6OkNcVLH4gUuIWC7kDSSE3jpUMjfepvJYGf6cDW9Jka9s/0TWvOWigzKT/rl/lZPjx/iXTlEenK5ESk7lI9X/t2qZZPmclxiOUzXqNGFt5t6e6M6YgkM36mfzyXahbFGTcPtzFumo6i6Ty5JZBO0VyjL30fJJxiabhp+LLU2CLT2NKjtU/6y1Oi3ryc3LIoev8wVu1b6O4maY2QcLZPfSzm/5ydSweb5fE5exc68zM9ub5jDoz7fEyvutuzu+5uiP8yeSuRVHdHzE/rZX7W30vfOFHRvstLn0yPlHkItxMXvZWEDjMw06/d/fkn/hUd+wk/65P5W6VQ5ATmZY9Ex/xmeE19twf+H7V7wfRZ/AD/S3/E37pDpVUKfZ/W9PJ/8ZuJfgzpw5D8J7jJf4Kb/M03+jG9fg4nldzL34meUl8Jtj530BMTouMsf8Z/thMgGZ/5T73PG/TiJ/Oz/phfMs3xyDS5r6nrfQtq9Rm3QvDLZnla4zJuJwBYaZms1NFZkKOzownOdPaETPS6GZzpZrDinMe3kJyhPlzU+340/oxeNz3LJn6mt7PDTGfrind6EwDNpkUtN/Z9OMZNH0lPkNLY00BvlpzH/EzPdDYK+SGys70wHd+3+kaCMW4Ot5v0hFslEujmfOjvYszomfpeLN/Z/IGjRsorHsbu7kes8Sf0dOoe1MrZ8wy3zDzByNQtsgbN9N/QM53NB+7D6i2nYCeY5DWTH/xpho32+Rkjsgc3xk2/ivEy4FWpUqYKYczPdGSyrHcv8uRuy2H6buGrUtQ3Ovvkjc+ue8Q8udvi8UZo0qdd1F/y5G7Lpi8xeD2PN0bp06c9H5kgTfq0mfpIwBjZHYd4iO5GrdX7jHq2xbgcchN91bNyxh/LHWOeD76ftE/YbhHEMW6ZZ4Jb5pngzGfTKum4yO4u0+7OG6lJslTQFfNdk2Q2xpCXL2OMm/xXXPEj3OYb6L6oYp7fVfzJLr1o353mO5s/5M328HiDkZ7yeVmq6y0V8muWrm8w8uREw+feU16epm9A8uRse0VlMDmROfRcgNf7snfc8tMTrzy7j0knZjMMewUORb4n5ytvOuuH+dseUWtMXm+zn7N29gL+qf0pv0SS+ogksY8k6x1JNp/dqpJz6vlYiRPLYfy5X9nOeuXEZPsZvVm+3oRnvBV6jTSL+Xr/Lc867qV/l/myRLyhmPXRSv8udKnkCfqGIk867hveUJTxa6RaxBMh/+TUkkkffhFcNBIw/3FSpCD+9oZI18vy2M24jwp+pre+vHoaY9gL8My+dvLUS19RuwXDEy/Q260pxUl3Y+iDf0fH9w/TyxvyZPrHPjVS84mUZsotUmRXftDXKJ764re4D1yH/Dw/5mf7fNlje0dshvbeav5Iff/YR0LgRHscxpAf7hr4SaRsdLJXP4uUp54DUTxgeTH/HQmvwPeJhGFy3zBXvAHob934Yv2zT/I60Sh9dbu6luP6E5I89jTwP26O1j/xNzrlWJyt4l0xTkiw+2D8eZND9w0Vb2H8bjid7UV5t7vOtLvOk26ASz2dd+Og480JIoHXN1677n55PrHIJvZ/lOrxTA==###4692:XlxV32DM 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1190eNqNW0u27CgO3BLmZ1y1jl4AYDzsWY/61N6btBRcE4nf7Teoe6IkA/ogCVAaY8x2mPvfuW3183dLZvv8zWVrf8LVbNfnrytrfCrejeB//vl3uKL5y/zl/vtv57e/vHV//8d585f9+1/OXR3/13mXzyjfhWrcvbBm7z9+W2Nbhb8dMg/jHOd1MT79ap1bX6eXdbp8TOt0fZ3O5atu54c/VZV/E/2EF1zqPA9/X6zgeR32oa8Qp3XYvg7rcvR2e47TTtHP0da4LOV1P/N0E0zzhD5P+LEL5tmsjLu7NR7+0tY4JJEX/se4ecGxXPe/L6z6ykawyOG7HFnksKSu4D5227vlWvOfL2w14dZMbOGDt22NS235g0MwfoVdFpwO4WecQ7vX3LeXX+LY6gefZaZ734X7aLy08084ZPneF8E2tHirJMt4R73ZL7+vse2uccvrRZOM90uwS4I337b7++Nq/w+9ZsFHue6JTZT178Wkeweq/MUIrk1wLibe8iq9u8+NQ5zlBT0ZwZcX/UOfzQrubhdW+k6qP9B5vYfi01yqOBkP82N8zM/2OO28vmCE/zrm9YK/RMFlM8eKv5zinz2aHit+69T+Vf2V+Nn/mX/4XxJ7sL2CymsPGY/5v9b/wp+i2JPtzXTIj/2E8XsG8Cs6+z/zf8lP/Lz/2N98ETr0yfw8H/PzetlfJZKFHskujWR+TkCtR7L4if256ZfndXtocDLTaWTFjLFSY8WijL166rmtcUuCL9funW3bbNm6teP+Tj2d8R7J03fxzFx7EPk4uJcN1pzIw3gr5x1j9nhZCTVnfmKm13LWP/EzfU/nrY99k/necN7atcLGn5N+nFlngp6S/QqHNkemopmkXZ903TOLjheOP2OezyXNDG29E0FP5OnRin36/70NgZ1S8hrnQ/h7JL+LAcYsD2NeX88r4enf3U5BdtblVvhSfDixJ39vwnXLV6vIyTgUwZful7Rd+Yl/o/f/5mm/ELbmKk//+NKvRuLygnm/MOZ4wJj18YWt1sQveNfaDfuhXmLXWHX//ELvtd+NYR+Wv2daWY9bY+ckcu9tjcPR7J9wMnNm53gWdf/ZJPuZ6agUBt1IfMJ4NQtGpbBzJZLnSoTjRTUSTzA++7Np1+0PNQlmfwqK8T3ru3o9m+j3mfSR0lzpcDxCfMD6OV6cea50ON5DftDZHpnnh/2i0ol/2D+u+Tk+MT/HS7aXi1rwaSXL9s6anyz8k/h5/zK/ZPr4OHv5ujrjlaR5EPskSMVdXnCusx5lnv1nns2G1Rkva6Ub/JVk/wt2xxrXU+b1qk/Gwx51jeFv7H8/+l3JkbocW9TSyM5ymF4aJdePYF5NieMkMEzD9KoYx0sUrQhlwEj1jH8OdbIVGaOIxlZFkXgd8/g8HzDGO8ylKtaSjuZ/o1+VQpmdU2c/E96uGrOGCsLWCx6pNcn3WD+Px9jG+XvPoYdM3VPaHNraHNqY7u1M5/k2T6GT5Om5Kjzp7A9N7YXrhmpmeiW6i7pV9JoJ8uLa5UjNPelbFAx6TZRa4pxaEErGVqHU82VvSm3sj7ud6ZeGupEadX7Qz3yez/W3KBjrP1Ve4yRU4BDtkmCb5tR0xjk1Mb1korc5dZ52Tp1ML3GmIxQlLQ38S2pJVEoAd/stS5MxXqbShviDFX2N61fSJ9NzOMXPs5rFzKmG6ePopCUr8x9V1xN0fcT/tX7ihz5OK6Un2xv6AJ3590PoxQhm/qMIvlSfzP+1PuJPWuqM+EP+1NSfRvwifo5vzM/xm/l5vcxvNJ6N+E3xDHTEf+bn+ZgfR90el9pqP/R4cUz5gfhBH/mH+HGJ+Plyxc/yMz/nY46nOLo0PaIxP/sj87O/czy1iqPyczzl/cD8TuPt0B/FS9ChD+ZnfTD/ZfQSVvc/5xOmY38FvYRljP0F3Ett/9QP049T91MdpfnE/7X/iL9VmR/r43zHdMzvVJ3ZrtcHOu935pdS8XiUvMavSl5rZF2Xv1CvOTkCrHEzsm74AeORJ6gEBo6UZxinZemen3KUlRyH5gvYoxTJB+UFI1/sVuOrXuID/0qvVKoTPsxKjvI46hxmkmPvcuw/RxDIES/RX3nBRvVbosE714xtu+NP2+SKibHTughXaOPyucnl82/0inNAWeMdcUkfL0QP9eeZytn5edHu9zvV0QOCvsg6Tek9NuQnxosaMPMz3VrBCLFdRU1eTOX0G6y5X/g2t8Z73OSW8pTTMWOsr7Q1zl42eznk5fYNj5dbws6o/BpCYtrK83vIf2mqZ5yjvBiaMvNXffd4Gw/0Q7/H7UCPyDeGy59Z6eryrG/QcUTg8fCi+fNORevV+bwRHOpmn+MDY/y9zS+mvYKZ5i9W5B0v+FEwSnjWdz/85ycd+ol2PR/To86HEM2Y/ftwgjez9v89if9Fp/Yh/q7XS17a1V+Jn/2f+eEP8D/WF/sL8zMd6z/9ej1Mh/4OpA7yN9Yf8x+fF+z7VWH2D9iH6TWI/MB+F/1sdk0PQehO9cf8X/GF+CUUnj0UHgiF5SUUujo3B+zUDPBJw8/mhOBlqXtY46ihK8k17BeGKTY9FSQ1Jeb/jT5CcaLQjGqM5HnDo/ohDPnhCl/yG5XXrXHMm24ZlZ/wYWUlLK/F7cUv9C3OoWNsXTPmn7cK4ZLnrfYlnxOMphbGcFXMxxiuD2x0a4xq9Re6z/NWgnx94zoJLXPqYjr84Q17DdUIHYyTmVMH6wehLLxghJ6q9mbM63+TB/phPPwdqaTN/v0bfa/z/mZ9pzinOtZHP8a3ZyrleAH6SJW0n0BHKmd/DmZOheyvPVVPqZTlKWnVvNQezV6bXVX5aPYqVcPeJUVufcEpCEYKZowS8Q0nO6+bcW4rOa6nHG4lR8rapIcqXpv6zm2NbRL+8bBCGOsOZpYDuOZ53YxRak1y7M9mRXMtH2aarAP22Jzg2tb4WDWt7dtTX2Y1D/Q15gk67gs+lvI8mgndtfQvk7f0tItzWqK/4FP3HR60GEc75y3GJs0lMuO08q/dPR6Aum7mLlJ/N8ckl2vd5AS26Y1D3sLUYEg4euEf5avV77Vm8G7bnzn/9IqRE36h9/I4PcePRsZHed9tFp/lfbdFfcYk6wWPx2Uar8es9NQVy3OoPIOu84/HziYYMdNXLU/Hi5jgcXzRhtZHTLue9GB0PU5uTqKu70yCPa3fp3n91pC+iH6ofMh5PUfEZ8xlum0z3eh44wXGCgY9KB32Cbpe2CeR/pKf9Rei8MN+m443HrdJP5Af+gl1tp/Ns/1YvkjyXRoDRg0V5wZj+Kuta33UXfbHUdf8PP8bf9PjN+uT6S3K96gxvvYv0b/mJ/7LCv+jZprsxXRgjM/7n+k8P/Mjvowal/Z7hb3cmv9LPuLf23z843gB+iP+zMdtr8fTc6aPGs3M8zH/l/zE33Ps/pyP9wPT4Q8hjobvsIqvoH/pz6/j+ziek/2ZzvpHrRTsOt4x/XN/M52JSF9MhzxJX645Hlxl0/ZXjQ/E/2Uf4m9p1gfHky/9EX9NlN8oXn/Rkf/S2h+YzvbkeD9+kOLX8azX1NOZ8Yuf/Zv4r8/F5nP9nO9O0Ydta37WH/NLreKfNeSx+sGL1byDfYQaK7zgU/U+5Cac8hxnGSPOI4/JOsNznXMTUrSfimrUhvhhDtZlX/B2Cj61CW1cbylmeoxkH+JneqYzF+Puf+Xrhy77p9kqoAaea+2zV47b56c9uHiGpW2l2wxPM6V5JuZ3dHFaIt3e2PnieNwutfV8TOf1vmFE2l6piGYdeklmOi5+cQpgfuy05PVtieXR9YHO/P0UOY3H/F/zE79Ycn967GzJzX4smZERx0+s0soj0vP0lVaej1MePP/Qn1TZvMY4fTZ9g2IMfbzhRJ7O2Kpc42KecKkrOY+nnMefdjhOmfmUyFJfMHZweMGHf7klbKPC+SO9kN+/4VnOz1up19Ph1ma/cM5/bpTN56URL5o2of4XZxz1EtGDn1/g0YFgT+3guASbfPkVxgt2sdexwngpfsNGmy/LJh02jJOdO3DSJePjOh7zRTyn2PUL/Bu9mPkFHx0SfvzYYe5wYIwX5WylQxEdTj8djn+mo0NqdOzZNndgKEazPfDoqHjhBz3qu0bUDjPGR5Z1YX62/08HU2sr/NMBNTpCt6mj9Bf6ofZFhwk6IEJUOdywt1/hrM3X5hJ/Yuwsfralzb364x10ZP1KT4Lf/A8/9jgvyTKM0Yz9k4VmvFOHkEMT/dbqE7tN+BiXpOdy/VEUr+9Qt8F6GHN8YAz/xZ024+TnDj80p2/wS/2xjElqL8Y/HUluhZ2uBx1sjE80r6Ojssp6khO7Xbq+onZk+plmOtvjtNQhG6mDNs90jlfowESHKMcbRx2yUTtOxv2Wfj/un7RjC/auas+U0Ck900uc6Zgf57HdayeQ3s+YONNtmunFaLzCj020QxZV3kH0I890UxFYZL/je3Swwj4jHuSZzvauitFBG9L/AAljrkQ=###4304:XlxV32DM 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117ceNqNW0mW7CgSvBKTEPp9jj4Ak5a161W9unsrw91IYUIdnZt4lu4Cx2cQSuf1V+tZfn6L7/vPr42Co+3p5zfZM//8bqYfH/52xg8Ogq07hc8LPv0Z7nTmz/Hi+GGzPa/4k+n9I88hdOZP1nz+XOwipzPyH9vrDw7Z+B/YbG+f57vg08u49TTuw26EzvxM5/Ghj3Ix/vw61Vf1gr3SYxfM/Ec9j/v6mH8PIud56o/qpwShh3h+7JSt0HMSjPUxHfrH8zwe0/Mu9qxOxruGSffxH/Qk68F8hxEM+ZnO62P+rYvfBSt2L1nw4U93p1t7bit+1wRvRuzy4D/6Z5yWRU/FdPvza7ysq1ehX/+NK/4rDj7zXEJvK/7H/MQP/4L/mmrCD9684NOYePc3l83+4ffij8kLHc8zP9PzIeO/YZbHV4kHjLdHwZj/Gz/PX43Ij/Vd5v/Ye/cSV7GqfQ6J61PtlarQmb9awSGo10SJoyjaOHm8B/8ueS4kkedQfsiXt9bVLyW+g+AR39fQn3E0T/mOuBIcN/HjQWd+9aOh3yB46FfjceiX+L3ms5EPnWDkX6azvWyY83sNlP/DS/7POn6UeP3Nx2v6kJf4t3LWuz62LPNBfxhv0Ikf+aclzefxf+e/B7/qIwS1fxB9wf6c75mf60Vx6/hoVetYmOtPzDL+yM/Ez3TUu6L+eNXDD2G34ldM53zK/D6JHRAfR5jjh+mIHx81Hk/Nx32OR9D3y1Kf+TT/tSD5NXvBTEd+ZRyqyJOSPA/5mH75hbvLu0XJt6UJZjrnE+b/55+/tjP1P+ZP+/svH+wf29K//uOD+eP+9W/vzz+u+7998NHnPYoq+qFLj3PqYTxSkRPRGdskeCxVW66wiQu9zQeM8axbY4zvy0zvSV1QU+nlS/6uquAFM39Qfp7/lV615cH8Wtq3up6PcdIQTk3GZ2y1JcF8jI+uKVjnb7uM73T+lIV+eB2fsE00PuES5/GvEuMlhcnztTRJZV3wllub9POFfnbBGJ/9A6WtZ3me8VV7092+rH8ej/FjPfQ86/MqCf4+X9RQu/oPv/I3lHLQH/ImbfVAJ30cRvBuNIVHKd2Ip5yEnqVgX46jqayc8n/FzQh++KvKh/HZnw5N4aCzPxQz0zneTdUtkpnzAZ6HfHh+q7Ie5BdeL9PhXzbM/gb88EeN5z2LPlhf+6H+kVRfxM/xy/ze9zD7++wvpvV4pzP/8G/FzM/zM7+k+vNK9VlTfc9zqo9Xqvc++Ry0u+lWulss9chrvGlopOOKogUGf+3SjQcjrlWOOdW+0UuYQyc7MV0rwp9heiPzRXV98CelI5RynOk5zPTLs6dQ6G4Ohb1L1xGKyRKqp+7mBbO8yc2hjlAboU6poDnRXy6i36Jdezez/q12TywvXO8qTWbFD1fpunt58Kv9ru1MXPGj1A370XoedJ2/JLFXTGv/AJ3978HP8hF/UHtifrY36BiP+bcgoem2ebzBT/MxP1KN0d0k+yPTgyF5dVdWDeJhprM8D35eP8VL1FKzHbJbZX976J/4nXbd7jDHKh6YDozns1O66ovpSUsJ6MzP8jH/J9Ud5pbqTjOnuvzpap3PqOJVXSkWHTpokSEMVzVprhrAe6CumPDVpU1VsLjZldGF9G2NMV8KStfUwqH0Rgcerk74pFDeM6VSSpVHmF0nmzlV8XhX6M6pjlynmTmV7p1SfZhT/VFnOroi0DOl4sPM87M9TpUfXYmvs354PKaPUpb1oKu/lELQ9eDBVD04Iv6HfxC/V/sgdIB/U5ukpt4EMz+P98aP8R72QOrR9bA9gntJVXlNR2rMEal3lofp6HKyE8z+yOtjfk9dIPs70yG/xy7TKl1LJ9NZfub3aU6VHA9MBx6pFAdOWpqZjl0d6MzP+Y/52f+YX1KtvVJtQVeZXrpKDHVtmKYqau0aj1CJ6irpJdRe6MAwHeMW5q7pIZ9uUKxf46gHEpiPMeQ73ThTWx4gvNK/yAfX9i8Yrt6c6IcxQgWhitAqQfBp5lB+6KeTfgjjrGlrmuoI83zYwA39faFjA4hQZfngqqe+c2AM/WfddfiXXckbfadS8MCdNvikT2zQUap4PaCPUkn+0Pu8K2F/OYheuBSTfOwPKOVDPjfLl0g+yP+7gZ8PKAK1GiwP00d8q/05/pgO/0D8sLzsP8z/eJ7WI6nO3VNdeUl12KAMV9QN1qlVj/Ge59TBGEttOBsw61TyRt/JNdBV2k2rehoNdFhhG/CaWrumFzzOCglnOhva0stZatSzEaJbfR3xKr+ZuybGRrs8uDY/j7M+V0YpmfBIRZoKcHb0SFUvdJzdDVdk+R3Z363tD/0wbv3RZc+lguZ7zE+la38pZd3R/Io7zc/2PsJ8Fsjy7rQrYHvVMKeiRvrMZk5FrO+D6BwPPc+pkv0t0wEQr7c53tXMZ7XYNY2zTDf7B69no66Y+dk/3/hHq8Nn6TQe80uq81eq85Lq/BamVLe7v/3uc9cUjjNxh9eGdo3zpq/x9YyesXfyGhJyAWNdTE9FrwloN8r8TD/wWrWscUHeMvfuNtz0EM5JD9ulh+3aIwTSQ9HXjC/YNvUXJ2fDjMcBq1ljlOZxlk8YB4Y425d1bNc6gqxjn81Zr8Jlf45DDifvH3uQ+ye7lfeJxa2xjcKP961vGO93GTedD++Li57Ujfs3GrgurfmDvm8FPeClh47/GE+3Z1nfHzM/072Rx7EevM+NWdbP9HiqfqA/4mf9Mr8YKl6G2tRQ22Qoaz+WukKvpFb0SblRFqUEXS6wxLtp5X5ziDFK2K6SMi6qKdxMaok0W2dLPfiVXpOOn+Vx3EQATnpTBfM3fa3J8yWvBwEawsy/pXn9zP/QH/HDE1yd5eObM6BvmuLHTRSVJ+qululha7iR01/4RZ5D5GH+h/zEL560/6Yua+3sSu7Hk3JFaYDd6oxlnHRLHW4aJn8c0vymjqu2tnuquNr6JbZ61QFXSxi3OId6rOQAiVID8QczpwYYrPf1eLYKHFcpiZ/pCG2r6+m6/u1Y01k/zC+KPn4Ntvt5d3HZ68rQRu18ZT65EWLxWnON0Xq4yZ757hduVdoPbQkwTymiDvuCN1WX6eqPjFXd4waV4rjJjSemQ/2xSgljfqZ3jU+UQMbFqfmmklhufj2/Iigfv74CxOWW74rYq+Crpi/xEWWiUPQ+BWG8t23qV+NYpv9/dPTC8NuHfJ3kI3w1G1kUoVdTCY9E+oK7meOG5cF7ezgc859m5ZD15vd21WLB723QG4bq511v8jKG2EcWvPW50n+jmy7+BbEZ97paRvtdRuyrsAqapVKQi4/9kCxxvOBWRgNhVhhZpiS9MKdhAfyNHs28bMY2zstm3Jbppd/UsG6YezvuTmv2Vu7ZhDGctObZKYG/0ql7YNyW1jx/s0O0L9mh9k0E1oZY7YOL6oy9VpFw6EVFtY/H/fcv9GvHZe7vExk79a9xFUAbVLRhuxSb0YYx/1a1SmEnrGn01jZO4z3WT/xOL/5f3rzkx84JDTHzfwyRzS1Nz2dux+VPx2+1Qnbweo/5yvVmhTecTWrfPqqJ0Xv3X+hnntWA+YEzdbvMn9xsBrzhx3w8nt/UP3V9b/xj/cQvarT3qn+susGctEqqXChewDKOu5kjr8xRdBiIY7J46VlE/YxdnLdRjKH+vap6CZcwq+sxv17pci8YXju2rYRjnc33wHk2J8uDJqxOavR3c+RVmsQ8iA6UUkQH447s7iTbMLZuzi6MNzM3TYxLXDRROdzcIa3cAUUPy+iKa1njcWs6rnGOs/oZV0pymczRKTrhTsms+ZkOeYDRytdjTX+sn/hFjffjmWOlRnjD8OqkUXRoVBF2jqKKcHrx6jG+epeLa2wDRU1YR22MsxqBTdWPT/waY0KYieWtFHWixnjrJONqB5UzWUNbrvMF5+U0t531vk/TxGuaeE2jNzkwDT4lQKwy3pzeB93XGC1NCms8nPQFx7zOWSNnxtUybxv/9LLxx+HyqD1Ga20ZZ2gTHi9L4hqjl3vDLUnviG+UHvM7mp/wVRqlozd6ckMY8vi8xjjZwkkQY/SWOMlieX2S9Zzagouibxv/ZFa1AOcHWc/UkTRTWePROYb5wAr4Gx2dPZb1hrFMWcbtYCEtz5vQqWAZLa2GKffS2FYbqTPO4+A8Yn/BOI/Al6eMsXyTZePFWD94Gl8+Qn1n1cb+C92F+ctLxlkbb58Eix7qrSb0VZY59IM6bKT8rh9uvuBr37fdNzo1zR/knfpB2Zb0g+EueHwwTPze6HIOPYAn/od8xC/LbLdlzvvF9sky3uc9jS+G9ctB3cjFNS76Su/Y9ZUR4Zzkev047iM8rt/jyzz9Emt82fiFvqX5OJLl33bt5N0adzVUOkRexskJhryM8WXlmfXLPsJnJsO/YDgCryfS8aoY8rbx3+sy/NUfoIZG08gw522YtkqGV2ztun087m5VjjUO+b/VajNM###4604:XlxV32DM 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11e4eNqNW0u25CYM3RJ/Q2cdWQDfYWYZ9cneQ1mSy9zCr7oH/c4tySAJSQgsj2PMf1b3/Prr8jix0r3e8RO9OMLG9rbDLRD2kfB///3jR1G/1C/7+x/r9C9tzF//Wqd+mb/+tnb8Osxve9g8Ij13OHrOesIx7LFqhJ0ZZodNpr+On0M8Yg8/4WN0df7e91jXrs957ZR8g2MkbCNhsoOednBkhxIWM1T722prbD6USmr+026cA1Sv4gubsMe+ES59qB2OVoWfsMvKv3C1hHF+11R+4e6YH7DMl/Ieq66OF866j/v8TfX+J3QTSL6maeERJ0dYHBD1iYbwXAa14z864dVhzXuhUtv5a2axxV97IbHFPz/olbBveyxqK7PHppKYEoeIM2Nve9nJE8OqJvILffpteZvB3uLW28UO2rwcNss4gcdNecU0jruZM2/DPyt7N5c1yp3ipT3OibAW8zgwxxd6BPVx/jLoefeAg1nNieMJfTWnf5sh98UM+Qx/ZXNT53hDwi95yjsSbh9YUZ4R9/Z1de8A667jGj7IL37XO4Uf8iN9RMISvgf7vW0kD9JzOZdBpbjnV5XzbCGM/Ggf5CdDh7vfusXSYTpcONOsvy/4ND4t2AOe6MSW9xHE4nAxEq5DmTv+Su9Kn3ran3FlftLzmHoepKctetFznB7lp6ZeUwKsJEEK+lwRLRYQeib6gXSnz99tIQliIHwowq6udG9+plt8nseXjIbyPtJZ3pH1Gbo90Xgor9BLohBH/sbyac0bBfDj/B/8ah0P9RX6NT/wd0vY1nW8p/mRnzwhvj3elrLL1MnRuso4pq/rTOOk9zhjTfh+DjPdSddGheD5/0wgpZ0Zrj7gEAjrRIFcCz1vePm/0atqtAOUPZ4FSeO6Rb/VyG81nAnbHSc0ydznc6W0zglxi2cCtadeluREHFU/Cz1ZVsGyjEivuqczoTlODMCP9BCoIG9lj2c+PvG6nGXaIZAdwrF6hT4TxLREdzRz5NJXHZRqr1QHWIfhzpTkaS9FnPo4LSNbxkQnvUbaMr7RTRyBfic8U/DJ7x2V0qUTtmWPW+6nnEWvOOqR/4TuFY2X7Sg7bHi+FgnPH+K99J96xHvpj/J7kZfpqG9Tw9PvZPdQ2TNYXpwP1w/5q1rtg/woH/KTJ9V37RLivnY5OtUiEhJTUzpCiKEAz2LuNPxh9jiH1fA4vuIzl6QOxDKeldQEOPFCBJJulnit3lNC14T9A0Z5cDxrWH6qUD70maG3OBIZut0MvWaudhravooXmXhQRI1OK6lG+glnPlMhVo0OvzMSTtwPogv+Rm/sUeLBYshrjwiEs91j1AfxPJzT2TPtsSzs1JcvIQgHP+qf0J1bFwb1yZybJSKRX5vdQvZbEVrTspJu7kFuHp4y7UGK57OG9pxeyL6IvSH+oIkfcePxouW9A3CvhEskTHKOt8Ppup7OzJTTvOWcdqFxYRykj7iZp94vgWrd2UP25MsejvVvbA/A3oE9AHcD+gNuaienvsvZdzWQyCn6Wku4hz1WhXA2HB+ApeaZmXmLS6YaSfwRce6ExT9JD3MrCavZ6RG6Pu9q5r7NlwKEm9/jpvR5WJO4041SraVo+Uo/jD7vjiRBIp6l98kvCZP0sHc97M4/RQ/JN9bSOPEBD7Obx91rxrj1z0rPib3mqbjwvFtceB6xB+LgVv0R962cr1sEz/boY3e4jZ6em7NwPPE6cv6rrIfM08I6j4skh+hpeJ3k+VhXPXA8nB/5cXzkJz1vh3in/E/rIeuuBtk/5j0ujvilQEAcKsklZwvEJhNezhr1uOUL3bf+WaHC0rz/hD3ObnN5XOP9En17GecCPSfzxLob53bE07bt5E2BziDdUcVvDz66hj1uZnM5UW9nMO3cLv/IPMXRCUDGrWGP5dLE9z0Ojo/gmk4YiHOESxXAdXfJUstdj/qTHnIpZQNfTfClFGLP/IfmO3zAotc8eJkdbmGVG3HZrke9X4qFh+tHtpisfOfIkJVGbD2flg2/NgIcKldUjSotxHNyTzsaaYjYK7JYaXxdDtgqOvWaRG8tEM8zKR0dDL2VQGwyX6czP+IZQSc+CvEjbsxfFGGydLtdy1W4jAn2FWIzyCrfvzjLwRYpWQVLqiOesV3u90KIayasCuG5eY/l3s4RluSlOKkL/+icpBXfO0WSb552Tjw3gXCn43wzmZaFzvdW16bA94KyyURv+Eae5PmQF+h6CrDcm1Wa79BkH6T7QsWI4at95Ef9kF+Kl+GIH+3lLPELHflxfZEf50f+eQZy980J7ekb3YNaWU/gR3qrhK8LqINw4PmR/iEf8JOr3w457gi75BgzraucqrUlnPoDjoRFj1ymB7z0oNp2fKUbwmInxPN00D6LqtchKJIeZqg1ZNMZslMVip4palLnkPIyJL9ubTc481ugUgiHwFmr0vPyks71Pb5etgTVdtiwPPO5th0/EjZ2j+cAiz6IjwDjZ8KXPjz/YH0/+Jk+5ew7eZ1b6QXsVbtcibN980q/3u0+2RvouH6oT2f5ZyLpW360L/DL+qRK46E+qu79R/jlpbDxPH/9Mj/wX/4X9vZS+cF/mb9n8I/8ZX7gP0OpqffuZ4bZdznISKpy7mokiWb8QefI0H2Pr66GsEaiYPE8jMRrfMZDr54gWDwhJK12OHTwJNBHVkI88UPf/jO9wvOoj0SS0FEeH1c6rdTrpiPxSvX15KLjmfTmIeuwVNooXvR3gwkFMeLq1iC3/Oodna6GPb3G1Wn1g9MmWGrBFZz+4IaZ6cydTLqOpx+CMtZ1fMHDfBkf5EXcIEnquNJrX+nFrEGH8yFG+348D+uJGOX5kA+SJq6XdByIq+F6RKCjPRvQ0V4BNg20V6xAB3/MEei4qbldqJhbfdDXQ6A+zlCxs9SRrJNpqlnqhZ1rCb3Bfpi4CU6ykjX8xseSKIhd5VMWZyHE02NPLKqhPBK6La6hfOG6yveoj7tCdQllaXp4ol+9XnGtb6754zq/ietS2bouFfInqD9QHweu4PrqigWyLtozcjPg5aqwnhlcFe2F+qC9kN9nuh9zds9fGr/RrHt+9C/kx/HQHhQKr/vYwqEAp1vzCgVr0zzdRjoYj8obWea+N7/HTnFjVqIpBftEJvpG744bv7gw8I5UP1+Iv3CgA/0TrpVcX0Ln2tXYFN/opsKGy/QYtF52Ecb2oDZKwcg//68/8cdIdJEH+ZHeHeHLdaX0yywvFBSWr47EPravqQVxjGtoGG5DEPpRV1dCumBJDYiv1JAhVTD2EHo4/tV/xfZBOtpj9H2qe6IH2KXQ/zP3183dZovNwfh1v7DBH+sB+MPfAaP+6I9IR3+Zu2xdClSIt8oXY11x/IE/FTgqor/EsKZSpGez0tGfClQN6A8WqgJcr4JHVYhnty2g3bsqsNk9VAUHF2BKCkZFd6BPWPphUmfTN+oPEfyNXvNqOpxfOq7R9VP8M3rFAlhaOD3LF9fQQOygYBuKXEt2pUOqJx7vA6M9Ub8AtxqAY/gyv+Pf+ez3gUHfD/055MV+iD2czdCeGW89QN7UV1dF+WdKqWsBvvpDglDC9XBYNYG8Tu1C4XwrybHgsQExu1csJBtt9op7BjzfxvG7+CNTrwpi6YPLnbCPdMN/dTd9oWtHN/7SLWW44Ejcu2LY2tIzgFgSYxC5AffI/X0st+W0PM3GeB0P8TWeg/Gl1wLGP7j7Sz7QUdxjIJ3n8qFKrLRBXL0vjJFu+F2jvDuK3IXXPb0z09yjIO/QEAfPjdz84Q3i+Vfdx58bo7k/L/h6F8bylkrPfaObePUKUU8Q9IBk6PkIhe1YV/+a6+bowwr+8Enk+0Kf65Tv+nnuBXIHjx/W7kLEok+CpjjBlvWTXqPC6y/vvNtB8sUHjPo6S89jfNXAdLWPryd6Yf0lvrIjPvEfw/NqzV2NjKdWYUe/ujS5AEB+pJcwlvjG+CuZeg4kXiJf4Bn+MuMbXd69PmHF/bkSfxK/Kl/fI9n7lyeIi+HXT/IhDu+2geNac7YV+RBnvr6Q512i9U0cxzHQ39D2WHEPoHTjIpZ4nhXgFjv+zks+IBmVP9SA56t8MAL0EtfnZf0OT/ySL4Uf7Yt08Y9g2H7cTHrZD3CRuGP7aa4m8IOXxnZDepF3ACC/+B+up7TfX/72hS762rz6l+CqVv/xnPek/x7jHTHmq4/8FdduaclPg++avtElP0t8on9KfnGRezoAe+5mlnyLWPLh1dNx8J0G+3GXg4WV/Z7twM+Lv8h+pbhDQfabb/SZ78p9/zGW+KW++PTnFaN/IZb1fsKN1//Sj/Pltf+xPa76BbDYR/ZHlP/at/oepz6WXkR8HuUR+wnGeEW62LfYfvxkX4k3z03Wsv9IL6Wt7F+AdSYc+FQlXzvI+PJ1g6wXYss91ld+Yvte+ekLvfT1A2rUD/0ZsXygLeMjLnEdH+s71Bcx5m/Ekes7Wf+n+JZeccSB4/faLwDXzHW5fN/L9d31QSHXd1f9V1d6Bbrn3mTJr4Pp1/7tuccYe3MZI92ENu7zIU6Vt0WZn3vHZf/F8RGjPjJ/dnt9kZ7zOv//4p43+Q==###4360:XlxV32DM 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11d8eNqNW0m2I6kO3RJdEJC1jr8A2mHNalSn9v5xSIoXXMvpzEG+c49kkIRQZ/x3NMb9Mr/8v3/7YH/ZZv76xwfzy/31P+/nr8P96w9fQhx2rn8hjNefOc5hXn+P+AGXXl9/4zmGho9BuFjiR5wb4emJH3GLhF0i/v/++3vp4Z96nJoeffT84rdhXvqYk9YZYRoNV0P8IhfiaXu5+BPJhbjEXW7ErWh6hIcePWx6xKVH9CW73llOdy3nOq1XdXwY4j8t6d1qb5c8g/T8Rj/Nfj6IR9j1Qlydpufx1DNueualZ17nxfuI3x2F5GL13vBMZP9szfUPcezEP53JGj4b+XnrOi5jtN9hHwnPbMpFP8Ylv4+Ev9ETrxfq73EyhMmOcdkxkh3d3P3FGv+vty+X6ckclw0a2SJnE19/ezNTw34Qf2TbIZ6BcK3Ej+uv/6/1pic64pJNuPZtH/DY10fcHeFpGIM8FegZ6OfY6ahPLDt9HdGmP+5nHet3fOBH+wC/A36U1zTmtzo/ro/85Crnz5Xzc2ohcjZ7ufLRjL9cztjL1YLV8YoZF57FuMuuztbX35GN/RN6L4R91bFJKye9PmcIkx7poUfLWog0hT4nehyDcPA6TplxmlcoRNwty1F0fLLc8ZhNw5Nx8bNq2DZaryfCpGd+6lm08zqiTeS/9LlSCK/AqWLb6XxTZDn4fAR/o88AegC2SdOjPPU4tfNax92f5+Uz4Th0bE/Ccj6I5Xxi0XGC80Hs2X9EL8TrntR3PetTz7Tp6ZaezpcRSE45L9HLRN4X8NJUsWf72ScYtdRxjj4n+wz25+Z0nMau/22vwfb6QjfDjituVR33SHp1Q5j06EuPg/SomxbzyltLj+jo3h/5FQKu/HDhs5rLr1civNa1k+Ndor/Cjzh5wjHR5y3HeZcphX+jR47Lsn8s9oprieUymXD+gGe1pI/Ef8Cozxj0OcHf6GgvxInTw2lIfsSrYLtqKdEP7W05jlfmR3tUtlf9sJ4pk0tpwuQHY/lB5Xvj91LQncsV/KsadAep6Bx91Ada6vRkkjec5lWtt2yahpOdXK2by7WthDiuzr7RWyMs1VkJpKq4ymAs9POkv66waSXFd3ZtwG/rxd2U1u2mxP0i06VaRLocxU1P+/rH2NdfrnA+j7oEwkIPQM9mpy87+s1VDGGhH4b0X7kgUsohPLh0fLM3n4fIf3R2yabLg3TP5yEYzwfpeTLmFIT862LUZwpDfsSFS9Rz0pWyrG/K9BftgXTBNf9+PaHfV53vD/oT+hvyv/kj+gvb90i6vyBd7Cu4erLffb+BXgzRw8F+A/xof+SXFkPWQ3/E+IL8Rezfyb7InwfvxyUl8r/5B/BTKJwrFE4KhXvB56t/ZfYVCLNnw3DOEEMVvihiaMFIt3wwkhOQH+m97Ae5WgxSJO7rn2nfXzDSbdD3/0SvsH+hMDwbH/AKBDSW8TpeiSE/AzdiCfRLbxW3CIGHL5rk3Dd5AMtFGkXHjS/SnVgAn4nW+7S/PyaPyXRcGmGxJ2IjiZPtOzHRxD0RvNmj7IEY5ZXPCx33i5DI3s677YkE/TEBPcHFXolqTzRhD6wyC5BEg/IfIH9wVNNJj5oiYelRc9rp3e302hizfEIX+VZPZXb9Cd+JGO7/mz9aokvthvwSiKRmRX4JfOcHe0piuf0J+FEe5EeM52G4ppYZAdo7T8uzAa6xgX/1xOaJkb+xfZune4j87jQyO1D50X7If2briU33B5FH6Mjvhy6/0KW1qDTxeefnuHJanR/lR37Zb8X3pPkr0g+2z0+85hmX5XwAdMwfyP9mf+DH9fC+SHxdhZYaz5CO8fBKxNasRNx4rHr0vSfpKxWHV3sqoTZyDVjjXiMhdm0PLYPb82pFNEo90n6Wc6Yn/kZfqe98qorrG273f9pBWm+5QPwTuuz3CedB+8tVHpU+39suv9SUiFdPk7dUxevfpcEXuouEP+2/XKE8z+OoPHbh0P6NfvD4Qs4vcE/SeH3cD3HvhKujmhDxaPO4xieT9qlllCdGeh7Xn4/8SLeBsIxxEB+MZWyD/jM5BM2Drx7gyOOIe1wCuHFvEqWUQBwg1fDYSz7fzV56oP1PT3rkomNc7+38QF/E4g9y3/H+f6Mbt5c+jseVd2hiXD/YY6a9lMF4EqBUeYsHfD/vUgLua3eEpRR6u09jp+N9SIHHhXJfwJ/OQljGgHieaeylJNpLxkl3KQf2RntSKLc/Y8Y9kFt/zRlXTyU1zFKrPR3zE5Yc8gnXsNfwiB3UmIgPGM6s2myfs7l9ztbHPqdzbp/TjX7nbAr0gYZkZ6bcahzVIFIDIH9yMOcEfpf2OSnKK/Qf/fW5q9gP+VFe5Ef86Txj0O2F9MBDmjtQMBZ5kI77IT854uOphU9Rm9tHM/kJBJ97J78pQ8fFUEKsk+UAbKHXRRwGYVtF7h1XXu8whEmP11OLQHocU/uaoxjKQ5Xj08l5qbB6SB9jp9M2j5cQwe8vU861z7n24fh9BIpTI3N9FHXcuN4I/DUQ4j4ov6683DRcGsn5CftAOGQ6JsSJ9Y5VrveOm2qHx0uJcKhf246229Nlwm3o2FjCqbDbAnYsx31dAUfe7541A5bz3F4q2PgTh+eHdwojyPckPDzjA0qD4xBgM/aCVbDcy2/0kmCWgRgSUjUQh+Meh20wW69kxx6HlwIUNw8jGeOKa4mi8FoP4izwu7H3zigP0iUupsAFtAxjuWBHOsrzxm/275NQ37fzQ35YD/nJUZ7vFM6uObxcfImTQ2ZQh45N2b+8QSx+NZvM6HYscRDjouCYtDj5eKegP1OoheKLvEhb9cyFV92lY36R5U9+uQW42UHhP+j4SCNtL+8AF0f4frEG2AZab3vJZR/PFOCVQnCvRrmsdEVtWqB+JJTBbZyOYyD+bnW8wuQmFmLTNDHLT9ZKfhOzXuHH+nImspO8OGtsX3lhhngYOh/f+eUb4DMSvl/OAZ6MRfC3/eWlW9Sx9HvyshKxxG3ZT/yhxT+kJ8IiH8o7uR8VQ7/xGzqY/SAezyTglQSndRPp4aI8cCyO/rb8ATd6GGe6jlMc8fnAEfE4B7VBbH7xt/uB4xd6h2uCeCbNDI9XHOlQH4sY6rbEG1Y3eT5PH/HqbuP7Nv2xTdSC0HDcZPLt9Cd/YRh1fHCTl8/RNBy4iZTbirh1EnMYvr2I2+5kiFewVNQcDzWDljIy9/L3K2aezRwfsNR+/uBDBRzhLiOucFcQG1WN+ROk+u4U5QpSZiUN/gJxeTcHdf7C8Q7qO5bepPGzZHmbKOfxjS5vHZ3XsfSiK5kQnf2peZJv8hBj8u1p7C+T5Ud9UpRhFT9HBv5D/JVvL+73Zh/gvwztzM+z2ez2atRdlk6+rCqQXqUWfrjObcJyFa9h8eSV8YKGHR959IRvyw+2PFdvcnKIJ1d7oumI+0nIK1k5CeRv8qpVToI/f8ctWU/COcgr4T6nXf7JD5vf5AF6jHwy9vfYczvSLH1+lSFZo0vk6lyWID+e35u9E+HadX5cH/lxPbQneZr9iUzVauXRCij2me5G4HfnVcerXTbP9IX4dMzPx4744Hft4gYk5mM4UZ2WJ+RnIMsryPqMTdWxteMS1xryFsTnJLE7x33Eq/myz4CKOI9dLcTrFihqPn8mkmAc6F73viQ2l0lsTrNjWuf5M400fvezGYlj8jMZKeYRi/5VfnYBWIb1oj/iIxEW70McXZ9vCcc9hgvdaWpYvkxSHvSTL8sHnOSyVf61AmDLaUYuPeLKtefh6dcRiCPzpzR+nsS6+FDDa5dMlpG7PNnLatXx61JfxuNYg3h5ySYW4mg0MR+drfWH6n0cSzJ/7mw7pnXSzyglZf3p7Ml2ip3smnn09wl7bmnlHBA3+e6NFTwMN22dzh33Q7x6x/3cARc452z265zgOiN/aLvBUV5p2YW+mk1pJoy234q6brtewI90wXfZm4an96icHIGO9kP+MvamGfnJER69d7daE5ENmyuwWfiLiPoBH6rflqffql3Ewf4v+7x+1fdc9w03wnL8gsU83+ipDv5KlOUFfBT+nNfxyTXJHg0fremwahKUSQpPnFvhCUzVceUJcLT8zRtgL5NbKxNqCUd/Rm/cYRvPdMAmSelCmNRsP11G3IN+Wmquyrdwrr0H+Jy7U9GxcYN7PHInxNkSPhtdQsR3h82XdEW99FT7G91zkhK1EctESMyA+iUusbbBu3u0zkP9ZWzk3Ja4UB4cvGP+gHkwUDoV0ogjn94SJmq4jv10EQ82y37az9a4qzFCfj3Ed1O+Nlk5U8Up7KGUtpmPbYb6u1Uu32UbGSzIsohlsNDOUTQsgwUJEYjldci6Q1XDqe0Z4g0nRU1vHqEwei2Fl8JOzp/Lace0zqMtSE07lZDgVLiurh9wbJq4z593x6BN2yJ/5yf7rCuQn6eN2DrubvkYEBsZiHCiRiyROkcdr0TYnokVseGE+DNI2XF2SmT3j7q/qN+hSUi4zc3l+X0JAFcuz0+uBxBLvVDNB5z0dkVwMUr74h9tRzWa1yTuCqTryCz2kDLngf8PyWV9QQ==###4432:XlxV32DM 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10e4eNqNWku25KiunRI/Y8gaxxsAxrh5e7eV6879cULaPrADR1R1svaRAiShH8JXNsX0/zbXyvXzn+IrCbaHqT/4KK2OeHeCNyOY+XMRDLopl/nB4ZD1bROcjOC+fpv2S4Lx+7i94BWC8PN69RR6aYKZ3xvhz3XNn452vv5QzbHS1waRB/ZhfqZjf6f6bdtlf3Csa/r//vefaEr5Y/6kv//xwf5xe/3nvz6YP+6f//P++mOL/+udj76EJKr0pV6iVTXltq3xFWSr+2gJ5yD8ULWqaTevRxHkKPespiHsq+CahZ9xCbNrvMmveLNr7C8xnYlrHCLJr0e7N5XfzK7E/B72MsBN1j+61/wcdRUcjGC2V3bz7xEad6jEOVTYHjnOofJmH9IHrmfaej+4lnng5/Nl/rf9if9y7YVbNnZlL6ZvubmXqzfl9y2MmOmHE7rNr0B/40+74C10D1jws38yv4TaMYZam0Ntf4Wa9wWmuZouhah/wAcdRb306NSUmVwxkis6cqVaZ1cpbnYV3i+22dW2NB9NMbMrRzfvnyKFgiFXIH0QitCf9al1dh3mf1uf+OEavUy4lT5Mh6sAlyT4dlWiH1qluoebFX+1ou/m1NWIn+3B/Ow/bG/Wl/lDnFMp+8PRBOfziZ9SOfFLKNQeCl5DIZc5FNxfb32pWo1d6knilaK12gVz/a5z/rF/tr+vn9t/Xn9pQ5AlM69cX0GWfhYXIZ2VxQ9VMm7mXGGvh5Cz8DPOyt8O4Uc+81XoKMXmAfd/JH94+T1jtErYj/FF+yN/hyb0cmjpTyat8KGt1L6rkzLe2yatzfVKPozh5LEKRpAAf6NbTRJxu+oK9yB44eKv47Uv23dXe5Y1RhI4qtjnTILv/uELPZfLrfoJ7M/+xLg57dTyGm+alJ78h8+TzztrkPXDWvrjznTSJxrBd5IneydNgt0uh/DN8nqt11if5UU/BLoE7zWGqntoPQ8NBQ/X3sT14LpPuJvw5VqM4YrJrfEZ1DXV9eCq2Yjq3+ioFzAd6s19lDCVX2O44hnUtIRDm02PehB0/VJnUzM/bkGgx0CuEGZXQCrC71OcXYn1Rb2Hq7Qw/x79BH7/Zh/S567fQesZyduK8HMogx/1CPZ94+f9iT/UOdWyPuyfzI+rkdvuUJj43/Yn/hCovpov+xP/K9QO00OtSKjZM0+h5rYeat7v/ZbXSFXKIvaQLvv66SpfUS+d6JGlNWK8X8JvwhojdJ7w1RSjlQyyfvDSAsAUwExneYGt/PX6Ri+bpDGvHdLWznPs+r/RTRN6PISOrN57NjNmSdssbhFtOtowhzLzZwwAjOiLrHwcgpGVQe/WtPOAYQ51lrdU0aeoPRq1gomuBnxesTQ/tv7sT4lSAVrRGmb9wc90TBU41F7laUF/sz/xoyrHLHS2J6r6j4Os+N/WJ/5S5q6Cz4Ppd1dSVN8668N0dD1nUf3rZ/2ZH/F/y0fnzfmB+TkemR9d71nX8fsmH/FLKrO/Lb95tfyHG5PbMSc3+0pu/V6NumJ18TPNxmF8192mztjWh/NId3OdQp6/nYPkeaNrHbqQ7AgjGHJdY6N9APRh3Ot4m/uCOfizmYO/37Xm5BBmOuuDuQOSD++X05zcItXVvczJYacRFlrae25A9rZ1Tm6eghlzjzt5avIOWRR50xfJvszJHvztELpNa37QryTFhvm7veV/Ti2+xF80GEFnfrY/80c3Fyc+b6az/GeZkx3b8y2+3vjnZMHnWbYm/WJEXzTzO+qrmJ/1ZX7G7G+SXHxPJRlXkvjQJ/UGV1pqp9M/dcXjXGNcMWyYp4/ATEef9MSPo3niZ/qlodpbRDvWvbpZO6aOWNa4R3Ibj/IJ36lFR5Rd/fPf0Is+fNxXGpIPqTYGwadRDNf6Qge+Uz3hXW/DT/vjvKuTKwWf/zc67GmTsStctM95Oh813+WzdSucNBTTIfyoo2e1y/UYo0+Cve5SEuY+6omOPg2p4G1/xR0ucYvz+k/4Dl3d/9S+5xt9q3PpYZxpOsHnAfpuNN7IX7q+bvo9+7OOzEFne6EUohRxvKYkGPu/nbeWsmoESyoLPZVFpLI0T1e213TF+oIsjqNCy1Ue8J0azBpbM6cGhHqJeiX7Qu9Zv05dGOF+NJNpWX5UofaAIW9ya2zdbNq39bULq36Nb3u0NbZu1p9xbrNrvO2vTUFra3y6daimJut9o9c678/2xhs1XJnthekSXJH1yXV2dd7voK5RXHkbXwvmN+ro/v5MCYvug+75wtX49yo44d4+XvoYnlf4fiuP+oCtVymX/x390BS3Hxiwz9jp1fwwgkXP2PVseCAMD91HcbOq+3lnu2uFjT4QYcrB2KnJMbUBTrlfgP8F/VR5yiEPUG3XB0o1JUI8mPszj3M01Te614sDTMfrgx/yAUO+b3RP8rN9fzr9sbFlzPLw7xvKNaYGhM9Lfx/k94zvqYczQTrz2f7f6Huh83Ft1wc5mVrklkZ/YPnw8NirfVvhXn3TeItnvCfBSDmMnWt5vpjNmOV9kh9TO/YXfNaDUGN+22Q/VNcnOqZYbK/u/2m1PtObEfs/0a2R8+L9Qef9mf4kP+i4qLO/B3RDKh/HM7of0NmfYF/QJZXtvynbNrd64E164Sx6AQbe9dYi66RxHbNK/Sgxqeptx0v85LbGzag91I9bL64vOrr5L3Rf5osy410HA7hYM0Y3h/MQPfOg53lOem5dz63nfd3nqHqOQRJ92dZ4i/OAgjFuiXuUhy/G1UkayscaaxrstzjBokcZz8uvzj27WY9zaY9jXCd+8p9db1HAQV8PZJ3hQwN7ffTDkPTbKwxCgsSjrHOO8rRP57NVfQ3xeu5tjWFvY9b4fi15wD7MH6a8YfqGTPRooz38Sg+cD/RwOigKdo0hd78DuFFO4G/0rdIHNg941uMa9aBBjfu53Nzn4aqc44GBWpU6+YbjeY15+LVPNeM++2of2Ove58R3nrou4dpW+9ihxaV91E+3KLd9fBADPH0QU39m4Zuuc875svmfdYIv3e46IsY7hzbJHu9IM476NHlfGgi3qPdardhv62OOoM0346r/Yp7A2GLO8LD+qX/HOwFjrIdLTr7kcnJfeohumlj2/rqH+Jm+OZ3LHJhHzPa49MRwqWF9gO9RNK23Jz358euJ+jOqDDjpObPl7jG5n7OORh06OXwCqOfG+J6HqH0Z2zTLnYvZx3PYN+mA7psIYZaHsauzXRnXMtuFcTSznVhe4OlyWcMYeWnVYUSNNDzRm10wvm55w5g7XTr/JJy8dlp1ja+inRe+7iK8ObE79GLc42Z/13O8RF/HpwxzqZ2AaxjmSjWOfjdfUkNfp+eXU/0BfuFOHXbouzXTj12HF+onzG/NfG7Mj/iY9d1HOeNKzp8SNsl56X73EIHk1Hkp8grzm0pyEv+2lDON51JWFWbXfAM54G+wD+Oq/8775HGfutoHfn7vo/Nl+4BbXO1Txn2uT35Wkw4ZFedgfyt8Pcbzm+My9XVSr7zm9icrlVGHYnaNkcf3uMa75hsMs97WxxDOr3HAU67aifGZMPRUv2Cs9sTwjOUBnua8tY52KsvhWCI9CulBOETSg7BetG65EI9F19lITuY/3awny8friZ7n6FdtFc+IE6zTC4sfz5/xff7lAcdZbsapzHqInEOH3XdbyYk4u+WMKpdfY8iFITLjSnIxzm0l5zXK6T/FaU4iD3AM9rdzPc3of8vh7MH67njH0vNmuu6H9ynG6Avgj4yrrrcd8jver5I9mH8PqrcZ8tFpRz3bSs/K/of3uvsdbqanS9YvD9iHWS/GjeRmHEmPN3lW/nu60S/cpzjrcvoxrrJdY2fovAjnQnmXcFnlvdOPcoZPcXbLqfUl+zW2ZZaLcXKzXIzrUs4wyvnxZheTxBVw/8n+u842+N/DJEzzbK8T21ifol9j1KczrzHqkzsE8/rob0Jd86Oe9b58yY84A130HPtLmhxSPbv1vB/b1nhzs16MLzPLzeujHoWy5kc+ufUkftTDWc999Iv4Kc4gB/JYamuMuuDiGsc4y804uVkPkTONcqZPfeMtJ+LlAZe42ieP+3y8n/gkcQHc4zj/rlNG/wkr/8H9o/vhPvqL39Z4C+Q/hC/2e1of/tDzyb7iRx5m/wE/7jfejPlg7I9pQqp64v5y66n9cG8rlhh93p0PCFfye14f8W0VM//p1vkA/NtSzzr6xcf7EeRAXGxtjRGv8z7nuM/H+9G9j/r19oBxP5r3aeO5pdXc5uB9tE55v8aI897fxBXGfOsJF51rXIfgt/21/0I8MEb/VfIao7+qh03G/D/8p46Z###4516:XlxV32DM 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118ceNqNW02a5CYMvRJ/xtA5Rw4AGC+zy2q+3D2Upecxr+yq6UU6bwRCEpIQwm1Maaab8bNXG4/fRrA3dn39btG643e16fV7DYKNsfn13//++yeabf8xP+HXPz7YH9fLX//6YH7cX397v/9k98tnX1qXeaEJXxOtP9bx9zjv1r5+b13kYtyWl6jPuJNevH7aZT37gL3qWfI97mQXXm9Psx15fLyzYzfDjl7s6E2f7BiGHYMvq+ox5DzmGSdyG3uPnZnlZpyLYMjNuDTB0EPktFc59zs5YyQ5dX+Nv8eO7Mu4sFyEm7mT0/2W0wU3yWmHnHbY0+3yk8R/gFsQfxM+/srHT3yWwWfxJSSZZ9oxzeRt7y9s+z0uTnDO6ieL4NrN9if03PbthXu9x0OdAzuNZ9EjXPWIn+zRkugPnIPsl/BZrnyWO3tEI/O2JnxyUb7+Htcg+sUs9nnCsAdjp/aH/ox9FzzbI171WD/t66lHIz0I10JyP+BTD8LBzHIzXuKdHutVj/xpP0Y8e8mn6k9P2KpcTv2LMPxxCHGLu+oFuRnv6t+zHumqR/m0H6ceirO9xymr3EHjgjDk3h6wLbP93/DtfuSrHttdnNW+12OenhPAe5A8JHzK4JOVjzUzn+5/ee/NEbJHqMc2suBxFO6HU65PuAvesylXlQf6I7rTVGOrYO/2fIRAFpzsLkaKpt7RWxR8ukKS2ATdD9YHvct8ppe0m+v6LezrkcFXXY/mMy5xnh80Nftyz49xSb19wtn2Y/wSTLzDsfdDnlSlAGBsiuCejb3DWceP1bweFXVK/UVdS12yJbH3aa8meDGC3/glwcEAz/aKRTDm837GIBjrv/mLYszn/UjEn/2J9Vmq+qvSeTzvL4/n+Hka3+J5NFdKZe3qnzye+fF4CfV6TRn9LvXlIOt6LTV7FT3DA4YcWxM5tnAv5xPdR9o3wjHN+yh6tIsei/2U+lByAc8l1zb4JKQ+Kt22kfrc61bh2kPqCbK1TK9udp0qAWaGKxyprvd9OTLfIvMZx0VSEVIhUgvwN7ppu7uu35Oovvh7eRjnvonldk01hI0VvDhJNcBBU8I3+jrO70PfeI/3JjjqkcI4aqoqXsbzfozLQp6OFsJN9ydU3Q+yz8gpkgI3PRoI83qMz9B/wKiasT9Z10dqYHkYG8XwN2BUd9/o2QiuVUOD/DWlOXWzP0XFoPN+jGUOvEEOsndU/uOKWu7sYSl1s7xIjbu5VjH9WsWEKZTHbfVVxfgjNzpRQbOTYpiWcUJoNHUtrVKAv9HHKTWptvs9yAVOT7Vtj59wWfd0xY5c+Rs9kelXDUGEMstj8/iXC/5GH641u0YW+cfWxbv1mD7sY+RiI3b0ri9X/I3urKQGpBbGSC1rv8e5za7bpW1g1i76sPyMR+ou11ADRqh9o7s0uzb7J8vD41GFIRTY3zydnuwPqKIQim/7meZQZ3qgVMD2LG1OBTVKtbdWkyS0BVcjeFQVB16yORosPL7tYp/cxX94/GIlVePo4fG8fzxeUsl+rS7MXZVUmh512ojp2AdtEDK2Zk7BTxh+wrhqVXaWFISTHp1TlbSbqx5zdROHHvF3tXfqofu0e9WDMI5Cv93jcfuTo1L1esLQi/HYZWno1QccNT9PetqrnsunahANJ+Cp4bRfG3lLuLMX9h2NmtXK0V4esNGSpenRzxilQ9fzwsJvkL+/0DeVB/HMOKhfIL5Fz2ujcYmf/AJ6duWDBtQb9prnjOZFwtBj7N9UkrCeT3TIA70YL7d6vhqRBSXB3Ohx7igJXj3kMFdfq5ctwkWqZxENKRii2nCPAx3BjI3TCxSqT+Lfu4TE7yNmxrte8E/TecG2CP5GHxe75RAjm3yHu2Kk3N7kdoL1t3LfSNm0J/eN7oMcGbjYlqXLhVNTSbM9f8J9lUbHE669HyWGr4IjqucqoV4iqlR9G6D9iG0+EtkesQvGkbW6Xq7rJcWrUfnYf8JcXbM9cKSiscH62Cj6gj/7qw/zkb9ryeGzvF2wPZiO20rU0B9A6FEw07vGzzhK2914ji8eX4vY6/R38re3+CD6G38az/7F+2U3wSgBeDzLx+Ml1VzfKpb109GBnjLkrP0et1VLxSR+wRh5pxbtfbe51PxGd1RCMF5uS4rrW0be747acXs7SuyaJD6AU7im5utbQvGf+KQk84CXcJXn1cvfIM/cA3fJvx4JjS9Ne33Va0oLkqLOlEd40V7kWXWuXTO4mlLHmzyS/geMkGIM/qlqiBF/pMygKYoxUiz4MX4Va1f+WP985kNKdrM+oC9668ItAw2nLeKZZR7POLZ5/pN+WJ/xor1apETeP+bHmOVlHNzMf+/6bqdHJjD8gem1zb1kp7g1lY/lZf+L5H9x5v+NvnxZf1nFnrnc4yf9gKEfjsQ3/RrpR7g3kp/wGmb+jIPuP45gjkfsH45gjien88flwt7Fg+8znf3dKv28VZM/e6KzvzqVD0c4+1sg+ps/xfltgvfb09vF236R/SRVXp8Ly/op5S7pbMSJnOHy7LiXK5/6iQ+eHYGnZ8f9+hZRPh4l6OEDTz38/foWUG9vf7n3o0tW8GyreA3mwuf1FrBoB5GOcOv38Lou2NdzgK3bMXtk3cOtx/l6FHTFipcz9m6T9rCX8a3I6lUf9bcsBW4q93jZOgrS43RhjAK49Hvsgozfqs7P3UmhIYUoemJPeEEPx2vvqAu/4lW+2I//6/oCxbgbWS/kexybjM9VC1eSb+uCUdA84WqlF8o4BuE/jhnBUewfrPQygcfd3X7C2E/Gm+Lm1Vu1Z7o6KeRfDyuHfl4weryg83imr1EKXsjDeFeM9ZdNsuLIUgffURMcvTHoy/S1SFaOKgd62r4p1iixVgtvwk57NJhvjfi5foJlgLHfjHMUjP2PYavX555Wt3Z9HmJcnYxHz9Gt2yannfAFXou+GBMd/Hq6x6Vs9Rq/8M9RMMtnGUbiBfZgetCX7pFI4p19shN8XljJPzfNF/CfWoX/qs8ow//cNJ5wUP/H/FA0fsV7xrrq73rxZczy9E3eA7PaJ1XBI+5EL9Vns/Lv3+hZ/915wWe1pvtj4jyecaT5Noof9uVeXsa8XtcvQU7+X+jAo2xodzhqdbL4Xq/7d8rjxL5xu8cj/6breoyrjof+SfmaRfYZ/uatXFwZI/6Sl/F5EfshPpjfG3/dz2hFDsYnH4/xcz5CgyrEz/kqFs2XaLxo/vtGL0byG/Jj1yqW+WN9pgODH+NM/Nl+yO+t3+OUJG/gPGE8qr14ze/FaFyrfHx+sP+zPE/yRad5QfnDP77R8SY40mO9w87oG5H6P86X83x0+kaj+em87TpdV+MPeNym7FV/Hs/0qOuAP9uH7Qn5V23MfaOHNPMfdV2/jgeGvzCGPYreChjDPth/5s/2TGgMEv8nuk0zf7xhQz9ej+l4czz3Tz/mhX05vjnevtEXqk+YP8tntBuA8573mzHze+OvH5XifGf8Vi8RtmWuj97kQz0E/0J9oPy/0c/6QeuLdJ5z+kUlrceY4wv5G/y/0ZFHzvrGUX3X5/qO5ePx53ra9PhGjxonseo39syf6i2+v/B4xiMO/XV9xsgHQe9zjJEfIN+i9VjXOGp9vg8xdmG+H/Vd6tOWZB23bVM9wxj1LOovxpub61uuT7jeZDrqXfBj/Pok9lqvMF6d1MeoX7he90nwmX8eMPLZ5X5g/oju1J64P9H+PN0fgMEPX4zuVu77wN/opUm/APdVxlH7B7i/8n7AH/wDDkbkBT/IMwauf0KHvE+4JpEX8mH+ov0LjH/Cqch8+DvjTfHZH6D9CUH9AfGD/dUvbpm+LduRp4rWvejndHOPu+4HxwfbH/HI/Jke01av+Yjt9UY3gnE/5PURb4uR/Px0H32i+zjfT9m+vB73r/g+yZj5veU/0v8Na35C/nxbv835nHFMei9RezI+71vKn88HPEDjj0IYH093n+QjfozRr8N59oYDyUf3+XE+evUvd13/7EepvrveQ7lfZbU/CDrfx3PTvJ7u79s1zfRRt8UrfQvqh0q3br4PZ9S9STD3yzAf+nG9sWicjnt2vKPHNtOr6ol8Fc5zQjD3o7Ly3/QzVa5noD/oXI/gLxmK/nGUpXogmvOecfzUMPezjJ5P+IYuE30cozO9zPQaBYPO5/0odPSPhLR/Tf0u8Aedz+uk/S3sL5+nNup5Av+jfL5pvxz243yH9fHBQ+1zPoB9YD+Ox6L9EtA5nlqa6dwv7zrfGvnwg/t1NQiGfNyv243Gm+77lma6VXlB5/gey03xPerwKb6qmeOL+02xz/HF/aJd7YH5Jc10k0Q+0N/6RRofVcdxv6e0mc79mOj0FRL5h+hrJ3pXP8F89RvQE9HXNtNdn/NLpfzC/Zaq/RjM5377Zmb6yNtTvyPoPRn2534IvrEFfdFvdnFfhH456X2Y6NAPdO6nDINb/Yum236L1W8qQed+iVH5T/+jfodtM537Ff8D3XyiMw==###4432:XlxV32DM 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1138eNqNW0my5KgSvBIChFD1Of4BmLTsXa/K+u5fmRHOy3BJlf02z9wcMQZBTFmLW9z5d+TDHeffkp1/4RYE92T5PI7++r+Hw7/+hya4ZcEpWn4hfi1uf/WXwhFf2HvBexa8ER+I9zo/8IfOH/xSLA8Mfi2yDhfOFb3HFxyy4N2P8cbhSG+cBaesuFi+NMsH7S/V9+zO/gQXJzhin6rF4Nc2lve+h2P/xC4f5f2ds3xgvo3wHrfKvi9ecHeCfbR8YL5Ifzi/XcfD+VXf3zMv4Xj/74p7Fpy8tPdhdN2fN17z0PF6e/en8nUU+R7ylXwv5nycYJxPzX3/5CPxQb8/gpwLvvf5DY/R5Hvwkfim/WN/jigY+8Pfd+XxvYt2fLSf/TtZb6git073Y3OCQ5L9gnxF3X/IV8yWX7Plk54v9mcrgrE/Tc8L8rfo+JC/4Uc2vBv7J7/U/ua73gNeb1+73IskmNsfi7Q/70W/2+9WZT7guf1RhuilReSJ5W3dhzfjUfsQRvzkuX2tgnHvuf1o0l9cjnB3X9Df6kTfcPsUdf/X473OGu19Ah/3Y9y1x/6ssuuX9hi/DtEPrC+wvi2rfqH2yy7zXLOeN+mrU4zD53jcflN9eN7vcdc+NpWncN8+rXJsWB/rU6f6eXm/Cqeep/bcH7c/mrSvC/SJfQ+YR/9F98dtgrei+0s88HmLtrv3xkWVM+of7TF/X3U8ah+q3M+tCc/tRxE5gbzxe838WhUnfR8J50XeFeBF/49V+yf+0l+W8fEet3SI/lqGfDf03oRR73jI13nPVe9KP8DM53is5n4Ofbd1/fh+84K5PfZnW2Qe2D+8V7x/3P48DYN3/p547Fcqai850QN8Pk88739bdF+Svr9Z5AX6kflTbRejHwmjfYc+VPnbcc8eeMgnt4e8xyLnvej9xvkzf2CeKg8b7sMh/TLP43H7XOS8sb5z39Ln/jAPeTm7G5+8W4bIgf/z99w+6fuK829FMOQD+7npeXP7lATj/Lk9467nP+Vf31PoyzqsPTDf3yZythf7PjGflYccMkb7hvem2fdsjw/963vP7f/99+/kjvHL/Yq//w5x+eVr+OufEN0v/9f/TqPol/e/gw/l0H2tTdaFewA7hvkWLS/jHOc4AePsZpzlHGcJZR96Pln9EMUxuvDCr35O4uxn3aWjNdt+whJ/hxBcWM9Z6+lUvRU4nWktK3/aJJtYKWI9nW98uuNh/eL1SVn6m9Knu43xmAcuyzhs//B6/swPZ61ltGdr5jztesdP6y+RNai4kvWY9BSXRW4d8I/1ZXH39naMLNYQ9hMY/TGfs7W21wXaR6RhVakbu8V1F+n4xkOaenXxheOu84e3RevF/ObrAG9Q14fvU7bappR7DO0B+ctq1bcu2hbWCbQb46TW19SO9P1eZJ5oD2179tP/C3/u+vrZP6+Px7vM3+mrpa8HXp+Q5fX5xsO6w+vF4+N85veK5/584duwrzes5y2IvLA88PjMr4fs5+Z0f/x8Hcsd9rR+xl33MweZl3euvq3yQ85l6668MMZjHDbBiJIwPp23/TMatVWx6uf3q+D5PeHSrPXF64c81XKPz9dg/fzeebU+dX3cH2NYp1HlhfEpv8un/ODV9FG9e7X+gHsUjPv+jQ/JWt/TOkc0zFn+nNwi1peuc1pjagV55VW/cHvmo1rZ0D9Oveipn6n/oVGSqa+/8Bh/SxqNZNzs+HimpnySPPH58nmcqHzO/xvP+93zg/f1wMdkvbeSDrN/wHM/VP6Tt+0f+UbRWtofvs/M5+DSO4iF9TfBc3++8Gt3+a3HII+MvY0G9wN6UPQZnxdjni/jp/38OV+JGiCaw7hp9Bnzg7wuRe0HDUJNe4Lw6SWZ6MBlfXRfGG8UjUY0YA8yT+6PMc+XMfpD/3jfEU0BRnSHcdL3AfYZz++pv0t0R61yxnh/p/eiVn1W++vyXhLm+TBG9ArzmdGGZKNhT/xwakfr/EYVe2xVLx7Rt9NLvMWIXkLPMEb0E9G9qPZornr+Te3X/c8Y58V4pWzC2vv4nD/s98WJfDBO6r9MfU+4w7vT+8P782R/P9m72L/UrD3/xJd8H73F/A+N3mK8J4z+GSeKDvP58H4+7S/kgfGgbEwq1h9rur/wv8oq/QeNrng1o2FvbofM/1xH+y98iTb6vhy96/66u/HwPfA33un5TP+C8J7s+NifouP3Yv1n8AFZTfUnn3BOff+8L08Y94VxK/fZDcyPz+si/4e0T2qHMub9Zszj8fp3b7NRrD9Xzf5s6z1meWZ8Wc+D/sN9Y/85ajbr9BvcHeb1ME6abcN5XfxzXe/kCZdis2GX/eH+GDfy7wlXjT9g/wfFIw71B5F9ZX9+GYJ/suvWHz3fJ6dxCtlv8tcqoqNZ/X7yl5DNR3aW/Ymk0X1k12EPTXvfazWBzq8Py3vi2V73TqOayJLjnHV+laoT2F5ciq0eYHsN85vVB2Tv1Giz+5HsGUSZkR1mewffz+w6ZdNWd8n+2+x9sdl5fi+L6g/Mn98bZN+xf4OirZWy9xxvXIbcJ+wv64tD2yN7zfxSbHab42U52ex0iZSdLjY7zfGww+l9fammlz1D92eJItdP9ycUe3843oX7h/UjSjzjAWpP/lQv2HjXrvESVD8wj+oR8Kf3Z+JZVbNTk6d4V2uW5/u/eXv/OZ6E/cP3LVke6wPP8Z6d9QfFa1ISjP1hPnviSf9kZ/VPHbJenB/Wj/Nr2fLVWZ7jOUW/n+MTj/7Ac7wG9zc/xHNgZ079S/GWHK3+vMRLWP95q/8aVW9xvGCJtvqK/f2QLR8yVV8lqz97tvrTs/4kfzSS/mQ+OcsnypaHYauz2F/2hXjqf6fqLPYX8T6WB39yo+ot9ucSVW+xPxayrc7yVI2xEh8cVWeR/m9k7x/J6m/2B6A/wbO/k+l96IOycdQ/qlXgT6B6aVY3kb+B8cGzvwAM/cL2fCae7XmMD/l3g6rHsq0O43xYaJbnfJWPtjqsF6oeI57t/U7VY5yvOpzlUQ01q6myrR7rxB/Eb8VWh6E6cFYvUvVYouqyQtVhqM6DfLM9jPcVPNuzTd8XvP9sj/N7D/s9eR2P5sPfc3v2J3i9Ttc742/lz/wlHoD8puoZPi/m2b/LKh/ALE+c/+X2nK/l9qv6R6Fbfw8854e4/Zx/svKH+fF8uD3no/k+PuWreX8f40nR7ifro0s+O97npxE/ueg7iq9w+83Z/DTb08xzf6d96j951vc4j6Xft7/k86g95LVpNdrlvSH+fB79ZzyR+2N+VvtJ7fXFn2H+tAtMfBT5NZ9m1bbhOf7K7c8JdVNNSP4W+I9qP9Me1UDbZvmn+AC3n9V6Wl/B9grH97k99OCMf5I9xfmFS/sk+ZGZ3yN7jXnkU5B/4XzMhdfxZ/6T7E3Ol3H7dog9OL8nf515/h44w+6leALns7h9yraaj/0F5iFfM7+j9QYzvkv8JT9I7blegOMtqOaa+X3yt8Y2Nq36rnftWX9z+9ZnnubWn+T6CW6P/sq493efxkf7lG19DcezUF8SI+JH9/U52E9uz/VCbA9f9Be3V/nb2n08Kqm8zeo6as8831fsb3b3/ijkheUP7VmeuL1Uky0/VWmhbKaabPW/X3VkFXKneuxY1b5+wIibIK7KGHHRGcckDLsQdh/j2qwdKOvwr6q4pFVxXF0X46uOb3/V8q1dbw+sFo0ixXqPT+vLm5pcwruzUSD0j1c1l1lTfYuXWcuq1RaEm7ev0oLfDuyIitksJ+NZ9eBt1hN4p5p4VF1wFjKOex5Rhp8opOxH0VduDJslfMJ4VRkX+o0RbuFGVtUTRtRx3mo9X+w/98fYe/s9+B7xm5B7q7GgCqTY3yiBd8VaqcAl3Vu1T3xM1irG+mpVrUfjZbUq8f03/scqF6uD8ZLt+HHr49OaQVZuH/d4atUHPKs0HzD2A1Y541jsb4qQNWYvaJ6n9g/8jUcUgM/fDZsFfMJl2CzgE573gXDS9U2rFVlHrUXO2Xq5zJdM/RNeve1/8/dVv5B35oEvXp7qtW/8IK+R5ZvljTHPjzHLA2PMp2Qrf8C5WXljPLydP8sHfsM4f8OXHqIG+tsA5ndvow583jFqVEP1c981Cl9mFtboa8Y8X8Y8HuOZRS02KgMc/Z/ntw2bRWUcir7niLIOa02An1lRtTKT/lZoa2RlEu80KvX0vuP7WUX1gNE/4+Bt/yNRVUqyVSeMc7y3P7gqG+8846DZllnVSt9jP/Z0j32038N+mVXJam94Z3+TA1wpy/Q0vtesB+OtWK+GsU9aTTx/U6PRqKq/CcvWy2JcyeuCl1O8rfIFZt6pNzyzRBXe+P33sLe8Vq1Ub6vWmd+c/c3bot4JV5W6JvNgHlWjwdmqXuDKWaYF1Qy2SvrE/weP340f###4496:XlxV32DM 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112ceNqNW0m27CgO3RK98a911AIwhmHOapQn916EJfmhaxwv/yDfuSlZqEN0CuvM+OdOk66/yV447yZ+/m7ZnJ+/zRN9r1bxn9nUz99eCSO/NVpeLITPw4Tr/2fCbSM68m8HyR//3Vb8j/GB/59//krWtj/mj//7Lx/sn2DSf/7ng/nj/vNf7/uf4P72wZdeLeld+9nHP59tu+T7NY6Z+MPe2wq3QHg/iP+BHeHTECY9+6ynU3rGoWf0Zedxch2uGv8G66XXZtc48jh2v7zyim87ANeq9UZ8toUdzvzY4cuh7LDDDuuLc7bO/h7+P55y7CynKDluyHG+DL/usxzTSc5RXnCgcfU4bh6nrvxuitZ3BOugvHvBbI/48bT0fTSXtb/SayK/pmONxe+F+ckOP+WPLys7JM976JckXzivzzUe85XGjcOyCd/58gu9Za034u5WdoQ5Hm2VP2LHUdkfaSUnTnK6fcnDDHm4PfMjzX4NqzwM2aZZn3iQnFzWeMzA/NR3m8eJ3/SVcURfLScPOZXtdkbrG/zf3vs0SomjUhl3KpWCpfQKdrvZZ4z8Qh/o5BJ8qWgt0WugUt8OogtGek+EZWlA/lRMm/VDfDIuBy0FKV0V8MatER5MFKqg6XvRdJQ3HN9n+ub0UlZ5abKG9DG8FMr3vvHS+PL9Bt9vvFSaw/jL77z0Dma/8vcoUjQlDGHjbJmn2siGMqcK+tuxvHv8xNjrfLj9XTn+dc2P+BF/3GqAP3beCnj/wo/6AT/qi/F4yGf/Hzv5FzHGY+/2SpiS1vmG+iJ/4PwTOuZjjZRv4i/kR38ivz1paYyBSw7kA9IPLiVSuke+XHlUPWGkd0/22HDnl+JH/yI/lap9lKqTS5XVpd6d/rM3++x6gg6lmH40DjXQbSD6PTXZNVvjUsDfC0b6cJWdQyG7WkxlGR/x4Fel6Zafb3lf6bbo8WXXHU+2h0MhqRk84e6M+zf0eNr4Dadig0p1GP/oFGrrOHUAS2qFxKVmo9QT/Bs98+5IdqmIA+8eJZVL0fFPMNWDIXyXKognYrQXsQt6aiMucMrB8YdXr/j3QnTEaI9gWXp/o4v9sjRgPEcpCfNSgvPFZb0UoL8tY1lKTiiNycBSBfOpJL3UlganQqOXQoynT3opRX9X+N7x0i3fDwa1lON8a7AVQH/K+LLUYj3B8ZBeMixNGH+gy6lc5jP665GfwO+NxhivnfN3rDBhxY/6IT+V8jJKeeBSnvWu07vPprN43mLUylsUlrsX9ivQLfgZ+Ufe9plOehxDj8x6pF0vKfba/Q5VXNBDSQk4/BrvCXa/gCXEOeiQCx4JpVLiDd+7T17ShO6cTvkIuyXZHUrK8/3A/f3pYMo5Tc8wJQ+YUgV2p4H5xX4c70HnJS4FPWUEI112d+J/5H/ED/hF3p7W9qZEqYT67WlNv8fn1Nt4/MOCfuVFP+B3WS8Z6G+hy/jInzneQ+9txb/JaSDSeA9+1A/5g85vzEe5aDvrmv8hH/hNg4tByGehizzk3+UisGv6bf/O4zWev8D/0A/4qZTU+UKufDuQx0qlUg7ksvSRnHPIsTsJclHfiAU/alLymy/xoEuUVsxBuhGurBvST0eXNJZ92w3dYcjlXEqE5TIjumav7ZKn73IlfGa+7AF6yZruebxwGNquMc6GMNJj0/ShN50A5JJWtp+GfQ/2yPdC90bTfdH0zfTt0ptztBfCUtMcX3r9nJgJy/JhE/lJ9E98KST6O/aPLJue/SOxRnoMmp7DSXGRS7xKWLZRSO9Z01PT8d2aji+Ov5vv+pWq6V3yRWo+y5eaj/RaNH3kq4pPhviIf4Uu/hX6iFeb6UYuzyT+keimrvmRLvNnHEUL1T7CpTIGeuZL4r1+55f5iPYgHeVvIxP5uBKW/oxEz5mPkcCfCsUrn3Tjhvx7bXWmI/+RaT4IRn60F/lbofFkW/jI971dB8DT8bEY+FFf5B8JftHvy2SoR0K/byCAH+Ujv/gzyyU9zieg4/ee8/0e36y/Tzxfkf8tvsJf4tlmjPUA6fg95hvWsxHta0bJjS3WQ1lfglvzY34gv+d8uddgqMdCF3nIj/mG/N2QPmIfrgdIR/0ybQFpu7pYj+76wXTkR/ppvtcXpD/8BevliNcB9UPZh3SRZ8O63iCd9iLTY6jf0uqRSG7oEtfRPXMdtmt8OM7v/TsWvRBbfsy47QTcEz82mdmO/nPMcwYeGTf/eZUZx7xQZWrwNrDzexvjB/1keltjSYFx3Fhicfkbdk5Pucf4fMMlJ1zEI8RNTcmqXfkbPQftWielRPThGzjZEqG+EbZMKK87HapQW1PfG8LyPcbD8VbmpqP/s6aneK8EeTVeb1TjxR/IvyXW56QShPy76/tMR37UH/kl1e+SC/6WqSTHQuR/5AfwX1PBz+/tW1z3N/ClPJcmyav0gmuBvAK8wRRFLFszNWX95z1/kyl76il7XFN2+1H1rj7s4u0FyxS0bo3vKviCZZUT0xDLKilVWlzlq14lWqNTGeLkaJWRaoi4GL0KPeyXXbBf43tVamss9grugezDVeSNHgKssqhfBf3qWr/O/hh7GLVLRvqtj6yybX0KFvpWftEP4oW4Nkh1wKJfq6Qf4hL0KQDzJWV9CsZ4u6xPwehv+T6+2HsETUd9ctOnLJqKc8tL1S0vyX3uI4o31NIgNxu1Eg52jbujR5ocyR7Em+FWHLmE5pYXea/8jX5wi4eclhBLK4mcRsnOuSXG1lVplNYeeZyJjK1d41uvROMiLk3rhbinlZ5zy0s7vrW8iJ7nUs7c8lL7yl5pRZO4SsuYxBFxYP3vx0TAR4a4AD7LSs+ppcYfeWXvHnRLTWqEVauL32Y520qO5LHI2dJKTp7l7Ktd8Va1nBrp0bS2NZZH1ZTWeNut/4YDP8LI6Q+x9ItoO/bZjuWNpbQqSR45Z9MzPmWW87U+iJy6kX3+DbN/5JEY8e0fA/4w/5KetX8Qb2Hlr2OuD+cyD7OeL11a3OYbXl/nefe1ZU3kyPzVcs5ZzrnKw6NRnRS/J8P1Ka6x1KdD+qicnr+/0U2leiC3PIjPpT/mU+bRVnZI/kgrq+TD3ta4dMKRT/2IpclhL2tsC897v8aB64LcdpMdc0uus9/mk7RUynxScoKZ5ZhVC+Gob3mWU7hl0CS+VQDsymqcuWW267q6jXG2H7/LOLKOn/say7zb2c+t8LyTW7oX+t0CCvxIv+dxgHnNOMA8RpxW8zrM+5vuV3Eb9SHM9dw7wlqOn/N4OR9j0i2ZEidZBxBLXop9d10L/47uWE+xH7FvKzvm/UUPq31BMNofzVve563xHSe3xhHWK8TSJKL1VC27y/V845e+u9V2tQ6GuWXX5FXcWm2Fbnupvrjc6KrDr/Eoe9fR3rY1Tq1dh3NpUkLcC+H7dQdxJqzt2H6OzN7Cev5pZrCfKZ348Vh+BZG7hGqNPTwmI+7wGG027hdp3H8EzQQHP97ej8M8JYWO8mTKypbjdLofJWP/0M50/lVHg2YFtB/5H3SwR/pl7otosMck8p/8qgX5H/KRv0H/Ddjr4HEb+U1meVHL+2mFhvGBn1Lps8Vtkkp6S+e2qy9mH7OLq4ntHMqdf2BBChuk50b0uy/hBYspb7jtNIsQS2vgOCUvsexe3vBINdU6iLjwKfWnSnEfjtetoXvQfS3YuvlGl67fQ97oAB8BWte461xCeZ7c1VvurnHl/zNyqDk+kVukJLUf8QTcOFXvPpcXfLfeAnbcSnj3IcH4EVpdEe/cZ/NmP8YDsfTp3FMhrVtr5XQu/hf8G32r3+OD9j7id7D8uo5XMroVE/0pdCmV6K/TEb679mG+Gu763/jWCeljVVa/CsD54Aq0ekI+ZlgKHvZCqUZ/JmjVxPmwQV8b+tsW3ReH/h9/20ynUrhPq2qCXUa8LqLHRmNsg/vcIiSmy1sMYkmlwPyxrVvg3uj3DwRYVcQx6FUJ9QuNuyHtGqeqW9oQtwQ/eAH5Ubot4xqLfZFb9OJLC+Ab/bpim1ddwBV+wIP+kBZIoaM9JetUQPu6IfrdbZr1+Bm6gmMG/YEf6bf9jvOHp8pewX/u7n7V+Qf8lMrzRU1aXvh0bs2UKVHBDpLzuQhJLMfr355ac200ky9n1aLGRsTCxkRhMSmXNZbZeXe5cmeb3NEfgV+IX7BzRlUrlNeDDjnyG7nD5+pmeXx/sM+YX6rnyfKELuMJ/ZDOCd69oLyHfci/c2gC2wf8jlNszIS04n/EB/jF/y6s7UF5yE+pMt91peVddQlaj62tUu6cqjD8rNKGqwobX1xlE2BDltsaN0gBxB2qQIQQjQ2KCrkvOmXGcqxSJjD9vh7jlJEF/ayQMlmnTIUUQH1c4mfFg0OC/Bv7J3OKAD/6D/j/D/DqZRY=###4484:XlxV32DM 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116ceNqFW03WJKkK3ZJ/YWj1Ot4CDMMY9qxHfXrvzwwgPrlJflmDqnMLAhERAU1XnXevP1d3+fVv6P7+jxEJH82117++3mwuNne8/s3Hdf8JmXA5iI78xyB8VBdf/yb+fv4dV3qpbrP4YyL+cLI+wI/6In/f3HXjQBM9uxs330F42/n7Qvoi/3///Z19Gn/cn/jv3zH5P8nFv/6Zo/wJf/0vxuuPD/9GH1ts1/myR+6u3/NPhKeS/UfO9SMnXl3JCVNOiO0sxN+7I4086Vs/YF9I3znp8oyzuTlO4nGS1rfOcWpsW6LvxkZ2yjvjQHZAPA538ni3XabV+oq/0TdH6/LYHXDshHfH3wcafz9oXhevm8xzL4S3+vrknR/nh/yO+cXvkZ/s6Kcdi9hx0+u+x9eCxdjEZbbBqgU9FNIHT+VRlVURFxb+UmxcL3LZT/hI/l60dhDG8a6iTXkNwsI/1+3G8y+SVzS9JaDDeHsnLPTcNX0rml4CYQkJO8tLjjHYE/VF+yH/kQk/Sw384rq12fNNg/n9B36Qj/yyPsKP9kC6rLdglId030iehEy0p9AlZCI/0lEf2gphCV2+qq2QZ0jJMwDyukjo2iLhc9hY5rE7G4segh3bTdb1Gz01bWfEJWs/pHnGZZ55+y3UR95XEuoD7xuSk5YjI3RLjs86BF2w70jOttrdW3YPifxR5OyZ8LMfAFfH/vEB+wL+AnivPnKcSBauzH8eNj7ZP70jeTTPvMxzb5a9Oq9f6PRdS5acfZVzKDlpykmx7YO+E3u5QPrL/kIcnJ4/4tpgvoBbt/QsyxHdLqVnnHrOc2Ukf69b6XxEHoQrY6S3QViOUOSf69hXOulR19TGW3afJ7QapzQ9DslpU84mqc2p5PT4kjOTmxBIA1nBrROe9jbxnv2xRqpPeHAWi3g0r5IMHH9UwlejlUJcmh4P8emJf0Y0PrHIMjL+N3rhFRT93jCsKOp/ddJHPAvnOynGih/LDinmis/IpiKKlwiiIlNfPCdWS86ZPSWnnYqFqdaNmyNMcs5Fn8MpOduUs8WWis+rB27V7+QvNr7YD3okKyAuRfsJ4sh2fpJTwL5bdh1rcj8se8j6yTxk/bSca4kMR7SKhBn50ipnRrS0ykH61jT9Hie71Q/Mk+4MV12LmtYJq6Im+1VOsiLu0ei7GYkaLQjhNmzsM+Gr2nhjPK3XLXwUS8+wFkW7dZJm9kvJYCoXsfUDLrzLZkZJGcxF+1zwN/rcX3HNzHH8eTDwvrH5BaviL68ZzGZmHjXTdzLOacp5ZTBZ5JxWETnjpJITJS4yfqNniqtHtPEswuKawSE+WZ5kcCj/uPgE/qDP0cj/ZZ4o7+TxnsoG5O2DmxTOnp98r+24ZHDJHx/i5LHGdccntcoY8pohld2KC3XmkOt+3fbL35lqs/HVCet9smZQpVj65naFdRyXCGs5ZZVjxkM/tJyrWPrUVc5pnQ9bIDmSkbdMOEQbx4vG6XzOdR63Vxr3G33j+T/xB/CciWGPV4bUZB464/Pn3UyYWyrmcR+Wkly2bdydNinukX50wk+yifxjtJUfceuE5ftwDupbBS72QR7is9H3soVc1kva2OXm1rFx4/lc1P9BPGv5voZ+xDkRTgfhNgjXU/qAej6Iy0G4ZBufgeTJ/KYnq/EFh+qqhTvrJyEbv++g/5v9GM/i2cYwX8Q4nqxf6Fr/T/TO6yv6ob4nj1cc923BH3f2Vwll6G/Tvm2loz+VTPhpJsH4penxcb0K6yff43qI/hKycb6Dxxf5tJWPJZXI3UolStYpT63XLSc3Gwc56j35DeJ5VFLxWW08j55tTQ0Qz3HU0YX6zdSjvs/zleLvNM+wQcjKd8iap852XJ1PFVqCfimXmnu5qewN+N/o7jrWaIryZrQ/VfQF/jYIS/SNgUwpSzpHG+tUUV4punWfEldv/L3nak6+n/MIq6knCirLAP0FPyHC0XiSBSF9Z/0ky0B+yfKFH/WVLDR1mz9uZI8EWa3gdBK9Ng5hwI/6feIPnN3jeiB9BLBP0PNF+pt9gB/ng+tFrr5WoU1XQ2Vu6TKrGM7OZBwvWWK0sczzOil7RXywH8o8BIuffKOL3aYjH+u+EvyNvjvt94iLM66w8qvKrVLlQtUf70ZP/QkJM8ZzQ0VvccRbpy0rLoHfz4RTbfGReYvzKYj8iM9GWBI4xGnoqTfWR05hHO8dcyEeybSI8+CCX7IWwF1adIetT4bbRNQvZR3yUN7Vnlu3btqb7SshLQxNj0DH9ahBj4/6ZaAXT+ufgj0e0tFfyBWv1RWhZZzu02kq3sV027N03TqNQpED/3d6baBq1he/En3ENRA/u3DArmRcgjbtm/7tg36J9f9Cb9/0h/EQP1ElQZRhLNH2E/YcfZ8oA+NniDpoD3FVoaO8a2hXx/USVxRXRnvEoek4foHsAukR6Ler7muvrWWrhpXej9ih8ikqhRJisbvPNpZ1/4QD6I24NWsea6/vOqzEV27HntOY/efYbDyKPs0Fi/9+oz/7x8F+YnxAqELcgjXP9bazBKt3MbiQkQS6W4XCvvTiQrHfe2gxx0n1l9QFbxjqLRpmuWyMVau7z3H22FIed90tyd9gPE8oE/t9UJ0pl8yArzYD5UuvjcyMWOroJwwAjg3qaMC96zoP8ZktO6yXpdV8p3OynMfeppyl1Raa5eW9aDEz7FDZ+QEHaAtImZ15l3yjRy6TpROKeO+6bH7DTZfRNM2101ez5TY765USBXmfaBlDtfEs7w9uPzgu9xUOO7uB4zIXsLiJZ3dHnJK2E+ILynvE0h5QHdp97VSaF1A7e81z9RxZbb4oRJyK7tIJfp4mfKHP/XiuaiM+hjWNtVFa99+8/2mYZ0tOW+QE6z5HvF/EyPSl4kOcwLsRy/SeJhjgbAa99R6zJst7q9Pe6042c7bx5clbfbjSr5ibM4j90Msq3lu5WfqNLs2sp3kFuAbdzCI7LPewwXxTWDgYyHWunCm92TgPa5i1QK7mdaGYW8bJzZKzXJOGYb7P6FrMrDlvK8n7FcTRaasibgla5ID3oFuUpOb6VLMWy7tOR3t+fk2rOFOzezM1G/uDsZOMVePQx3bLuygIIJYzYc+8ywCHrHcV4ieW865CLN6ldllZM9daf1v2p5XYLDlr5ph+i7EixhfuxEcbJw4ypXDMBSzm6cHGR9CdaMR96M40TSOsjx4O8xIu87NPDo5DLheHjUvWnVkaJ/50mP1udaMi57ePd1RSWzIGxHnohrA8/BY1w0lY1EKM4yH2QzekEe/YkAZ9TjAD8pdgmWlNfPNpeed0B9W1y6acNXHsZgqwvfbC/ZqWdnNjfHobzzybjvpKdZlgeRj/jR4ayXveLgHOhbB601HWO+LuLffcO7ylOfjtTLNx7tY4a+Z4mYfBrCdUtzmZ+q6Z13FZdo+vCp/e9kR+I8Xb38b+JAsO7tIj7o3mJ299EMs6Pw/VESdrHusrurj/dse/PW8tCMsrZ5LTVjn5tzdEj5xuyXnlRpe83YC3Akd8HbMxtpm8e6rZLs4+qcar3L1DPIuUm79F7u7xAfhzl0f4eY6WNP0A+tFJnjxULqyPTAXHE/pZCF+cdNeDW0iNx+MW0ggn/f8hfXfC8vwMx89Oj386TU9A7+XadbpGWPKdi+nP85BA+LkYAvkN5t+bnn+D+Z9Jz++C+flM9pBECNdL6M9vKIB/v4Zbi1DknzF8XxMU5Ed6LHR3/eCN7PEcMUBH+73zkz7yHBP9DeminzzHvDaypyRg3+g4H9kfJ7cgcT3xe+TH8dAfcX+iP6B85H/Wgy80cb9842/byRd9vH/A34K0dPgIQ36ki3y5aPpkf6FvPJ58j/sZ6TK+fI8Y5c+qcF/9GfdzfHkg3cEXvpVR/G/+CfwUivvPw+gZulUobvd9mXs9cIXmL9ej0nRH3AMnDdXGG6+A/FTlTf7Pr/lM3AfIByzN5oMfSCFu3OSV8VEfLx7CP3lAei6ajvLKMH5yUdYKFV4rSPLj5OE0l5KeH9wNjoCAz6IfBNI4Y30YWewVnWnmsT59Dmy50mx8Ov27ScRl6N/LId7g93MB6KloOurnmS5nB9Ll93nP2Vm0fjheFf5o86N85CdLrzd8Ed6f9PuGb1ZC8unTuuafHoZk4wNMi9gH/RPXJDdzP+8m+pohI+7wE9hP+Mn8Ae/8E9knrYGfSgp+lrrBUgM9BS1v46WWNAnHk6UWOtrDO+0KHn4SnMCVAtAvdoXne/mpaNLzk/k0mc8GPy1lflwf5D8y3yRV217oP8iP8t/4u14/tLfQH38D/jpsecL/Nv6w9f2pHLW9P83v0SeA/3/7HvjvrVrXPlHcrL6ebPlnHhf3nYaNG6wD4sFY0iXEnu2kKqO69qGyeechP1F/QvfOofoD7p7nxa/ZEYu/nsnGRW6SOe2WQ67Jk9RvdPi9KuLWjd8V1ruR9X8Cghio###4396:XlxV32DM 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Information +------------------ +Command Line : map -ise /mwave/work/nt/xess/xilinx/vga/vga.ise -intstyle ise +-p xc2s200-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o fpga_map.ncd fpga.ngd +fpga.pcf +Target Device : xc2s200 +Target Package : fg256 +Target Speed : -5 +Mapper Version : spartan2 -- $Revision: 1.34.32.1 $ +Mapped Date : Mon Jan 1 22:22:08 2007 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 7 +Logic Utilization: + Total Number Slice Registers: 174 out of 4,704 3% + Number used as Flip Flops: 173 + Number used as Latches: 1 + Number of 4 input LUTs: 688 out of 4,704 14% +Logic Distribution: + Number of occupied Slices: 402 out of 2,352 17% + Number of Slices containing only related logic: 402 out of 402 100% + Number of Slices containing unrelated logic: 0 out of 402 0% + *See NOTES below for an explanation of the effects of unrelated logic +Total Number 4 input LUTs: 716 out of 4,704 15% + Number used as logic: 688 + Number used as a route-thru: 28 + Number of bonded IOBs: 22 out of 176 12% + IOB Flip Flops: 2 + Number of Block RAMs: 7 out of 14 50% + Number of GCLKs: 3 out of 4 75% + Number of GCLKIOBs: 1 out of 4 25% + +Total equivalent gate count for design: 120,964 +Additional JTAG gate count for IOBs: 1,104 +Peak Memory Usage: 370 MB + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Modular Design Summary +Section 11 - Timing Report +Section 12 - Configuration String Information + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- +WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol + "gray_cnt_FFd1_BUFG" (output signal=gray_cnt_FFd1) has a mix of clock and + non-clock loads. The non-clock loads are: + Pin D of gray_cnt_FFd2 +WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFG symbol + "vga/crtclk_BUFG" (output signal=vga/crtclk) has a mix of clock and non-clock + loads. The non-clock loads are: + Pin D of vga/crtclk +WARNING:Pack:249 - The following adjacent carry multiplexers occupy different + slice components. The resulting carry chain will have suboptimal timing. + vga/crt/Madd_ram_addr_Madd_cy<7> + vga/crt/Madd_ram_addr_Madd_cy<8> +WARNING:Pack:249 - The following adjacent carry multiplexers occupy different + slice components. The resulting carry chain will have suboptimal timing. + vga/Madd_ram_addr_video_Madd_cy<7> + vga/Madd_ram_addr_video_Madd_cy<8> +WARNING:Pack:249 - The following adjacent carry multiplexers occupy different + slice components. The resulting carry chain will have suboptimal timing. + vga/vgacore/Mcount_hcnt_cy<0> + vga/vgacore/Mcount_hcnt_cy<1> +WARNING:Pack:249 - The following adjacent carry multiplexers occupy different + slice components. The resulting carry chain will have suboptimal timing. + vga/vgacore/Mcount_vcnt_cy<0> + vga/vgacore/Mcount_vcnt_cy<1> +WARNING:PhysDesignRules:372 - Gated clock. Clock net vga/crt/_or0000 is sourced + by a combinatorial pin. This is not good design practice. Use the CE pin to + control the loading of data into the flip-flop. + +Section 3 - Informational +------------------------- +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs in the + schematic. + +Section 4 - Removed Logic Summary +--------------------------------- + 2 block(s) optimized away + +Section 5 - Removed Logic +------------------------- + +Optimized Block(s): +TYPE BLOCK +GND XST_GND +VCC XST_VCC + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Strength | Rate | | | Delay | ++------------------------------------------------------------------------------------------------------------------------+ +| clka | GCLKIOB | INPUT | LVTTL | | | | | | +| fpga_d1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d3 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d4 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d5 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d6 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_d7 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| fpga_din_d0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| ps2_clk | IOB | INPUT | LVTTL | | | INFF | | IFD | +| ps2_data | IOB | INPUT | LVTTL | | | INFF | | IFD | +| reset_n | IOB | INPUT | LVTTL | | | | | | +| vga_blue0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_blue1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_blue2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_green0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_green1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_green2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_hsync_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_red0 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_red1 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_red2 | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | +| vga_vsync_n | IOB | OUTPUT | LVTTL | 12 | SLOW | | | | ++------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Modular Design Summary +----------------------------------- +Modular Design not used for this design. + +Section 11 - Timing Report +-------------------------- +No timing report for this architecture. + +Section 12 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings diff --git a/xilinx/vga/fpga_map.ncd b/xilinx/vga/fpga_map.ncd new file mode 100644 index 0000000..0c249e5 --- /dev/null +++ b/xilinx/vga/fpga_map.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.4 +###5176:XlxV32DM 3fff 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K7zW48574KwHWrhwyhHnS4A9CKzKhi3gmSz7THZRYKgeBs+1zOPkDV5s7GGblCflQdnmz1un3Blv+8q88lGnmkEdH+kf0W6zVkUNwJb9KWr7TtmsKK+N/naXmNeivGi3NFdRxw/Kg3Khf6GcKbO+xfpWfBMGbQ/Um3rlaV5RUcuse7LuyboFZZ2z0b9RrrRX+mfKrGMwfuyUN8obfE3w1eWcnwik93Mnp2V1I9FCyYNKoOB+yutmPPplsBP0on3mpmYTowepa+cKzoNUuviaUJsGPlWIZ7eEHMpntAg8j8dIJC4e8guHJY3ySbFeXBy2ZPmy2MqmC4vrfMVu3xlbmddYRGX97FhcwMKl617kyLL0J4FmU+rQNs2j6pwJnMyZoClskA9gb5OujI1myk/O3snDMohpu8d8TDdgqh0TTeDARAM4MdEETkw0gQsTTaCYQtowSUxgwwS2TpkAw1taRaHr7hA3pqYbwYnpJnBiuhHsBLgEukknsGPKGRyYcgIHphzBgSkHcGLKEZyYcgQnphzBhSkncGLSGVNO4MKUE7gw5QROTDmBA1POYMeUEzgx5QROTDmBE1NO4MR0M7j4xPox4YTpOk5MN4B+eHHTdVMeqPvUD1T5krdx291Lfy1soeWBb/gfixEd5jr7Mou6JoRxRmG+E3U15WJ3PI3L0cUZoj8Tm2x7qa/JRn4VkInzPnkV6fZ2tg/JYSQ1YnJRoaQS6N5gOMnBXiaks5JM9r1wg8TiEr+7RfMyQElGHM3gzwaVzD5e9iRWG5V0+JBekF6QzKD7sOgkIyQjJIexekJZP5Euy390W9ys5YVnrunTVBsCkfVk/d7i9sx6Kohksxg7nlkv+gpdEonswL8LNc2ghHEjcLWsXStHX82BNP/0eQbzaARozzz9M3ian+LWq+W3yaa05FdG8VWLThU5DSvh+RD2S6aAQ8t+B5RL/zTJqJKfpuvTpAHJl5Nn8c147AwE3SdRbN8uicMmzpRNRb+1ki6VA5kyq+XP4MHgYR7dOTLewS9Hpo7mVwKlF5EXqZ6vLn26uEiThRRnGuqkXQYKodE8t/BpmuZAGdWfuet7Rk8WU3xu5ytv6CRs+ejwaZoWsZxZ9W2yFwh+2M7NVdhPLi0QTx5ZtvnpktC+aC7auzwTrCcB9ab2aZoWgHxZ6216l6Uf9u/O4879ZTO3nq5nv/P6dEkcFYk0fJF28opHu1ROz6okc/8MHgwmw0RQ2/p04bbv0SO7PvBP5Uc3GdobBtEj+XtNcyB90Rd54Td5kdZ5H5XBab+7cRA9OQvJgx1E7f5bzIo8T8+ZEiWLvySKzszozNT3L+Lc5IysLzz1SsRlHLmMiByih6HnnK6K1Xyw3gOo9ftlejrqpwtnWhVwcTvu/BVqF7TRkjZEc7hLq5h4tfArDXR57virGXJ/7viHf+gmD2jOxqV48Tcr/ka0TH8z4E4++pdYZT1N49PEm29/d5fMg0c+KplkLvrqk+9WkEHoLxVe1B12hdAP/qQe5DPKa26u0qeJVModVfEm/pNq5Wman6ZkR31vOj5Nw075/hptvE1oSeIdt35u3n7to4bAxwr+XdvklTFoapmTJSYyAt1LnxeUQlX+Xgo//Vd/b9IXjxzZGvmd/k2pbwVJBNvWX9Q/paYfJ+bkz6jJ0PkZGhmSQf3VZ/rXrdPUWH+qCmDnp04j0aC9vyQC2PV/rfTZyIBEBicUBhSG/ad18J8vPx5tF+nLnAzJrKpRNh+hQyM4+WEVtJe1V3x+k1N308b4rI6/p4uvir+nj/V/Nk5+ug==###6900:XlxV32DM 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9b15Rs1Lo7zxnJp3c0rJCFrZ3pJmoiWlw1JdOmuZN7SZNHzm+Xb2VDnZ9EyqO+8zrav8E2nBxBvjNL5n6sPyKVaP59ApzisqK2M9ieRC5M1t9NwPz8wjcvpy9jNN5K1yRM7IW+XIW+XI8+/I8+/wWDnwnJz7++w3FYE3vuGaOU3L957zbscSWeg1oJfA8/xAf8H747l5sNhfspye7bTcm+kxkc9IfsnIcTjxEC8RlstdoZWdX6Kc5o2tlm8+R7hPyif2Q383/fF8T2m1+wktXw/zl5g/ix4em45YcS2HPozIWHLEkpsZMKuq+Aq5Guvg9HXQ5jrg8Hy1xf4jdu+0Yf8Bu/d1ULH7CG3YfYRW7D5CK3ZPytfKjXKb+V5bP7yBzzvrhbfdCTtIx0yHWpm7iMJnH2XMvKLh2/cmfrAOEpRbWNN3mBles1/sNbJuY59Xg5acbPOFr5XrzJ1a/X3edRrOPV9gvYVnpvetTHIs4FfCNW8uzP65lAj4geB3AKy/gJ5CmYlfKzNvIWP/2Odzzuy8vmV/PDc9KA/wzvro4Jmy80vz0YTZCw/Y7wd7PymfrA8eWdz0d7P+eECj64B7O/NXaV756TzWZhGYb9lqydmOkPbNksZfpQBVN3LWyHTu7uw7Ru7O3Y29YdwJOjDuBOWGyIwUI8wk9jKXe5ksDkfjzAvkzONrNe4AHRi3O/UAdWPO0I7xZmjHeCN0YLwROjDeAG0YL2l0v6u3Mosv7vNhieEYVSzzFsCcsN8KcNvEx1xqvFzaWZnnV4EPLwLjDDiLsM+HBsaPDzmC98eHHCFjlCdGilE9x7xa9Atsf4JkZT7Q4YG8Gi8PQQxP85GVGSkf+PCqOXHtkOYdA8+B7mNeCvunGYpffKpxPfPbAXM6aaZ8ArasyZkaP2PWCE6SK5umx+rizDWUlHyLQaU4RAh3E8IJ44lo9q3OkKsQBWvlmzSPhU++ou4NxEOuneO//KNZvn3Zc+xBoF/5yw99Kziv/LsngjuuvKd51+KJYK0tg2uW7/zvb9OL/f2f1tYL/cvWZPfbusf/52TXbKd+ueoVrzeNNOGSRx8r8uheqbL0N+FDn5YUmiaayj4ZDu+FlxcPT0vbdSy9ZZpkaiZqCn0rbsOo9dY9z9Q4K/XsF3k93wvUTDGuz7pAMpzNWw1/rjF4jz3mc43oL3cEMlVfmeyUPgmSS14+jWwE7v1dviLx/p4I5Jn4fmVPCOkZYadJpIncfh4WbvbQaBImCxJF52knycZXcNokmYr1C9CTL0FPJvyVXFmcnDB7jLYAdn0/4IJXpNDednrdLbqJFi1Kk7I0aTQR1YeHJhnBZ95Nn0X5WDtNGupBLd70602aSgubqsOiD6Hc/GrqGTXYusYpj2gRwUj500tALxG9JDN8e6m8+53qyaX8ec93um2BxFaKX+129xG98rq3umy97QskI93cffRWP4gV62K02Zd5T30TbAzrvUDDGgH5XbH80L7mXXFMLsbwe+7pU/wpSue7hz6fouyaQzj+2TRF9BrQa0SvEb0m9JrQa0avFRPG7tyUsQhNk5x0keki0kWgC7yGTVlkCq3rxr6gpt3pYpp4NI+kJt4GiazGIboN/5rDvj+WKqelRhqvZ02chjgNcTLidMTpiDNUnf7WfdiG3ue7yqLXSfE11LJ9mR596rwHPv+rPE+vXMc0yu37nMovkxoJfX/O3sjiR2gj1x6hjefuULthxm3rc/dMtsNpI3czyLlkqN6J+nVz4VK7bL5QioaTFajTSeKDrGr0+x4tQKX88FVA8btQZcE3XHwzolvgbtBMedVkSjR6QBO0CRWX7o8zLrMp2V7c228LpJuVPxXq8yH0Zcc1oYTHYYXGn/8B7lUYSg==###5740:XlxV32DM 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\ No newline at end of file diff --git a/xilinx/vga/fpga_pad.csv b/xilinx/vga/fpga_pad.csv new file mode 100644 index 0000000..ad3762b --- /dev/null +++ b/xilinx/vga/fpga_pad.csv @@ -0,0 +1,287 @@ +#Release 8.2i - par I.31 +#Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +#Mon Jan 1 22:22:43 2007 + +# +## NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +#INPUT FILE: fpga_map.ncd +#OUTPUT FILE: fpga_pad.csv +#PART TYPE: xc2s200 +#SPEED GRADE: -5 +#PACKAGE: fg256 +# +# Pinout by Pin Number: +# +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,DCI Value,IO Register,Signal Integrity, +A1,,,GND,,,,,,,,,,,,, +A2,,IOB,IO,UNUSED,,7,,,,,,,,,, +A3,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,, +A4,,IOB,IO,UNUSED,,0,,,,,,,,,, +A5,,IOB,IO,UNUSED,,0,,,,,,,,,, +A6,,IOB,IO,UNUSED,,0,,,,,,,,,, +A7,,IOB,IO,UNUSED,,0,,,,,,,,,, +A8,,IOB,IO,UNUSED,,1,,,,,,,,,, +A9,,IOB,IO,UNUSED,,1,,,,,,,,,, +A10,,IOB,IO,UNUSED,,1,,,,,,,,,, +A11,,IOB,IO,UNUSED,,1,,,,,,,,,, +A12,,IOB,IO,UNUSED,,1,,,,,,,,,, +A13,,IOB,IO,UNUSED,,1,,,,,,,,,, +A14,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,, +A15,,,TDI,,,,,,,,,,,,, +A16,,,GND,,,,,,,,,,,,, +B1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,, +B2,,,GND,,,,,,,,,,,,, +B3,,IOB,IO,UNUSED,,0,,,,,,,,,, +B4,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,, +B5,,IOB,IO,UNUSED,,0,,,,,,,,,, +B6,,IOB,IO,UNUSED,,0,,,,,,,,,, +B7,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,, +B8,,GCLKIOB,GCK3,UNUSED,,0,,,,,,,,,, +B9,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,, +B10,,IOB,IO,UNUSED,,1,,,,,,,,,, +B11,,IOB,IO,UNUSED,,1,,,,,,,,,, +B12,,IOB,IO,UNUSED,,1,,,,,,,,,, +B13,,IOB,IO_CS,UNUSED,,1,,,,,,,,,, +B14,,,TDO,,,,,,,,,,,,, +B15,,,GND,,,,,,,,,,,,, +B16,,IOB,IO,UNUSED,,2,,,,,,,,,, +C1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,, +C2,,IOB,IO,UNUSED,,7,,,,,,,,,, +C3,,,VCCINT,,,,,,,,2.5,,,,, +C4,,,TCK,,,,,,,,,,,,, +C5,,IOB,IO,UNUSED,,0,,,,,,,,,, +C6,,IOB,IO_VREF_0,UNUSED,,0,,,,,,,,,, +C7,,IOB,IO,UNUSED,,0,,,,,,,,,, +C8,,IOB,IO,UNUSED,,0,,,,,,,,,, +C9,,GCLKIOB,GCK2,UNUSED,,1,,,,,,,,,, +C10,,IOB,IO,UNUSED,,1,,,,,,,,,, +C11,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,, +C12,,IOB,IO,UNUSED,,1,,,,,,,,,, +C13,,IOB,IO_WRITE,UNUSED,,1,,,,,,,,,, +C14,,,VCCINT,,,,,,,,2.5,,,,, +C15,,IOB,IO_DOUT_BUSY,UNUSED,,2,,,,,,,,,, +C16,,IOB,IO,UNUSED,,2,,,,,,,,,, +D1,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,, +D2,,IOB,IO,UNUSED,,7,,,,,,,,,, +D3,,,TMS,,,,,,,,,,,,, +D4,,,VCCINT,,,,,,,,2.5,,,,, +D5,,IOB,IO,UNUSED,,0,,,,,,,,,, +D6,,IOB,IO,UNUSED,,0,,,,,,,,,, +D7,,IOB,IO,UNUSED,,0,,,,,,,,,, +D8,,IOB,IO,UNUSED,,0,,,,,,,,,, +D9,,IOB,IO,UNUSED,,1,,,,,,,,,, +D10,,IOB,IO,UNUSED,,1,,,,,,,,,, +D11,,IOB,IO,UNUSED,,1,,,,,,,,,, +D12,,IOB,IO,UNUSED,,1,,,,,,,,,, +D13,,,VCCINT,,,,,,,,2.5,,,,, +D14,fpga_din_d0,IOB,IO_DIN_D0,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +D15,,,CCLK,,,,,,,,,,,,, +D16,,IOB,IO,UNUSED,,2,,,,,,,,,, +E1,ps2_data,IOB,IO,INPUT,LVTTL,7,,,,IFD,,LOCATED,,YES,NONE, +E2,,IOB,IO,UNUSED,,7,,,,,,,,,, +E3,reset_n,IOB,IO,INPUT,LVTTL,7,,,,NONE,,LOCATED,,NO,NONE, +E4,,IOB,IO,UNUSED,,7,,,,,,,,,, +E5,,,VCCINT,,,,,,,,2.5,,,,, +E6,,IOB,IO,UNUSED,,0,,,,,,,,,, +E7,,IOB,IO,UNUSED,,0,,,,,,,,,, +E8,,,VCCO_0,,,0,,,,,any******,,,,, +E9,,,VCCO_1,,,1,,,,,any******,,,,, +E10,,IOB,IO,UNUSED,,1,,,,,,,,,, +E11,,IOB,IO_VREF_1,UNUSED,,1,,,,,,,,,, +E12,,,VCCINT,,,,,,,,2.5,,,,, +E13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,, +E14,,IOB,IO,UNUSED,,2,,,,,,,,,, +E15,,IOB,IO,UNUSED,,2,,,,,,,,,, +E16,fpga_d1,IOB,IO_D1,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +F1,,IOB,IO,UNUSED,,7,,,,,,,,,, +F2,,IOB,IO,UNUSED,,7,,,,,,,,,, +F3,,IOB,IO,UNUSED,,7,,,,,,,,,, +F4,ps2_clk,IOB,IO,INPUT,LVTTL,7,,,,IFD,,LOCATED,,YES,NONE, +F5,,IOB,IO,UNUSED,,7,,,,,,,,,, +F6,,,GND,,,,,,,,,,,,, +F7,,,GND,,,,,,,,,,,,, +F8,,,VCCO_0,,,0,,,,,any******,,,,, +F9,,,VCCO_1,,,1,,,,,any******,,,,, +F10,,,GND,,,,,,,,,,,,, +F11,,,GND,,,,,,,,,,,,, +F12,,IOB,IO,UNUSED,,2,,,,,,,,,, +F13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,, +F14,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,, +F15,fpga_d2,IOB,IO_D2,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +F16,,IOB,IO,UNUSED,,2,,,,,,,,,, +G1,,PCIIOB,IO_IRDY,UNUSED,,7,,,,,,,,,, +G2,,IOB,IO,UNUSED,,7,,,,,,,,,, +G3,,IOB,IO,UNUSED,,7,,,,,,,,,, +G4,,IOB,IO,UNUSED,,7,,,,,,,,,, +G5,,IOB,IO,UNUSED,,7,,,,,,,,,, +G6,,,GND,,,,,,,,,,,,, +G7,,,GND,,,,,,,,,,,,, +G8,,,GND,,,,,,,,,,,,, +G9,,,GND,,,,,,,,,,,,, +G10,,,GND,,,,,,,,,,,,, +G11,,,GND,,,,,,,,,,,,, +G12,,IOB,IO,UNUSED,,2,,,,,,,,,, +G13,,IOB,IO,UNUSED,,2,,,,,,,,,, +G14,,IOB,IO,UNUSED,,2,,,,,,,,,, +G15,,IOB,IO,UNUSED,,2,,,,,,,,,, +G16,fpga_d3,IOB,IO_D3,OUTPUT,LVTTL,2,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +H1,,IOB,IO,UNUSED,,6,,,,,,,,,, +H2,vga_green0,IOB,IO,OUTPUT,LVTTL,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +H3,,IOB,IO_VREF_7,UNUSED,,7,,,,,,,,,, +H4,vga_blue0,IOB,IO,OUTPUT,LVTTL,7,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +H5,,,VCCO_7,,,7,,,,,3.30,,,,, +H6,,,VCCO_7,,,7,,,,,3.30,,,,, +H7,,,GND,,,,,,,,,,,,, +H8,,,GND,,,,,,,,,,,,, +H9,,,GND,,,,,,,,,,,,, +H10,,,GND,,,,,,,,,,,,, +H11,,,VCCO_2,,,2,,,,,3.30,,,,, +H12,,,VCCO_2,,,2,,,,,3.30,,,,, +H13,,IOB,IO_VREF_2,UNUSED,,2,,,,,,,,,, +H14,,IOB,IO,UNUSED,,2,,,,,,,,,, +H15,,IOB,IO,UNUSED,,2,,,,,,,,,, +H16,,PCIIOB,IO_IRDY,UNUSED,,2,,,,,,,,,, +J1,vga_red0,IOB,IO,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +J2,,PCIIOB,IO_TRDY,UNUSED,,6,,,,,,,,,, +J3,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,, +J4,,IOB,IO,UNUSED,,6,,,,,,,,,, +J5,,,VCCO_6,,,6,,,,,3.30,,,,, +J6,,,VCCO_6,,,6,,,,,3.30,,,,, +J7,,,GND,,,,,,,,,,,,, +J8,,,GND,,,,,,,,,,,,, +J9,,,GND,,,,,,,,,,,,, +J10,,,GND,,,,,,,,,,,,, +J11,,,VCCO_3,,,3,,,,,3.30,,,,, +J12,,,VCCO_3,,,3,,,,,3.30,,,,, +J13,,IOB,IO,UNUSED,,2,,,,,,,,,, +J14,,IOB,IO,UNUSED,,3,,,,,,,,,, +J15,,PCIIOB,IO_TRDY,UNUSED,,3,,,,,,,,,, +J16,fpga_d4,IOB,IO_D4,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +K1,vga_vsync_n,IOB,IO,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +K2,,IOB,IO,UNUSED,,6,,,,,,,,,, +K3,vga_blue1,IOB,IO,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +K4,vga_hsync_n,IOB,IO,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +K5,vga_green1,IOB,IO,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +K6,,,GND,,,,,,,,,,,,, +K7,,,GND,,,,,,,,,,,,, +K8,,,GND,,,,,,,,,,,,, +K9,,,GND,,,,,,,,,,,,, +K10,,,GND,,,,,,,,,,,,, +K11,,,GND,,,,,,,,,,,,, +K12,,IOB,IO,UNUSED,,3,,,,,,,,,, +K13,,IOB,IO,UNUSED,,3,,,,,,,,,, +K14,,IOB,IO,UNUSED,,3,,,,,,,,,, +K15,,IOB,IO,UNUSED,,3,,,,,,,,,, +K16,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,, +L1,,IOB,IO,UNUSED,,6,,,,,,,,,, +L2,,IOB,IO,UNUSED,,6,,,,,,,,,, +L3,,IOB,IO,UNUSED,,6,,,,,,,,,, +L4,,IOB,IO,UNUSED,,6,,,,,,,,,, +L5,vga_blue2,IOB,IO,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +L6,,,GND,,,,,,,,,,,,, +L7,,,GND,,,,,,,,,,,,, +L8,,,VCCO_5,,,5,,,,,3.30,,,,, +L9,,,VCCO_4,,,4,,,,,any******,,,,, +L10,,,GND,,,,,,,,,,,,, +L11,,,GND,,,,,,,,,,,,, +L12,,IOB,IO,UNUSED,,3,,,,,,,,,, +L13,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,, +L14,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,, +L15,,IOB,IO,UNUSED,,3,,,,,,,,,, +L16,,IOB,IO,UNUSED,,3,,,,,,,,,, +M1,vga_red1,IOB,IO_VREF_6,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +M2,,IOB,IO,UNUSED,,6,,,,,,,,,, +M3,,IOB,IO,UNUSED,,6,,,,,,,,,, +M4,,IOB,IO,UNUSED,,6,,,,,,,,,, +M5,,,VCCINT,,,,,,,,2.5,,,,, +M6,,IOB,IO,UNUSED,,5,,,,,,,,,, +M7,,IOB,IO,UNUSED,,5,,,,,,,,,, +M8,,,VCCO_5,,,5,,,,,3.30,,,,, +M9,,,VCCO_4,,,4,,,,,any******,,,,, +M10,,IOB,IO,UNUSED,,4,,,,,,,,,, +M11,,IOB,IO,UNUSED,,4,,,,,,,,,, +M12,,,VCCINT,,,,,,,,2.5,,,,, +M13,,IOB,IO_VREF_3,UNUSED,,3,,,,,,,,,, +M14,,IOB,IO,UNUSED,,3,,,,,,,,,, +M15,,IOB,IO,UNUSED,,3,,,,,,,,,, +M16,fpga_d5,IOB,IO_D5,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +N1,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,, +N2,,IOB,IO_VREF_6,UNUSED,,6,,,,,,,,,, +N3,,,M0,,,,,,,,,,,,, +N4,,,VCCINT,,,,,,,,2.5,,,,, +N5,,IOB,IO,UNUSED,,5,,,,,,,,,, +N6,,IOB,IO,UNUSED,,5,,,,,,,,,, +N7,,IOB,IO,UNUSED,,5,,,,,,,,,, +N8,,GCLKIOB,GCK0,UNUSED,,4,,,,,,,,,, +N9,,IOB,IO,UNUSED,,4,,,,,,,,,, +N10,,IOB,IO,UNUSED,,4,,,,,,,,,, +N11,,IOB,IO,UNUSED,,4,,,,,,,,,, +N12,,IOB,IO,UNUSED,,4,,,,,,,,,, +N13,,,VCCINT,,,,,,,,2.5,,,,, +N14,fpga_d7,IOB,IO_D7,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +N15,,IOB,IO_INIT,UNUSED,,3,,,,,,,,,, +N16,fpga_d6,IOB,IO_D6,OUTPUT,LVTTL,3,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +P1,,IOB,IO,UNUSED,,6,,,,,,,,,, +P2,,,M1,,,,,,,,,,,,, +P3,,,VCCINT,,,,,,,,2.5,,,,, +P4,,,NC,,,,,,,,,,,,, +P5,,IOB,IO,UNUSED,,5,,,,,,,,,, +P6,,IOB,IO,UNUSED,,5,,,,,,,,,, +P7,,IOB,IO,UNUSED,,5,,,,,,,,,, +P8,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,, +P9,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,, +P10,,IOB,IO,UNUSED,,4,,,,,,,,,, +P11,,IOB,IO,UNUSED,,4,,,,,,,,,, +P12,,IOB,IO,UNUSED,,4,,,,,,,,,, +P13,,IOB,IO,UNUSED,,4,,,,,,,,,, +P14,,,VCCINT,,,,,,,,2.5,,,,, +P15,,,PROGRAM,,,,,,,,,,,,, +P16,,IOB,IO,UNUSED,,3,,,,,,,,,, +R1,vga_green2,IOB,IO,OUTPUT,LVTTL,6,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +R2,,,GND,,,,,,,,,,,,, +R3,,,M2,,,,,,,,,,,,, +R4,,,NC,,,,,,,,,,,,, +R5,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,, +R6,,IOB,IO,UNUSED,,5,,,,,,,,,, +R7,,IOB,IO,UNUSED,,5,,,,,,,,,, +R8,clka,GCLKIOB,GCK1,INPUT,LVTTL,5,,,,NONE,,LOCATED,,NO,NONE, +R9,,IOB,IO,UNUSED,,4,,,,,,,,,, +R10,,IOB,IO,UNUSED,,4,,,,,,,,,, +R11,,IOB,IO,UNUSED,,4,,,,,,,,,, +R12,,IOB,IO,UNUSED,,4,,,,,,,,,, +R13,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,, +R14,,,DONE,,,,,,,,,,,,, +R15,,,GND,,,,,,,,,,,,, +R16,,IOB,IO,UNUSED,,3,,,,,,,,,, +T1,,,GND,,,,,,,,,,,,, +T2,vga_red2,IOB,IO_VREF_5,OUTPUT,LVTTL,5,12,SLOW,NONE**,,,LOCATED,,NO,NONE, +T3,,IOB,IO,UNUSED,,5,,,,,,,,,, +T4,,IOB,IO_VREF_5,UNUSED,,5,,,,,,,,,, +T5,,IOB,IO,UNUSED,,5,,,,,,,,,, +T6,,IOB,IO,UNUSED,,5,,,,,,,,,, +T7,,IOB,IO,UNUSED,,5,,,,,,,,,, +T8,,IOB,IO,UNUSED,,5,,,,,,,,,, +T9,,IOB,IO,UNUSED,,4,,,,,,,,,, +T10,,IOB,IO,UNUSED,,4,,,,,,,,,, +T11,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,, +T12,,IOB,IO_VREF_4,UNUSED,,4,,,,,,,,,, +T13,,IOB,IO,UNUSED,,4,,,,,,,,,, +T14,,IOB,IO,UNUSED,,4,,,,,,,,,, +T15,,IOB,IO,UNUSED,,3,,,,,,,,,, +T16,,,GND,,,,,,,,,,,,, + +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +# +#* Default value. +#** This default Pullup/Pulldown value can be overridden in Bitgen. +#****** Special VCCO requirements may apply. Please consult the device +# family datasheet for specific guideline on VCCO requirements. +# +# +# \ No newline at end of file diff --git a/xilinx/vga/fpga_pad.txt b/xilinx/vga/fpga_pad.txt new file mode 100644 index 0000000..65638c5 --- /dev/null +++ b/xilinx/vga/fpga_pad.txt @@ -0,0 +1,286 @@ +Release 8.2i - par I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Mon Jan 1 22:22:43 2007 + + +INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: +1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. +2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. +3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. + +INPUT FILE: fpga_map.ncd +OUTPUT FILE: fpga_pad.txt +PART TYPE: xc2s200 +SPEED GRADE: -5 +PACKAGE: fg256 + +Pinout by Pin Number: + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|DCI Value|IO Register|Signal Integrity| ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|A1 | | |GND | | | | | | | | | | | | | +|A2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|A3 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|A4 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|A8 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A9 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A11 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A13 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|A14 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|A15 | | |TDI | | | | | | | | | | | | | +|A16 | | |GND | | | | | | | | | | | | | +|B1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|B2 | | |GND | | | | | | | | | | | | | +|B3 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|B4 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|B5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|B6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|B7 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|B8 | |GCLKIOB |GCK3 |UNUSED | |0 | | | | | | | | | | +|B9 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|B10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|B11 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|B12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|B13 | |IOB |IO_CS |UNUSED | |1 | | | | | | | | | | +|B14 | | |TDO | | | | | | | | | | | | | +|B15 | | |GND | | | | | | | | | | | | | +|B16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|C1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|C2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|C3 | | |VCCINT | | | | | | | |2.5 | | | | | +|C4 | | |TCK | | | | | | | | | | | | | +|C5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|C6 | |IOB |IO_VREF_0 |UNUSED | |0 | | | | | | | | | | +|C7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|C8 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|C9 | |GCLKIOB |GCK2 |UNUSED | |1 | | | | | | | | | | +|C10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|C11 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|C12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|C13 | |IOB |IO_WRITE |UNUSED | |1 | | | | | | | | | | +|C14 | | |VCCINT | | | | | | | |2.5 | | | | | +|C15 | |IOB |IO_DOUT_BUSY|UNUSED | |2 | | | | | | | | | | +|C16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|D1 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|D2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|D3 | | |TMS | | | | | | | | | | | | | +|D4 | | |VCCINT | | | | | | | |2.5 | | | | | +|D5 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D8 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|D9 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D11 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|D13 | | |VCCINT | | | | | | | |2.5 | | | | | +|D14 |fpga_din_d0|IOB |IO_DIN_D0 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|D15 | | |CCLK | | | | | | | | | | | | | +|D16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|E1 |ps2_data |IOB |IO |INPUT |LVTTL |7 | | | |IFD | |LOCATED | |YES |NONE | +|E2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|E3 |reset_n |IOB |IO |INPUT |LVTTL |7 | | | |NONE | |LOCATED | |NO |NONE | +|E4 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|E5 | | |VCCINT | | | | | | | |2.5 | | | | | +|E6 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|E7 | |IOB |IO |UNUSED | |0 | | | | | | | | | | +|E8 | | |VCCO_0 | | |0 | | | | |any******| | | | | +|E9 | | |VCCO_1 | | |1 | | | | |any******| | | | | +|E10 | |IOB |IO |UNUSED | |1 | | | | | | | | | | +|E11 | |IOB |IO_VREF_1 |UNUSED | |1 | | | | | | | | | | +|E12 | | |VCCINT | | | | | | | |2.5 | | | | | +|E13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|E14 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|E15 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|E16 |fpga_d1 |IOB |IO_D1 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|F1 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F3 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F4 |ps2_clk |IOB |IO |INPUT |LVTTL |7 | | | |IFD | |LOCATED | |YES |NONE | +|F5 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|F6 | | |GND | | | | | | | | | | | | | +|F7 | | |GND | | | | | | | | | | | | | +|F8 | | |VCCO_0 | | |0 | | | | |any******| | | | | +|F9 | | |VCCO_1 | | |1 | | | | |any******| | | | | +|F10 | | |GND | | | | | | | | | | | | | +|F11 | | |GND | | | | | | | | | | | | | +|F12 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|F13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|F14 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|F15 |fpga_d2 |IOB |IO_D2 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|F16 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G1 | |PCIIOB |IO_IRDY |UNUSED | |7 | | | | | | | | | | +|G2 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G3 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G4 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G5 | |IOB |IO |UNUSED | |7 | | | | | | | | | | +|G6 | | |GND | | | | | | | | | | | | | +|G7 | | |GND | | | | | | | | | | | | | +|G8 | | |GND | | | | | | | | | | | | | +|G9 | | |GND | | | | | | | | | | | | | +|G10 | | |GND | | | | | | | | | | | | | +|G11 | | |GND | | | | | | | | | | | | | +|G12 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G13 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G14 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G15 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|G16 |fpga_d3 |IOB |IO_D3 |OUTPUT |LVTTL |2 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|H1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|H2 |vga_green0 |IOB |IO |OUTPUT |LVTTL |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|H3 | |IOB |IO_VREF_7 |UNUSED | |7 | | | | | | | | | | +|H4 |vga_blue0 |IOB |IO |OUTPUT |LVTTL |7 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|H5 | | |VCCO_7 | | |7 | | | | |3.30 | | | | | +|H6 | | |VCCO_7 | | |7 | | | | |3.30 | | | | | +|H7 | | |GND | | | | | | | | | | | | | +|H8 | | |GND | | | | | | | | | | | | | +|H9 | | |GND | | | | | | | | | | | | | +|H10 | | |GND | | | | | | | | | | | | | +|H11 | | |VCCO_2 | | |2 | | | | |3.30 | | | | | +|H12 | | |VCCO_2 | | |2 | | | | |3.30 | | | | | +|H13 | |IOB |IO_VREF_2 |UNUSED | |2 | | | | | | | | | | +|H14 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|H15 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|H16 | |PCIIOB |IO_IRDY |UNUSED | |2 | | | | | | | | | | +|J1 |vga_red0 |IOB |IO |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|J2 | |PCIIOB |IO_TRDY |UNUSED | |6 | | | | | | | | | | +|J3 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | | +|J4 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|J5 | | |VCCO_6 | | |6 | | | | |3.30 | | | | | +|J6 | | |VCCO_6 | | |6 | | | | |3.30 | | | | | +|J7 | | |GND | | | | | | | | | | | | | +|J8 | | |GND | | | | | | | | | | | | | +|J9 | | |GND | | | | | | | | | | | | | +|J10 | | |GND | | | | | | | | | | | | | +|J11 | | |VCCO_3 | | |3 | | | | |3.30 | | | | | +|J12 | | |VCCO_3 | | |3 | | | | |3.30 | | | | | +|J13 | |IOB |IO |UNUSED | |2 | | | | | | | | | | +|J14 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|J15 | |PCIIOB |IO_TRDY |UNUSED | |3 | | | | | | | | | | +|J16 |fpga_d4 |IOB |IO_D4 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|K1 |vga_vsync_n|IOB |IO |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|K2 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|K3 |vga_blue1 |IOB |IO |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|K4 |vga_hsync_n|IOB |IO |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|K5 |vga_green1 |IOB |IO |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|K6 | | |GND | | | | | | | | | | | | | +|K7 | | |GND | | | | | | | | | | | | | +|K8 | | |GND | | | | | | | | | | | | | +|K9 | | |GND | | | | | | | | | | | | | +|K10 | | |GND | | | | | | | | | | | | | +|K11 | | |GND | | | | | | | | | | | | | +|K12 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K13 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K14 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|K16 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|L1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L2 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L3 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L4 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|L5 |vga_blue2 |IOB |IO |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|L6 | | |GND | | | | | | | | | | | | | +|L7 | | |GND | | | | | | | | | | | | | +|L8 | | |VCCO_5 | | |5 | | | | |3.30 | | | | | +|L9 | | |VCCO_4 | | |4 | | | | |any******| | | | | +|L10 | | |GND | | | | | | | | | | | | | +|L11 | | |GND | | | | | | | | | | | | | +|L12 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|L13 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|L14 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|L15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|L16 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|M1 |vga_red1 |IOB |IO_VREF_6 |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|M2 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|M3 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|M4 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|M5 | | |VCCINT | | | | | | | |2.5 | | | | | +|M6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|M7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|M8 | | |VCCO_5 | | |5 | | | | |3.30 | | | | | +|M9 | | |VCCO_4 | | |4 | | | | |any******| | | | | +|M10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|M11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|M12 | | |VCCINT | | | | | | | |2.5 | | | | | +|M13 | |IOB |IO_VREF_3 |UNUSED | |3 | | | | | | | | | | +|M14 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|M15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|M16 |fpga_d5 |IOB |IO_D5 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|N1 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | | +|N2 | |IOB |IO_VREF_6 |UNUSED | |6 | | | | | | | | | | +|N3 | | |M0 | | | | | | | | | | | | | +|N4 | | |VCCINT | | | | | | | |2.5 | | | | | +|N5 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|N6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|N7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|N8 | |GCLKIOB |GCK0 |UNUSED | |4 | | | | | | | | | | +|N9 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N12 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|N13 | | |VCCINT | | | | | | | |2.5 | | | | | +|N14 |fpga_d7 |IOB |IO_D7 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|N15 | |IOB |IO_INIT |UNUSED | |3 | | | | | | | | | | +|N16 |fpga_d6 |IOB |IO_D6 |OUTPUT |LVTTL |3 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|P1 | |IOB |IO |UNUSED | |6 | | | | | | | | | | +|P2 | | |M1 | | | | | | | | | | | | | +|P3 | | |VCCINT | | | | | | | |2.5 | | | | | +|P4 | | |NC | | | | | | | | | | | | | +|P5 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|P6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|P7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|P8 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | | +|P9 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|P10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P12 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P13 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|P14 | | |VCCINT | | | | | | | |2.5 | | | | | +|P15 | | |PROGRAM | | | | | | | | | | | | | +|P16 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|R1 |vga_green2 |IOB |IO |OUTPUT |LVTTL |6 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|R2 | | |GND | | | | | | | | | | | | | +|R3 | | |M2 | | | | | | | | | | | | | +|R4 | | |NC | | | | | | | | | | | | | +|R5 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | | +|R6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|R7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|R8 |clka |GCLKIOB |GCK1 |INPUT |LVTTL |5 | | | |NONE | |LOCATED | |NO |NONE | +|R9 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R11 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R12 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|R13 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|R14 | | |DONE | | | | | | | | | | | | | +|R15 | | |GND | | | | | | | | | | | | | +|R16 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|T1 | | |GND | | | | | | | | | | | | | +|T2 |vga_red2 |IOB |IO_VREF_5 |OUTPUT |LVTTL |5 |12 |SLOW |NONE** | | |LOCATED | |NO |NONE | +|T3 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T4 | |IOB |IO_VREF_5 |UNUSED | |5 | | | | | | | | | | +|T5 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T6 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T7 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T8 | |IOB |IO |UNUSED | |5 | | | | | | | | | | +|T9 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T10 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T11 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|T12 | |IOB |IO_VREF_4 |UNUSED | |4 | | | | | | | | | | +|T13 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T14 | |IOB |IO |UNUSED | |4 | | | | | | | | | | +|T15 | |IOB |IO |UNUSED | |3 | | | | | | | | | | +|T16 | | |GND | | | | | | | | | | | | | ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/xilinx/vga/fpga_summary.html b/xilinx/vga/fpga_summary.html new file mode 100644 index 0000000..8d5687b --- /dev/null +++ b/xilinx/vga/fpga_summary.html @@ -0,0 +1,183 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
VGA Project Status
Project File:vga.iseCurrent State:Programming File Generated
Module Name:fpga
  • Errors:
No Errors
Target Device:xc2s200-5fg256
  • Warnings:
29 Warnings
Product Version:ISE 8.2i
  • Updated:
Mon Jan 1 22:23:05 2007
+ 
+ + +
VGA Partition Summary
No partition information was found.
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers1744,7043% 
    Number used as Flip Flops173   
    Number used as Latches1   
Number of 4 input LUTs6884,70414% 
Logic Distribution     
    Number of occupied Slices4022,35217% 
    Number of Slices containing only related logic402402100% 
    Number of Slices containing unrelated logic04020% 
Total Number 4 input LUTs7164,70415% 
        Number used as logic688   
        Number used as a route-thru28   
Number of bonded IOBs2217612% 
        IOB Flip Flops2   
Number of Block RAMs71450% 
Number of GCLKs3475% 
Number of GCLKIOBs1425% 
Total equivalent gate count for design120,964   
Additional JTAG gate count for IOBs1,104   
+ 
+ + + + + + + + + + + + + + + + + + + +
Performance Summary
Final Timing Score:0Pinout Data:Pinout Report
Routing Results:All Signals Completely RoutedClock Data:Clock Report
Timing Constraints:All Constraints Met  
+ 
+ + + + + + + + + +
Detailed Reports
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentMon Jan 1 22:21:50 2007021 Warnings6 Infos
Translation ReportCurrentMon Jan 1 22:22:03 2007007 Infos
Map ReportCurrentMon Jan 1 22:22:16 200707 Warnings2 Infos
Place and Route ReportCurrentMon Jan 1 22:22:44 2007002 Infos
Static Timing ReportCurrentMon Jan 1 22:22:52 2007002 Infos
Bitgen ReportCurrentMon Jan 1 22:23:05 200701 Warning0
+ 
+ + + +
Secondary Reports
Report NameStatusGenerated
Xplorer Report  
+ \ No newline at end of file diff --git a/xilinx/vga/fpga_usage.xml b/xilinx/vga/fpga_usage.xml new file mode 100644 index 0000000..c4ff63a --- /dev/null +++ b/xilinx/vga/fpga_usage.xml @@ -0,0 +1,706 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/xilinx/vga/fpga_vhdl.prj b/xilinx/vga/fpga_vhdl.prj new file mode 100644 index 0000000..e69de29 diff --git a/xilinx/vga/netgen/par/fpga_timesim.nlf b/xilinx/vga/netgen/par/fpga_timesim.nlf new file mode 100644 index 0000000..930565d --- /dev/null +++ b/xilinx/vga/netgen/par/fpga_timesim.nlf @@ -0,0 +1,28 @@ +Release 8.2i - netgen I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Command Line: netgen -intstyle ise -s 5 -pcf fpga.pcf -sdf_anno true -sdf_path +netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim fpga.ncd +fpga_timesim.v + +Read and Annotate design 'fpga.ncd' ... +Loading device for application Rf_Device from file 'v200.nph' in environment +/opt/Xilinx. + "fpga" is an NCD, version 3.1, device xc2s200, package fg256, speed -5 +Loading constraints from 'fpga.pcf'... +The speed grade (-5) differs from the speed grade specified in the .ncd file +(-5). +The number of routable networks is 686 +Flattening design ... +Processing design ... + Preping design's networks ... + Preping design's macros ... +Writing Verilog SDF file 'netgen/par/fpga_timesim.sdf' ... +Writing Verilog netlist file +'/mwave/work/nt/xess/xilinx/vga/netgen/par/fpga_timesim.v' ... +INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM + simulation primitives and has to be used with SIMPRIM simulation library for + correct compilation and simulation. +Number of warnings: 0 +Number of info messages: 1 +Total memory usage is 232020 kilobytes diff --git a/xilinx/vga/netgen/par/fpga_timesim.sdf b/xilinx/vga/netgen/par/fpga_timesim.sdf new file mode 100644 index 0000000..89c0e12 --- /dev/null +++ b/xilinx/vga/netgen/par/fpga_timesim.sdf @@ -0,0 +1,22790 @@ +(DELAYFILE + (SDFVERSION "3.0") + (DESIGN "fpga") + (DATE "Fri Dec 29 10:07:44 2006") + (VENDOR "Xilinx") + (PROGRAM "Xilinx SDF Writer") + (VERSION "I.31") + (DIVIDER /) + (VOLTAGE 2.375) + (TEMPERATURE 85) + (TIMESCALE 1 ps) + (CELL (CELLTYPE "X_BUF") + (INSTANCE ps2_clk_IBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 773 )( 773 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE ps2_clk\/DELAY) + (DELAY + (ABSOLUTE + (IOPATH I O ( 819 )( 819 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_d1_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_d1\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3635 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_d2_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_d2\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3608 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_d3_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_d3\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2625 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_d4_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_d4\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3215 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_d5_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_d5\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3987 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_d6_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_d6\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3654 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_d7_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_d7\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4169 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE ps2_data_IBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 773 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE ps2_data\/DELAY) + (DELAY + (ABSOLUTE + (IOPATH I O ( 819 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE fpga_din_d0_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE fpga_din_d0\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4314 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_blue0_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_blue0\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3764 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_blue1_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_blue1\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5186 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_vsync_n_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga_vsync_n\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2820 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_blue2_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_blue2\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6195 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_hsync_n_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga_hsync_n\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3857 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_red0_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_red0\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4604 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_red1_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_red1\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5833 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_red2_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_red2\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5548 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE reset_n\/IMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 151 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE reset_n_IBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 773 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_green0_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_green0\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4238 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_green1_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_green1\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4325 )) + ) + ) + ) + (CELL (CELLTYPE "X_OBUF") + (INSTANCE vga_green2_OBUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4470 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga_green2\/OUTMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5557 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/inst_Mram_mem11\/CLKBMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2233 )( 2233 )) + ) + ) + ) + (CELL (CELLTYPE "X_RAMB4_S1_S1") + (INSTANCE vga\/inst_Mram_mem11) + (DELAY + (ABSOLUTE + (PORT CLKA ( 2265 )) + (PORT WEA ( 4807 )) + (PORT ADDRA[0] ( 3001 )) + (PORT ADDRA[1] ( 2999 )) + (PORT ADDRA[2] ( 3403 )) + (PORT ADDRA[3] ( 3117 )) + (PORT ADDRA[4] ( 4377 )) + (PORT ADDRA[5] ( 2920 )) + (PORT ADDRA[6] ( 2976 )) + (PORT ADDRA[7] ( 2921 )) + (PORT ADDRA[8] ( 4752 )) + (PORT ADDRA[9] ( 3703 )) + (PORT ADDRA[10] ( 3508 )) + (PORT ADDRA[11] ( 3144 )) + (PORT ADDRB[0] ( 3260 )) + (PORT ADDRB[1] ( 4303 )) + (PORT ADDRB[2] ( 6434 )) + (PORT ADDRB[3] ( 4027 )) + (PORT ADDRB[4] ( 3433 )) + (PORT ADDRB[5] ( 2913 )) + (PORT ADDRB[6] ( 5349 )) + (PORT ADDRB[7] ( 5203 )) + (PORT ADDRB[8] ( 2848 )) + (PORT ADDRB[9] ( 3380 )) + (PORT ADDRB[10] ( 3999 )) + (PORT ADDRB[11] ( 2539 )) + (PORT DIA[0] ( 2978 )) + (IOPATH CLKA DOA[0] ( 3985 )) + (IOPATH CLKB DOB[0] ( 3985 )) + ) + ) + (TIMINGCHECK + (WIDTH (negedge CLKA) (1806)) + (WIDTH (posedge CLKA) (1806)) + (SETUPHOLD (posedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[2]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[2]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[3]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[3]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[4]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[4]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[5]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[5]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[6]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[6]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge DIA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge DIA[0]) (posedge CLKA) (1345)(0)) + (WIDTH (negedge CLKB) (1806)) + (WIDTH (posedge CLKB) (1806)) + (SETUPHOLD (posedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[10]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[10]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[11]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[11]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge DIB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge DIB[0]) (posedge CLKB) (1345)(0)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/inst_Mram_mem21\/CLKBMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2532 )( 2532 )) + ) + ) + ) + (CELL (CELLTYPE "X_RAMB4_S1_S1") + (INSTANCE vga\/inst_Mram_mem21) + (DELAY + (ABSOLUTE + (PORT CLKA ( 2565 )) + (PORT WEA ( 5107 )) + (PORT ADDRA[0] ( 2989 )) + (PORT ADDRA[1] ( 3648 )) + (PORT ADDRA[2] ( 2795 )) + (PORT ADDRA[3] ( 3454 )) + (PORT ADDRA[4] ( 3435 )) + (PORT ADDRA[5] ( 2804 )) + (PORT ADDRA[6] ( 3528 )) + (PORT ADDRA[7] ( 3068 )) + (PORT ADDRA[8] ( 2995 )) + (PORT ADDRA[9] ( 3849 )) + (PORT ADDRA[10] ( 3845 )) + (PORT ADDRA[11] ( 3482 )) + (PORT ADDRB[0] ( 2363 )) + (PORT ADDRB[1] ( 4494 )) + (PORT ADDRB[2] ( 6771 )) + (PORT ADDRB[3] ( 4365 )) + (PORT ADDRB[4] ( 4463 )) + (PORT ADDRB[5] ( 2881 )) + (PORT ADDRB[6] ( 5686 )) + (PORT ADDRB[7] ( 5396 )) + (PORT ADDRB[8] ( 3185 )) + (PORT ADDRB[9] ( 3718 )) + (PORT ADDRB[10] ( 4336 )) + (PORT ADDRB[11] ( 2876 )) + (PORT DIA[0] ( 4167 )) + (IOPATH CLKA DOA[0] ( 3985 )) + (IOPATH CLKB DOB[0] ( 3985 )) + ) + ) + (TIMINGCHECK + (WIDTH (negedge CLKA) (1806)) + (WIDTH (posedge CLKA) (1806)) + (SETUPHOLD (posedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[2]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[2]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[3]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[3]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[4]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[4]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[5]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[5]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[6]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[6]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge DIA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge DIA[0]) (posedge CLKA) (1345)(0)) + (WIDTH (negedge CLKB) (1806)) + (WIDTH (posedge CLKB) (1806)) + (SETUPHOLD (posedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[10]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[10]) (posedge CLKB) (1345)(0)) + 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(PORT ADDRB[6] ( 5830 )) + (PORT ADDRB[7] ( 5539 )) + (PORT ADDRB[8] ( 3329 )) + (PORT ADDRB[9] ( 3861 )) + (PORT ADDRB[10] ( 4480 )) + (PORT ADDRB[11] ( 3020 )) + (PORT DIA[0] ( 4049 )) + (IOPATH CLKA DOA[0] ( 3985 )) + (IOPATH CLKB DOB[0] ( 3985 )) + ) + ) + (TIMINGCHECK + (WIDTH (negedge CLKA) (1806)) + (WIDTH (posedge CLKA) (1806)) + (SETUPHOLD (posedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[2]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[2]) (posedge CLKA) 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(SETUPHOLD (posedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge DIA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge DIA[0]) (posedge CLKA) (1345)(0)) + (WIDTH (negedge CLKB) (1806)) + (WIDTH (posedge CLKB) (1806)) + (SETUPHOLD (posedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[10]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[10]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[11]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[11]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge DIB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge DIB[0]) (posedge CLKB) (1345)(0)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/inst_Mram_mem8\/CLKBMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1944 )( 1944 )) + ) + ) + ) + (CELL (CELLTYPE "X_RAMB4_S1_S1") + (INSTANCE vga\/inst_Mram_mem8) + (DELAY + (ABSOLUTE + (PORT CLKA ( 1976 )) + (PORT WEA ( 4518 )) + (PORT ADDRA[0] ( 2938 )) + (PORT ADDRA[1] ( 2801 )) + (PORT ADDRA[2] ( 3568 )) + (PORT ADDRA[3] ( 2799 )) + (PORT ADDRA[4] ( 3985 )) + (PORT ADDRA[5] ( 2620 )) + (PORT ADDRA[6] ( 3504 )) + (PORT ADDRA[7] ( 3401 )) + (PORT ADDRA[8] ( 3294 )) + (PORT ADDRA[9] ( 4414 )) + (PORT ADDRA[10] ( 3909 )) + (PORT ADDRA[11] ( 3379 )) + (PORT ADDRB[0] ( 4140 )) + (PORT ADDRB[1] ( 2807 )) + (PORT ADDRB[2] ( 5199 )) + (PORT ADDRB[3] ( 3690 )) + (PORT ADDRB[4] ( 3902 )) + (PORT ADDRB[5] ( 3064 )) + (PORT ADDRB[6] ( 4827 )) + (PORT ADDRB[7] ( 3518 )) + (PORT ADDRB[8] ( 3374 )) + (PORT ADDRB[9] ( 3043 )) + (PORT ADDRB[10] ( 3727 )) + (PORT ADDRB[11] ( 3690 )) + (PORT DIA[0] ( 3681 )) + (IOPATH CLKA DOA[0] ( 3985 )) + (IOPATH CLKB DOB[0] ( 3985 )) + ) + ) + (TIMINGCHECK + (WIDTH (negedge CLKA) (1806)) + (WIDTH (posedge CLKA) (1806)) + (SETUPHOLD (posedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ENA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge RSTA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge WEA) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[1]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[2]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[2]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[3]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[3]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[4]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[4]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[5]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[5]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[6]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[6]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[7]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[8]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[9]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[10]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge ADDRA[11]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (posedge DIA[0]) (posedge CLKA) (1345)(0)) + (SETUPHOLD (negedge DIA[0]) (posedge CLKA) (1345)(0)) + (WIDTH (negedge CLKB) (1806)) + (WIDTH (posedge CLKB) (1806)) + (SETUPHOLD (posedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ENB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge RSTB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge WEB) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[1]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[2]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[3]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[4]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[5]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[6]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[7]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[8]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[9]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[10]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[10]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge ADDRB[11]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge ADDRB[11]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (posedge DIB[0]) (posedge CLKB) (1345)(0)) + (SETUPHOLD (negedge DIB[0]) (posedge CLKB) (1345)(0)) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1201_SW0) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3413 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1201_SW0_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2948 )) + (PORT ADR1 ( 554 )) + (PORT ADR2 ( 1729 )) + (PORT ADR3 ( 3072 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1201_SW0_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2618 )) + (PORT ADR1 ( 2546 )) + (PORT ADR2 ( 1649 )) + (PORT ADR3 ( 2841 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3084\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2416) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3104 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2416_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2658 )) + (PORT ADR1 ( 2499 )) + (PORT ADR2 ( 1216 )) + (PORT ADR3 ( 3147 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2416_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2668 )) + (PORT ADR1 ( 2449 )) + (PORT ADR2 ( 2012 )) + (PORT ADR3 ( 2567 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2_map1774\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1352_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3085 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>13521) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3192 )) + (PORT ADR1 ( 2720 )) + (PORT ADR2 ( 3286 )) + (PORT ADR3 ( 2279 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1_map1229\/G) + (DELAY + (ABSOLUTE + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1_map1229\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1207) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3363 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1207_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1634 )) + (PORT ADR1 ( 4390 )) + (PORT ADR3 ( 944 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1207_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 956 )) + (PORT ADR1 ( 4483 )) + (PORT ADR3 ( 921 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1_map1098\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/charload1_SW0) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2683 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload1_SW0_G) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1256 )) + (PORT ADR2 ( 1140 )) + (PORT ADR3 ( 367 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload1_SW0_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1857 )) + (PORT ADR1 ( 1329 )) + (PORT ADR2 ( 1243 )) + (PORT ADR3 ( 1257 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N560\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1382) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3182 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1382_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2172 )) + (PORT ADR1 ( 887 )) + (PORT ADR2 ( 396 )) + (PORT ADR3 ( 367 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1382_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 434 )) + (PORT ADR1 ( 577 )) + (PORT ADR2 ( 1944 )) + (PORT ADR3 ( 747 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1299) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4757 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1299_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2495 )) + (PORT ADR1 ( 3445 )) + (PORT ADR2 ( 2483 )) + (PORT ADR3 ( 2841 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1299_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3776 )) + (PORT ADR1 ( 2878 )) + (PORT ADR2 ( 2536 )) + (PORT ADR3 ( 1683 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1_map1221\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1437) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2105 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1437_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1380 )) + (PORT ADR1 ( 3336 )) + (PORT ADR2 ( 2747 )) + (PORT ADR3 ( 2983 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1437_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3596 )) + (PORT ADR1 ( 2835 )) + (PORT ADR2 ( 1693 )) + (PORT ADR3 ( 3030 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1_map1633\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1673) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2749 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1673_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2355 )) + (PORT ADR2 ( 1416 )) + (PORT ADR3 ( 855 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1673_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1960 )) + (PORT ADR1 ( 385 )) + (PORT ADR2 ( 428 )) + (PORT ADR3 ( 1247 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_0) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3504 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>2) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2154 )) + (PORT ADR2 ( 910 )) + (PORT ADR3 ( 1622 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>3) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1426 )) + (PORT ADR3 ( 1988 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f51\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1588) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2355 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1588_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2554 )) + (PORT ADR1 ( 2958 )) + (PORT ADR2 ( 1557 )) + (PORT ADR3 ( 2282 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1588_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2631 )) + (PORT ADR1 ( 2586 )) + (PORT ADR2 ( 1161 )) + (PORT ADR3 ( 2205 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1_map1666\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_1) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 5879 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>4) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1250 )) + (PORT ADR1 ( 4076 )) + (PORT ADR3 ( 1368 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>5) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 957 )) + (PORT ADR3 ( 3992 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f61\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f6_0) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 4249 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_2) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 6381 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>6) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 900 )) + (PORT ADR3 ( 3672 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>7) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1064 )) + (PORT ADR2 ( 977 )) + (PORT ADR3 ( 3703 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f53\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/pixel\<8\>19_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2450 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/pixel\<8\>191) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 749 )) + (PORT ADR1 ( 1413 )) + (PORT ADR3 ( 1340 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_or000011) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1503 )) + (PORT ADR1 ( 922 )) + (PORT ADR2 ( 1469 )) + (PORT ADR3 ( 1378 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/pixel\<8\>_map785\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/pixel\<8\>_map785\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_3) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 6511 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>8) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4342 )) + (PORT ADR1 ( 1058 )) + (PORT ADR3 ( 924 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>9) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4272 )) + (PORT ADR1 ( 1154 )) + (PORT ADR3 ( 902 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f62\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f6_1) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 4415 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_4) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 6281 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE 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(PORT ADR1 ( 1929 )) + (PORT ADR3 ( 2246 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>13) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2349 )) + (PORT ADR3 ( 860 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f63\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f6_2) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 4581 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_6) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 5845 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>_f5_65) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1114 )) + (PORT ADR1 ( 2506 )) + (PORT ADR2 ( 396 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>15) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2416 )) + (PORT ADR2 ( 2200 )) + (PORT ADR3 ( 1562 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f57\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_7) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 6097 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>16) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 2876 )) + (PORT ADR3 ( 727 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>17) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3052 )) + (PORT ADR1 ( 577 )) + (PORT ADR3 ( 937 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f58\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_8) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3715 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>18) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2635 )) + (PORT ADR2 ( 1227 )) + (PORT ADR3 ( 1444 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>19) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 626 )) + (PORT ADR1 ( 385 )) + (PORT ADR3 ( 2111 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f59\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_9) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4028 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>201) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1479 )) + (PORT ADR2 ( 4010 )) + (PORT ADR3 ( 1200 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>211) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 4446 )) + (PORT ADR2 ( 3492 )) + (PORT ADR3 ( 1228 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f65\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f6_4) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 4896 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<5\>3450) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2280 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL 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0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload8_SW0_SW01) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 456 )) + (PORT ADR1 ( 5888 )) + (PORT ADR2 ( 4368 )) + (PORT ADR3 ( 2733 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE N3150\/G) + (DELAY + (ABSOLUTE + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3150\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3672 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2127 )) + (PORT ADR2 ( 1219 )) + (PORT ADR3 ( 367 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2105 )) + (PORT ADR2 ( 1960 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f6\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f6) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 3237 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4895 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>5) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 900 )) + (PORT ADR2 ( 738 )) + (PORT ADR3 ( 5599 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>13) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 434 )) + (PORT ADR2 ( 761 )) + (PORT ADR3 ( 5646 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f5\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1291_SW0) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4248 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1291_SW0_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2391 )) + (PORT ADR1 ( 1077 )) + (PORT ADR2 ( 924 )) + (PORT ADR3 ( 2528 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1291_SW0_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2384 )) + (PORT ADR1 ( 2443 )) + (PORT ADR2 ( 902 )) + (PORT ADR3 ( 771 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3104\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<4\>_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2373 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<3\>) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1532 )) + (PORT ADR2 ( 4335 )) + (PORT ADR3 ( 1383 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<3\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 385 )) + (PORT ADR2 ( 4110 )) + (PORT ADR3 ( 1766 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<4\>_f5\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<5\>_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4857 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<4\>3) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1936 )) + (PORT ADR2 ( 742 )) + (PORT ADR3 ( 3658 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<4\>11) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1165 )) + (PORT ADR2 ( 3797 )) + (PORT ADR3 ( 896 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<5\>_f5\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1410_SW0_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3046 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1410_SW01) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2715 )) + (PORT ADR2 ( 2824 )) + (PORT ADR3 ( 1705 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1410_SW02) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3211 )) + (PORT ADR2 ( 3138 )) + (PORT ADR3 ( 2485 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3126\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/state_FFd2\-In_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2515 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd2\-In1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1445 )) + (PORT ADR1 ( 2174 )) + (PORT ADR2 ( 2150 )) + (PORT ADR3 ( 1393 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd2\-In2) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2101 )) + (PORT ADR1 ( 1533 )) + (PORT ADR2 ( 1496 )) + (PORT ADR3 ( 1144 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/ps2\/bitcnt_x\<2\>1) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 1920 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<2\>1_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 910 )) + (PORT ADR1 ( 910 )) + (PORT ADR3 ( 989 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<2\>1_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1742 )) + (PORT ADR1 ( 1106 )) + (PORT ADR2 ( 1007 )) + (PORT ADR3 ( 3276 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/bitcnt_r_2) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 699 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/bitcnt_r\<2\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7398 )( 7398 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/ps2\/bitcnt_x\<0\>1_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 1490 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<0\>11) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3464 )) + (PORT ADR1 ( 1142 )) + (PORT ADR2 ( 1509 )) + (PORT ADR3 ( 1139 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<0\>12) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1397 )) + (PORT ADR2 ( 1200 )) + (PORT ADR3 ( 1540 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/bitcnt_r_0) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 702 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/bitcnt_r\<0\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6640 )( 6640 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/ps2\/bitcnt_x\<1\>1_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 1916 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<1\>11) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1167 )) + (PORT ADR3 ( 1039 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<1\>12) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 969 )) + (PORT ADR1 ( 1233 )) + (PORT ADR2 ( 3388 )) + (PORT ADR3 ( 1445 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/bitcnt_r_1) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 702 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/bitcnt_r\<1\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6640 )( 6640 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>111_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4907 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1111) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3100 )) + (PORT ADR1 ( 3127 )) + (PORT ADR2 ( 2636 )) + (PORT ADR3 ( 3257 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1112) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3087 )) + (PORT ADR3 ( 2800 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1_map1056\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<1\>_mmx_out1_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3852 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>_mmx_out11) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4671 )) + (PORT ADR1 ( 3830 )) + (PORT ADR2 ( 4112 )) + (PORT ADR3 ( 3765 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>_mmx_out12) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4133 )) + (PORT ADR1 ( 4396 )) + (PORT ADR2 ( 3538 )) + (PORT ADR3 ( 4503 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<1\>_mmx_out\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/charload237_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3859 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload2371) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1376 )) + (PORT ADR3 ( 1136 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload2372) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2692 )) + (PORT ADR1 ( 923 )) + (PORT ADR2 ( 1553 )) + (PORT ADR3 ( 1392 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f51) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3590 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>20) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2261 )) + (PORT ADR2 ( 396 )) + (PORT ADR3 ( 367 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>110) + (DELAY + (ABSOLUTE + (PORT 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(DELAY + (ABSOLUTE + (PORT ADR2 ( 964 )) + (PORT ADR3 ( 2898 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f6123\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f62) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 2770 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f53) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 6056 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>26) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 456 )) + (PORT ADR1 ( 2331 )) + (PORT ADR3 ( 936 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 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(PORT ADR3 ( 1199 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/pixel_hold\<0\>_rt) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 570 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_101) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4448 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>22) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4697 )) + (PORT ADR2 ( 1919 )) + (PORT ADR3 ( 1299 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>231) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4675 )) + (PORT ADR1 ( 1404 )) + (PORT ADR3 ( 972 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f51112\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/charload458_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3877 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload4581) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1211 )) + (PORT ADR1 ( 2223 )) + (PORT ADR2 ( 821 )) + (PORT ADR3 ( 1664 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload4582) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1461 )) + (PORT ADR1 ( 1870 )) + (PORT ADR2 ( 952 )) + (PORT ADR3 ( 1966 )) + (IOPATH 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)) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<3\>_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1291 )) + (PORT ADR1 ( 1213 )) + (PORT ADR2 ( 752 )) + (PORT ADR3 ( 629 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/bitcnt_x\<3\>_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1215 )) + (PORT ADR1 ( 3532 )) + (PORT ADR2 ( 1454 )) + (PORT ADR3 ( 971 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/bitcnt_r_3) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 699 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/bitcnt_r\<3\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7398 )( 7398 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/charload758_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3008 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload7581) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1730 )) + (PORT ADR1 ( 1743 )) + (PORT ADR2 ( 1590 )) + (PORT ADR3 ( 1211 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload7582) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1145 )) + (PORT ADR1 ( 1766 )) + (PORT ADR2 ( 1462 )) + (PORT ADR3 ( 1325 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>172_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4987 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1721) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2817 )) + (PORT ADR1 ( 2537 )) + (PORT ADR2 ( 3468 )) + (PORT ADR3 ( 2913 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1722) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2795 )) + (PORT ADR1 ( 2459 )) + (PORT ADR2 ( 3374 )) + (PORT ADR3 ( 2960 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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vga\/scancode_convert\/scancode_rom\/data\<4\>1_map1548\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/ram_addr_mux\<4\>_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3423 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<4\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2514 )) + (PORT ADR1 ( 2312 )) + (PORT ADR2 ( 929 )) + (PORT ADR3 ( 2648 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<4\>2) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2987 )) + (PORT ADR1 ( 2335 )) + (PORT ADR2 ( 2294 )) + (PORT ADR3 ( 1342 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<4\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_4) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 1404 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2260_SW0) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3426 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2260_SW0_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2199 )) + (PORT ADR1 ( 900 )) + (PORT ADR2 ( 910 )) + (PORT ADR3 ( 2650 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2260_SW0_F) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 577 )) + (PORT ADR2 ( 428 )) + (PORT ADR3 ( 1827 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3106\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/charload217) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 5006 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload217_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2490 )) + (PORT ADR1 ( 2223 )) + (PORT ADR2 ( 4510 )) + (PORT ADR3 ( 917 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload217_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2177 )) + (PORT ADR1 ( 1930 )) + (PORT ADR2 ( 4542 )) + (PORT ADR3 ( 2123 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload2_map865\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/state_FFd3\-In48_SW0) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 1982 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd3\-In48_SW0_G) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2169 )) + (PORT ADR2 ( 991 )) + (PORT ADR3 ( 2166 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd3\-In48_SW0_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1464 )) + (PORT ADR1 ( 1299 )) + (PORT ADR2 ( 1023 )) + (PORT ADR3 ( 414 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3144\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<1\>1641) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4344 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>1641_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4469 )) + (PORT ADR1 ( 3666 )) + (PORT ADR2 ( 3576 )) + (PORT ADR3 ( 4155 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>1641_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3634 )) + (PORT ADR1 ( 3690 )) + (PORT ADR2 ( 3263 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<1\>112\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<1\>1741) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4156 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>1741_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4018 )) + (PORT ADR1 ( 4346 )) + (PORT ADR2 ( 3334 )) + (PORT ADR3 ( 4240 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>1741_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4756 )) + (PORT ADR1 ( 3853 )) + (PORT ADR2 ( 3366 )) + (PORT ADR3 ( 4293 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<1\>2\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_01) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2629 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>21) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2252 )) + (PORT ADR1 ( 1733 )) + (PORT ADR3 ( 741 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>31) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1439 )) + (PORT ADR1 ( 1480 )) + (PORT ADR3 ( 1996 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f511\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_02) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3136 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>25) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4480 )) + (PORT ADR2 ( 1115 )) + (PORT ADR3 ( 1143 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>32) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1394 )) + (PORT ADR1 ( 3092 )) + (PORT ADR3 ( 852 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f5112\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_10) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3784 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>_f5_102) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1572 )) + (PORT ADR2 ( 2255 )) + (PORT ADR3 ( 4129 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>23) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4630 )) + (PORT ADR2 ( 1861 )) + (PORT ADR3 ( 921 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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(ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f63) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 4138 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_11) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 2900 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>41) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2561 )) + (PORT ADR2 ( 912 )) + (PORT ADR3 ( 697 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>51) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2539 )) + (PORT ADR2 ( 428 )) + (PORT ADR3 ( 2278 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f611\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f6_01) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 2764 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_04) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3289 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>29) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1572 )) + (PORT ADR2 ( 1154 )) + (PORT ADR3 ( 2780 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>34) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3033 )) + (PORT ADR2 ( 942 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f511234\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_12) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 4050 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>42) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1068 )) + (PORT ADR2 ( 3752 )) + (PORT ADR3 ( 701 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>52) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 969 )) + 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0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>193) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4465 )) + (PORT ADR1 ( 1615 )) + (PORT ADR2 ( 1221 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>203) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1535 )) + (PORT ADR2 ( 4256 )) + (PORT ADR3 ( 1161 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<3\>_f6412\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 182 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<3\>_f6_32) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 4744 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) 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vga\/rom_addr_char\<3\>_f6_41) + (DELAY + (ABSOLUTE + (PORT IA ( 194 )) + (PORT IB ( 95 )) + (PORT SEL ( 3856 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_84) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 6058 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>14) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1171 )) + (PORT ADR1 ( 2522 )) + (PORT ADR2 ( 954 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>214) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3431 )) + (PORT ADR1 ( 1544 )) + (PORT ADR2 ( 1523 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f591234\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/rom_addr_char\<2\>_f5_92) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3935 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>213) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1518 )) + (PORT ADR2 ( 3934 )) + (PORT ADR3 ( 1153 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>222) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4299 )) + (PORT ADR1 ( 1333 )) + (PORT ADR2 ( 1767 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/rom_addr_char\<2\>_f51012\/F5USED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1217_f5) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 5173 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>12171) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 3505 )) + (PORT ADR2 ( 2562 )) + (PORT ADR3 ( 2911 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>12172) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 3467 )) + (PORT ADR2 ( 2594 )) + (PORT ADR3 ( 2574 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1_map1201\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<5\>3159_SW0) + (DELAY + (ABSOLUTE + (PORT IA ( 544 )) + (PORT IB ( 532 )) + (PORT SEL ( 3019 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<5\>3159_SW0_G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 648 )) + (PORT ADR1 ( 362 )) + (PORT ADR2 ( 748 )) + (PORT ADR3 ( 2954 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<5\>3159_SW0_F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2845 )) + (PORT ADR1 ( 577 )) + (PORT ADR2 ( 2763 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3112\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 200 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_cy\<5\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/crt\/Madd_ram_addrC_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 1943 )) + (PORT I1 ( 2162 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_lut\<5\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1987 )) + (PORT ADR1 ( 1762 )) + (PORT ADR2 ( 1881 )) + (PORT ADR3 ( 2386 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_lut\<6\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2219 )) + (PORT ADR1 ( 2549 )) + (PORT ADR3 ( 1156 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<5\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<5\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/crt\/Madd_ram_addrC1_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 2617 )) + (PORT I1 ( 2243 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_cy\<6\>) + (DELAY + (ABSOLUTE + (PORT IA ( 155 )) + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_xor\<6\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_cy\<8\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_xor\<8\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/crt\/Madd_ram_addrC3_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 1948 )) + (PORT I1 ( 2710 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_lut\<8\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2535 )) + (PORT ADR1 ( 1767 )) + (PORT ADR2 ( 1726 )) + (PORT ADR3 ( 1699 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_lut\<9\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1909 )) + (PORT ADR1 ( 1962 )) + (PORT ADR2 ( 1744 )) + (PORT ADR3 ( 2071 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<8\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<8\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/crt\/Madd_ram_addrC4_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 2030 )) + (PORT I1 ( 1933 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_cy\<9\>) + (DELAY + (ABSOLUTE + (PORT IA ( 155 )) + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_xor\<9\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<8\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_cy\<10\>) + (DELAY + (ABSOLUTE + (PORT IA ( 2652 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_xor\<10\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_lut\<10\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2336 )) + (PORT ADR1 ( 1832 )) + (PORT ADR3 ( 2045 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v\<5\>_rt) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2102 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<10\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<10\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_xor\<11\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<10\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_cy\<0\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_lut\<0\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1266 )) + (PORT ADR1 ( 1248 )) + (PORT ADR2 ( 1099 )) + (PORT ADR3 ( 1024 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt\<4\>_rt) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1147 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_cy\<1\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_cy\<2\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_lut\<2\>) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1339 )) + (PORT ADR2 ( 1077 )) + (PORT ADR3 ( 911 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_lut\<3\>) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1101 )) + (PORT ADR3 ( 1199 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_cy\<3\>) + (DELAY + (ABSOLUTE + (PORT IA ( 155 )) + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_cy\<3\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_cy\<4\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_lut\<4\>_INV_0) + (DELAY + (ABSOLUTE + (PORT ADR3 ( 960 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_mux00021) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2738 )) + (PORT ADR1 ( 1708 )) + (PORT ADR2 ( 1090 )) + (PORT ADR3 ( 1136 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hblank\/XBUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hblank\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/Madd_ram_addr_video_Madd_cy\<5\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/Madd_ram_addr_videoC_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 2667 )) + (PORT I1 ( 3619 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/Madd_ram_addr_video_Madd_lut\<5\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3444 )) + (PORT ADR1 ( 2486 )) + (PORT ADR2 ( 2207 )) + (PORT ADR3 ( 2048 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/Madd_ram_addr_video_Madd_lut\<6\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2089 )) + (PORT ADR1 ( 2312 )) + (PORT ADR2 ( 1424 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_video\<5\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_video\<5\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/Madd_ram_addr_videoC1_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 2380 )) + (PORT I1 ( 2113 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/Madd_ram_addr_video_Madd_cy\<6\>) + (DELAY + (ABSOLUTE + (PORT IA ( 155 )) + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O 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(DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/ps2\/Madd__addsub0000_cy\<1\>) + (DELAY + (ABSOLUTE + (PORT IA ( 155 )) + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/ps2\/Madd__addsub0000_xor\<1\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/ps2\/Madd__addsub0000_cy\<2\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/ps2\/Madd__addsub0000_xor\<2\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE 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284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/_addsub0000\<12\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/_addsub0000\<12\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/ps2\/Madd__addsub0000_xor\<13\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/_addsub0000\<12\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_v_cy\<0\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Mcount_cursor_v_lut\<0\>_INV_0) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 835 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<1\>\/G) + (DELAY + (ABSOLUTE + (PORT ADR3 ( 1349 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<1\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_v_cy\<1\>) + (DELAY + (ABSOLUTE + (PORT IA ( 155 )) + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_v_xor\<1\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_v_cy\<2\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_v_xor\<2\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<2\>\/F) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 931 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<2\>\/G) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 811 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<2\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<2\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_v_cy\<3\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_v_xor\<3\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<2\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_v_cy\<4\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_v_xor\<4\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<4\>\/F) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1537 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v\<5\>_rt\.1) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1483 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<4\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<4\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_v_xor\<5\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<4\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_h_cy\<0\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Mcount_cursor_h_lut\<0\>_INV_0) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1312 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<1\>1\/G) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1263 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<1\>1\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE 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284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<2\>1\/G) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1429 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<2\>1\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<2\>1\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_h_cy\<3\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_h_xor\<3\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<2\>1\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_h_cy\<4\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_h_xor\<4\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<4\>1\/F) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1126 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Result\<4\>1\/G) + (DELAY + (ABSOLUTE + (PORT ADR3 ( 1117 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<4\>1\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<4\>1\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Mcount_cursor_h_cy\<5\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_h_xor\<5\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<4\>1\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Mcount_cursor_h_xor\<6\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h\<6\>_rt) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1079 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<6\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/Result\<6\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<1\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<1\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_11) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1009 )) + (PORT ADR3 ( 748 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_21) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 782 )) + (PORT ADR3 ( 1023 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<2\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<2\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hcnt\<1\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4384 )( 4384 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<1\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<1\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<3\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<3\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_31) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1264 )) + (PORT ADR3 ( 861 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_41) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1195 )) + (PORT ADR1 ( 1320 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<4\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<4\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hcnt\<3\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3823 )( 3823 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<3\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<5\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<5\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_51) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1438 )) + (PORT ADR3 ( 1055 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_61) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1730 )) + (PORT ADR3 ( 1086 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<6\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<6\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hcnt\<5\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3833 )( 3833 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<5\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<7\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<7\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_71) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3269 )) + (PORT ADR2 ( 1612 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_81) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1027 )) + (PORT ADR3 ( 1442 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<8\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<8\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hcnt\<7\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3833 )( 3833 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<7\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<9\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<9\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_91) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1577 )) + (PORT ADR3 ( 1621 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/hcnt_Eqn_101) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1009 )) + (PORT ADR3 ( 1473 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_xor\<10\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hcnt\<9\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3772 )( 3772 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<9\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_9) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 706 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<9\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<0\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/vgacore\/vcnt_Eqn_0_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 542 )) + (PORT I1 ( 1526 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcount_vcnt_lut\<0\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1351 )) + (PORT ADR1 ( 361 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcount_vcnt_lut\<0\>_1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1278 )) + (PORT ADR1 ( 384 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<0\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2227 )( 2227 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<0\>_rt) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<0\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4828 )( 4828 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_0) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<0\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<1\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<1\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1402 )) + (PORT ADR1 ( 1373 )) + (PORT ADR2 ( 742 )) + (PORT ADR3 ( 1873 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_21) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1265 )) + (PORT ADR1 ( 1413 )) + (PORT ADR2 ( 1102 )) + (PORT ADR3 ( 1908 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<1\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<1\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2200 )( 2200 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<1\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<2\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<2\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<1\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4751 )( 4751 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<1\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<3\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<3\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_3) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1252 )) + (PORT ADR1 ( 554 )) + (PORT ADR2 ( 1767 )) + (PORT ADR3 ( 845 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_41) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1953 )) + (PORT ADR2 ( 1213 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<3\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2059 )( 2059 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<4\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<4\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<3\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3872 )( 3872 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<3\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<5\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<5\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_51) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1579 )) + (PORT ADR3 ( 1150 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_61) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1299 )) + (PORT ADR2 ( 1504 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<5\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1910 )( 1910 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<6\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<6\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<5\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4318 )( 4318 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<5\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<7\>) + (DELAY + (ABSOLUTE + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<7\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_71) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1343 )) + (PORT ADR3 ( 945 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_81) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1413 )) + (PORT ADR3 ( 1256 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<7\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1910 )( 1910 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_cy\<8\>) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<8\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 131 )) + (PORT I1 ( 382 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<7\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3780 )( 3780 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<7\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/vgacore\/Mcount_vcnt_xor\<9\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_92) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1335 )) + (PORT ADR1 ( 1611 )) + (PORT ADR3 ( 961 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<9\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2432 )( 2432 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<9\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE 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(posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1181) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2580 )) + (PORT ADR1 ( 2426 )) + (PORT ADR2 ( 1993 )) + (PORT ADR3 ( 2813 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1201_SW1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1844 )) + (PORT ADR1 ( 3005 )) + (PORT ADR2 ( 1147 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1_map1831\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1_map1831\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_cmp_eq00041_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1386 )) + (PORT ADR2 ( 1066 )) + (PORT ADR3 ( 964 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_cmp_eq00041) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1192 )) + (PORT ADR1 ( 1163 )) + (PORT ADR2 ( 1028 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/_cmp_eq00041_SW0\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/_cmp_eq00041_SW0\/O\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) 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+ (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1264) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2764 )) + (PORT ADR1 ( 3037 )) + (PORT ADR2 ( 1997 )) + (PORT ADR3 ( 1464 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1329) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2901 )) + (PORT ADR1 ( 3041 )) + (PORT ADR2 ( 896 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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(DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/ascii_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 2014 )) + (PORT CLK ( 704 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>199) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2726 )) + (PORT ADR1 ( 2269 )) + (PORT ADR2 ( 1950 )) + (PORT ADR3 ( 4179 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>1125) + (DELAY + (ABSOLUTE + (PORT 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(PORT ADR2 ( 1160 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1308_SW1\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1308_SW1\/O\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_cmp_eq000211) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 898 )) + (PORT ADR1 ( 1109 )) + (PORT ADR2 ( 1333 )) + (PORT ADR3 ( 1290 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_cmp_eq000221) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1303 )) + (PORT ADR1 ( 826 )) + (PORT ADR2 ( 1055 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/N31\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/N31\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1392_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3545 )) + (PORT ADR1 ( 1850 )) + (PORT ADR2 ( 679 )) + (PORT ADR3 ( 2273 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1620) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 434 )) + (PORT ADR1 ( 910 )) + (PORT ADR2 ( 2854 )) + (PORT ADR3 ( 414 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1392_SW0\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<4\>1392_SW0\/O\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1247) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1237 )) + (PORT ADR1 ( 887 )) + (PORT ADR2 ( 1216 )) + (PORT ADR3 ( 367 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_mux0008\<6\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 969 )) + (PORT ADR1 ( 2079 )) + (PORT ADR2 ( 2081 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/ascii\<6\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/ascii_6) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 2075 )) + (PORT CLK ( 704 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<5\>3247) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1671 )) + (PORT ADR1 ( 2382 )) + (PORT ADR2 ( 2370 )) + (PORT ADR3 ( 1755 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE 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(CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_and0000) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2060 )) + (PORT ADR1 ( 1803 )) + (PORT ADR2 ( 1173 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/_and0000_SW0\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/_and0000_SW0\/O\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/eol_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1326 )) + (PORT ADR1 ( 1226 )) + (PORT ADR2 ( 956 )) + (PORT ADR3 ( 887 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/eol) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1340 )) + (PORT ADR1 ( 811 )) + (PORT ADR2 ( 1065 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/eol_SW0\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/eol_SW0\/O\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_cmp_eq0000) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1340 )) + (PORT ADR1 ( 1400 )) + (PORT ADR2 ( 919 )) + (PORT ADR3 ( 700 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_not00101) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1296 )) + (PORT ADR1 ( 3370 )) + (PORT ADR2 ( 971 )) + (PORT ADR3 ( 221 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/_cmp_eq0000\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/_cmp_eq0000\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/scroll_SW0) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1061 )) + (PORT ADR2 ( 1014 )) + (PORT ADR3 ( 1090 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/scroll) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1525 )) + (PORT ADR1 ( 1167 )) + (PORT ADR2 ( 709 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/scroll_SW0\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/scroll_SW0\/O\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/state_FFd4\-In24) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1413 )) + (PORT ADR1 ( 1697 )) + (PORT ADR2 ( 1219 )) + (PORT ADR3 ( 1443 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/state_FFd4\-In34) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1283 )) + (PORT ADR1 ( 1290 )) + (PORT ADR2 ( 998 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/state_FFd4\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/state_FFd4) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 721 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/state_FFd4\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 8005 )( 8005 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_and0001) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2047 )) + (PORT ADR1 ( 554 )) + (PORT ADR2 ( 396 )) + (PORT ADR3 ( 1443 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v_Eqn_11) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1146 )) + (PORT ADR3 ( 221 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + 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284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_not0007) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2212 )) + (PORT ADR1 ( 1851 )) + (PORT ADR2 ( 1608 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/shift_set_map833\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/shift_set_map833\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>126_SW1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2446 )) + (PORT ADR2 ( 3053 )) + (PORT ADR3 ( 2197 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE 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+ (PORT ADR1 ( 1727 )) + (PORT ADR2 ( 1150 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/raise1\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/raise1\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>111) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3495 )) + (PORT ADR2 ( 2368 )) + (PORT ADR3 ( 2312 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>186) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1897 )) + (PORT ADR1 ( 2724 )) + (PORT ADR2 ( 940 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/N25\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/N25\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_and000093) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3494 )) + (PORT ADR1 ( 2427 )) + (PORT ADR2 ( 2030 )) + (PORT ADR3 ( 2137 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_and0000238) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1473 )) + (PORT ADR1 ( 929 )) + (PORT ADR2 ( 1190 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/_and000093\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/_and000093\/O\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>176) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2819 )) + (PORT ADR1 ( 362 )) + (PORT ADR2 ( 2409 )) + (PORT ADR3 ( 936 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1104) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2456 )) + (PORT ADR1 ( 577 )) + (PORT ADR2 ( 2224 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>176\/O\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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(IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v_Eqn_01) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1058 )) + (PORT ADR3 ( 1003 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_v\<0\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_v_0) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1077 )) + (PORT CLK ( 699 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/cursor_v\<0\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5327 )( 5327 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v_Eqn_31) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 674 )) + (PORT ADR2 ( 396 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v_Eqn_21) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 652 )) + (PORT ADR3 ( 414 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/cursor_v\<3\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5233 )( 5233 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v_Eqn_51) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 455 )) + (PORT ADR3 ( 1143 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_v_Eqn_41) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 433 )) + (PORT ADR3 ( 1207 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/cursor_v\<5\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4871 )( 4871 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_mux0002\<1\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2503 )) + (PORT ADR1 ( 2614 )) + (PORT ADR2 ( 2429 )) + (PORT ADR3 ( 1077 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_mux0002\<0\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2481 )) + (PORT ADR1 ( 2777 )) + (PORT ADR2 ( 1157 )) + (PORT ADR3 ( 2134 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/ram_data\<1\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4806 )( 4806 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_mux0002\<3\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2938 )) + (PORT ADR1 ( 2824 )) + (PORT ADR2 ( 2690 )) + (PORT ADR3 ( 1896 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_mux0002\<2\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2680 )) + (PORT ADR1 ( 2847 )) + (PORT ADR2 ( 2722 )) + (PORT ADR3 ( 1754 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/ram_data\<3\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4436 )( 4436 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_mux0002\<5\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2397 )) + (PORT ADR1 ( 1727 )) + (PORT ADR2 ( 2215 )) + (PORT ADR3 ( 1891 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_mux0002\<4\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1668 )) + (PORT ADR1 ( 2183 )) + (PORT ADR2 ( 2131 )) + (PORT ADR3 ( 2176 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/ram_data\<5\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4949 )( 4949 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_not00121) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1251 )) + (PORT ADR2 ( 742 )) + (PORT ADR3 ( 1394 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/state_FFd1\-In1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 983 )) + (PORT ADR2 ( 1407 )) + (PORT ADR3 ( 1027 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/state_FFd1\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/state_FFd1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 705 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/state_FFd1\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7369 )( 7369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/state_FFd2\-In111) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1238 )) + (PORT ADR2 ( 3305 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/state_FFd5\-In) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1296 )) + (PORT ADR1 ( 1333 )) + (PORT ADR2 ( 3114 )) + (PORT ADR3 ( 440 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/state_FFd6\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/state_FFd6\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7693 )( 7693 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/capslock_toggle1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2046 )) + (PORT ADR1 ( 1478 )) + (PORT ADR2 ( 2169 )) + (PORT ADR3 ( 1730 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/shift_set17) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1613 )) + (PORT ADR1 ( 896 )) + (PORT ADR2 ( 1674 )) + (PORT ADR3 ( 1604 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/shift\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/shift) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 844 )) + (PORT CLK ( 719 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/shift\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 8727 )( 8727 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/shift_set14) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 3240 )) + (PORT ADR2 ( 931 )) + (PORT ADR3 ( 1045 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/release_prefix_set1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 652 )) + (PORT ADR1 ( 3263 )) + (PORT ADR2 ( 1100 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/release_prefix\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/release_prefix) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 879 )) + (PORT CLK ( 713 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/release_prefix\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7998 )( 7998 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<11\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1737 )) + (PORT ADR3 ( 719 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<10\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1760 )) + (PORT ADR2 ( 745 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<11\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7498 )( 7498 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<13\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1008 )) + (PORT ADR3 ( 1466 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<12\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1736 )) + (PORT ADR1 ( 923 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<13\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7650 )( 7650 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_13) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 708 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<13\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/ps2_clk_edge11) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2440 )) + (PORT ADR1 ( 1798 )) + (PORT ADR2 ( 3355 )) + (PORT ADR3 ( 1513 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/error_x24) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1552 )) + (PORT ADR1 ( 1210 )) + (PORT ADR2 ( 3458 )) + (PORT ADR3 ( 964 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/error_r\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/error_r) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 690 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/error_r\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6474 )( 6474 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1610 )) + (PORT ADR1 ( 1576 )) + (PORT ADR2 ( 1887 )) + (PORT ADR3 ( 930 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pixel_hold_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 695 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<1\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3049 )) + (PORT ADR2 ( 1341 )) + (PORT ADR3 ( 1803 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<0\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2172 )) + (PORT ADR2 ( 1598 )) + (PORT ADR3 ( 1850 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<1\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<1\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_0) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1875 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<3\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1553 )) + (PORT ADR2 ( 2012 )) + (PORT ADR3 ( 2691 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<2\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2166 )) + (PORT ADR2 ( 2692 )) + (PORT ADR3 ( 1356 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<3\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<3\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1918 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<5\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1394 )) + (PORT ADR2 ( 1662 )) + (PORT ADR3 ( 1732 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<5\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_5) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 3902 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<7\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1345 )) + (PORT ADR2 ( 1406 )) + (PORT ADR3 ( 1265 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<6\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1515 )) + (PORT ADR1 ( 1757 )) + (PORT ADR2 ( 1448 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<7\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<7\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_6) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1918 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<9\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 648 )) + (PORT ADR2 ( 1377 )) + (PORT ADR3 ( 1303 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<8\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 577 )) + (PORT ADR2 ( 1250 )) + (PORT ADR3 ( 1328 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<9\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<9\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_8) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1557 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/hold_count__mux0000\<1\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1202 )) + (PORT ADR1 ( 1160 )) + (PORT ADR3 ( 1035 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/hold_count__mux0000\<0\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1242 )) + (PORT ADR2 ( 961 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/hold_count\<1\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7064 )( 7064 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_not00111) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 455 )) + (PORT ADR1 ( 1581 )) + (PORT ADR2 ( 1620 )) + (PORT ADR3 ( 1064 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/hold_count__mux0000\<2\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1189 )) + (PORT ADR1 ( 1081 )) + (PORT ADR2 ( 1050 )) + (PORT ADR3 ( 1032 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/hold_count\<2\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/hold_count_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 713 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/hold_count\<2\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7812 )( 7812 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/_cmp_eq000142) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1667 )) + (PORT ADR1 ( 1142 )) + (PORT ADR2 ( 932 )) + (PORT ADR3 ( 1106 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<0\>1) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1007 )) + (PORT ADR3 ( 764 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<0\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_0) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<0\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6316 )( 6316 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<3\>1) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 738 )) + (PORT ADR3 ( 825 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<2\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 956 )) + (PORT ADR3 ( 967 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<3\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5963 )( 5963 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<5\>1) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 738 )) + (PORT ADR3 ( 879 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<4\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 956 )) + (PORT ADR3 ( 1071 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<5\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6089 )( 6089 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<7\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 966 )) + (PORT ADR1 ( 1666 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<6\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1380 )) + (PORT ADR2 ( 780 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<7\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5852 )( 5852 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_7) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 697 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<7\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<9\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 554 )) + (PORT ADR2 ( 1457 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<8\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 626 )) + (PORT ADR2 ( 1489 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<9\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7355 )( 7355 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/write_ctrl) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2298 )) + (PORT ADR1 ( 1639 )) + (PORT ADR3 ( 1699 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/write_delay__mux0000\<0\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1249 )) + (PORT ADR1 ( 1652 )) + (PORT ADR2 ( 1684 )) + (PORT ADR3 ( 2129 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/write_delay\<0\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/write_delay_0) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 698 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/write_delay\<0\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6337 )( 6337 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/write_delay__mux0000\<2\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 433 )) + (PORT ADR1 ( 1159 )) + (PORT ADR2 ( 952 )) + (PORT ADR3 ( 940 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/write_delay_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 695 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/write_delay\<2\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6514 )( 6514 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_cmp_eq00001) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1196 )) + (PORT ADR2 ( 1035 )) + (PORT ADR3 ( 995 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/charload\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 714 )( 714 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/charload) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/charload\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3372 )( 3372 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_not00101) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1567 )) + (PORT ADR1 ( 2240 )) + (PORT ADR2 ( 1685 )) + (PORT ADR3 ( 861 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Mrom_set_newline1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1905 )) + (PORT ADR1 ( 2168 )) + (PORT ADR2 ( 1244 )) + (PORT ADR3 ( 908 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/newline\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/newline) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 687 )) + (PORT CLK ( 675 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/newline\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5895 )( 5895 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/pclk__mux0000\<1\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1254 )) + (PORT ADR1 ( 896 )) + (PORT ADR2 ( 2236 )) + (PORT ADR3 ( 968 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/pclk__mux0000\<0\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1214 )) + (PORT ADR1 ( 2329 )) + (PORT ADR2 ( 1254 )) + (PORT ADR3 ( 3290 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/pclk\<1\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3426 )( 3426 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h_Eqn_11) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1165 )) + (PORT ADR2 ( 907 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h_Eqn_01) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1028 )) + (PORT ADR3 ( 896 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/cursor_h\<1\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4826 )( 4826 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h_Eqn_31) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 925 )) + (PORT ADR3 ( 393 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h_Eqn_21) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 973 )) + (PORT ADR3 ( 440 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/cursor_h\<3\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3942 )( 3942 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h_Eqn_51) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 361 )) + (PORT ADR2 ( 861 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h_Eqn_41) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1145 )) + (PORT ADR1 ( 384 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/cursor_h\<5\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6077 )( 6077 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/cursor_h_Eqn_61) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 428 )) + (PORT ADR3 ( 946 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_h_6) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 939 )) + (PORT CLK ( 699 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/cursor_h\<6\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4126 )( 4126 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/ps2_clk_r\<2\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3205 )( 3205 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/ps2_clk_r_1) + (DELAY + (ABSOLUTE + (PORT I ( 1806 )) + (PORT CLK ( 708 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/ps2_clk_r\<2\>\/FFY\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/ps2_clk_r\<4\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2710 )( 2710 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/ps2_clk_r_3) + (DELAY + (ABSOLUTE + (PORT I ( 2255 )) + (PORT CLK ( 700 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/ps2_clk_r\<4\>\/FFY\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1354) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3736 )) + (PORT ADR1 ( 2344 )) + (PORT ADR2 ( 2465 )) + (PORT ADR3 ( 2391 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2109) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2771 )) + (PORT ADR1 ( 2369 )) + (PORT ADR2 ( 2031 )) + (PORT ADR3 ( 2067 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1_map1129\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1_map1129\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1370_SW2) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2738 )) + (PORT ADR1 ( 2638 )) + (PORT ADR2 ( 2632 )) + (PORT ADR3 ( 3686 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2147) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2641 )) + (PORT ADR1 ( 3287 )) + (PORT ADR2 ( 2869 )) + (PORT ADR3 ( 3733 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3178\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3178\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<5\>3852_SW1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1310 )) + (PORT ADR1 ( 2138 )) + (PORT ADR2 ( 2469 )) + (PORT ADR3 ( 2690 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2184) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3406 )) + (PORT ADR1 ( 1460 )) + (PORT ADR2 ( 2434 )) + (PORT ADR3 ( 2726 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3136\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3136\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_cmp_eq00051) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1181 )) + (PORT ADR1 ( 1085 )) + (PORT ADR2 ( 931 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/state_FFd5\-In_SW0) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1184 )) + (PORT ADR2 ( 1283 )) + (PORT ADR3 ( 221 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/_cmp_eq0005\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/_cmp_eq0005\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_not00071) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1621 )) + (PORT ADR1 ( 1847 )) + (PORT ADR2 ( 1820 )) + (PORT ADR3 ( 1422 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_not00061) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1958 )) + (PORT ADR1 ( 2370 )) + (PORT ADR2 ( 1526 )) + (PORT ADR3 ( 1215 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/_not0007\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/_not0007\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1123) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2833 )) + (PORT ADR1 ( 2725 )) + (PORT ADR2 ( 3142 )) + (PORT ADR3 ( 3049 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<2\>1308) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3310 )) + (PORT ADR1 ( 2061 )) + (PORT ADR2 ( 3138 )) + (PORT ADR3 ( 2496 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1_map1449\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1_map1449\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_and0001_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1997 )) + (PORT ADR3 ( 1496 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_not00081) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1864 )) + (PORT ADR1 ( 1342 )) + (PORT ADR2 ( 1863 )) + (PORT ADR3 ( 1660 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N235\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N235\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data216) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2928 )) + (PORT ADR1 ( 2663 )) + (PORT ADR2 ( 2533 )) + (PORT ADR3 ( 2518 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data10) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2745 )) + (PORT ADR1 ( 2686 )) + (PORT ADR2 ( 2469 )) + (PORT ADR3 ( 2679 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N224\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) 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(PORT ADR2 ( 4161 )) + (PORT ADR3 ( 4930 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N219\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N219\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data211) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4242 )) + (PORT ADR1 ( 4327 )) + (PORT ADR2 ( 4662 )) + (PORT ADR3 ( 3931 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data13) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4275 )) + (PORT ADR1 ( 4699 )) + (PORT ADR2 ( 3845 )) + (PORT ADR3 ( 4201 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N218\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N218\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data99) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4752 )) + (PORT ADR1 ( 3578 )) + (PORT ADR2 ( 4727 )) + (PORT ADR3 ( 2799 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data30) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4730 )) + (PORT ADR1 ( 3601 )) + (PORT ADR2 ( 4759 )) + (PORT ADR3 ( 2846 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N104\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N104\/YUSED) + (DELAY + (ABSOLUTE + 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"X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data31) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3359 )) + (PORT ADR1 ( 4332 )) + (PORT ADR2 ( 4252 )) + (PORT ADR3 ( 2994 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N102\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N102\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data207) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3847 )) + (PORT ADR1 ( 4418 )) + (PORT ADR2 ( 3856 )) + (PORT ADR3 ( 3654 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data23) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3825 )) + (PORT ADR1 ( 4448 )) + (PORT ADR2 ( 3615 )) + (PORT ADR3 ( 3299 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N214\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N214\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data96) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3088 )) + (PORT ADR1 ( 3007 )) + (PORT ADR2 ( 3567 )) + (PORT ADR3 ( 5721 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data40) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4522 )) + (PORT ADR1 ( 2357 )) + (PORT ADR2 ( 3313 )) + (PORT ADR3 ( 5747 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N101\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N101\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data94) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4446 )) + (PORT ADR1 ( 3343 )) + (PORT ADR2 ( 3212 )) + (PORT ADR3 ( 5354 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data32) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4424 )) + (PORT ADR1 ( 5874 )) + (PORT ADR2 ( 3139 )) + (PORT ADR3 ( 3147 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N99\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N99\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data206) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3425 )) + (PORT ADR1 ( 3132 )) + (PORT ADR2 ( 3331 )) + (PORT ADR3 ( 3329 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data24) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3792 )) + (PORT ADR1 ( 3155 )) + (PORT ADR2 ( 3118 )) + (PORT ADR3 ( 3136 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N213\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N213\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data93) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 5238 )) + (PORT ADR1 ( 3183 )) + (PORT ADR2 ( 4293 )) + (PORT ADR3 ( 3068 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data41) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3550 )) + (PORT ADR1 ( 5908 )) + (PORT ADR2 ( 2424 )) + (PORT ADR3 ( 3858 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N98\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N98\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data201) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4796 )) + (PORT ADR1 ( 3841 )) + (PORT ADR2 ( 3595 )) + (PORT ADR3 ( 3827 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data25) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4005 )) + (PORT ADR1 ( 4077 )) + (PORT ADR2 ( 3627 )) + (PORT ADR3 ( 3601 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N208\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N208\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data198) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4242 )) + (PORT ADR1 ( 3881 )) + (PORT ADR2 ( 3796 )) + (PORT ADR3 ( 3433 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data17) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3861 )) + (PORT ADR1 ( 3904 )) + (PORT ADR2 ( 3583 )) + (PORT ADR3 ( 3831 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N205\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N205\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data91) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2210 )) + (PORT ADR1 ( 3068 )) + (PORT ADR2 ( 3829 )) + (PORT ADR3 ( 2223 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data50) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2371 )) + (PORT ADR1 ( 3091 )) + (PORT ADR2 ( 3798 )) + (PORT ADR3 ( 3023 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N96\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N96\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data90) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 6329 )) + (PORT ADR1 ( 4510 )) + (PORT ADR2 ( 3519 )) + (PORT ADR3 ( 2354 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data42) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 5616 )) + (PORT ADR1 ( 4571 )) + (PORT ADR2 ( 2455 )) + (PORT ADR3 ( 3674 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N95\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N95\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data89) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 5356 )) + (PORT ADR1 ( 2429 )) + (PORT ADR2 ( 3033 )) + (PORT ADR3 ( 3805 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data34) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 5334 )) + (PORT ADR1 ( 3337 )) + (PORT ADR2 ( 3755 )) + (PORT ADR3 ( 2854 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N94\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N94\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data28) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3726 )) + (PORT ADR1 ( 4052 )) + (PORT ADR2 ( 4772 )) + (PORT ADR3 ( 2692 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data26) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3704 )) + (PORT ADR1 ( 4032 )) + (PORT ADR2 ( 3229 )) + (PORT ADR3 ( 2739 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N31\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N31\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data194) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4879 )) + (PORT ADR1 ( 3117 )) + (PORT ADR2 ( 3723 )) + (PORT ADR3 ( 3491 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data18) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3691 )) + (PORT ADR1 ( 3977 )) + (PORT ADR2 ( 3062 )) + (PORT ADR3 ( 3538 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N201\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N201\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/pixel\<8\>27) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1536 )) + (PORT ADR2 ( 770 )) + (PORT ADR3 ( 2137 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE pixel\<8\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>114_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 6002 )) + (PORT ADR1 ( 3439 )) + (PORT ADR2 ( 2849 )) + (PORT ADR3 ( 2050 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data51) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 5568 )) + (PORT ADR2 ( 2881 )) + (PORT ADR3 ( 3661 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3166\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3166\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data86) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2347 )) + (PORT ADR1 ( 1870 )) + (PORT ADR2 ( 3425 )) + (PORT ADR3 ( 2596 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data43) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2137 )) + (PORT ADR1 ( 2516 )) + (PORT ADR2 ( 3457 )) + (PORT ADR3 ( 2334 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N90\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N90\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data85) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3048 )) + (PORT ADR1 ( 2278 )) + (PORT ADR2 ( 2095 )) + (PORT ADR3 ( 2065 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data35) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2215 )) + (PORT ADR1 ( 2806 )) + (PORT ADR2 ( 3400 )) + (PORT ADR3 ( 2107 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N89\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N89\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>6_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3759 )) + (PORT ADR1 ( 4155 )) + (PORT ADR2 ( 3839 )) + (PORT ADR3 ( 4573 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data27) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4221 )) + (PORT ADR1 ( 4605 )) + (PORT ADR2 ( 3919 )) + (PORT ADR3 ( 3337 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3146\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3146\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data187) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3176 )) + (PORT ADR1 ( 3411 )) + (PORT ADR2 ( 3031 )) + (PORT ADR3 ( 3135 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data19) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3273 )) + (PORT ADR1 ( 2811 )) + (PORT ADR2 ( 2950 )) + (PORT ADR3 ( 3367 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N194\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N194\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data84) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4909 )) + (PORT ADR1 ( 3313 )) + (PORT ADR2 ( 3814 )) + (PORT ADR3 ( 3235 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data60) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4323 )) + (PORT ADR1 ( 3336 )) + (PORT ADR2 ( 4863 )) + (PORT ADR3 ( 4643 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N88\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N88\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data83) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3111 )) + (PORT ADR1 ( 2975 )) + (PORT ADR2 ( 3783 )) + (PORT ADR3 ( 2330 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data52) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2478 )) + (PORT ADR1 ( 2998 )) + (PORT ADR2 ( 2944 )) + (PORT ADR3 ( 3930 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N87\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N87\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data82) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3614 )) + (PORT ADR1 ( 2288 )) + (PORT ADR2 ( 2382 )) + (PORT ADR3 ( 2692 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data44) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3592 )) + (PORT ADR1 ( 2751 )) + (PORT ADR2 ( 2345 )) + (PORT ADR3 ( 2739 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N86\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N86\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data81) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2568 )) + (PORT ADR1 ( 1804 )) + (PORT ADR2 ( 2335 )) + (PORT ADR3 ( 2611 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data36) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2546 )) + (PORT ADR1 ( 2676 )) + (PORT ADR2 ( 2770 )) + (PORT ADR3 ( 1718 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N85\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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(TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/key_up\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7098 )( 7098 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data145) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3585 )) + (PORT ADR1 ( 2788 )) + (PORT ADR2 ( 2682 )) + (PORT ADR3 ( 2176 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data141) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2889 )) + (PORT ADR1 ( 2892 )) + (PORT ADR2 ( 3249 )) + (PORT ADR3 ( 3112 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N151\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N151\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data144) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3374 )) + (PORT ADR1 ( 2639 )) + (PORT ADR2 ( 2517 )) + (PORT ADR3 ( 2657 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data133) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3352 )) + (PORT ADR1 ( 2505 )) + (PORT ADR2 ( 2595 )) + (PORT ADR3 ( 2297 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N150\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N150\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data143) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2496 )) + (PORT ADR1 ( 3648 )) + (PORT ADR2 ( 3124 )) + (PORT ADR3 ( 3006 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data125) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2474 )) + (PORT ADR1 ( 3784 )) + (PORT ADR2 ( 3156 )) + (PORT ADR3 ( 3053 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N149\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N149\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data139) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3886 )) + (PORT ADR1 ( 3079 )) + (PORT ADR2 ( 3624 )) + (PORT ADR3 ( 2754 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data109) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2471 )) + (PORT ADR1 ( 2606 )) + (PORT ADR2 ( 3876 )) + (PORT ADR3 ( 3563 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N145\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N145\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data138) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3287 )) + (PORT ADR1 ( 3282 )) + (PORT ADR2 ( 3603 )) + (PORT ADR3 ( 2215 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data126) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3265 )) + (PORT ADR1 ( 3305 )) + (PORT ADR2 ( 3635 )) + (PORT ADR3 ( 2262 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N144\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N144\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data137) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2651 )) + (PORT ADR1 ( 3219 )) + (PORT ADR2 ( 1979 )) + (PORT ADR3 ( 3054 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data127) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1927 )) + (PORT ADR1 ( 3170 )) + (PORT ADR2 ( 3277 )) + (PORT ADR3 ( 2570 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N143\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N143\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data129) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3438 )) + (PORT ADR1 ( 2137 )) + (PORT ADR2 ( 2497 )) + (PORT ADR3 ( 2484 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data136) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3402 )) + (PORT ADR1 ( 3316 )) + (PORT ADR2 ( 2425 )) + (PORT ADR3 ( 1715 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N134\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N134\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2925 )) + (PORT ADR1 ( 2511 )) + (PORT ADR2 ( 2466 )) + (PORT ADR3 ( 3003 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data128) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2660 )) + (PORT ADR1 ( 3366 )) + (PORT ADR2 ( 2923 )) + (PORT ADR3 ( 2112 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N2\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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(IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>186_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1874 )) + (PORT ADR1 ( 2948 )) + (PORT ADR2 ( 2172 )) + (PORT ADR3 ( 3367 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<6\>1305) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2748 )) + (PORT ADR1 ( 2498 )) + (PORT ADR2 ( 2244 )) + (PORT ADR3 ( 2980 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3124\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3124\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_cy\<7\>) + (DELAY + (ABSOLUTE + (PORT IA ( 1278 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_xor\<7\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_lut\<7\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 962 )) + (PORT ADR1 ( 2030 )) + (PORT ADR3 ( 1456 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/Madd_ram_addrC21) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1880 )) + (PORT ADR2 ( 1700 )) + (PORT ADR3 ( 1680 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<7\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<7\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/crt\/Madd_ram_addr_Madd_cy\<7\>_rt) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_write\<7\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/raise1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1650 )) + (PORT ADR2 ( 1153 )) + (PORT ADR3 ( 1441 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>144) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2077 )) + (PORT ADR1 ( 2632 )) + (PORT ADR2 ( 2488 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/raise\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/raise\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<3\>81) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2438 )) + (PORT ADR2 ( 592 )) + (PORT ADR3 ( 2199 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<5\>3746) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1790 )) + (PORT ADR1 ( 2505 )) + (PORT ADR2 ( 624 )) + (PORT ADR3 ( 2246 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/N43\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/N43\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload8_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2714 )) + (PORT ADR1 ( 2107 )) + (PORT ADR2 ( 1331 )) + (PORT ADR3 ( 886 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload8) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1371 )) + (PORT ADR1 ( 1846 )) + (PORT ADR2 ( 1631 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/pixel_hold\<7\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + 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(CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2_map1701\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<1\>2_map1701\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_Out41) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1224 )) + (PORT ADR1 ( 1810 )) + (PORT ADR3 ( 1825 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/write_delay__mux0000\<1\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1336 )) + (PORT ADR2 ( 1006 )) + (PORT ADR3 ( 221 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/write_delay\<1\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/write_delay_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 695 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/write_delay\<1\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5539 )( 5539 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_Out92) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4072 )) + (PORT ADR1 ( 3253 )) + (PORT ADR3 ( 3091 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_mux00001) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4493 )) + (PORT ADR1 ( 1214 )) + (PORT ADR2 ( 1038 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_wclk\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE gray_cnt_FFd11\/BYMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1108 )( 1108 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE gray_cnt_FFd11\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7574 )( 7574 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE gray_cnt_FFd2) + (DELAY + (ABSOLUTE + (PORT I ( 354 )) + (PORT CLK ( 743 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE gray_cnt_FFd11\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/ram_we_n1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 3564 )) + (PORT ADR2 ( 3272 )) + (PORT ADR3 ( 3586 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ram_addr_mux\<11\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1818 )) + (PORT ADR1 ( 1127 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<11\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/video_ram\/ram_addr_w\<11\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_11) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 3955 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/capslock\/BYMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1135 )( 1135 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/capslock) + (DELAY + (ABSOLUTE + (PORT I ( 354 )) + (PORT CE ( 701 )) + (PORT CLK ( 725 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/capslock\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 8701 )( 8701 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/Madd_ram_addr_video_Madd_cy\<7\>) + (DELAY + (ABSOLUTE + (PORT IA ( 1280 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_XOR2") + (INSTANCE vga\/Madd_ram_addr_video_Madd_xor\<7\>) + (DELAY + (ABSOLUTE + (PORT I0 ( 94 )) + (PORT I1 ( 213 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/Madd_ram_addr_video_Madd_lut\<7\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 964 )) + (PORT ADR1 ( 1815 )) + (PORT ADR3 ( 2121 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/Madd_ram_addr_videoC21) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2687 )) + (PORT ADR1 ( 1980 )) + (PORT ADR3 ( 1765 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_video\<7\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_video\<7\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/Madd_ram_addr_video_Madd_cy\<7\>_rt) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ram_addr_video\<7\>\/CYINIT) + (DELAY + (ABSOLUTE + (IOPATH I O ( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/vcnt_Eqn_1_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1281 )) + (PORT ADR2 ( 1239 )) + (PORT ADR3 ( 1126 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/Madd_ram_addr_videoR21) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1337 )) + (PORT ADR2 ( 1212 )) + (PORT ADR3 ( 2077 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N839\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N839\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/ps2_clk_edge2) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2192 )) + (PORT ADR1 ( 2353 )) + (PORT ADR2 ( 1425 )) + (PORT ADR3 ( 1338 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/timer_x\<1\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 956 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<1\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 696 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/timer_r\<1\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3588 )( 3588 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/error_x13) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1264 )) + (PORT ADR1 ( 1497 )) + (PORT ADR2 ( 1275 )) + (PORT ADR3 ( 1005 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/_cmp_eq00001) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1535 )) + (PORT ADR1 ( 1437 )) + (PORT ADR2 ( 1045 )) + (PORT ADR3 ( 1055 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/error_x_map855\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/error_x_map855\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/ps2\/_cmp_eq00018) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1189 )) + (PORT ADR1 ( 1112 )) + (PORT ADR2 ( 617 )) + (PORT ADR3 ( 603 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/_cmp_eq0001_map1032\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and00005) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1738 )) + (PORT ADR1 ( 1555 )) + (PORT ADR2 ( 1275 )) + (PORT ADR3 ( 1277 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and000015) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1392 )) + (PORT ADR1 ( 4023 )) + (PORT ADR2 ( 944 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/_and0000_map807\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/_and0000_map807\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt_1_1\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3918 )( 3918 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_1_1) + (DELAY + (ABSOLUTE + (PORT I ( 1257 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt_1_1\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4856 )( 4856 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt_2_1\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3918 )( 3918 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_2_1) + (DELAY + (ABSOLUTE + (PORT I ( 1310 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt_2_1\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5117 )( 5117 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_not00091) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1917 )) + (PORT ADR1 ( 2027 )) + (PORT ADR2 ( 1386 )) + (PORT ADR3 ( 1546 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/_not0009\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>3) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1401 )) + (PORT ADR1 ( 4015 )) + (PORT ADR2 ( 2396 )) + (PORT ADR3 ( 907 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload317) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2599 )) + (PORT ADR1 ( 1634 )) + (PORT ADR2 ( 4578 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N0112\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N0112\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>6) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3008 )) + (PORT ADR1 ( 5881 )) + (PORT ADR2 ( 1762 )) + (PORT ADR3 ( 1127 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<4\>71) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1550 )) + (PORT ADR1 ( 4155 )) + (PORT ADR2 ( 1804 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N011234567\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N011234567\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload713) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2036 )) + (PORT ADR1 ( 1497 )) + (PORT ADR2 ( 1775 )) + (PORT ADR3 ( 1872 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<4\>1) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1619 )) + (PORT ADR2 ( 1785 )) + (PORT ADR3 ( 1594 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload7_map993\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload7_map993\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/strobe_out) + (DELAY + (ABSOLUTE + (PORT I ( 2257 )) + (PORT CE ( 879 )) + (PORT CLK ( 709 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/scancode_convert\/strobe_out\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7277 )( 7277 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data3) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3688 )) + (PORT ADR1 ( 2803 )) + (PORT ADR2 ( 2028 )) + (PORT ADR3 ( 3057 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>11) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 5887 )) + (PORT ADR1 ( 3060 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N4\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N4\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data7) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3782 )) + (PORT ADR1 ( 1782 )) + (PORT ADR2 ( 2259 )) + (PORT ADR3 ( 2262 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data4) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2576 )) + (PORT ADR1 ( 2441 )) + (PORT ADR2 ( 3453 )) + (PORT ADR3 ( 1731 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N10\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N10\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>113_SW0) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2160 )) + (PORT ADR2 ( 2344 )) + (PORT ADR3 ( 1583 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data5) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2214 )) + (PORT ADR1 ( 2625 )) + (PORT ADR2 ( 1646 )) + (PORT ADR3 ( 2111 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3170\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3170\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data6) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2563 )) + (PORT ADR1 ( 2531 )) + (PORT ADR2 ( 2396 )) + (PORT ADR3 ( 1817 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<2\>12) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2969 )) + (PORT ADR2 ( 2473 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N8\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/N8\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>121_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2673 )) + (PORT ADR1 ( 2089 )) + (PORT ADR2 ( 3199 )) + (PORT ADR3 ( 2249 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/char_rom\/Mrom_data9) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2651 )) + (PORT ADR1 ( 2566 )) + (PORT ADR3 ( 2296 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3160\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3160\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_Out911) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 2257 )) + (PORT ADR3 ( 2116 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_mux0002\<6\>1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2096 )) + (PORT ADR1 ( 1660 )) + (PORT ADR2 ( 1178 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/ram_data\<6\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd3\-In37) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 884 )) + (PORT ADR1 ( 743 )) + (PORT ADR2 ( 845 )) + (PORT ADR3 ( 1155 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd3\-In48) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1612 )) + (PORT ADR2 ( 902 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/state_FFd3\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/state_FFd3) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 692 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/state_FFd3\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6202 )( 6202 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/insert_crt_data1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2447 )) + (PORT ADR2 ( 2011 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd1\-In_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1000 )) + (PORT ADR1 ( 1172 )) + (PORT ADR2 ( 1527 )) + (PORT ADR3 ( 1208 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/insert_crt_data\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/insert_crt_data\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd1\-In_SW1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 693 )) + (PORT ADR1 ( 1623 )) + (PORT ADR2 ( 818 )) + (PORT ADR3 ( 1183 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/state_FFd1\-In) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 956 )) + (PORT ADR1 ( 385 )) + (PORT ADR2 ( 962 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/state_FFd1\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/state_FFd1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 689 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/state_FFd1\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4022 )( 4022 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_cmp_eq000111) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1842 )) + (PORT ADR1 ( 2356 )) + (PORT ADR2 ( 2005 )) + (PORT ADR3 ( 1898 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_and0000_SW1) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2392 )) + (PORT ADR1 ( 1026 )) + (PORT ADR2 ( 1866 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/N16\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/N16\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/rom_addr_char\<1\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2319 )( 2319 )) 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(CELLTYPE "X_FF") + (INSTANCE vga\/rom_addr_char_4) + (DELAY + (ABSOLUTE + (PORT I ( 3031 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/rom_addr_char\<6\>\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2518 )( 2518 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/rom_addr_char_6) + (DELAY + (ABSOLUTE + (PORT I ( 2609 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1158) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2636 )) + (PORT ADR1 ( 3144 )) + (PORT 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(IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>241) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1901 )) + (PORT ADR3 ( 2530 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/N28\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/N28\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/sc_0) + (DELAY + (ABSOLUTE + (PORT I ( 2472 )) + (PORT CE ( 3057 )) + (PORT CLK ( 795 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) 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1309 )) + (PORT ADR1 ( 1227 )) + (PORT ADR2 ( 974 )) + (PORT ADR3 ( 1085 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_and0000129) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2069 )) + (PORT ADR1 ( 1865 )) + (PORT ADR2 ( 1292 )) + (PORT ADR3 ( 1723 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3108\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3108\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_or00001) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 909 )) + (PORT ADR3 ( 1208 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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+ ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_and0000156) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1839 )) + (PORT ADR1 ( 1413 )) + (PORT ADR2 ( 1589 )) + (PORT ADR3 ( 1305 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/_and0000_map929\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/pixelData\<0\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1040 )( 1040 )) + ) + ) + ) + (CELL (CELLTYPE "X_SFF") + (INSTANCE vga\/pixelData_0) + (DELAY + (ABSOLUTE + (PORT CLK ( 696 )) + (PORT SRST ( 305 )) + (IOPATH CLK O ( 1292 )) + (IOPATH SET O ( 1292 )) + (IOPATH RST O ( 1292 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) 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ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/_cmp_eq0001_map1041\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/rom_addr_char_0_1\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2319 )( 2319 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/rom_addr_char_0_1) + (DELAY + (ABSOLUTE + (PORT I ( 3591 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/rom_addr_char_1_1\/CKINV) + (DELAY + (ABSOLUTE + (IOPATH I O ( 2100 )( 2100 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/rom_addr_char_1_1) + (DELAY + (ABSOLUTE + (PORT I ( 2681 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK 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(IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/ps2\/rdy_r\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3706 )( 3706 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/crt\/_cmp_eq00011) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 626 )) + (PORT ADR1 ( 2152 )) + (PORT ADR2 ( 2193 )) + (PORT ADR3 ( 1606 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/_cmp_eq0001\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>14) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2569 )) + (PORT ADR1 ( 3287 )) + (PORT ADR2 ( 2611 )) + (PORT ADR3 ( 2394 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/scancode_rom\/data\<0\>1_map1423\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and000015_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1848 )) + (PORT ADR3 ( 1522 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and000033) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2009 )) + (PORT ADR1 ( 3294 )) + (PORT ADR2 ( 1630 )) + (PORT ADR3 ( 1433 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3132\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3132\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_and000026) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1627 )) + (PORT ADR1 ( 1478 )) + (PORT ADR2 ( 2030 )) + (PORT ADR3 ( 2850 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and000046) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1800 )) + (PORT ADR1 ( 1501 )) + (PORT ADR2 ( 1539 )) + (PORT ADR3 ( 1338 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/_and0000_map879\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/_and0000_map879\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and000047) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 999 )) + (PORT ADR1 ( 900 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and000074) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1373 )) + (PORT ADR1 ( 1346 )) + (PORT ADR2 ( 786 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hsync\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hsync) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 703 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hsync\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4640 )( 4640 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload513) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3372 )) + (PORT ADR1 ( 1497 )) + (PORT ADR2 ( 3641 )) + (PORT ADR3 ( 1715 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload413) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1917 )) + (PORT ADR1 ( 1553 )) + (PORT ADR2 ( 3376 )) + (PORT ADR3 ( 3567 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload5_map965\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload5_map965\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>152_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2494 )) + (PORT ADR1 ( 2532 )) + (PORT ADR3 ( 1930 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/rom_addr_char\<1\>104_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2472 )) + (PORT ADR1 ( 3769 )) + (PORT ADR3 ( 2342 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3172\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3172\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/_and000053) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1746 )) + (PORT ADR1 ( 2604 )) + (PORT ADR2 ( 1340 )) + (PORT ADR3 ( 1968 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/_and0000_map890\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload617) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1870 )) + (PORT ADR1 ( 5593 )) + (PORT ADR2 ( 2336 )) + (PORT ADR3 ( 1380 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload628) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 4376 )) + (PORT ADR1 ( 3503 )) + (PORT ADR2 ( 950 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload6_map1010\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload6_map1010\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload637) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1167 )) + (PORT ADR1 ( 3902 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/charload669) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1996 )) + (PORT ADR1 ( 385 )) + (PORT ADR2 ( 942 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload6_map1014\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/charload6_map1014\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crtclk1\/BYMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1914 )( 1914 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crtclk) + (DELAY + (ABSOLUTE + (PORT I ( 354 )) + (PORT CLK ( 780 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crtclk1\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7193 )( 7193 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/sc_0_1) + (DELAY + (ABSOLUTE + (PORT I ( 2197 )) + (PORT CE ( 2282 )) + (PORT CLK ( 725 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt_data\<1\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6793 )( 6793 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt_data_0) + (DELAY + (ABSOLUTE + (PORT I ( 2499 )) + (PORT CLK ( 3748 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt_data\<1\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/sc_1_1) + (DELAY + (ABSOLUTE + (PORT I ( 2655 )) + (PORT CE ( 2369 )) + (PORT CLK ( 711 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt_data\<3\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6266 )( 6266 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt_data_2) + (DELAY + (ABSOLUTE + (PORT I ( 3033 )) + (PORT CLK ( 1950 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt_data\<3\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt_data\<5\>\/SRMUX) + (DELAY + (ABSOLUTE + (IOPATH I O ( 6974 )( 6974 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt_data_4) + (DELAY + (ABSOLUTE + (PORT I ( 2979 )) + (PORT CLK ( 3798 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt_data\<5\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt_data_6) + (DELAY + (ABSOLUTE + (PORT I ( 2626 )) + (PORT CLK ( 3798 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt_data\<6\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 7238 )( 7238 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<0\>) + (DELAY + (ABSOLUTE + (PORT IA ( 316 )) + (PORT IB ( 46 )) + (PORT SEL ( 1153 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_AND2") + (INSTANCE vga\/vgacore\/hcnt_Eqn_0_mand) + (DELAY + (ABSOLUTE + (PORT I0 ( 1178 )) + (PORT I1 ( 1364 )) + (IOPATH I0 O ( 0 )( 0 )) + (IOPATH I1 O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcount_hcnt_lut\<0\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1189 )) + (PORT ADR1 ( 997 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/Mcompar__cmp_lt0000_cy\<4\>_inv_INV_0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1893 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<0\>\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_MUX2") + (INSTANCE vga\/vgacore\/Mcount_hcnt_cy\<0\>_rt) + (DELAY + (ABSOLUTE + (PORT IB ( 50 )) + (PORT SEL ( 1112 )) + (IOPATH IA O ( 0 )( 0 )) + (IOPATH IB O ( 0 )( 0 )) + (IOPATH SEL O ( 0 )( 0 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_0) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hcnt\<0\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4793 )( 4793 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/scancode_convert\/_cmp_eq0000_SW0_SW0) + (DELAY + (ABSOLUTE + (PORT ADR2 ( 1166 )) + (PORT ADR3 ( 1141 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE N3100\/YUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and0001_SW0) + (DELAY + (ABSOLUTE + (PORT ADR1 ( 1033 )) + (PORT ADR2 ( 1715 )) + (PORT ADR3 ( 2029 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/vgacore\/_and0001) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 2733 )) + (PORT ADR1 ( 1749 )) + (PORT ADR2 ( 1947 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vsync\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vsync) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 700 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vsync\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3582 )( 3582 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/pclk__mux0000\<2\>_SW0) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 3972 )) + (PORT ADR1 ( 3388 )) + (PORT ADR2 ( 3209 )) + (PORT ADR3 ( 1461 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_LUT4") + (INSTANCE vga\/pclk__mux0000\<2\>) + (DELAY + (ABSOLUTE + (PORT ADR0 ( 1204 )) + (PORT ADR1 ( 1206 )) + (PORT ADR2 ( 1042 )) + (PORT ADR3 ( 222 )) + (IOPATH ADR0 O ( 284 )) + (IOPATH ADR1 O ( 284 )) + (IOPATH ADR2 O ( 284 )) + (IOPATH ADR3 O ( 284 )) + ) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/pclk\<2\>\/XUSED) + (DELAY + (ABSOLUTE + (IOPATH I O ( 369 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pclk_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 704 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/pclk\<2\>\/FFY\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3731 )( 3731 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/ascii_3) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CE ( 1933 )) + (PORT CLK ( 795 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/ascii_4) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CE ( 2075 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pixel_hold_0) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 719 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pixel_hold_1) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 717 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pixel_hold_5) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 720 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pixel_hold_3) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 719 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pixel_hold_6) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 693 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hblank) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 702 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/hblank\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4138 )( 4138 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<1\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_4) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<3\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_6) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<5\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_8) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 702 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<7\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_10) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 706 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<9\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_0_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<0\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<1\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_4) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<3\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_6) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<5\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_8) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<7\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_v_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 893 )) + (PORT CLK ( 684 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_v\<3\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_v_4) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 954 )) + (PORT CLK ( 683 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_v\<5\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/ram_data_0) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1375 )) + (PORT CLK ( 685 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/ram_data\<1\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/ram_data_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1876 )) + (PORT CLK ( 765 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/ram_data\<3\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/ram_data_4) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1157 )) + (PORT CLK ( 685 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/ram_data\<5\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + 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)) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/hold_count\<1\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_2) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<3\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_4) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 696 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<5\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_6) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 697 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge 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SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_h\<5\>\/FFY\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ram_wclk) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 704 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE 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727 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE ps2_clk\/IFF\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1044 )( 1044 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/sc_r_9) + (DELAY + (ABSOLUTE + (PORT I ( 2479 )) + (PORT CE ( 2828 )) + (PORT CLK ( 587 )) + (PORT RST ( 695 )) + (IOPATH CLK O ( 727 )( 727 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE ps2_data\/IFF\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 713 )( 713 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/state_FFd2) + (DELAY + (ABSOLUTE + (PORT I ( 421 )) + (PORT CLK ( 672 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/crt\/state_FFd2\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 5786 )( 5786 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_3) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<3\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_5) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<5\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/hcnt_7) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 702 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/hcnt\<7\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE 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(posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<5\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_7) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/vgacore\/vcnt\<7\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/vgacore\/vcnt_9) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_INV") + (INSTANCE vga\/vgacore\/vcnt\<9\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 4138 )( 4138 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/ascii_5) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 2071 )) + (PORT CLK ( 708 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_v_3) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 893 )) + (PORT CLK ( 684 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_v\<3\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_v_5) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 954 )) + (PORT CLK ( 683 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_v\<5\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/ram_data_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1375 )) + (PORT CLK ( 685 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/ram_data\<1\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/ram_data_3) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1876 )) + (PORT CLK ( 765 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/ram_data\<3\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/ram_data_5) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1157 )) + (PORT CLK ( 685 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/ram_data\<5\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/state_FFd6) + (DELAY + (ABSOLUTE + (PORT CLK ( 713 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/state_FFd6\/FFX\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_11) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 705 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<11\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1875 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_3) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1918 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_7) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1918 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/video_ram\/ram_addr_w_9) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 1557 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/hold_count_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 705 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/scancode_convert\/hold_count\<1\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_3) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 794 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<3\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_5) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 696 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<5\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/timer_r_9) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 705 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/timer_r\<9\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/pclk_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CLK ( 704 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/pclk\<1\>\/FFX\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_h_1) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 1203 )) + (PORT CLK ( 685 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_h\<1\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_h_3) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 908 )) + (PORT CLK ( 684 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_h\<3\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt\/cursor_h_5) + (DELAY + (ABSOLUTE + (PORT I ( 590 )) + (PORT CE ( 797 )) + (PORT CLK ( 683 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt\/cursor_h\<5\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/sc_1) + (DELAY + (ABSOLUTE + (PORT I ( 2917 )) + (PORT CE ( 3057 )) + (PORT CLK ( 795 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/sc_3) + (DELAY + (ABSOLUTE + (PORT I ( 2275 )) + (PORT CE ( 2978 )) + (PORT CLK ( 710 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/scancode_convert\/sc_5) + (DELAY + (ABSOLUTE + (PORT I ( 1896 )) + (PORT CE ( 2691 )) + (PORT CLK ( 795 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (posedge CE) (posedge CLK) (885)(0)) + (SETUPHOLD (negedge CE) (posedge CLK) (885)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/rom_addr_char_1) + (DELAY + (ABSOLUTE + (PORT I ( 3119 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/rom_addr_char_3) + (DELAY + (ABSOLUTE + (PORT I ( 1893 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/rom_addr_char_5) + (DELAY + (ABSOLUTE + (PORT I ( 2530 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/ps2_clk_r_2) + (DELAY + (ABSOLUTE + (PORT I ( 1221 )) + (PORT CLK ( 708 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/ps2_clk_r\<2\>\/FFX\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/ps2\/ps2_clk_r_4) + (DELAY + (ABSOLUTE + (PORT I ( 1170 )) + (PORT CLK ( 700 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 985 )( 985 )) + (IOPATH RST O ( 0 )( 0 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge SET) (posedge CLK) (520)) + (WIDTH (posedge SET) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/ps2\/ps2_clk_r\<4\>\/FFX\/SETOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE gray_cnt_FFd1) + (DELAY + (ABSOLUTE + (PORT I ( 1150 )) + (PORT CLK ( 743 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE gray_cnt_FFd11\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt_data_1) + (DELAY + (ABSOLUTE + (PORT I ( 2696 )) + (PORT CLK ( 3748 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt_data\<1\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt_data_3) + (DELAY + (ABSOLUTE + (PORT I ( 3162 )) + (PORT CLK ( 1950 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt_data\<3\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_FF") + (INSTANCE vga\/crt_data_5) + (DELAY + (ABSOLUTE + (PORT I ( 2580 )) + (PORT CLK ( 3798 )) + (IOPATH CLK O ( 1292 )( 1292 )) + (IOPATH SET O ( 0 )( 0 )) + (IOPATH RST O ( 985 )( 985 )) + ) + ) + (TIMINGCHECK + (SETUPHOLD (posedge I) (posedge CLK) (478)(0)) + (SETUPHOLD (negedge I) (posedge CLK) (478)(0)) + (PERIOD (posedge CLK) (3612)) + (RECOVERY (negedge RST) (posedge CLK) (520)) + (WIDTH (posedge RST) (3010)) + ) + ) + (CELL (CELLTYPE "X_BUF") + (INSTANCE vga\/crt_data\<5\>\/FFX\/RSTOR) + (DELAY + (ABSOLUTE + (IOPATH I O ( 305 )( 305 )) + ) + ) + ) + (CELL (CELLTYPE "X_CKBUF") + (INSTANCE vga\/crtclk_BUFG\/BUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3416 )) + ) + ) + ) + (CELL (CELLTYPE "X_CKBUF") + (INSTANCE clka_BUFGP\/BUFG\/BUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 1562 )) + ) + ) + ) + (CELL (CELLTYPE "X_CKBUF") + (INSTANCE gray_cnt_FFd1_BUFG\/BUF) + (DELAY + (ABSOLUTE + (IOPATH I O ( 3233 )) + ) + ) + ) +) diff --git a/xilinx/vga/netgen/par/fpga_timesim.v b/xilinx/vga/netgen/par/fpga_timesim.v new file mode 100644 index 0000000..fb58542 --- /dev/null +++ b/xilinx/vga/netgen/par/fpga_timesim.v @@ -0,0 +1,15597 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: I.31 +// \ \ Application: netgen +// / / Filename: fpga_timesim.v +// /___/ /\ Timestamp: Fri Dec 29 10:07:45 2006 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -s 5 -pcf fpga.pcf -sdf_anno true -sdf_path netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim fpga.ncd fpga_timesim.v +// Device : 2s200fg256-5 (PRODUCTION 1.27 2006-05-03) +// Input file : fpga.ncd +// Output file : /mwave/work/nt/xess/xilinx/vga/netgen/par/fpga_timesim.v +// # of Modules : 1 +// Design Name : fpga +// Xilinx : /opt/Xilinx +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Development System Reference Guide, Chapter 23 +// Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module fpga ( + reset_n, ps2_clk, ps2_data, clka, vga_hsync_n, fpga_din_d0, vga_red0, vga_red1, vga_red2, vga_green0, vga_green1, vga_green2, vga_blue0, vga_blue1, +vga_blue2, vga_vsync_n, fpga_d1, fpga_d2, fpga_d3, fpga_d4, fpga_d5, fpga_d6, fpga_d7 +); + input reset_n; + input ps2_clk; + input ps2_data; + input clka; + output vga_hsync_n; + output fpga_din_d0; + output vga_red0; + output vga_red1; + output vga_red2; + output vga_green0; + output vga_green1; + output vga_green2; + output vga_blue0; + output vga_blue1; + output vga_blue2; + output vga_vsync_n; + output fpga_d1; + output fpga_d2; + output fpga_d3; + output fpga_d4; + output fpga_d5; + output fpga_d6; + output fpga_d7; + wire gray_cnt_FFd1_0; + wire reset_n_IBUF_0; + wire \vga/ps2/rdy_r_1 ; + wire \vga/ps2/ps2_clk_fall_edge_0 ; + wire \pixel<8>_0 ; + wire \vga/vgacore/vsync_2 ; + wire \vga/vgacore/hsync_3 ; + wire \vga/crtclk1 ; + wire \vga/crtclk_4 ; + wire clka_BUFGP; + wire gray_cnt_FFd11; + wire \vga/ram_wclk_5 ; + wire \vga/N226_0 ; + wire \vga/ram_addr_mux<11>_0 ; + wire \vga/ram_addr_mux<10>_0 ; + wire \vga/ram_addr_mux<9>_0 ; + wire \vga/ram_addr_mux<8>_0 ; + wire \vga/ram_addr_mux<7>_0 ; + wire \vga/ram_addr_mux<6>_0 ; + wire \vga/ram_addr_mux<5>_0 ; + wire \vga/ram_addr_mux<4>_0 ; + wire \vga/ram_addr_mux<3>_0 ; + wire \vga/ram_addr_mux<2>_0 ; + wire \vga/ram_addr_mux<1>_0 ; + wire \vga/ram_addr_mux<0>_0 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1831 ; + wire N3084_0; + wire \vga/scancode_convert/scancode_rom/N9 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1774_0 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1229_0 ; + wire N3141_0; + wire N3142_0; + wire \vga/scancode_convert/scancode_rom/N28_0 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1056_0 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1098_0 ; + wire \vga/rom_addr_char<4>11_0 ; + wire \vga/rom_addr_char<4>_f5_0 ; + wire \vga/rom_addr_char<3>_f6_0_6 ; + wire \vga/rom_addr_char<3>_f61_0 ; + wire N560_0; + wire \vga/scancode_convert/_or0000_0 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1201_0 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1221_0 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1158_0 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1171_0 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1185_0 ; + wire \vga/scancode_convert/raise ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1633_0 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1669_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1534_0 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1560_0 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1565_0 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1609_0 ; + wire \vga/N11_0 ; + wire \vga/N12_0 ; + wire \vga/rom_addr_char<2>_f51_0 ; + wire \vga/N10_0 ; + wire \vga/rom_addr_char_1_1_7 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1666_0 ; + wire \vga/N21_0 ; + wire \vga/N22_0 ; + wire \vga/rom_addr_char<2>_f53_0 ; + wire \vga/N20_0 ; + wire \vga/vgacore/vcnt_1_1_8 ; + wire N3146_0; + wire \vga/N16_0 ; + wire \vga/N17_0 ; + wire \vga/vgacore/N51_0 ; + wire \vga/vgacore/vcnt_2_1_9 ; + wire \vga/pixel<8>_map785_0 ; + wire N3222_0; + wire \vga/N29_0 ; + wire \vga/N30_0 ; + wire \vga/rom_addr_char<2>_f55_0 ; + wire \vga/N27_0 ; + wire \vga/N28_0 ; + wire \vga/rom_addr_char<3>_f62_0 ; + wire \vga/N25_0 ; + wire \vga/N26_0 ; + wire \vga/N23_0 ; + wire \vga/N24_0 ; + wire \vga/N7_0 ; + wire \vga/N37_0 ; + wire \vga/rom_addr_char<2>_f57_0 ; + wire \vga/N35_0 ; + wire \vga/rom_addr_char<3>_f63_0 ; + wire \vga/N33_0 ; + wire \vga/N34_0 ; + wire \vga/N31_0 ; + wire \vga/N32_0 ; + wire \vga/N45_0 ; + wire \vga/N43_0 ; + wire \vga/N44_0 ; + wire \vga/rom_addr_char<2>_f58_0 ; + wire \vga/N40_0 ; + wire \vga/N41_0 ; + wire \vga/N38_0 ; + wire \vga/N39_0 ; + wire \vga/rom_addr_char<2>_f59_0 ; + wire \vga/N113_0 ; + wire \vga/N75_0 ; + wire \vga/rom_addr_char<2>_f5111_0 ; + wire \vga/N72_0 ; + wire \vga/N99_0 ; + wire \vga/rom_addr_char<3>_f65_0 ; + wire \vga/scancode_convert/sc_0_1_10 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1337_0 ; + wire \vga/N224_0 ; + wire N3150_0; + wire \vga/N14 ; + wire \vga/N15_0 ; + wire \vga/N13_0 ; + wire \vga/rom_addr_char<1>112_0 ; + wire \vga/rom_addr_char<1>_mmx_out_0 ; + wire \vga/rom_addr_char<1>2_0 ; + wire \vga/rom_addr_char<3>_f5_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1461_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1475_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1449_0 ; + wire \vga/scancode_convert/scancode_rom/N7 ; + wire N3104_0; + wire \vga/rom_addr_char<2>11_0 ; + wire \vga/rom_addr_char<2>2_0 ; + wire \vga/rom_addr_char<3>_f621_0 ; + wire \vga/rom_addr_char<3>_f631_0 ; + wire \vga/rom_addr_char<3>_f64_0 ; + wire \vga/rom_addr_char<5>_f5_0 ; + wire \vga/scancode_convert/scancode_rom/N12 ; + wire N3126_0; + wire \vga/crt/state_FFd3_11 ; + wire \vga/crt/state_FFd2_12 ; + wire \vga/crt/state_FFd1_13 ; + wire \vga/scancode_convert/key_up_14 ; + wire \vga/scancode_convert/strobe_out_15 ; + wire \vga/crt/scroll_0 ; + wire \vga/crt/eol_0 ; + wire \vga/ps2/error_r_16 ; + wire \vga/ps2/_cmp_eq0001 ; + wire \vga/vgacore/vcnt_0_1_17 ; + wire \vga/rom_addr_char_0_1_18 ; + wire \vga/charload_19 ; + wire \vga/cursor_match_0 ; + wire \vga/charload2_map865_0 ; + wire \vga/N142_0 ; + wire \vga/N143_0 ; + wire \vga/rom_addr_char<2>_f511_0 ; + wire \vga/rom_addr_char<3>_f612_0 ; + wire \vga/N53_0 ; + wire \vga/rom_addr_char<2>_f5112_0 ; + wire \vga/rom_addr_char<3>_f6123_0 ; + wire \vga/N94_0 ; + wire \vga/N95_0 ; + wire N3166_0; + wire \vga/rom_addr_char<2>_f51234_0 ; + wire \vga/N2_0 ; + wire \vga/rom_addr_char<2>_f511234_0 ; + wire \vga/N186_0 ; + wire \vga/rom_addr_char<3>_f612345_0 ; + wire \vga/charload3_map953_0 ; + wire \vga/N70_0 ; + wire \vga/N71_0 ; + wire \vga/rom_addr_char<2>_f51112_0 ; + wire \vga/N68_0 ; + wire \vga/N69_0 ; + wire \vga/charload4_map979_0 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1751_0 ; + wire \vga/rom_addr_char<3>_f6212_0 ; + wire \vga/rom_addr_char<3>_f6312_0 ; + wire \vga/rom_addr_char<3>_f641_0 ; + wire \vga/rom_addr_char<3>_f651_0 ; + wire \vga/rom_addr_char<5>_f51_0 ; + wire \vga/rom_addr_char<3>_f61123_0 ; + wire \vga/rom_addr_char<3>_f62123_0 ; + wire \vga/rom_addr_char<3>_f63123_0 ; + wire \vga/rom_addr_char<3>_f6412_0 ; + wire \vga/rom_addr_char<5>_f512_0 ; + wire \vga/rom_addr_char<3>_f621234_0 ; + wire \vga/rom_addr_char<3>_f631234_0 ; + wire \vga/rom_addr_char<3>_f64123_0 ; + wire \vga/rom_addr_char<5>_f5123_0 ; + wire \vga/charload5_map965_0 ; + wire \vga/charload7_map993_0 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1548_0 ; + wire \vga/ram_we_n ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1717_0 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1729_0 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1701_0 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1708_0 ; + wire N3106_0; + wire \vga/N4 ; + wire N3164_0; + wire \vga/crt/newline_20 ; + wire \vga/crt/_cmp_eq0001_0 ; + wire N3144_0; + wire \vga/N138_0 ; + wire \vga/N139_0 ; + wire \vga/N47_0 ; + wire \vga/N137_0 ; + wire \vga/N49_0 ; + wire \vga/N50_0 ; + wire \vga/N48_0 ; + wire \vga/N155_0 ; + wire \vga/N64_0 ; + wire \vga/N104_0 ; + wire \vga/N105_0 ; + wire \vga/rom_addr_char<2>_f52123_0 ; + wire \vga/rom_addr_char<3>_f61234_0 ; + wire \vga/N150_0 ; + wire \vga/N151_0 ; + wire \vga/rom_addr_char<2>_f531_0 ; + wire \vga/N55_0 ; + wire \vga/N149_0 ; + wire \vga/rom_addr_char<3>_f611_0 ; + wire \vga/N184_0 ; + wire \vga/N8 ; + wire \vga/N183_0 ; + wire \vga/N59_0 ; + wire \vga/N60_0 ; + wire \vga/rom_addr_char<2>_f5312_0 ; + wire \vga/N58_0 ; + wire \vga/rom_addr_char<3>_f6112_0 ; + wire \vga/N101_0 ; + wire \vga/N102_0 ; + wire \vga/N146_0 ; + wire \vga/N147_0 ; + wire \vga/N144_0 ; + wire \vga/N145_0 ; + wire \vga/N194_0 ; + wire \vga/rom_addr_char<2>_f531234_0 ; + wire \vga/N193_0 ; + wire \vga/rom_addr_char<3>_f611234_0 ; + wire \vga/N56_0 ; + wire \vga/N57_0 ; + wire \vga/N54_0 ; + wire \vga/N127_0 ; + wire \vga/N128_0 ; + wire \vga/rom_addr_char<2>_f54123_0 ; + wire \vga/N125_0 ; + wire \vga/N126_0 ; + wire \vga/rom_addr_char<2>_f551_0 ; + wire \vga/N171_0 ; + wire \vga/N172_0 ; + wire \vga/N191_0 ; + wire \vga/N192_0 ; + wire \vga/N190_0 ; + wire \vga/N82_0 ; + wire \vga/N83_0 ; + wire \vga/rom_addr_char<2>_f5512_0 ; + wire \vga/N80_0 ; + wire \vga/N81_0 ; + wire \vga/N78_0 ; + wire \vga/N79_0 ; + wire \vga/N121_0 ; + wire \vga/N170_0 ; + wire \vga/N167_0 ; + wire \vga/N213_0 ; + wire \vga/rom_addr_char<2>_f551234_0 ; + wire N3170_0; + wire \vga/N133_0 ; + wire \vga/N134_0 ; + wire \vga/rom_addr_char<2>_f56123_0 ; + wire \vga/N131_0 ; + wire \vga/N132_0 ; + wire N3160_0; + wire \vga/rom_addr_char<2>_f571_0 ; + wire \vga/N178_0 ; + wire \vga/N179_0 ; + wire N3148_0; + wire \vga/N208_0 ; + wire \vga/N89_0 ; + wire \vga/N90_0 ; + wire \vga/rom_addr_char<2>_f5712_0 ; + wire \vga/N87_0 ; + wire \vga/N88_0 ; + wire \vga/N129_0 ; + wire \vga/N130_0 ; + wire \vga/N176_0 ; + wire \vga/N86_0 ; + wire \vga/N175_0 ; + wire \vga/rom_addr_char<2>_f571234_0 ; + wire \vga/N218_0 ; + wire \vga/N219_0 ; + wire \vga/N85_0 ; + wire N3172_0; + wire \vga/rom_addr_char<2>_f58123_0 ; + wire \vga/N110_0 ; + wire \vga/N111_0 ; + wire \vga/N67_0 ; + wire \vga/N159_0 ; + wire \vga/rom_addr_char<2>_f591_0 ; + wire \vga/N65_0 ; + wire \vga/N157_0 ; + wire \vga/N216_0 ; + wire \vga/N214_0 ; + wire \vga/N215_0 ; + wire \vga/rom_addr_char<2>_f5912_0 ; + wire \vga/N66_0 ; + wire \vga/N63_0 ; + wire \vga/N106_0 ; + wire \vga/N62_0 ; + wire \vga/N152_0 ; + wire \vga/rom_addr_char<2>_f591234_0 ; + wire \vga/N205_0 ; + wire \vga/N61_0 ; + wire \vga/N120_0 ; + wire \vga/rom_addr_char<2>_f51012_0 ; + wire \vga/N117_0 ; + wire \vga/N118_0 ; + wire \vga/N74_0 ; + wire \vga/N73_0 ; + wire \vga/N201_0 ; + wire \vga/N115_0 ; + wire \vga/N116_0 ; + wire \vga/N114_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1249_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1245_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1260_0 ; + wire N3112_0; + wire \vga/crt/Madd_ram_addrR2_0 ; + wire \vga/ram_addr_write<5>_0 ; + wire \vga/ram_addr_write<6>_0 ; + wire \vga/ram_addr_write<8>_0 ; + wire \vga/ram_addr_write<9>_0 ; + wire \vga/ram_addr_write<10>_0 ; + wire \vga/ram_addr_write<11>_0 ; + wire GLOBAL_LOGIC1; + wire GLOBAL_LOGIC0; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy<4>_0 ; + wire \vga/vgacore/hblank_21 ; + wire \vga/Madd_ram_addr_videoR2_0 ; + wire \vga/ram_addr_video<5>_0 ; + wire \vga/ram_addr_video<6>_0 ; + wire \vga/ram_addr_video<8>_0 ; + wire \vga/ram_addr_video<9>_0 ; + wire \vga/ram_addr_video<10>_0 ; + wire \vga/ram_addr_video<11>_0 ; + wire \vga/ps2/_addsub0000<1>_0 ; + wire \vga/ps2/_addsub0000<2>_0 ; + wire \vga/ps2/_addsub0000<3>_0 ; + wire \vga/ps2/_addsub0000<4>_0 ; + wire \vga/ps2/_addsub0000<5>_0 ; + wire \vga/ps2/_addsub0000<6>_0 ; + wire \vga/ps2/_addsub0000<7>_0 ; + wire \vga/ps2/_addsub0000<8>_0 ; + wire \vga/ps2/_addsub0000<9>_0 ; + wire \vga/ps2/_addsub0000<10>_0 ; + wire \vga/ps2/_addsub0000<11>_0 ; + wire \vga/ps2/_addsub0000<12>_0 ; + wire \vga/ps2/_addsub0000<13>_0 ; + wire \vga/crt/Result<1>_0 ; + wire \vga/crt/Result<2>_0 ; + wire \vga/crt/Result<3>_0 ; + wire \vga/crt/Result<4>_0 ; + wire \vga/crt/Result<5>_0 ; + wire \vga/crt/Result<1>1_0 ; + wire \vga/crt/Result<2>1_0 ; + wire \vga/crt/Result<3>1_0 ; + wire \vga/crt/Result<4>1_0 ; + wire \vga/crt/Result<5>1_0 ; + wire \vga/crt/Result<6>_0 ; + wire \vga/vgacore/hcnt_Eqn_bis_0 ; + wire \vga/vgacore/vcnt_Eqn_bis_0_0 ; + wire N839_0; + wire \vga/vgacore/Result<1>1_0 ; + wire \vga/vgacore/Result<2>1_0 ; + wire N786_0; + wire \vga/vgacore/N0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1437/O ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1526_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1529_0 ; + wire \vga/scancode_convert/ctrl_22 ; + wire \vga/scancode_convert/sc_1_1_23 ; + wire \vga/scancode_convert/shift_24 ; + wire \vga/scancode_convert/capslock_25 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1503_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1539/O ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1445_0 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1808_0 ; + wire N3085_0; + wire \vga/scancode_convert/_cmp_eq00041_SW0/O ; + wire \vga/scancode_convert/N10_0 ; + wire \vga/scancode_convert/scancode_rom/data<1>2465/O ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1690_0 ; + wire \vga/scancode_convert/scancode_rom/data<2>1264/O ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1121_0 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1124_0 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1129_0 ; + wire \vga/scancode_convert/scancode_rom/data<2>1410/O ; + wire \vga/scancode_convert/scancode_rom/data<3>199/O ; + wire N3174_0; + wire \vga/scancode_convert/scancode_rom/data<4>1308_SW1/O ; + wire \vga/scancode_convert/N31 ; + wire \vga/scancode_convert/N11_0 ; + wire \vga/scancode_convert/scancode_rom/data<4>1392_SW0/O ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1820_0 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1803_0 ; + wire \vga/scancode_convert/scancode_rom/data<6>1247/O ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1863_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3247/O ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1276_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1295_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3359/O ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1340_0 ; + wire N3130_0; + wire \vga/scancode_convert/scancode_rom/data<6>1333/O ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1850_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1394_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3852_SW0/O ; + wire N3136_0; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1416_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3664/O ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1363_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1381_0 ; + wire \vga/scancode_convert/scancode_rom/data<5>3895_SW0/O ; + wire N3108_0; + wire \vga/scancode_convert/release_prefix_26 ; + wire \vga/scancode_convert/_and0000_0 ; + wire \vga/scancode_convert/_cmp_eq0000_27 ; + wire \vga/scancode_convert/state_FFd2-In_SW0/O ; + wire \vga/scancode_convert/state_FFd2_28 ; + wire \vga/scancode_convert/state_FFd3-In_SW0/O ; + wire \vga/scancode_convert/state_FFd3_29 ; + wire N306_0; + wire \vga/crt/_and0000_SW0/O ; + wire \vga/crt/_and0000_0 ; + wire \vga/crt/eol_SW0/O ; + wire N3100_0; + wire \vga/scancode_convert/state_FFd4_30 ; + wire \vga/scancode_convert/state_FFd5_31 ; + wire \vga/scancode_convert/_not0010_0 ; + wire \vga/crt/scroll_SW0/O ; + wire \vga/scancode_convert/state_FFd4-In24/O ; + wire \vga/crt/_not0007_0 ; + wire N235_0; + wire \vga/crt/_and0001_32 ; + wire \vga/scancode_convert/scancode_rom/N18_0 ; + wire \vga/scancode_convert/scancode_rom/data<1>218/O ; + wire \vga/scancode_convert/scancode_rom/N25 ; + wire \vga/scancode_convert/shift_set_map833 ; + wire \vga/scancode_convert/_not0007_0 ; + wire \vga/scancode_convert/scancode_rom/data<3>126_SW1/O ; + wire \vga/scancode_convert/scancode_rom/N43_0 ; + wire \vga/scancode_convert/scancode_rom/data<4>145/O ; + wire \vga/scancode_convert/raise1_33 ; + wire N3124_0; + wire \vga/_and0000_map879_0 ; + wire \vga/_and0000_map890_0 ; + wire \vga/_and000093/O ; + wire \vga/_and0000_map943_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1429_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1438_0 ; + wire \vga/scancode_convert/scancode_rom/data<0>176/O ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1423_0 ; + wire N3178_0; + wire \vga/scancode_convert/scancode_rom/data<0>1370_SW1/O ; + wire \vga/crt/_not0008_0 ; + wire \vga/scancode_convert/_cmp_eq0005 ; + wire \vga/scancode_convert/state_FFd1_34 ; + wire \vga/scancode_convert/_not0012_0 ; + wire N124_0; + wire \vga/scancode_convert/state_FFd6_35 ; + wire \vga/scancode_convert/shift_set_map836_0 ; + wire \vga/scancode_convert/capslock_toggle_0 ; + wire \vga/ps2/ps2_clk_edge ; + wire \vga/ps2/error_x_map855_0 ; + wire \vga/ram_addr_write<7>_0 ; + wire \vga/ram_addr_video<7>_0 ; + wire \vga/scancode_convert/_not0011_0 ; + wire \vga/ps2/_cmp_eq0001_map1047_0 ; + wire \vga/crt/_cmp_eq0004 ; + wire \vga/crt/_not0010 ; + wire \vga/clearing ; + wire \vga/crt/N91 ; + wire \vga/crt/_not0006_0 ; + wire \vga/insert_crt_data ; + wire \vga/N222_0 ; + wire \vga/N221_0 ; + wire \vga/N98_0 ; + wire \vga/N96_0 ; + wire N3162; + wire \vga/scancode_convert/_not0009_0 ; + wire N3158; + wire \vga/crt/Madd_ram_addrC2 ; + wire \vga/rom_addr_char<4>11234_0 ; + wire N562; + wire gray_cnt_FFd2_36; + wire \vga/Madd_ram_addr_videoC2 ; + wire \vga/ps2/_cmp_eq0000_0 ; + wire \vga/ps2/_cmp_eq0001_map1032_0 ; + wire N3132_0; + wire \vga/vgacore/_and0000_map807 ; + wire \vga/vgacore/_and0000_map811_0 ; + wire \vga/N6_0 ; + wire \vga/N0112 ; + wire \vga/N11123_0 ; + wire \vga/N011234567 ; + wire \vga/N1112_0 ; + wire \vga/crt/state_FFd3-In_map800 ; + wire N116_0; + wire N117; + wire \vga/crt/N16 ; + wire \vga/_and0000_map918_0 ; + wire \vga/charload6_map1018_0 ; + wire \vga/charload6_map1022 ; + wire \vga/_and0000_map929_0 ; + wire \vga/ps2/_cmp_eq0001_map1035_0 ; + wire \vga/_and0000_map940_0 ; + wire \vga/_and0000_map941 ; + wire \vga/ps2/_cmp_eq0001_map1041_0 ; + wire \vga/vgacore/_and0000_map817_0 ; + wire \vga/vgacore/_and0000_map824_0 ; + wire \vga/vgacore/_and0000_map825 ; + wire \vga/charload6_map1010 ; + wire \vga/charload6_map1012_0 ; + wire \vga/charload6_map1014 ; + wire N44; + wire N89; + wire \ps2_clk/IDELAY ; + wire ps2_clk_IBUF_37; + wire \fpga_d1/OUTMUX_38 ; + wire \fpga_d2/OUTMUX_39 ; + wire \fpga_d3/OUTMUX_40 ; + wire \fpga_d4/OUTMUX_41 ; + wire \fpga_d5/OUTMUX_42 ; + wire \fpga_d6/OUTMUX_43 ; + wire \fpga_d7/OUTMUX_44 ; + wire \ps2_data/IDELAY ; + wire ps2_data_IBUF_45; + wire \fpga_din_d0/OUTMUX_46 ; + wire \vga_blue0/OUTMUX_47 ; + wire \vga_blue1/OUTMUX_48 ; + wire \vga_vsync_n/OUTMUX_49 ; + wire \vga_blue2/OUTMUX_50 ; + wire \vga_hsync_n/OUTMUX_51 ; + wire \vga_red0/OUTMUX_52 ; + wire \vga_red1/OUTMUX_53 ; + wire \vga_red2/OUTMUX_54 ; + wire reset_n_IBUF_55; + wire \vga_green0/OUTMUX_56 ; + wire \vga_green1/OUTMUX_57 ; + wire \vga_green2/OUTMUX_58 ; + wire \vga/inst_Mram_mem11/DOA0 ; + wire \vga/inst_Mram_mem11/DIB0 ; + wire \vga/inst_Mram_mem11/LOGIC_ZERO_59 ; + wire \vga/inst_Mram_mem11/LOGIC_ONE_60 ; + wire \vga/inst_Mram_mem11/CLKB_INTNOT ; + wire \vga/inst_Mram_mem21/DOA0 ; + wire \vga/inst_Mram_mem21/DIB0 ; + wire \vga/inst_Mram_mem21/LOGIC_ZERO_61 ; + wire \vga/inst_Mram_mem21/LOGIC_ONE_62 ; + wire \vga/inst_Mram_mem21/CLKB_INTNOT ; + wire \vga/inst_Mram_mem31/DOA0 ; + wire \vga/inst_Mram_mem31/DIB0 ; + wire \vga/inst_Mram_mem31/LOGIC_ZERO_63 ; + wire \vga/inst_Mram_mem31/LOGIC_ONE_64 ; + wire \vga/inst_Mram_mem31/CLKB_INTNOT ; + wire \vga/inst_Mram_mem41/DOA0 ; + wire \vga/inst_Mram_mem41/DIB0 ; + wire \vga/inst_Mram_mem41/LOGIC_ZERO_65 ; + wire \vga/inst_Mram_mem41/LOGIC_ONE_66 ; + wire \vga/inst_Mram_mem41/CLKB_INTNOT ; + wire \vga/inst_Mram_mem51/DOA0 ; + wire \vga/inst_Mram_mem51/DIB0 ; + wire \vga/inst_Mram_mem51/LOGIC_ZERO_67 ; + wire \vga/inst_Mram_mem51/LOGIC_ONE_68 ; + wire \vga/inst_Mram_mem51/CLKB_INTNOT ; + wire \vga/inst_Mram_mem61/DOA0 ; + wire \vga/inst_Mram_mem61/DIB0 ; + wire \vga/inst_Mram_mem61/LOGIC_ZERO_69 ; + wire \vga/inst_Mram_mem61/LOGIC_ONE_70 ; + wire \vga/inst_Mram_mem61/CLKB_INTNOT ; + wire \vga/inst_Mram_mem8/DOA0 ; + wire \vga/inst_Mram_mem8/DIB0 ; + wire \vga/inst_Mram_mem8/LOGIC_ZERO_71 ; + wire \vga/inst_Mram_mem8/LOGIC_ONE_72 ; + wire \vga/inst_Mram_mem8/CLKB_INTNOT ; + wire N3199; + wire N3198; + wire N3084; + wire N3187; + wire N3186; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1774 ; + wire N3245; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1229/GROM ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1229 ; + wire N3201; + wire N3200; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1098 ; + wire N3193; + wire N3192; + wire N560; + wire N3117; + wire N3116; + wire N3191; + wire N3190; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1221 ; + wire N3119; + wire N3118; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1633 ; + wire N3121; + wire N3120; + wire \vga/N2123 ; + wire \vga/N312 ; + wire \vga/rom_addr_char<2>_f51_73 ; + wire N3203; + wire N3202; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1666 ; + wire \vga/N412 ; + wire \vga/N512 ; + wire \vga/rom_addr_char<3>_f61_74 ; + wire \vga/rom_addr_char<2>_f52_75 ; + wire \vga/N612 ; + wire \vga/N712 ; + wire \vga/rom_addr_char<2>_f53_76 ; + wire N3221; + wire \vga/pixel<8>_map785 ; + wire N3222; + wire \vga/N912 ; + wire \vga/N1011 ; + wire \vga/rom_addr_char<3>_f62_77 ; + wire \vga/rom_addr_char<2>_f54_78 ; + wire \vga/N1111 ; + wire \vga/N1211 ; + wire \vga/rom_addr_char<2>_f55 ; + wire \vga/N1311 ; + wire \vga/N1411 ; + wire \vga/rom_addr_char<3>_f63_79 ; + wire \vga/rom_addr_char<2>_f56 ; + wire N3078; + wire \vga/N1611 ; + wire \vga/rom_addr_char<2>_f57 ; + wire \vga/N1711 ; + wire \vga/N1811 ; + wire \vga/rom_addr_char<2>_f58 ; + wire \vga/N2011 ; + wire \vga/N2111 ; + wire \vga/rom_addr_char<2>_f59 ; + wire \vga/N2112 ; + wire \vga/N2212 ; + wire \vga/rom_addr_char<3>_f65 ; + wire \vga/rom_addr_char<2>_f510 ; + wire N3215; + wire N3214; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1337 ; + wire N3259; + wire \N3150/GROM ; + wire N3150; + wire \vga/N01 ; + wire \vga/N1101 ; + wire \vga/rom_addr_char<3>_f6_80 ; + wire \vga/rom_addr_char<2>_f5_85 ; + wire \vga/N1712345 ; + wire \vga/N1812345 ; + wire \vga/rom_addr_char<3>_f5_86 ; + wire N3189; + wire N3188; + wire N3104; + wire \vga/N1911 ; + wire \vga/N2211 ; + wire \vga/rom_addr_char<4>_f5_87 ; + wire \vga/N1612 ; + wire \vga/N251 ; + wire \vga/rom_addr_char<5>_f5_88 ; + wire N3254; + wire N3255; + wire N3126; + wire N3226; + wire N3227; + wire \vga/crt/state_FFd2-In ; + wire N3207; + wire N3206; + wire \vga/ps2/bitcnt_r<2>/FFX/RST ; + wire N3224; + wire N3225; + wire \vga/ps2/bitcnt_r<0>/FFX/RST ; + wire N3230; + wire N3231; + wire \vga/ps2/bitcnt_r<1>/FFX/RST ; + wire N3242; + wire N3243; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1056 ; + wire N3261; + wire N3262; + wire \vga/rom_addr_char<1>_mmx_out ; + wire N3228; + wire N3229; + wire \vga/N01123 ; + wire \vga/N111234 ; + wire \vga/rom_addr_char<3>_f612 ; + wire \vga/rom_addr_char<2>_f512 ; + wire \vga/vgacore/N51/FROM ; + wire N3244; + wire \vga/vgacore/N51 ; + wire \vga/N011234 ; + wire \vga/N1112345 ; + wire \vga/rom_addr_char<3>_f6123 ; + wire \vga/rom_addr_char<2>_f5123 ; + wire \vga/N0112345 ; + wire \vga/N11123456 ; + wire \vga/rom_addr_char<2>_f51234 ; + wire \vga/N01123456 ; + wire \vga/N111234567 ; + wire \vga/rom_addr_char<3>_f612345 ; + wire \vga/rom_addr_char<2>_f512345 ; + wire N3233; + wire \vga/pixel_hold<0>_rt_89 ; + wire \vga/N231 ; + wire \vga/N2412 ; + wire \vga/rom_addr_char<2>_f51112 ; + wire N3236; + wire N3237; + wire N3249; + wire N3250; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1751 ; + wire \vga/N16123 ; + wire \vga/N2512 ; + wire \vga/rom_addr_char<5>_f51_90 ; + wire \vga/N141234 ; + wire \vga/N23123 ; + wire \vga/rom_addr_char<5>_f512 ; + wire \vga/N1612345 ; + wire \vga/N231234 ; + wire \vga/rom_addr_char<5>_f5123 ; + wire N3234; + wire N3235; + wire N3205; + wire N3204; + wire \vga/ps2/bitcnt_r<3>/FFX/RST ; + wire N3238; + wire N3239; + wire N3256; + wire N3257; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1171 ; + wire N3248; + wire \vga/scancode_convert/sc<3>_rt_91 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1548 ; + wire N3219; + wire N3220; + wire N3185; + wire N3184; + wire N3106; + wire N3211; + wire N3210; + wire \vga/charload2_map865 ; + wire N3209; + wire N3208; + wire N3144; + wire N3195; + wire N3194; + wire \vga/rom_addr_char<1>112_92 ; + wire N3197; + wire N3196; + wire \vga/rom_addr_char<1>2_93 ; + wire \vga/N21234 ; + wire \vga/N3123 ; + wire \vga/rom_addr_char<2>_f511 ; + wire \vga/N212345 ; + wire \vga/N31234 ; + wire \vga/rom_addr_char<2>_f5112 ; + wire N3079; + wire \vga/N241 ; + wire \vga/rom_addr_char<2>_f5111 ; + wire \vga/N2123456 ; + wire \vga/N312345 ; + wire \vga/rom_addr_char<3>_f61234 ; + wire \vga/rom_addr_char<2>_f51123 ; + wire \vga/N4123 ; + wire \vga/N5 ; + wire \vga/rom_addr_char<3>_f611 ; + wire \vga/rom_addr_char<2>_f521 ; + wire \vga/N21234567 ; + wire \vga/N3123456 ; + wire \vga/rom_addr_char<2>_f511234 ; + wire \vga/N41234 ; + wire \vga/N5123 ; + wire \vga/rom_addr_char<3>_f6112 ; + wire \vga/rom_addr_char<2>_f5212 ; + wire \vga/N412345 ; + wire \vga/N51234 ; + wire \vga/rom_addr_char<2>_f52123 ; + wire \vga/N6123 ; + wire \vga/N7123 ; + wire \vga/rom_addr_char<2>_f531 ; + wire \vga/N4123456 ; + wire \vga/N512345 ; + wire \vga/rom_addr_char<3>_f611234 ; + wire \vga/rom_addr_char<2>_f521234 ; + wire \vga/N61234 ; + wire \vga/N71234 ; + wire \vga/rom_addr_char<2>_f5312 ; + wire \vga/N612345 ; + wire \vga/N712345 ; + wire \vga/rom_addr_char<3>_f61123 ; + wire \vga/rom_addr_char<2>_f53123 ; + wire \vga/N8123 ; + wire \vga/N9 ; + wire \vga/rom_addr_char<3>_f621 ; + wire \vga/rom_addr_char<2>_f541 ; + wire \vga/N6123456 ; + wire \vga/N7123456 ; + wire \vga/rom_addr_char<2>_f531234 ; + wire \vga/N81234 ; + wire \vga/N91 ; + wire \vga/rom_addr_char<3>_f6212 ; + wire \vga/rom_addr_char<2>_f5412 ; + wire \vga/N10123 ; + wire \vga/N9123 ; + wire \vga/rom_addr_char<2>_f54123 ; + wire \vga/N1012 ; + wire \vga/N11112 ; + wire \vga/rom_addr_char<2>_f551 ; + wire \vga/N8123456 ; + wire \vga/N91234 ; + wire \vga/rom_addr_char<3>_f621234 ; + wire \vga/rom_addr_char<2>_f541234 ; + wire N3080; + wire \vga/N111123 ; + wire \vga/rom_addr_char<2>_f5512 ; + wire \vga/N101234 ; + wire \vga/N1110 ; + wire \vga/rom_addr_char<3>_f62123 ; + wire \vga/rom_addr_char<2>_f55123 ; + wire \vga/N1212 ; + wire \vga/N1312 ; + wire \vga/rom_addr_char<3>_f631 ; + wire \vga/rom_addr_char<2>_f561 ; + wire \vga/N1012345 ; + wire \vga/N1111234 ; + wire \vga/rom_addr_char<2>_f551234 ; + wire \vga/N12123 ; + wire \vga/N13123 ; + wire \vga/rom_addr_char<3>_f6312 ; + wire \vga/rom_addr_char<2>_f5612 ; + wire \vga/N121234 ; + wire \vga/N131234 ; + wire \vga/rom_addr_char<2>_f56123 ; + wire \vga/N1412 ; + wire \vga/N1512 ; + wire \vga/rom_addr_char<2>_f571 ; + wire \vga/N1212345 ; + wire \vga/N1312345 ; + wire \vga/rom_addr_char<3>_f631234 ; + wire \vga/rom_addr_char<2>_f561234 ; + wire \vga/N14123 ; + wire \vga/N15123 ; + wire \vga/rom_addr_char<2>_f5712 ; + wire \vga/N151234 ; + wire \vga/N161234 ; + wire \vga/rom_addr_char<3>_f63123 ; + wire \vga/rom_addr_char<2>_f57123 ; + wire \vga/N1712 ; + wire \vga/N1812 ; + wire \vga/rom_addr_char<3>_f64_94 ; + wire \vga/rom_addr_char<2>_f581 ; + wire \vga/N1412345 ; + wire \vga/N1512345 ; + wire \vga/rom_addr_char<2>_f571234 ; + wire \vga/N17123 ; + wire \vga/N18123 ; + wire \vga/rom_addr_char<3>_f641 ; + wire \vga/rom_addr_char<2>_f5812 ; + wire \vga/N19123 ; + wire \vga/N181234 ; + wire \vga/rom_addr_char<2>_f58123 ; + wire \vga/N1912 ; + wire \vga/N2012 ; + wire \vga/rom_addr_char<2>_f591 ; + wire \vga/N1912345 ; + wire \vga/N2012345 ; + wire \vga/rom_addr_char<3>_f64123 ; + wire \vga/rom_addr_char<2>_f581234 ; + wire N3081; + wire \vga/N20123 ; + wire \vga/rom_addr_char<2>_f5912 ; + wire \vga/N191234 ; + wire \vga/N201234 ; + wire \vga/rom_addr_char<3>_f6412 ; + wire \vga/rom_addr_char<2>_f59123 ; + wire \vga/N21123 ; + wire \vga/N22123 ; + wire \vga/rom_addr_char<3>_f651 ; + wire \vga/rom_addr_char<2>_f5101 ; + wire \vga/N1511 ; + wire \vga/N2212345 ; + wire \vga/rom_addr_char<2>_f591234 ; + wire \vga/N211234 ; + wire \vga/N221234 ; + wire \vga/rom_addr_char<2>_f51012 ; + wire N3264; + wire N3265; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1201 ; + wire N3213; + wire N3212; + wire N3112; + wire \vga/crt/Madd_ram_addrC_mand1 ; + wire \vga/ram_addr_write<5>/CYMUXG ; + wire \vga/crt/Madd_ram_addrC1_mand1 ; + wire \vga/crt/N8 ; + wire \vga/crt/Madd_ram_addr_Madd_cy[5] ; + wire \vga/ram_addr_write<5>/LOGIC_ZERO_95 ; + wire \vga/crt/Madd_ram_addrC3_mand1 ; + wire \vga/crt/N10 ; + wire \vga/ram_addr_write<8>/CYMUXG ; + wire \vga/crt/Madd_ram_addrC4_mand1 ; + wire \vga/crt/N11 ; + wire \vga/crt/Madd_ram_addr_Madd_cy[8] ; + wire \vga/ram_addr_write<8>/CYINIT_96 ; + wire \vga/crt/N12 ; + wire \vga/crt/cursor_v<5>_rt_97 ; + wire \vga/crt/Madd_ram_addr_Madd_cy[10] ; + wire \vga/ram_addr_write<10>/CYINIT_98 ; + wire \vga/vgacore/N4 ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy<1>/CYMUXG ; + wire \vga/vgacore/hcnt<4>_rt_99 ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy[0] ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ZERO_100 ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ONE_101 ; + wire \vga/vgacore/N5 ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYMUXG ; + wire \vga/vgacore/N6 ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy[2] ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYINIT_102 ; + wire \vga/vgacore/hblank/LOGIC_ONE_103 ; + wire \vga/vgacore/N7 ; + wire \vga/vgacore/Mcompar__cmp_lt0000_cy[4] ; + wire \vga/vgacore/hblank/CYINIT_104 ; + wire \vga/vgacore/_mux0002 ; + wire \vga/Madd_ram_addr_videoC_mand1 ; + wire \vga/ram_addr_video<5>/CYMUXG ; + wire \vga/Madd_ram_addr_videoC1_mand1 ; + wire \vga/N229 ; + wire \vga/Madd_ram_addr_video_Madd_cy[5] ; + wire \vga/ram_addr_video<5>/LOGIC_ZERO_105 ; + wire \vga/Madd_ram_addr_videoC3_mand1 ; + wire \vga/N2313 ; + wire \vga/ram_addr_video<8>/CYMUXG ; + wire \vga/Madd_ram_addr_videoC4_mand1 ; + wire \vga/N232 ; + wire \vga/Madd_ram_addr_video_Madd_cy[8] ; + wire \vga/ram_addr_video<8>/CYINIT_106 ; + wire \vga/N233 ; + wire \vga/vgacore/vcnt<8>_rt_107 ; + wire \vga/Madd_ram_addr_video_Madd_cy[10] ; + wire \vga/ram_addr_video<10>/CYINIT_108 ; + wire \vga/ps2/N5 ; + wire \vga/ps2/_addsub0000<1>/CYMUXG ; + wire \vga/ps2/_addsub0000<1>/GROM ; + wire \vga/ps2/Madd__addsub0000_cy[0] ; + wire \vga/ps2/_addsub0000<1>/LOGIC_ZERO_109 ; + wire \vga/ps2/_addsub0000<2>/FROM ; + wire \vga/ps2/_addsub0000<2>/CYMUXG ; + wire \vga/ps2/_addsub0000<2>/LOGIC_ZERO_110 ; + wire \vga/ps2/_addsub0000<2>/GROM ; + wire \vga/ps2/Madd__addsub0000_cy[2] ; + wire \vga/ps2/_addsub0000<2>/CYINIT_111 ; + wire \vga/ps2/_addsub0000<4>/FROM ; + wire \vga/ps2/_addsub0000<4>/CYMUXG ; + wire \vga/ps2/_addsub0000<4>/LOGIC_ZERO_112 ; + wire \vga/ps2/_addsub0000<4>/GROM ; + wire \vga/ps2/Madd__addsub0000_cy[4] ; + wire \vga/ps2/_addsub0000<4>/CYINIT_113 ; + wire \vga/ps2/_addsub0000<6>/FROM ; + wire \vga/ps2/_addsub0000<6>/CYMUXG ; + wire \vga/ps2/_addsub0000<6>/LOGIC_ZERO_114 ; + wire \vga/ps2/_addsub0000<6>/GROM ; + wire \vga/ps2/Madd__addsub0000_cy[6] ; + wire \vga/ps2/_addsub0000<6>/CYINIT_115 ; + wire \vga/ps2/_addsub0000<8>/FROM ; + wire \vga/ps2/_addsub0000<8>/CYMUXG ; + wire \vga/ps2/_addsub0000<8>/LOGIC_ZERO_116 ; + wire \vga/ps2/_addsub0000<8>/GROM ; + wire \vga/ps2/Madd__addsub0000_cy[8] ; + wire \vga/ps2/_addsub0000<8>/CYINIT_117 ; + wire \vga/ps2/_addsub0000<10>/FROM ; + wire \vga/ps2/_addsub0000<10>/CYMUXG ; + wire \vga/ps2/_addsub0000<10>/LOGIC_ZERO_118 ; + wire \vga/ps2/_addsub0000<10>/GROM ; + wire \vga/ps2/Madd__addsub0000_cy[10] ; + wire \vga/ps2/_addsub0000<10>/CYINIT_119 ; + wire \vga/ps2/_addsub0000<12>/LOGIC_ZERO_120 ; + wire \vga/ps2/_addsub0000<12>/FROM ; + wire \vga/ps2/timer_r<13>_rt_121 ; + wire \vga/ps2/Madd__addsub0000_cy[12] ; + wire \vga/ps2/_addsub0000<12>/CYINIT_122 ; + wire \vga/crt/Result<1>/CYMUXG ; + wire \vga/crt/Result<1>/GROM ; + wire \vga/crt/Mcount_cursor_v_cy[0] ; + wire \vga/crt/Result<1>/LOGIC_ZERO_123 ; + wire \vga/crt/Result<2>/FROM ; + wire \vga/crt/Result<2>/CYMUXG ; + wire \vga/crt/Result<2>/LOGIC_ZERO_124 ; + wire \vga/crt/Result<2>/GROM ; + wire \vga/crt/Mcount_cursor_v_cy[2] ; + wire \vga/crt/Result<2>/CYINIT_125 ; + wire \vga/crt/Result<4>/LOGIC_ZERO_126 ; + wire \vga/crt/Result<4>/FROM ; + wire \vga/crt/Result<4>/GROM ; + wire \vga/crt/Mcount_cursor_v_cy[4] ; + wire \vga/crt/Result<4>/CYINIT_127 ; + wire \vga/crt/Result<0>1 ; + wire \vga/crt/Result<1>1/CYMUXG ; + wire \vga/crt/Result<1>1 ; + wire \vga/crt/Result<1>1/GROM ; + wire \vga/crt/Mcount_cursor_h_cy[0] ; + wire \vga/crt/Result<1>1/LOGIC_ZERO_128 ; + wire \vga/crt/Result<2>1/FROM ; + wire \vga/crt/Result<2>1 ; + wire \vga/crt/Result<2>1/CYMUXG ; + wire \vga/crt/Result<2>1/LOGIC_ZERO_129 ; + wire \vga/crt/Result<3>1 ; + wire \vga/crt/Result<2>1/GROM ; + wire \vga/crt/Mcount_cursor_h_cy[2] ; + wire \vga/crt/Result<2>1/CYINIT_130 ; + wire \vga/crt/Result<4>1/FROM ; + wire \vga/crt/Result<4>1 ; + wire \vga/crt/Result<4>1/CYMUXG ; + wire \vga/crt/Result<4>1/LOGIC_ZERO_131 ; + wire \vga/crt/Result<5>1 ; + wire \vga/crt/Result<4>1/GROM ; + wire \vga/crt/Mcount_cursor_h_cy[4] ; + wire \vga/crt/Result<4>1/CYINIT_132 ; + wire \vga/crt/cursor_h<6>_rt_133 ; + wire \vga/crt/Result<6>/CYINIT_134 ; + wire \vga/vgacore/hcnt_Eqn_1 ; + wire \vga/vgacore/hcnt<1>/CYMUXG ; + wire \vga/vgacore/hcnt<1>/LOGIC_ZERO_135 ; + wire \vga/vgacore/hcnt_Eqn_2 ; + wire \vga/vgacore/Mcount_hcnt_cy[1] ; + wire \vga/vgacore/hcnt<1>/CYINIT_136 ; + wire \vga/vgacore/hcnt<1>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/hcnt<1>/FFX/RST ; + wire \vga/vgacore/hcnt_Eqn_3 ; + wire \vga/vgacore/hcnt<3>/CYMUXG ; + wire \vga/vgacore/hcnt<3>/LOGIC_ZERO_137 ; + wire \vga/vgacore/hcnt_Eqn_4 ; + wire \vga/vgacore/Mcount_hcnt_cy[3] ; + wire \vga/vgacore/hcnt<3>/CYINIT_138 ; + wire \vga/vgacore/hcnt<3>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/hcnt_Eqn_5 ; + wire \vga/vgacore/hcnt<5>/CYMUXG ; + wire \vga/vgacore/hcnt<5>/LOGIC_ZERO_139 ; + wire \vga/vgacore/hcnt_Eqn_6 ; + wire \vga/vgacore/Mcount_hcnt_cy[5] ; + wire \vga/vgacore/hcnt<5>/CYINIT_140 ; + wire \vga/vgacore/hcnt<5>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/hcnt_Eqn_7 ; + wire \vga/vgacore/hcnt<7>/CYMUXG ; + wire \vga/vgacore/hcnt<7>/LOGIC_ZERO_141 ; + wire \vga/vgacore/hcnt_Eqn_8 ; + wire \vga/vgacore/Mcount_hcnt_cy[7] ; + wire \vga/vgacore/hcnt<7>/CYINIT_142 ; + wire \vga/vgacore/hcnt<7>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/hcnt<9>/LOGIC_ZERO_143 ; + wire \vga/vgacore/hcnt_Eqn_9 ; + wire \vga/vgacore/hcnt_Eqn_10 ; + wire \vga/vgacore/Mcount_hcnt_cy[9] ; + wire \vga/vgacore/hcnt<9>/CYINIT_144 ; + wire \vga/vgacore/hcnt<9>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/hcnt<9>/FFX/RST ; + wire \vga/vgacore/vcnt_Eqn_0_mand1 ; + wire \vga/vgacore/Result<0>1 ; + wire \vga/vgacore/vcnt<0>/CYMUXG ; + wire \vga/vgacore/vcnt<0>/LOGIC_ONE_145 ; + wire \vga/vgacore/Mcount_vcnt_cy<0>_rt_146 ; + wire \vga/vgacore/vcnt<0>/LOGIC_ZERO_147 ; + wire \vga/vgacore/vcnt<0>/SRMUX_OUTPUTNOT ; + wire N3216; + wire \vga/vgacore/vcnt<0>/CKMUXNOT ; + wire \vga/vgacore/vcnt<0>/FFX/RST ; + wire \vga/vgacore/vcnt_Eqn_1_148 ; + wire \vga/vgacore/Result<1>1 ; + wire \vga/vgacore/vcnt<1>/CYMUXG ; + wire \vga/vgacore/vcnt<1>/LOGIC_ZERO_149 ; + wire \vga/vgacore/vcnt_Eqn_2 ; + wire \vga/vgacore/Mcount_vcnt_cy[1] ; + wire \vga/vgacore/vcnt<1>/CYINIT_150 ; + wire \vga/vgacore/vcnt<1>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/Result<2>1 ; + wire \vga/vgacore/vcnt<1>/CKMUXNOT ; + wire \vga/vgacore/vcnt_Eqn_3_151 ; + wire \vga/vgacore/Result<3>1 ; + wire \vga/vgacore/vcnt<3>/CYMUXG ; + wire \vga/vgacore/vcnt<3>/LOGIC_ZERO_152 ; + wire \vga/vgacore/vcnt_Eqn_4 ; + wire \vga/vgacore/Mcount_vcnt_cy[3] ; + wire \vga/vgacore/vcnt<3>/CYINIT_153 ; + wire \vga/vgacore/vcnt<3>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/Result<4>1 ; + wire \vga/vgacore/vcnt<3>/CKMUXNOT ; + wire \vga/vgacore/vcnt_Eqn_5 ; + wire \vga/vgacore/Result<5>1 ; + wire \vga/vgacore/vcnt<5>/CYMUXG ; + wire \vga/vgacore/vcnt<5>/LOGIC_ZERO_154 ; + wire \vga/vgacore/vcnt_Eqn_6 ; + wire \vga/vgacore/Mcount_vcnt_cy[5] ; + wire \vga/vgacore/vcnt<5>/CYINIT_155 ; + wire \vga/vgacore/vcnt<5>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/Result<6>1 ; + wire \vga/vgacore/vcnt<5>/CKMUXNOT ; + wire \vga/vgacore/vcnt_Eqn_7 ; + wire \vga/vgacore/Result<7>1 ; + wire \vga/vgacore/vcnt<7>/CYMUXG ; + wire \vga/vgacore/vcnt<7>/LOGIC_ZERO_156 ; + wire \vga/vgacore/vcnt_Eqn_8 ; + wire \vga/vgacore/Mcount_vcnt_cy[7] ; + wire \vga/vgacore/vcnt<7>/CYINIT_157 ; + wire \vga/vgacore/vcnt<7>/SRMUX_OUTPUTNOT ; + wire \vga/vgacore/Result<8>1 ; + wire \vga/vgacore/vcnt<7>/CKMUXNOT ; + wire \vga/vgacore/vcnt_Eqn_9 ; + wire \vga/vgacore/Result<9>1 ; + wire \vga/vgacore/vcnt<9>/CKMUXNOT ; + wire \vga/vgacore/vcnt<9>/CYINIT_158 ; + wire \vga/scancode_convert/scancode_rom/data<0>1437/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1529 ; + wire \vga/scancode_convert/scancode_rom/N9_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1526 ; + wire \vga/scancode_convert/scancode_rom/data<0>1539/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1831_pack_1 ; + wire N3085; + wire \vga/scancode_convert/_cmp_eq00041_SW0/O_pack_1 ; + wire \vga/scancode_convert/N10 ; + wire \vga/scancode_convert/scancode_rom/data<1>2465/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<2>1264/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1124 ; + wire \vga/scancode_convert/scancode_rom/data<2>1410/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<3>199/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1185 ; + wire \vga/scancode_convert/scancode_rom/data<4>1308_SW1/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1609 ; + wire \vga/scancode_convert/N31_pack_1 ; + wire \vga/scancode_convert/N11 ; + wire \vga/scancode_convert/scancode_rom/data<4>1392_SW0/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1669 ; + wire \vga/scancode_convert/scancode_rom/data<6>1247/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<5>3247/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1295 ; + wire \vga/scancode_convert/scancode_rom/N12_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1820 ; + wire \vga/scancode_convert/scancode_rom/data<5>3359/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1340 ; + wire \vga/scancode_convert/scancode_rom/data<6>1333/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1863 ; + wire \vga/scancode_convert/scancode_rom/data<5>3852_SW0/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1416 ; + wire \vga/scancode_convert/scancode_rom/data<5>3664/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1381 ; + wire \vga/scancode_convert/scancode_rom/data<5>3895_SW0/O_pack_1 ; + wire \vga/vgacore/N0_pack_1 ; + wire \vga/vgacore/vcnt_Eqn_bis_0 ; + wire \vga/scancode_convert/state_FFd2-In_SW0/O_pack_1 ; + wire \vga/scancode_convert/state_FFd2-In_159 ; + wire \vga/scancode_convert/state_FFd2/FFY/RST ; + wire \vga/scancode_convert/state_FFd3-In_SW0/O_pack_1 ; + wire \vga/scancode_convert/state_FFd3-In_160 ; + wire \vga/scancode_convert/state_FFd3/FFY/RST ; + wire \vga/crt/_and0000_SW0/O_pack_1 ; + wire \vga/crt/_and0000_161 ; + wire \vga/crt/eol_SW0/O_pack_1 ; + wire \vga/crt/eol_162 ; + wire \vga/scancode_convert/_cmp_eq0000_pack_1 ; + wire \vga/scancode_convert/_not0010 ; + wire \vga/crt/scroll_SW0/O_pack_1 ; + wire \vga/crt/scroll_163 ; + wire \vga/scancode_convert/state_FFd4-In24/O_pack_1 ; + wire \vga/scancode_convert/state_FFd4-In ; + wire \vga/scancode_convert/state_FFd4/FFY/RST ; + wire \vga/crt/_and0001_pack_1 ; + wire \vga/crt/cursor_v_Eqn_1 ; + wire \vga/crt/cursor_v<1>/FFY/RST ; + wire \vga/scancode_convert/scancode_rom/data<1>218/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1690 ; + wire \vga/scancode_convert/shift_set_map833_pack_1 ; + wire \vga/scancode_convert/_not0007_164 ; + wire \vga/scancode_convert/scancode_rom/data<3>126_SW1/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1158 ; + wire \vga/scancode_convert/scancode_rom/data<4>145/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1560 ; + wire \vga/scancode_convert/raise1_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1260 ; + wire \vga/scancode_convert/scancode_rom/N25_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1803 ; + wire \vga/_and000093/O_pack_1 ; + wire \vga/cursor_match ; + wire \vga/scancode_convert/scancode_rom/data<0>176/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1445 ; + wire \vga/scancode_convert/scancode_rom/data<0>1370_SW1/O_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1503 ; + wire \vga/scancode_convert/scancode_rom/N7_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1534 ; + wire \vga/crt/Madd_ram_addrR2 ; + wire \vga/crt/cursor_v_Eqn_0 ; + wire \vga/crt/cursor_v<0>/FFY/RST ; + wire \vga/crt/cursor_v_Eqn_3 ; + wire \vga/crt/cursor_v<3>/SRMUX_OUTPUTNOT ; + wire \vga/crt/cursor_v_Eqn_2 ; + wire \vga/crt/cursor_v_Eqn_5 ; + wire \vga/crt/cursor_v<5>/SRMUX_OUTPUTNOT ; + wire \vga/crt/cursor_v_Eqn_4 ; + wire \vga/crt/ram_data<1>/SRMUX_OUTPUTNOT ; + wire \vga/crt/ram_data<3>/SRMUX_OUTPUTNOT ; + wire \vga/crt/ram_data<5>/SRMUX_OUTPUTNOT ; + wire \vga/scancode_convert/_not0012 ; + wire \vga/scancode_convert/state_FFd1-In ; + wire \vga/scancode_convert/state_FFd1/FFY/RST ; + wire \vga/scancode_convert/state_FFd6/LOGIC_ZERO_165 ; + wire \vga/scancode_convert/_and0000 ; + wire \vga/scancode_convert/state_FFd6/SRMUX_OUTPUTNOT ; + wire \vga/scancode_convert/state_FFd5-In_166 ; + wire \vga/scancode_convert/capslock_toggle ; + wire \vga/scancode_convert/shift_set ; + wire \vga/scancode_convert/shift/FFY/RST ; + wire \vga/scancode_convert/shift_set_map836 ; + wire \vga/scancode_convert/release_prefix_set ; + wire \vga/scancode_convert/release_prefix/FFY/RST ; + wire \vga/ps2/timer_r<11>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/timer_r<13>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/timer_r<13>/FFX/RST ; + wire \vga/ps2/ps2_clk_fall_edge ; + wire \vga/ps2/error_x ; + wire \vga/ps2/error_r/FFY/RST ; + wire \vga/scancode_convert/hold_count<1>/SRMUX_OUTPUTNOT ; + wire \vga/scancode_convert/_not0011 ; + wire \vga/scancode_convert/hold_count<2>/FFY/RST ; + wire \vga/ps2/_cmp_eq0001_map1047 ; + wire \vga/ps2/timer_r<0>/FFY/RST ; + wire \vga/ps2/timer_r<3>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/timer_r<5>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/timer_r<7>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/timer_r<7>/FFX/RST ; + wire \vga/ps2/timer_r<9>/SRMUX_OUTPUTNOT ; + wire \vga/N226 ; + wire \vga/crt/write_delay<0>/FFY/RST ; + wire \vga/crt/write_delay<2>/FFY/RST ; + wire \vga/_cmp_eq0000 ; + wire \vga/charload/CKMUXNOT ; + wire \vga/charload/FFY/RST ; + wire \vga/crt/_not0010_pack_1 ; + wire \vga/crt/N3 ; + wire \vga/crt/newline/FFY/RST ; + wire \vga/pclk<1>/SRMUX_OUTPUTNOT ; + wire \vga/crt/cursor_h_Eqn_1 ; + wire \vga/crt/cursor_h<1>/SRMUX_OUTPUTNOT ; + wire \vga/crt/cursor_h_Eqn_0 ; + wire \vga/crt/cursor_h_Eqn_3 ; + wire \vga/crt/cursor_h<3>/SRMUX_OUTPUTNOT ; + wire \vga/crt/cursor_h_Eqn_2 ; + wire \vga/crt/cursor_h_Eqn_5 ; + wire \vga/crt/cursor_h<5>/SRMUX_OUTPUTNOT ; + wire \vga/crt/cursor_h_Eqn_4 ; + wire \vga/crt/cursor_h_Eqn_6 ; + wire \vga/crt/cursor_h<6>/FFY/RST ; + wire \vga/ps2/ps2_clk_r<2>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/ps2_clk_r<2>/FFY/SET ; + wire \vga/ps2/ps2_clk_r<4>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/ps2_clk_r<4>/FFY/SET ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1129 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1708 ; + wire N3178; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1717 ; + wire N3136; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1729 ; + wire \vga/scancode_convert/_cmp_eq0005_pack_1 ; + wire N124; + wire \vga/crt/_not0007 ; + wire \vga/crt/_not0006 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1449 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1121 ; + wire N235; + wire \vga/crt/_not0008 ; + wire \vga/N224 ; + wire \vga/N13 ; + wire \vga/N14_pack_1 ; + wire \vga/rom_addr_char<2>11_167 ; + wire \vga/N222 ; + wire \vga/N23 ; + wire \vga/N221 ; + wire \vga/N15 ; + wire \vga/N219 ; + wire \vga/N24 ; + wire \vga/N218 ; + wire \vga/N16 ; + wire \vga/N104 ; + wire \vga/N33 ; + wire \vga/N216 ; + wire \vga/N25 ; + wire \vga/N215 ; + wire \vga/N17 ; + wire \vga/N102 ; + wire \vga/N34 ; + wire \vga/N214 ; + wire \vga/N26 ; + wire \vga/N101 ; + wire \vga/N43 ; + wire \vga/N99 ; + wire \vga/N35 ; + wire \vga/N213 ; + wire \vga/N27 ; + wire \vga/N98 ; + wire \vga/N44 ; + wire \vga/N208 ; + wire \vga/N28 ; + wire \vga/N205 ; + wire \vga/N20 ; + wire \vga/N96 ; + wire \vga/N54 ; + wire \vga/N95 ; + wire \vga/N45 ; + wire \vga/N94 ; + wire \vga/N37 ; + wire \vga/N31 ; + wire \vga/N29 ; + wire \vga/N201 ; + wire \vga/N21 ; + wire N3166; + wire \vga/N55 ; + wire \vga/N90 ; + wire \vga/N47 ; + wire \vga/N89 ; + wire \vga/N38 ; + wire N3146; + wire \vga/N30 ; + wire \vga/N194 ; + wire \vga/N22 ; + wire \vga/N88 ; + wire \vga/N64 ; + wire \vga/N87 ; + wire \vga/N56 ; + wire \vga/N86 ; + wire \vga/N48 ; + wire \vga/N85 ; + wire \vga/N39 ; + wire \vga/N83 ; + wire \vga/N65 ; + wire \vga/N82 ; + wire \vga/N57 ; + wire \vga/N81 ; + wire \vga/N49 ; + wire \vga/N80 ; + wire \vga/N40 ; + wire \vga/N79 ; + wire \vga/N32 ; + wire N3162_pack_1; + wire \vga/rom_addr_char<2>2 ; + wire \vga/N78 ; + wire \vga/N74 ; + wire \vga/N75 ; + wire \vga/N66 ; + wire \vga/N73 ; + wire \vga/N58 ; + wire \vga/N72 ; + wire \vga/N50 ; + wire \vga/N71 ; + wire \vga/N41 ; + wire \vga/N70 ; + wire \vga/N67 ; + wire \vga/N69 ; + wire \vga/N59 ; + wire \vga/N63 ; + wire \vga/N68 ; + wire \vga/N62 ; + wire \vga/N60 ; + wire N3164; + wire \vga/N61 ; + wire \vga/N11 ; + wire \vga/N53 ; + wire N3158_pack_1; + wire \vga/scancode_convert/ctrl_set_168 ; + wire \vga/scancode_convert/ctrl/FFY/RST ; + wire N3142; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1565 ; + wire \vga/N193 ; + wire \vga/N105 ; + wire \vga/N192 ; + wire \vga/N106 ; + wire \vga/N191 ; + wire \vga/N115 ; + wire \vga/N190 ; + wire \vga/N116 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1808 ; + wire N3141; + wire \vga/N186 ; + wire \vga/N125 ; + wire \vga/N184 ; + wire \vga/N117 ; + wire \vga/N183 ; + wire \vga/N126 ; + wire \vga/N179 ; + wire \vga/N118 ; + wire \vga/N178 ; + wire \vga/N110 ; + wire \vga/N176 ; + wire \vga/N127 ; + wire \vga/N175 ; + wire \vga/N111 ; + wire \vga/N172 ; + wire \vga/N137 ; + wire \vga/N171 ; + wire \vga/N128 ; + wire \vga/N170 ; + wire \vga/N120 ; + wire \vga/N167 ; + wire \vga/N146 ; + wire \vga/N159 ; + wire \vga/N138 ; + wire \vga/N157 ; + wire \vga/N129 ; + wire \vga/N155 ; + wire \vga/N121 ; + wire \vga/N152 ; + wire \vga/N113 ; + wire N3174; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1276 ; + wire \vga/scancode_convert/key_up/FFY/RST ; + wire \vga/N151 ; + wire \vga/N147 ; + wire \vga/N150 ; + wire \vga/N139 ; + wire \vga/N149 ; + wire \vga/N130 ; + wire \vga/N145 ; + wire \vga/N114 ; + wire \vga/N144 ; + wire \vga/N131 ; + wire \vga/N143 ; + wire \vga/N132 ; + wire \vga/N134 ; + wire \vga/N142 ; + wire \vga/N2 ; + wire \vga/N133 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1475 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1363 ; + wire N3124; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1850 ; + wire \vga/crt/N9 ; + wire \vga/crt/Madd_ram_addrC2_pack_1 ; + wire \vga/ram_addr_write<7>/CYMUXG ; + wire \vga/ram_addr_write<7>/LOGIC_ONE_169 ; + wire \vga/crt/Madd_ram_addr_Madd_cy<7>_rt_170 ; + wire \vga/ram_addr_write<7>/CYINIT_171 ; + wire \vga/scancode_convert/raise_pack_1 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1438 ; + wire \vga/scancode_convert/scancode_rom/N43 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1394 ; + wire N562_pack_1; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1701 ; + wire N3130; + wire \vga/crt/_cmp_eq0004_pack_1 ; + wire \vga/crt/write_delay<1>/FFY/RST ; + wire \vga/clearing_pack_1 ; + wire \vga/_mux0000 ; + wire \gray_cnt_FFd11/SRMUX_OUTPUTNOT ; + wire \gray_cnt_FFd11/BYMUXNOT ; + wire \gray_cnt_FFd11/FFY/RST ; + wire \vga/ram_we_n_pack_1 ; + wire \vga/scancode_convert/capslock/BYMUXNOT ; + wire \vga/scancode_convert/capslock/FFY/RST ; + wire \vga/N230 ; + wire \vga/Madd_ram_addr_videoC2_pack_1 ; + wire \vga/ram_addr_video<7>/CYMUXG ; + wire \vga/ram_addr_video<7>/LOGIC_ONE_172 ; + wire \vga/Madd_ram_addr_video_Madd_cy<7>_rt_173 ; + wire \vga/ram_addr_video<7>/CYINIT_174 ; + wire N839; + wire \vga/Madd_ram_addr_videoR2 ; + wire \vga/ps2/ps2_clk_edge_pack_1 ; + wire \vga/ps2/timer_r<1>/FFY/RST ; + wire \vga/ps2/error_x_map855 ; + wire \vga/ps2/_cmp_eq0000 ; + wire \vga/ps2/_cmp_eq0001_map1032 ; + wire \vga/vgacore/_and0000_map807_pack_1 ; + wire \vga/vgacore/_and0000_map811 ; + wire \vga/vgacore/vcnt_1_1/CKMUXNOT ; + wire \vga/vgacore/vcnt_1_1/FFY/RST ; + wire \vga/vgacore/vcnt_2_1/CKMUXNOT ; + wire \vga/vgacore/vcnt_2_1/FFY/RST ; + wire \vga/scancode_convert/_not0009 ; + wire \vga/N0112_pack_1 ; + wire \vga/charload3_map953 ; + wire \vga/N011234567_pack_1 ; + wire \vga/rom_addr_char<4>11234 ; + wire \vga/charload7_map993 ; + wire \vga/rom_addr_char<4>11_175 ; + wire \vga/scancode_convert/strobe_out/FFY/RST ; + wire \vga/N4_pack_1 ; + wire \vga/N1112 ; + wire \vga/N10 ; + wire \vga/N6 ; + wire N3170; + wire \vga/N7 ; + wire \vga/N8_pack_1 ; + wire \vga/N11123 ; + wire N3160; + wire \vga/N12 ; + wire \vga/crt/N91_pack_1 ; + wire \vga/crt/state_FFd3-In_map800_pack_1 ; + wire \vga/crt/state_FFd3-In ; + wire \vga/crt/state_FFd3/FFY/RST ; + wire \vga/insert_crt_data_pack_1 ; + wire N116; + wire N117_pack_1; + wire \vga/crt/state_FFd1-In_176 ; + wire \vga/crt/state_FFd1/FFY/RST ; + wire \vga/crt/N16_pack_1 ; + wire N306; + wire \vga/rom_addr_char<1>/CKMUXNOT ; + wire \vga/rom_addr_char<3>/CKMUXNOT ; + wire \vga/rom_addr_char<5>/CKMUXNOT ; + wire \vga/rom_addr_char<6>/CKMUXNOT ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1461 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1429 ; + wire \vga/scancode_convert/scancode_rom/N28 ; + wire \vga/scancode_convert/scancode_rom/N18 ; + wire \vga/ps2/sc_r<1>/FFX/RST ; + wire \vga/ps2/sc_r<1>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/sc_r<1>/FFY/RST ; + wire \vga/ps2/sc_r<3>/FFX/RST ; + wire \vga/ps2/sc_r<3>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/sc_r<3>/FFY/RST ; + wire \vga/ps2/sc_r<5>/FFX/RST ; + wire \vga/ps2/sc_r<5>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/sc_r<5>/FFY/RST ; + wire \vga/ps2/sc_r<7>/FFX/RST ; + wire \vga/ps2/sc_r<7>/SRMUX_OUTPUTNOT ; + wire \vga/ps2/sc_r<7>/FFY/RST ; + wire \vga/ps2/sc_r<8>/FFY/RST ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1245 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1249 ; + wire N786; + wire N3108; + wire \vga/_and0000_map918 ; + wire \vga/scancode_convert/_or0000 ; + wire \vga/charload6_map1022_pack_1 ; + wire \vga/_and0000_map929 ; + wire \vga/pixelData<0>/SRMUX_OUTPUTNOT ; + wire \vga/pixelData<0>/LOGIC_ONE_177 ; + wire \vga/ps2/_cmp_eq0001_map1035 ; + wire \vga/_and0000_map940 ; + wire \vga/_and0000_map941_pack_1 ; + wire \vga/_and0000_map943 ; + wire \vga/ps2/_cmp_eq0001_map1041 ; + wire \vga/rom_addr_char_0_1/CKMUXNOT ; + wire \vga/rom_addr_char_1_1/CKMUXNOT ; + wire \vga/ps2/_cmp_eq0001_pack_1 ; + wire \vga/ps2/scancode_rdy ; + wire \vga/ps2/rdy_r/FFY/RST ; + wire \vga/crt/_cmp_eq0001 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1423 ; + wire N3132; + wire \vga/vgacore/_and0000_map817 ; + wire \vga/_and0000_map879 ; + wire \vga/vgacore/_and0000_map824 ; + wire \vga/vgacore/_and0000_map825_pack_1 ; + wire \vga/vgacore/_and0000 ; + wire \vga/vgacore/hsync/FFY/RST ; + wire \vga/charload5_map965 ; + wire \vga/charload4_map979 ; + wire N3172; + wire N3148; + wire \vga/_and0000_map890 ; + wire \vga/charload6_map1010_pack_1 ; + wire \vga/charload6_map1012 ; + wire \vga/charload6_map1014_pack_1 ; + wire \vga/charload6_map1018 ; + wire \vga/crtclk1/BYMUXNOT ; + wire \vga/crtclk1/FFY/RST ; + wire \vga/crt_data<1>/SRMUX_OUTPUTNOT ; + wire \vga/crt_data<1>/FFY/RST ; + wire \vga/crt_data<3>/SRMUX_OUTPUTNOT ; + wire \vga/crt_data<3>/FFY/RST ; + wire \vga/crt_data<5>/SRMUX_OUTPUTNOT ; + wire \vga/crt_data<5>/FFY/RST ; + wire \vga/crt_data<6>/FFY/RST ; + wire \vga/vgacore/hcnt_Eqn_0_mand1 ; + wire \vga/vgacore/hcnt_Eqn_bis_0_pack_1 ; + wire \vga/vgacore/hcnt<0>/CYMUXG ; + wire \vga/vgacore/hcnt<0>/LOGIC_ONE_178 ; + wire \vga/vgacore/Mcount_hcnt_cy<0>_rt_179 ; + wire \vga/vgacore/hcnt<0>/LOGIC_ZERO_180 ; + wire \vga/vgacore/hcnt<0>/FFX/RST ; + wire N3100; + wire N44_pack_1; + wire \vga/vgacore/_and0001_181 ; + wire \vga/vgacore/vsync/FFY/RST ; + wire N89_pack_1; + wire \vga/pclk<2>/FFY/SET ; + wire \vga/vgacore/hblank/FFY/RST ; + wire \vga/vgacore/hcnt<1>/FFY/RST ; + wire \vga/vgacore/hcnt<3>/FFY/RST ; + wire \vga/vgacore/hcnt<5>/FFY/RST ; + wire \vga/vgacore/hcnt<7>/FFY/RST ; + wire \vga/vgacore/hcnt<9>/FFY/RST ; + wire \vga/vgacore/vcnt<0>/FFY/RST ; + wire \vga/vgacore/vcnt<1>/FFY/RST ; + wire \vga/vgacore/vcnt<3>/FFY/RST ; + wire \vga/vgacore/vcnt<5>/FFY/RST ; + wire \vga/vgacore/vcnt<7>/FFY/RST ; + wire \vga/crt/cursor_v<3>/FFY/RST ; + wire \vga/crt/cursor_v<5>/FFY/RST ; + wire \vga/crt/ram_data<1>/FFY/RST ; + wire \vga/crt/ram_data<3>/FFY/RST ; + wire \vga/crt/ram_data<5>/FFY/RST ; + wire \vga/scancode_convert/state_FFd6/FFY/RST ; + wire \vga/ps2/timer_r<11>/FFY/RST ; + wire \vga/ps2/timer_r<13>/FFY/RST ; + wire \vga/scancode_convert/hold_count<1>/FFY/RST ; + wire \vga/ps2/timer_r<3>/FFY/RST ; + wire \vga/ps2/timer_r<5>/FFY/RST ; + wire \vga/ps2/timer_r<7>/FFY/RST ; + wire \vga/ps2/timer_r<9>/FFY/RST ; + wire \vga/pclk<1>/FFY/SET ; + wire \vga/crt/cursor_h<1>/FFY/RST ; + wire \vga/crt/cursor_h<3>/FFY/RST ; + wire \vga/crt/cursor_h<5>/FFY/RST ; + wire \vga/ram_wclk/FFY/RST ; + wire \vga/crt/ram_data<6>/FFY/RST ; + wire \ps2_clk/IFF/SET ; + wire \ps2_data/IFF/RST ; + wire \vga/crt/state_FFd2/FFX/RST ; + wire \vga/vgacore/hcnt<3>/FFX/RST ; + wire \vga/vgacore/hcnt<5>/FFX/RST ; + wire \vga/vgacore/hcnt<7>/FFX/RST ; + wire \vga/vgacore/vcnt<1>/FFX/RST ; + wire \vga/vgacore/vcnt<3>/FFX/RST ; + wire \vga/vgacore/vcnt<5>/FFX/RST ; + wire \vga/vgacore/vcnt<7>/FFX/RST ; + wire \vga/vgacore/vcnt<9>/FFX/RST ; + wire \vga/crt/cursor_v<3>/FFX/RST ; + wire \vga/crt/cursor_v<5>/FFX/RST ; + wire \vga/crt/ram_data<1>/FFX/RST ; + wire \vga/crt/ram_data<3>/FFX/RST ; + wire \vga/crt/ram_data<5>/FFX/RST ; + wire \vga/scancode_convert/state_FFd6/FFX/SET ; + wire \vga/ps2/timer_r<11>/FFX/RST ; + wire \vga/scancode_convert/hold_count<1>/FFX/RST ; + wire \vga/ps2/timer_r<3>/FFX/RST ; + wire \vga/ps2/timer_r<5>/FFX/RST ; + wire \vga/ps2/timer_r<9>/FFX/RST ; + wire \vga/pclk<1>/FFX/SET ; + wire \vga/crt/cursor_h<1>/FFX/RST ; + wire \vga/crt/cursor_h<3>/FFX/RST ; + wire \vga/crt/cursor_h<5>/FFX/RST ; + wire \vga/ps2/ps2_clk_r<2>/FFX/SET ; + wire \vga/ps2/ps2_clk_r<4>/FFX/SET ; + wire \gray_cnt_FFd11/FFX/RST ; + wire \vga/crt_data<1>/FFX/RST ; + wire \vga/crt_data<3>/FFX/RST ; + wire \vga/crt_data<5>/FFX/RST ; + wire GND; + wire VCC; + wire \NLW_vga/vgacore/Mcount_vcnt_cy<0>_rt_IA_UNCONNECTED ; + wire \NLW_vga/crt/Madd_ram_addr_Madd_cy<7>_rt_IA_UNCONNECTED ; + wire \NLW_vga/Madd_ram_addr_video_Madd_cy<7>_rt_IA_UNCONNECTED ; + wire \NLW_vga/vgacore/Mcount_hcnt_cy<0>_rt_IA_UNCONNECTED ; + wire [4 : 0] \vga/ps2/ps2_clk_r ; + wire [6 : 0] \vga/scancode_convert/ascii ; + wire [9 : 0] \vga/ps2/sc_r ; + wire [2 : 0] \vga/pclk ; + wire [11 : 0] \vga/video_ram/ram_addr_w ; + wire [6 : 0] \vga/crt/ram_data ; + wire [6 : 0] \vga/ram_data_out ; + wire [6 : 0] \vga/scancode_convert/sc ; + wire [6 : 0] \vga/rom_addr_char ; + wire [9 : 0] \vga/vgacore/vcnt ; + wire [3 : 0] \vga/ps2/bitcnt_r ; + wire [7 : 0] \vga/pixel_hold ; + wire [6 : 0] \vga/crt/cursor_h ; + wire [5 : 0] \vga/crt/cursor_v ; + wire [10 : 0] \vga/vgacore/hcnt ; + wire [13 : 0] \vga/ps2/timer_r ; + wire [6 : 0] \vga/crt_data ; + wire [2 : 0] \vga/scancode_convert/hold_count ; + wire [2 : 0] \vga/crt/write_delay ; + wire [0 : 0] \vga/pixelData ; + wire [5 : 0] \vga/scancode_convert/rom_data ; + wire [3 : 0] \vga/ps2/bitcnt_x ; + wire [7 : 0] \vga/_mux0002 ; + wire [11 : 0] \vga/ram_addr_mux ; + wire [11 : 5] \vga/ram_addr_write ; + wire [11 : 5] \vga/ram_addr_video ; + wire [13 : 1] \vga/ps2/_addsub0000 ; + wire [6 : 0] \vga/crt/Result ; + wire [10 : 0] \vga/vgacore/Result ; + wire [6 : 6] \vga/scancode_convert/_mux0008 ; + wire [6 : 0] \vga/crt/_mux0002 ; + wire [13 : 0] \vga/ps2/timer_x ; + wire [2 : 0] \vga/scancode_convert/hold_count__mux0000 ; + wire [2 : 0] \vga/crt/write_delay__mux0000 ; + wire [2 : 0] \vga/pclk__mux0000 ; + wire [8 : 8] pixel; + initial $sdf_annotate("netgen/par/fpga_timesim.sdf"); + defparam \ps2_clk/PAD .LOC = "PAD309"; + X_IPAD \ps2_clk/PAD ( + .PAD(ps2_clk) + ); + defparam ps2_clk_IBUF.LOC = "PAD309"; + X_BUF ps2_clk_IBUF ( + .I(ps2_clk), + .O(ps2_clk_IBUF_37) + ); + defparam \ps2_clk/DELAY .LOC = "PAD309"; + X_BUF \ps2_clk/DELAY ( + .I(ps2_clk_IBUF_37), + .O(\ps2_clk/IDELAY ) + ); + defparam \fpga_d1/PAD .LOC = "PAD106"; + X_OPAD \fpga_d1/PAD ( + .PAD(fpga_d1) + ); + defparam fpga_d1_OBUF.LOC = "PAD106"; + X_OBUF fpga_d1_OBUF ( + .I(\fpga_d1/OUTMUX_38 ), + .O(fpga_d1) + ); + defparam \fpga_d1/OUTMUX .LOC = "PAD106"; + X_BUF \fpga_d1/OUTMUX ( + .I(\vga/ps2/rdy_r_1 ), + .O(\fpga_d1/OUTMUX_38 ) + ); + defparam \fpga_d2/PAD .LOC = "PAD107"; + X_OPAD \fpga_d2/PAD ( + .PAD(fpga_d2) + ); + defparam fpga_d2_OBUF.LOC = "PAD107"; + X_OBUF fpga_d2_OBUF ( + .I(\fpga_d2/OUTMUX_39 ), + .O(fpga_d2) + ); + defparam \fpga_d2/OUTMUX .LOC = "PAD107"; + X_BUF \fpga_d2/OUTMUX ( + .I(\vga/scancode_convert/ascii [5]), + .O(\fpga_d2/OUTMUX_39 ) + ); + defparam \fpga_d3/PAD .LOC = "PAD118"; + X_OPAD \fpga_d3/PAD ( + .PAD(fpga_d3) + ); + defparam fpga_d3_OBUF.LOC = "PAD118"; + X_OBUF fpga_d3_OBUF ( + .I(\fpga_d3/OUTMUX_40 ), + .O(fpga_d3) + ); + defparam \fpga_d3/OUTMUX .LOC = "PAD118"; + X_BUF \fpga_d3/OUTMUX ( + .I(\vga/scancode_convert/ascii [4]), + .O(\fpga_d3/OUTMUX_40 ) + ); + defparam \fpga_d4/PAD .LOC = "PAD135"; + X_OPAD \fpga_d4/PAD ( + .PAD(fpga_d4) + ); + defparam fpga_d4_OBUF.LOC = "PAD135"; + X_OBUF fpga_d4_OBUF ( + .I(\fpga_d4/OUTMUX_41 ), + .O(fpga_d4) + ); + defparam \fpga_d4/OUTMUX .LOC = "PAD135"; + X_BUF \fpga_d4/OUTMUX ( + .I(\vga/scancode_convert/ascii [3]), + .O(\fpga_d4/OUTMUX_41 ) + ); + defparam \fpga_d5/PAD .LOC = "PAD146"; + X_OPAD \fpga_d5/PAD ( + .PAD(fpga_d5) + ); + defparam fpga_d5_OBUF.LOC = "PAD146"; + X_OBUF fpga_d5_OBUF ( + .I(\fpga_d5/OUTMUX_42 ), + .O(fpga_d5) + ); + defparam \fpga_d5/OUTMUX .LOC = "PAD146"; + X_BUF \fpga_d5/OUTMUX ( + .I(\vga/scancode_convert/ascii [2]), + .O(\fpga_d5/OUTMUX_42 ) + ); + defparam \fpga_d6/PAD .LOC = "PAD147"; + X_OPAD \fpga_d6/PAD ( + .PAD(fpga_d6) + ); + defparam fpga_d6_OBUF.LOC = "PAD147"; + X_OBUF fpga_d6_OBUF ( + .I(\fpga_d6/OUTMUX_43 ), + .O(fpga_d6) + ); + defparam \fpga_d6/OUTMUX .LOC = "PAD147"; + X_BUF \fpga_d6/OUTMUX ( + .I(\vga/scancode_convert/ascii [1]), + .O(\fpga_d6/OUTMUX_43 ) + ); + defparam \fpga_d7/PAD .LOC = "PAD167"; + X_OPAD \fpga_d7/PAD ( + .PAD(fpga_d7) + ); + defparam fpga_d7_OBUF.LOC = "PAD167"; + X_OBUF fpga_d7_OBUF ( + .I(\fpga_d7/OUTMUX_44 ), + .O(fpga_d7) + ); + defparam \fpga_d7/OUTMUX .LOC = "PAD167"; + X_BUF \fpga_d7/OUTMUX ( + .I(\vga/scancode_convert/ascii [0]), + .O(\fpga_d7/OUTMUX_44 ) + ); + defparam \ps2_data/PAD .LOC = "PAD315"; + X_IPAD \ps2_data/PAD ( + .PAD(ps2_data) + ); + defparam ps2_data_IBUF.LOC = "PAD315"; + X_BUF ps2_data_IBUF ( + .I(ps2_data), + .O(ps2_data_IBUF_45) + ); + defparam \ps2_data/DELAY .LOC = "PAD315"; + X_BUF \ps2_data/DELAY ( + .I(ps2_data_IBUF_45), + .O(\ps2_data/IDELAY ) + ); + defparam \fpga_din_d0/PAD .LOC = "PAD86"; + X_OPAD \fpga_din_d0/PAD ( + .PAD(fpga_din_d0) + ); + defparam fpga_din_d0_OBUF.LOC = "PAD86"; + X_OBUF fpga_din_d0_OBUF ( + .I(\fpga_din_d0/OUTMUX_46 ), + .O(fpga_din_d0) + ); + defparam \fpga_din_d0/OUTMUX .LOC = "PAD86"; + X_BUF \fpga_din_d0/OUTMUX ( + .I(\vga/scancode_convert/ascii [6]), + .O(\fpga_din_d0/OUTMUX_46 ) + ); + defparam \vga_blue0/PAD .LOC = "PAD296"; + X_OPAD \vga_blue0/PAD ( + .PAD(vga_blue0) + ); + defparam vga_blue0_OBUF.LOC = "PAD296"; + X_OBUF vga_blue0_OBUF ( + .I(\vga_blue0/OUTMUX_47 ), + .O(vga_blue0) + ); + defparam \vga_blue0/OUTMUX .LOC = "PAD296"; + X_BUF \vga_blue0/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_blue0/OUTMUX_47 ) + ); + defparam \vga_blue1/PAD .LOC = "PAD279"; + X_OPAD \vga_blue1/PAD ( + .PAD(vga_blue1) + ); + defparam vga_blue1_OBUF.LOC = "PAD279"; + X_OBUF vga_blue1_OBUF ( + .I(\vga_blue1/OUTMUX_48 ), + .O(vga_blue1) + ); + defparam \vga_blue1/OUTMUX .LOC = "PAD279"; + X_BUF \vga_blue1/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_blue1/OUTMUX_48 ) + ); + defparam \vga_vsync_n/PAD .LOC = "PAD280"; + X_OPAD \vga_vsync_n/PAD ( + .PAD(vga_vsync_n) + ); + defparam vga_vsync_n_OBUF.LOC = "PAD280"; + X_OBUF vga_vsync_n_OBUF ( + .I(\vga_vsync_n/OUTMUX_49 ), + .O(vga_vsync_n) + ); + defparam \vga_vsync_n/OUTMUX .LOC = "PAD280"; + X_INV \vga_vsync_n/OUTMUX ( + .I(\vga/vgacore/vsync_2 ), + .O(\vga_vsync_n/OUTMUX_49 ) + ); + defparam \vga_blue2/PAD .LOC = "PAD263"; + X_OPAD \vga_blue2/PAD ( + .PAD(vga_blue2) + ); + defparam vga_blue2_OBUF.LOC = "PAD263"; + X_OBUF vga_blue2_OBUF ( + .I(\vga_blue2/OUTMUX_50 ), + .O(vga_blue2) + ); + defparam \vga_blue2/OUTMUX .LOC = "PAD263"; + X_BUF \vga_blue2/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_blue2/OUTMUX_50 ) + ); + defparam \vga_hsync_n/PAD .LOC = "PAD274"; + X_OPAD \vga_hsync_n/PAD ( + .PAD(vga_hsync_n) + ); + defparam vga_hsync_n_OBUF.LOC = "PAD274"; + X_OBUF vga_hsync_n_OBUF ( + .I(\vga_hsync_n/OUTMUX_51 ), + .O(vga_hsync_n) + ); + defparam \vga_hsync_n/OUTMUX .LOC = "PAD274"; + X_INV \vga_hsync_n/OUTMUX ( + .I(\vga/vgacore/hsync_3 ), + .O(\vga_hsync_n/OUTMUX_51 ) + ); + defparam \vga_red0/PAD .LOC = "PAD286"; + X_OPAD \vga_red0/PAD ( + .PAD(vga_red0) + ); + defparam vga_red0_OBUF.LOC = "PAD286"; + X_OBUF vga_red0_OBUF ( + .I(\vga_red0/OUTMUX_52 ), + .O(vga_red0) + ); + defparam \vga_red0/OUTMUX .LOC = "PAD286"; + X_BUF \vga_red0/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_red0/OUTMUX_52 ) + ); + defparam \vga_red1/PAD .LOC = "PAD273"; + X_OPAD \vga_red1/PAD ( + .PAD(vga_red1) + ); + defparam vga_red1_OBUF.LOC = "PAD273"; + X_OBUF vga_red1_OBUF ( + .I(\vga_red1/OUTMUX_53 ), + .O(vga_red1) + ); + defparam \vga_red1/OUTMUX .LOC = "PAD273"; + X_BUF \vga_red1/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_red1/OUTMUX_53 ) + ); + defparam \vga_red2/PAD .LOC = "PAD246"; + X_OPAD \vga_red2/PAD ( + .PAD(vga_red2) + ); + defparam vga_red2_OBUF.LOC = "PAD246"; + X_OBUF vga_red2_OBUF ( + .I(\vga_red2/OUTMUX_54 ), + .O(vga_red2) + ); + defparam \vga_red2/OUTMUX .LOC = "PAD246"; + X_BUF \vga_red2/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_red2/OUTMUX_54 ) + ); + defparam \reset_n/PAD .LOC = "PAD326"; + X_IPAD \reset_n/PAD ( + .PAD(reset_n) + ); + defparam \reset_n/IMUX .LOC = "PAD326"; + X_BUF \reset_n/IMUX ( + .I(reset_n_IBUF_55), + .O(reset_n_IBUF_0) + ); + defparam reset_n_IBUF.LOC = "PAD326"; + X_BUF reset_n_IBUF ( + .I(reset_n), + .O(reset_n_IBUF_55) + ); + defparam \vga_green0/PAD .LOC = "PAD300"; + X_OPAD \vga_green0/PAD ( + .PAD(vga_green0) + ); + defparam vga_green0_OBUF.LOC = "PAD300"; + X_OBUF vga_green0_OBUF ( + .I(\vga_green0/OUTMUX_56 ), + .O(vga_green0) + ); + defparam \vga_green0/OUTMUX .LOC = "PAD300"; + X_BUF \vga_green0/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_green0/OUTMUX_56 ) + ); + defparam \vga_green1/PAD .LOC = "PAD284"; + X_OPAD \vga_green1/PAD ( + .PAD(vga_green1) + ); + defparam vga_green1_OBUF.LOC = "PAD284"; + X_OBUF vga_green1_OBUF ( + .I(\vga_green1/OUTMUX_57 ), + .O(vga_green1) + ); + defparam \vga_green1/OUTMUX .LOC = "PAD284"; + X_BUF \vga_green1/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_green1/OUTMUX_57 ) + ); + defparam \vga_green2/PAD .LOC = "PAD254"; + X_OPAD \vga_green2/PAD ( + .PAD(vga_green2) + ); + defparam vga_green2_OBUF.LOC = "PAD254"; + X_OBUF vga_green2_OBUF ( + .I(\vga_green2/OUTMUX_58 ), + .O(vga_green2) + ); + defparam \vga_green2/OUTMUX .LOC = "PAD254"; + X_BUF \vga_green2/OUTMUX ( + .I(\pixel<8>_0 ), + .O(\vga_green2/OUTMUX_58 ) + ); + defparam \vga/inst_Mram_mem11/LOGIC_ONE .LOC = "RAMB4_R4C0"; + X_ONE \vga/inst_Mram_mem11/LOGIC_ONE ( + .O(\vga/inst_Mram_mem11/LOGIC_ONE_60 ) + ); + defparam \vga/inst_Mram_mem11/LOGIC_ZERO .LOC = "RAMB4_R4C0"; + X_ZERO \vga/inst_Mram_mem11/LOGIC_ZERO ( + .O(\vga/inst_Mram_mem11/LOGIC_ZERO_59 ) + ); + defparam \vga/inst_Mram_mem11/CLKBMUX .LOC = "RAMB4_R4C0"; + X_INV \vga/inst_Mram_mem11/CLKBMUX ( + .I(\vga/pclk [2]), + .O(\vga/inst_Mram_mem11/CLKB_INTNOT ) + ); + defparam \vga/inst_Mram_mem11 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem11 .LOC = "RAMB4_R4C0"; + defparam \vga/inst_Mram_mem11 .SETUP_ALL = 3737; + X_RAMB4_S1_S1 \vga/inst_Mram_mem11 ( + .CLKA(\vga/ram_wclk_5 ), + .CLKB(\vga/inst_Mram_mem11/CLKB_INTNOT ), + .ENA(\vga/inst_Mram_mem11/LOGIC_ONE_60 ), + .ENB(\vga/inst_Mram_mem11/LOGIC_ONE_60 ), + .RSTA(\vga/inst_Mram_mem11/LOGIC_ZERO_59 ), + .RSTB(\vga/inst_Mram_mem11/LOGIC_ZERO_59 ), + .WEA(\vga/N226_0 ), + .WEB(\vga/inst_Mram_mem11/LOGIC_ZERO_59 ), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux<11>_0 , \vga/ram_addr_mux<10>_0 , \vga/ram_addr_mux<9>_0 , \vga/ram_addr_mux<8>_0 , \vga/ram_addr_mux<7>_0 , +\vga/ram_addr_mux<6>_0 , \vga/ram_addr_mux<5>_0 , \vga/ram_addr_mux<4>_0 , \vga/ram_addr_mux<3>_0 , \vga/ram_addr_mux<2>_0 , \vga/ram_addr_mux<1>_0 , +\vga/ram_addr_mux<0>_0 }), + .DIA({\vga/crt/ram_data [1]}), + .DIB({\vga/inst_Mram_mem11/DIB0 }), + .DOA({\vga/inst_Mram_mem11/DOA0 }), + .DOB({\vga/ram_data_out [1]}) + ); + defparam \vga/inst_Mram_mem21/LOGIC_ONE .LOC = "RAMB4_R5C0"; + X_ONE \vga/inst_Mram_mem21/LOGIC_ONE ( + .O(\vga/inst_Mram_mem21/LOGIC_ONE_62 ) + ); + defparam \vga/inst_Mram_mem21/LOGIC_ZERO .LOC = "RAMB4_R5C0"; + X_ZERO \vga/inst_Mram_mem21/LOGIC_ZERO ( + .O(\vga/inst_Mram_mem21/LOGIC_ZERO_61 ) + ); + defparam \vga/inst_Mram_mem21/CLKBMUX .LOC = "RAMB4_R5C0"; + X_INV \vga/inst_Mram_mem21/CLKBMUX ( + .I(\vga/pclk [2]), + .O(\vga/inst_Mram_mem21/CLKB_INTNOT ) + ); + defparam \vga/inst_Mram_mem21 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem21 .LOC = "RAMB4_R5C0"; + defparam \vga/inst_Mram_mem21 .SETUP_ALL = 3737; + X_RAMB4_S1_S1 \vga/inst_Mram_mem21 ( + .CLKA(\vga/ram_wclk_5 ), + .CLKB(\vga/inst_Mram_mem21/CLKB_INTNOT ), + .ENA(\vga/inst_Mram_mem21/LOGIC_ONE_62 ), + .ENB(\vga/inst_Mram_mem21/LOGIC_ONE_62 ), + .RSTA(\vga/inst_Mram_mem21/LOGIC_ZERO_61 ), + .RSTB(\vga/inst_Mram_mem21/LOGIC_ZERO_61 ), + .WEA(\vga/N226_0 ), + .WEB(\vga/inst_Mram_mem21/LOGIC_ZERO_61 ), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux<11>_0 , \vga/ram_addr_mux<10>_0 , \vga/ram_addr_mux<9>_0 , \vga/ram_addr_mux<8>_0 , \vga/ram_addr_mux<7>_0 , +\vga/ram_addr_mux<6>_0 , \vga/ram_addr_mux<5>_0 , \vga/ram_addr_mux<4>_0 , \vga/ram_addr_mux<3>_0 , \vga/ram_addr_mux<2>_0 , \vga/ram_addr_mux<1>_0 , +\vga/ram_addr_mux<0>_0 }), + .DIA({\vga/crt/ram_data [2]}), + .DIB({\vga/inst_Mram_mem21/DIB0 }), + .DOA({\vga/inst_Mram_mem21/DOA0 }), + .DOB({\vga/ram_data_out [2]}) + ); + defparam \vga/inst_Mram_mem31/LOGIC_ONE .LOC = "RAMB4_R6C0"; + X_ONE \vga/inst_Mram_mem31/LOGIC_ONE ( + .O(\vga/inst_Mram_mem31/LOGIC_ONE_64 ) + ); + defparam \vga/inst_Mram_mem31/LOGIC_ZERO .LOC = "RAMB4_R6C0"; + X_ZERO \vga/inst_Mram_mem31/LOGIC_ZERO ( + .O(\vga/inst_Mram_mem31/LOGIC_ZERO_63 ) + ); + defparam \vga/inst_Mram_mem31/CLKBMUX .LOC = "RAMB4_R6C0"; + X_INV \vga/inst_Mram_mem31/CLKBMUX ( + .I(\vga/pclk [2]), + .O(\vga/inst_Mram_mem31/CLKB_INTNOT ) + ); + defparam \vga/inst_Mram_mem31 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem31 .LOC = "RAMB4_R6C0"; + defparam \vga/inst_Mram_mem31 .SETUP_ALL = 3737; + X_RAMB4_S1_S1 \vga/inst_Mram_mem31 ( + .CLKA(\vga/ram_wclk_5 ), + .CLKB(\vga/inst_Mram_mem31/CLKB_INTNOT ), + .ENA(\vga/inst_Mram_mem31/LOGIC_ONE_64 ), + .ENB(\vga/inst_Mram_mem31/LOGIC_ONE_64 ), + .RSTA(\vga/inst_Mram_mem31/LOGIC_ZERO_63 ), + .RSTB(\vga/inst_Mram_mem31/LOGIC_ZERO_63 ), + .WEA(\vga/N226_0 ), + .WEB(\vga/inst_Mram_mem31/LOGIC_ZERO_63 ), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux<11>_0 , \vga/ram_addr_mux<10>_0 , \vga/ram_addr_mux<9>_0 , \vga/ram_addr_mux<8>_0 , \vga/ram_addr_mux<7>_0 , +\vga/ram_addr_mux<6>_0 , \vga/ram_addr_mux<5>_0 , \vga/ram_addr_mux<4>_0 , \vga/ram_addr_mux<3>_0 , \vga/ram_addr_mux<2>_0 , \vga/ram_addr_mux<1>_0 , +\vga/ram_addr_mux<0>_0 }), + .DIA({\vga/crt/ram_data [3]}), + .DIB({\vga/inst_Mram_mem31/DIB0 }), + .DOA({\vga/inst_Mram_mem31/DOA0 }), + .DOB({\vga/ram_data_out [3]}) + ); + defparam \vga/inst_Mram_mem41/LOGIC_ONE .LOC = "RAMB4_R0C0"; + X_ONE \vga/inst_Mram_mem41/LOGIC_ONE ( + .O(\vga/inst_Mram_mem41/LOGIC_ONE_66 ) + ); + defparam \vga/inst_Mram_mem41/LOGIC_ZERO .LOC = "RAMB4_R0C0"; + X_ZERO \vga/inst_Mram_mem41/LOGIC_ZERO ( + .O(\vga/inst_Mram_mem41/LOGIC_ZERO_65 ) + ); + defparam \vga/inst_Mram_mem41/CLKBMUX .LOC = "RAMB4_R0C0"; + X_INV \vga/inst_Mram_mem41/CLKBMUX ( + .I(\vga/pclk [2]), + .O(\vga/inst_Mram_mem41/CLKB_INTNOT ) + ); + defparam \vga/inst_Mram_mem41 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem41 .LOC = "RAMB4_R0C0"; + defparam \vga/inst_Mram_mem41 .SETUP_ALL = 3737; + X_RAMB4_S1_S1 \vga/inst_Mram_mem41 ( + .CLKA(\vga/ram_wclk_5 ), + .CLKB(\vga/inst_Mram_mem41/CLKB_INTNOT ), + .ENA(\vga/inst_Mram_mem41/LOGIC_ONE_66 ), + .ENB(\vga/inst_Mram_mem41/LOGIC_ONE_66 ), + .RSTA(\vga/inst_Mram_mem41/LOGIC_ZERO_65 ), + .RSTB(\vga/inst_Mram_mem41/LOGIC_ZERO_65 ), + .WEA(\vga/N226_0 ), + .WEB(\vga/inst_Mram_mem41/LOGIC_ZERO_65 ), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux<11>_0 , \vga/ram_addr_mux<10>_0 , \vga/ram_addr_mux<9>_0 , \vga/ram_addr_mux<8>_0 , \vga/ram_addr_mux<7>_0 , +\vga/ram_addr_mux<6>_0 , \vga/ram_addr_mux<5>_0 , \vga/ram_addr_mux<4>_0 , \vga/ram_addr_mux<3>_0 , \vga/ram_addr_mux<2>_0 , \vga/ram_addr_mux<1>_0 , +\vga/ram_addr_mux<0>_0 }), + .DIA({\vga/crt/ram_data [4]}), + .DIB({\vga/inst_Mram_mem41/DIB0 }), + .DOA({\vga/inst_Mram_mem41/DOA0 }), + .DOB({\vga/ram_data_out [4]}) + ); + defparam \vga/inst_Mram_mem51/LOGIC_ONE .LOC = "RAMB4_R2C0"; + X_ONE \vga/inst_Mram_mem51/LOGIC_ONE ( + .O(\vga/inst_Mram_mem51/LOGIC_ONE_68 ) + ); + defparam \vga/inst_Mram_mem51/LOGIC_ZERO .LOC = "RAMB4_R2C0"; + X_ZERO \vga/inst_Mram_mem51/LOGIC_ZERO ( + .O(\vga/inst_Mram_mem51/LOGIC_ZERO_67 ) + ); + defparam \vga/inst_Mram_mem51/CLKBMUX .LOC = "RAMB4_R2C0"; + X_INV \vga/inst_Mram_mem51/CLKBMUX ( + .I(\vga/pclk [2]), + .O(\vga/inst_Mram_mem51/CLKB_INTNOT ) + ); + defparam \vga/inst_Mram_mem51 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem51 .LOC = "RAMB4_R2C0"; + defparam \vga/inst_Mram_mem51 .SETUP_ALL = 3737; + X_RAMB4_S1_S1 \vga/inst_Mram_mem51 ( + .CLKA(\vga/ram_wclk_5 ), + .CLKB(\vga/inst_Mram_mem51/CLKB_INTNOT ), + .ENA(\vga/inst_Mram_mem51/LOGIC_ONE_68 ), + .ENB(\vga/inst_Mram_mem51/LOGIC_ONE_68 ), + .RSTA(\vga/inst_Mram_mem51/LOGIC_ZERO_67 ), + .RSTB(\vga/inst_Mram_mem51/LOGIC_ZERO_67 ), + .WEA(\vga/N226_0 ), + .WEB(\vga/inst_Mram_mem51/LOGIC_ZERO_67 ), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux<11>_0 , \vga/ram_addr_mux<10>_0 , \vga/ram_addr_mux<9>_0 , \vga/ram_addr_mux<8>_0 , \vga/ram_addr_mux<7>_0 , +\vga/ram_addr_mux<6>_0 , \vga/ram_addr_mux<5>_0 , \vga/ram_addr_mux<4>_0 , \vga/ram_addr_mux<3>_0 , \vga/ram_addr_mux<2>_0 , \vga/ram_addr_mux<1>_0 , +\vga/ram_addr_mux<0>_0 }), + .DIA({\vga/crt/ram_data [5]}), + .DIB({\vga/inst_Mram_mem51/DIB0 }), + .DOA({\vga/inst_Mram_mem51/DOA0 }), + .DOB({\vga/ram_data_out [5]}) + ); + defparam \vga/inst_Mram_mem61/LOGIC_ONE .LOC = "RAMB4_R1C0"; + X_ONE \vga/inst_Mram_mem61/LOGIC_ONE ( + .O(\vga/inst_Mram_mem61/LOGIC_ONE_70 ) + ); + defparam \vga/inst_Mram_mem61/LOGIC_ZERO .LOC = "RAMB4_R1C0"; + X_ZERO \vga/inst_Mram_mem61/LOGIC_ZERO ( + .O(\vga/inst_Mram_mem61/LOGIC_ZERO_69 ) + ); + defparam \vga/inst_Mram_mem61/CLKBMUX .LOC = "RAMB4_R1C0"; + X_INV \vga/inst_Mram_mem61/CLKBMUX ( + .I(\vga/pclk [2]), + .O(\vga/inst_Mram_mem61/CLKB_INTNOT ) + ); + defparam \vga/inst_Mram_mem61 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem61 .LOC = "RAMB4_R1C0"; + defparam \vga/inst_Mram_mem61 .SETUP_ALL = 3737; + X_RAMB4_S1_S1 \vga/inst_Mram_mem61 ( + .CLKA(\vga/ram_wclk_5 ), + .CLKB(\vga/inst_Mram_mem61/CLKB_INTNOT ), + .ENA(\vga/inst_Mram_mem61/LOGIC_ONE_70 ), + .ENB(\vga/inst_Mram_mem61/LOGIC_ONE_70 ), + .RSTA(\vga/inst_Mram_mem61/LOGIC_ZERO_69 ), + .RSTB(\vga/inst_Mram_mem61/LOGIC_ZERO_69 ), + .WEA(\vga/N226_0 ), + .WEB(\vga/inst_Mram_mem61/LOGIC_ZERO_69 ), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux<11>_0 , \vga/ram_addr_mux<10>_0 , \vga/ram_addr_mux<9>_0 , \vga/ram_addr_mux<8>_0 , \vga/ram_addr_mux<7>_0 , +\vga/ram_addr_mux<6>_0 , \vga/ram_addr_mux<5>_0 , \vga/ram_addr_mux<4>_0 , \vga/ram_addr_mux<3>_0 , \vga/ram_addr_mux<2>_0 , \vga/ram_addr_mux<1>_0 , +\vga/ram_addr_mux<0>_0 }), + .DIA({\vga/crt/ram_data [6]}), + .DIB({\vga/inst_Mram_mem61/DIB0 }), + .DOA({\vga/inst_Mram_mem61/DOA0 }), + .DOB({\vga/ram_data_out [6]}) + ); + defparam \vga/inst_Mram_mem8/LOGIC_ONE .LOC = "RAMB4_R3C0"; + X_ONE \vga/inst_Mram_mem8/LOGIC_ONE ( + .O(\vga/inst_Mram_mem8/LOGIC_ONE_72 ) + ); + defparam \vga/inst_Mram_mem8/LOGIC_ZERO .LOC = "RAMB4_R3C0"; + X_ZERO \vga/inst_Mram_mem8/LOGIC_ZERO ( + .O(\vga/inst_Mram_mem8/LOGIC_ZERO_71 ) + ); + defparam \vga/inst_Mram_mem8/CLKBMUX .LOC = "RAMB4_R3C0"; + X_INV \vga/inst_Mram_mem8/CLKBMUX ( + .I(\vga/pclk [2]), + .O(\vga/inst_Mram_mem8/CLKB_INTNOT ) + ); + defparam \vga/inst_Mram_mem8 .INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + defparam \vga/inst_Mram_mem8 .LOC = "RAMB4_R3C0"; + defparam \vga/inst_Mram_mem8 .SETUP_ALL = 3737; + X_RAMB4_S1_S1 \vga/inst_Mram_mem8 ( + .CLKA(\vga/ram_wclk_5 ), + .CLKB(\vga/inst_Mram_mem8/CLKB_INTNOT ), + .ENA(\vga/inst_Mram_mem8/LOGIC_ONE_72 ), + .ENB(\vga/inst_Mram_mem8/LOGIC_ONE_72 ), + .RSTA(\vga/inst_Mram_mem8/LOGIC_ZERO_71 ), + .RSTB(\vga/inst_Mram_mem8/LOGIC_ZERO_71 ), + .WEA(\vga/N226_0 ), + .WEB(\vga/inst_Mram_mem8/LOGIC_ZERO_71 ), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux<11>_0 , \vga/ram_addr_mux<10>_0 , \vga/ram_addr_mux<9>_0 , \vga/ram_addr_mux<8>_0 , \vga/ram_addr_mux<7>_0 , +\vga/ram_addr_mux<6>_0 , \vga/ram_addr_mux<5>_0 , \vga/ram_addr_mux<4>_0 , \vga/ram_addr_mux<3>_0 , \vga/ram_addr_mux<2>_0 , \vga/ram_addr_mux<1>_0 , +\vga/ram_addr_mux<0>_0 }), + .DIA({\vga/crt/ram_data [0]}), + .DIB({\vga/inst_Mram_mem8/DIB0 }), + .DOA({\vga/inst_Mram_mem8/DOA0 }), + .DOB({\vga/ram_data_out [0]}) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW0 .LOC = "CLB_R11C37.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<6>1201_SW0 ( + .IA(N3198), + .IB(N3199), + .SEL(\vga/scancode_convert/sc [3]), + .O(N3084) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW0_G .INIT = 16'hDF8F; + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW0_G .LOC = "CLB_R11C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1201_SW0_G ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/scancode_rom/data<6>1_map1831 ), + .ADR2(\vga/scancode_convert/sc [5]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3199) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW0_F .INIT = 16'h0FEF; + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW0_F .LOC = "CLB_R11C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1201_SW0_F ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [5]), + .ADR3(\vga/scancode_convert/sc [2]), + .O(N3198) + ); + defparam \N3084/XUSED .LOC = "CLB_R11C37.S0"; + X_BUF \N3084/XUSED ( + .I(N3084), + .O(N3084_0) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2416 .LOC = "CLB_R13C36.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<1>2416 ( + .IA(N3186), + .IB(N3187), + .SEL(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1774 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2416_G .INIT = 16'h7555; + defparam \vga/scancode_convert/scancode_rom/data<1>2416_G .LOC = "CLB_R13C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2416_G ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/scancode_rom/N9 ), + .ADR3(\vga/scancode_convert/sc [4]), + .O(N3187) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2416_F .INIT = 16'h13FF; + defparam \vga/scancode_convert/scancode_rom/data<1>2416_F .LOC = "CLB_R13C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2416_F ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [2]), + .O(N3186) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2_map1774/XUSED .LOC = "CLB_R13C36.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<1>2_map1774/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2_map1774 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1774_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1352_f5 .LOC = "CLB_R18C34.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<3>1352_f5 ( + .IA(\vga/scancode_convert/scancode_rom/data<3>1_map1229/GROM ), + .IB(N3245), + .SEL(\vga/scancode_convert/sc [5]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1229 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>13521 .INIT = 16'h0040; + defparam \vga/scancode_convert/scancode_rom/data<3>13521 .LOC = "CLB_R18C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>13521 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [2]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3245) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1_map1229/G .INIT = 16'hFFFF; + defparam \vga/scancode_convert/scancode_rom/data<3>1_map1229/G .LOC = "CLB_R18C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1_map1229/G ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1229/GROM ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1_map1229/XUSED .LOC = "CLB_R18C34.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>1_map1229/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>1_map1229 ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1229_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1207 .LOC = "CLB_R15C37.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<2>1207 ( + .IA(N3200), + .IB(N3201), + .SEL(\vga/scancode_convert/sc [5]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1098 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1207_G .INIT = 16'h4477; + defparam \vga/scancode_convert/scancode_rom/data<2>1207_G .LOC = "CLB_R15C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1207_G ( + .ADR0(N3142_0), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(VCC), + .ADR3(N3141_0), + .O(N3201) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1207_F .INIT = 16'h88AA; + defparam \vga/scancode_convert/scancode_rom/data<2>1207_F .LOC = "CLB_R15C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1207_F ( + .ADR0(\vga/scancode_convert/scancode_rom/data<2>1_map1056_0 ), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/scancode_rom/N28_0 ), + .O(N3200) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1_map1098/XUSED .LOC = "CLB_R15C37.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<2>1_map1098/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<2>1_map1098 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1098_0 ) + ); + defparam \vga/charload1_SW0 .LOC = "CLB_R12C3.S0"; + X_MUX2 \vga/charload1_SW0 ( + .IA(N3192), + .IB(N3193), + .SEL(\vga/rom_addr_char [6]), + .O(N560) + ); + defparam \vga/charload1_SW0_G .INIT = 16'hF3C0; + defparam \vga/charload1_SW0_G .LOC = "CLB_R12C3.S0"; + X_LUT4 \vga/charload1_SW0_G ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char [5]), + .ADR2(\vga/rom_addr_char<4>_f5_0 ), + .ADR3(\vga/rom_addr_char<4>11_0 ), + .O(N3193) + ); + defparam \vga/charload1_SW0_F .INIT = 16'h88C0; + defparam \vga/charload1_SW0_F .LOC = "CLB_R12C3.S0"; + X_LUT4 \vga/charload1_SW0_F ( + .ADR0(\vga/rom_addr_char<3>_f61_0 ), + .ADR1(\vga/rom_addr_char [5]), + .ADR2(\vga/rom_addr_char<3>_f6_0_6 ), + .ADR3(\vga/rom_addr_char [4]), + .O(N3192) + ); + defparam \N560/XUSED .LOC = "CLB_R12C3.S0"; + X_BUF \N560/XUSED ( + .I(N560), + .O(N560_0) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1382 .LOC = "CLB_R18C35.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<3>1382 ( + .IA(N3116), + .IB(N3117), + .SEL(\vga/scancode_convert/sc [6]), + .O(\vga/scancode_convert/rom_data [3]) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1382_G .INIT = 16'hEA00; + defparam \vga/scancode_convert/scancode_rom/data<3>1382_G .LOC = "CLB_R18C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1382_G ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/scancode_rom/data<3>1_map1221_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<3>1_map1201_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<3>1_map1229_0 ), + .O(N3117) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1382_F .INIT = 16'h8F80; + defparam \vga/scancode_convert/scancode_rom/data<3>1382_F .LOC = "CLB_R18C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1382_F ( + .ADR0(\vga/scancode_convert/scancode_rom/data<3>1_map1171_0 ), + .ADR1(\vga/scancode_convert/scancode_rom/data<3>1_map1185_0 ), + .ADR2(\vga/scancode_convert/sc [5]), + .ADR3(\vga/scancode_convert/scancode_rom/data<3>1_map1158_0 ), + .O(N3116) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1299 .LOC = "CLB_R17C35.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<3>1299 ( + .IA(N3190), + .IB(N3191), + .SEL(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1221 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1299_G .INIT = 16'h7377; + defparam \vga/scancode_convert/scancode_rom/data<3>1299_G .LOC = "CLB_R17C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1299_G ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3191) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1299_F .INIT = 16'h7F5F; + defparam \vga/scancode_convert/scancode_rom/data<3>1299_F .LOC = "CLB_R17C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1299_F ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/scancode_rom/N9 ), + .O(N3190) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1_map1221/XUSED .LOC = "CLB_R17C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>1_map1221/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>1_map1221 ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1221_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1437 .LOC = "CLB_R10C36.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<4>1437 ( + .IA(N3118), + .IB(N3119), + .SEL(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1633 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1437_G .INIT = 16'h9040; + defparam \vga/scancode_convert/scancode_rom/data<4>1437_G .LOC = "CLB_R10C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1437_G ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3119) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1437_F .INIT = 16'h8000; + defparam \vga/scancode_convert/scancode_rom/data<4>1437_F .LOC = "CLB_R10C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1437_F ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3118) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1_map1633/XUSED .LOC = "CLB_R10C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>1_map1633/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1_map1633 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1633_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1673 .LOC = "CLB_R12C36.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<4>1673 ( + .IA(N3120), + .IB(N3121), + .SEL(\vga/scancode_convert/sc [6]), + .O(\vga/scancode_convert/rom_data [4]) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1673_G .INIT = 16'hF0A0; + defparam \vga/scancode_convert/scancode_rom/data<4>1673_G .LOC = "CLB_R12C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1673_G ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(VCC), + .ADR2(\vga/scancode_convert/scancode_rom/data<0>1_map1534_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<4>1_map1669_0 ), + .O(N3121) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1673_F .INIT = 16'hE444; + defparam \vga/scancode_convert/scancode_rom/data<4>1673_F .LOC = "CLB_R12C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1673_F ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/scancode_rom/data<4>1_map1560_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<4>1_map1609_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<4>1_map1565_0 ), + .O(N3120) + ); + defparam \vga/rom_addr_char<2>_f5_0 .LOC = "CLB_R19C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_0 ( + .IA(\vga/N312 ), + .IB(\vga/N2123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51_73 ) + ); + defparam \vga/rom_addr_char<1>2 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>2 .LOC = "CLB_R19C3.S0"; + X_LUT4 \vga/rom_addr_char<1>2 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N12_0 ), + .ADR3(\vga/N11_0 ), + .O(\vga/N2123 ) + ); + defparam \vga/rom_addr_char<1>3 .INIT = 16'hF000; + defparam \vga/rom_addr_char<1>3 .LOC = "CLB_R19C3.S0"; + X_LUT4 \vga/rom_addr_char<1>3 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/N10_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N312 ) + ); + defparam \vga/rom_addr_char<2>_f51/F5USED .LOC = "CLB_R19C3.S0"; + X_BUF \vga/rom_addr_char<2>_f51/F5USED ( + .I(\vga/rom_addr_char<2>_f51_73 ), + .O(\vga/rom_addr_char<2>_f51_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1588 .LOC = "CLB_R10C35.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<4>1588 ( + .IA(N3202), + .IB(N3203), + .SEL(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1666 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1588_G .INIT = 16'h2212; + defparam \vga/scancode_convert/scancode_rom/data<4>1588_G .LOC = "CLB_R10C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1588_G ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3203) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1588_F .INIT = 16'h4556; + defparam \vga/scancode_convert/scancode_rom/data<4>1588_F .LOC = "CLB_R10C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1588_F ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3202) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1_map1666/XUSED .LOC = "CLB_R10C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>1_map1666/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1_map1666 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1666_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_1 .LOC = "CLB_R3C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_1 ( + .IA(\vga/N512 ), + .IB(\vga/N412 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f52_75 ) + ); + defparam \vga/rom_addr_char<1>4 .INIT = 16'hEE22; + defparam \vga/rom_addr_char<1>4 .LOC = "CLB_R3C3.S1"; + X_LUT4 \vga/rom_addr_char<1>4 ( + .ADR0(\vga/N21_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N22_0 ), + .O(\vga/N412 ) + ); + defparam \vga/rom_addr_char<1>5 .INIT = 16'h00F0; + defparam \vga/rom_addr_char<1>5 .LOC = "CLB_R3C3.S1"; + X_LUT4 \vga/rom_addr_char<1>5 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/N20_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N512 ) + ); + defparam \vga/rom_addr_char<3>_f61/YUSED .LOC = "CLB_R3C3.S1"; + X_BUF \vga/rom_addr_char<3>_f61/YUSED ( + .I(\vga/rom_addr_char<3>_f61_74 ), + .O(\vga/rom_addr_char<3>_f61_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_0 .LOC = "CLB_R3C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_0 ( + .IA(\vga/rom_addr_char<2>_f53_0 ), + .IB(\vga/rom_addr_char<2>_f52_75 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f61_74 ) + ); + defparam \vga/rom_addr_char<2>_f5_2 .LOC = "CLB_R3C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_2 ( + .IA(\vga/N712 ), + .IB(\vga/N612 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f53_76 ) + ); + defparam \vga/rom_addr_char<1>6 .INIT = 16'h0033; + defparam \vga/rom_addr_char<1>6 .LOC = "CLB_R3C3.S0"; + X_LUT4 \vga/rom_addr_char<1>6 ( + .ADR0(VCC), + .ADR1(N3146_0), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N612 ) + ); + defparam \vga/rom_addr_char<1>7 .INIT = 16'hAAF0; + defparam \vga/rom_addr_char<1>7 .LOC = "CLB_R3C3.S0"; + X_LUT4 \vga/rom_addr_char<1>7 ( + .ADR0(\vga/N17_0 ), + .ADR1(VCC), + .ADR2(\vga/N16_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N712 ) + ); + defparam \vga/rom_addr_char<2>_f53/F5USED .LOC = "CLB_R3C3.S0"; + X_BUF \vga/rom_addr_char<2>_f53/F5USED ( + .I(\vga/rom_addr_char<2>_f53_76 ), + .O(\vga/rom_addr_char<2>_f53_0 ) + ); + defparam \vga/pixel<8>19_f5 .LOC = "CLB_R16C8.S1"; + X_MUX2 \vga/pixel<8>19_f5 ( + .IA(N3222), + .IB(N3221), + .SEL(\vga/vgacore/vcnt [9]), + .O(\vga/pixel<8>_map785 ) + ); + defparam \vga/pixel<8>191 .INIT = 16'hDD55; + defparam \vga/pixel<8>191 .LOC = "CLB_R16C8.S1"; + X_LUT4 \vga/pixel<8>191 ( + .ADR0(\vga/vgacore/N51_0 ), + .ADR1(\vga/vgacore/vcnt [3]), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(N3221) + ); + defparam \vga/vgacore/_or000011 .INIT = 16'h7FFF; + defparam \vga/vgacore/_or000011 .LOC = "CLB_R16C8.S1"; + X_LUT4 \vga/vgacore/_or000011 ( + .ADR0(\vga/vgacore/vcnt [6]), + .ADR1(\vga/vgacore/vcnt [5]), + .ADR2(\vga/vgacore/vcnt [7]), + .ADR3(\vga/vgacore/vcnt [8]), + .O(N3222) + ); + defparam \vga/pixel<8>_map785/XUSED .LOC = "CLB_R16C8.S1"; + X_BUF \vga/pixel<8>_map785/XUSED ( + .I(\vga/pixel<8>_map785 ), + .O(\vga/pixel<8>_map785_0 ) + ); + defparam \vga/pixel<8>_map785/YUSED .LOC = "CLB_R16C8.S1"; + X_BUF \vga/pixel<8>_map785/YUSED ( + .I(N3222), + .O(N3222_0) + ); + defparam \vga/rom_addr_char<2>_f5_3 .LOC = "CLB_R4C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_3 ( + .IA(\vga/N1011 ), + .IB(\vga/N912 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f54_78 ) + ); + defparam \vga/rom_addr_char<1>8 .INIT = 16'hEE44; + defparam \vga/rom_addr_char<1>8 .LOC = "CLB_R4C3.S1"; + X_LUT4 \vga/rom_addr_char<1>8 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N29_0 ), + .ADR2(VCC), + .ADR3(\vga/N30_0 ), + .O(\vga/N912 ) + ); + defparam \vga/rom_addr_char<1>9 .INIT = 16'hEE44; + defparam \vga/rom_addr_char<1>9 .LOC = "CLB_R4C3.S1"; + X_LUT4 \vga/rom_addr_char<1>9 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N27_0 ), + .ADR2(VCC), + .ADR3(\vga/N28_0 ), + .O(\vga/N1011 ) + ); + defparam \vga/rom_addr_char<3>_f62/YUSED .LOC = "CLB_R4C3.S1"; + X_BUF \vga/rom_addr_char<3>_f62/YUSED ( + .I(\vga/rom_addr_char<3>_f62_77 ), + .O(\vga/rom_addr_char<3>_f62_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_1 .LOC = "CLB_R4C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_1 ( + .IA(\vga/rom_addr_char<2>_f55_0 ), + .IB(\vga/rom_addr_char<2>_f54_78 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f62_77 ) + ); + defparam \vga/rom_addr_char<2>_f5_4 .LOC = "CLB_R4C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_4 ( + .IA(\vga/N1211 ), + .IB(\vga/N1111 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f55 ) + ); + defparam \vga/rom_addr_char<1>10 .INIT = 16'hACAC; + defparam \vga/rom_addr_char<1>10 .LOC = "CLB_R4C3.S0"; + X_LUT4 \vga/rom_addr_char<1>10 ( + .ADR0(\vga/N26_0 ), + .ADR1(\vga/N25_0 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(VCC), + .O(\vga/N1111 ) + ); + defparam \vga/rom_addr_char<1>11 .INIT = 16'hFA0A; + defparam \vga/rom_addr_char<1>11 .LOC = "CLB_R4C3.S0"; + X_LUT4 \vga/rom_addr_char<1>11 ( + .ADR0(\vga/N23_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N24_0 ), + .O(\vga/N1211 ) + ); + defparam \vga/rom_addr_char<2>_f55/F5USED .LOC = "CLB_R4C3.S0"; + X_BUF \vga/rom_addr_char<2>_f55/F5USED ( + .I(\vga/rom_addr_char<2>_f55 ), + .O(\vga/rom_addr_char<2>_f55_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_5 .LOC = "CLB_R10C2.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_5 ( + .IA(\vga/N1411 ), + .IB(\vga/N1311 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f56 ) + ); + defparam \vga/rom_addr_char<1>12 .INIT = 16'hAACC; + defparam \vga/rom_addr_char<1>12 .LOC = "CLB_R10C2.S1"; + X_LUT4 \vga/rom_addr_char<1>12 ( + .ADR0(\vga/N37_0 ), + .ADR1(\vga/N7_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N1311 ) + ); + defparam \vga/rom_addr_char<1>13 .INIT = 16'h3300; + defparam \vga/rom_addr_char<1>13 .LOC = "CLB_R10C2.S1"; + X_LUT4 \vga/rom_addr_char<1>13 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(VCC), + .ADR3(\vga/N35_0 ), + .O(\vga/N1411 ) + ); + defparam \vga/rom_addr_char<3>_f63/YUSED .LOC = "CLB_R10C2.S1"; + X_BUF \vga/rom_addr_char<3>_f63/YUSED ( + .I(\vga/rom_addr_char<3>_f63_79 ), + .O(\vga/rom_addr_char<3>_f63_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_2 .LOC = "CLB_R10C2.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_2 ( + .IA(\vga/rom_addr_char<2>_f57_0 ), + .IB(\vga/rom_addr_char<2>_f56 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f63_79 ) + ); + defparam \vga/rom_addr_char<2>_f5_6 .LOC = "CLB_R10C2.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_6 ( + .IA(\vga/N1611 ), + .IB(N3078), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f57 ) + ); + defparam \vga/rom_addr_char<2>_f5_65 .INIT = 16'hB8B8; + defparam \vga/rom_addr_char<2>_f5_65 .LOC = "CLB_R10C2.S0"; + X_LUT4 \vga/rom_addr_char<2>_f5_65 ( + .ADR0(\vga/N34_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(\vga/N33_0 ), + .ADR3(VCC), + .O(N3078) + ); + defparam \vga/rom_addr_char<1>15 .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<1>15 .LOC = "CLB_R10C2.S0"; + X_LUT4 \vga/rom_addr_char<1>15 ( + .ADR0(VCC), + .ADR1(\vga/N32_0 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N31_0 ), + .O(\vga/N1611 ) + ); + defparam \vga/rom_addr_char<2>_f57/F5USED .LOC = "CLB_R10C2.S0"; + X_BUF \vga/rom_addr_char<2>_f57/F5USED ( + .I(\vga/rom_addr_char<2>_f57 ), + .O(\vga/rom_addr_char<2>_f57_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_7 .LOC = "CLB_R8C1.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_7 ( + .IA(\vga/N1811 ), + .IB(\vga/N1711 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f58 ) + ); + defparam \vga/rom_addr_char<1>16 .INIT = 16'hF000; + defparam \vga/rom_addr_char<1>16 .LOC = "CLB_R8C1.S1"; + X_LUT4 \vga/rom_addr_char<1>16 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N45_0 ), + .O(\vga/N1711 ) + ); + defparam \vga/rom_addr_char<1>17 .INIT = 16'hDD88; + defparam \vga/rom_addr_char<1>17 .LOC = "CLB_R8C1.S1"; + X_LUT4 \vga/rom_addr_char<1>17 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/N44_0 ), + .ADR2(VCC), + .ADR3(\vga/N43_0 ), + .O(\vga/N1811 ) + ); + defparam \vga/rom_addr_char<2>_f58/XUSED .LOC = "CLB_R8C1.S1"; + X_BUF \vga/rom_addr_char<2>_f58/XUSED ( + .I(\vga/rom_addr_char<2>_f58 ), + .O(\vga/rom_addr_char<2>_f58_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_8 .LOC = "CLB_R21C5.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_8 ( + .IA(\vga/N2111 ), + .IB(\vga/N2011 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f59 ) + ); + defparam \vga/rom_addr_char<1>18 .INIT = 16'hF3C0; + defparam \vga/rom_addr_char<1>18 .LOC = "CLB_R21C5.S1"; + X_LUT4 \vga/rom_addr_char<1>18 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N41_0 ), + .ADR3(\vga/N40_0 ), + .O(\vga/N2011 ) + ); + defparam \vga/rom_addr_char<1>19 .INIT = 16'hAACC; + defparam \vga/rom_addr_char<1>19 .LOC = "CLB_R21C5.S1"; + X_LUT4 \vga/rom_addr_char<1>19 ( + .ADR0(\vga/N39_0 ), + .ADR1(\vga/N38_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N2111 ) + ); + defparam \vga/rom_addr_char<2>_f59/XUSED .LOC = "CLB_R21C5.S1"; + X_BUF \vga/rom_addr_char<2>_f59/XUSED ( + .I(\vga/rom_addr_char<2>_f59 ), + .O(\vga/rom_addr_char<2>_f59_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_9 .LOC = "CLB_R27C13.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_9 ( + .IA(\vga/N2212 ), + .IB(\vga/N2112 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f510 ) + ); + defparam \vga/rom_addr_char<1>201 .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<1>201 .LOC = "CLB_R27C13.S1"; + X_LUT4 \vga/rom_addr_char<1>201 ( + .ADR0(VCC), + .ADR1(\vga/N75_0 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N113_0 ), + .O(\vga/N2112 ) + ); + defparam \vga/rom_addr_char<1>211 .INIT = 16'hF3C0; + defparam \vga/rom_addr_char<1>211 .LOC = "CLB_R27C13.S1"; + X_LUT4 \vga/rom_addr_char<1>211 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(\vga/N99_0 ), + .ADR3(\vga/N72_0 ), + .O(\vga/N2212 ) + ); + defparam \vga/rom_addr_char<3>_f65/YUSED .LOC = "CLB_R27C13.S1"; + X_BUF \vga/rom_addr_char<3>_f65/YUSED ( + .I(\vga/rom_addr_char<3>_f65 ), + .O(\vga/rom_addr_char<3>_f65_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_4 .LOC = "CLB_R27C13.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_4 ( + .IA(\vga/rom_addr_char<2>_f5111_0 ), + .IB(\vga/rom_addr_char<2>_f510 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f65 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3450 .LOC = "CLB_R11C34.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<5>3450 ( + .IA(N3214), + .IB(N3215), + .SEL(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1337 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3450_G .INIT = 16'h5FD5; + defparam \vga/scancode_convert/scancode_rom/data<5>3450_G .LOC = "CLB_R11C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3450_G ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/sc_0_1_10 ), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3215) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3450_F .INIT = 16'h77FF; + defparam \vga/scancode_convert/scancode_rom/data<5>3450_F .LOC = "CLB_R11C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3450_F ( + .ADR0(\vga/scancode_convert/sc_0_1_10 ), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3214) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3_map1337/XUSED .LOC = "CLB_R11C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3_map1337/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1337 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1337_0 ) + ); + defparam \vga/charload8_SW0_SW0_f5 .LOC = "CLB_R11C5.S1"; + X_MUX2 \vga/charload8_SW0_SW0_f5 ( + .IA(\N3150/GROM ), + .IB(N3259), + .SEL(\vga/rom_addr_char [4]), + .O(N3150) + ); + defparam \vga/charload8_SW0_SW01 .INIT = 16'h7FFF; + defparam \vga/charload8_SW0_SW01 .LOC = "CLB_R11C5.S1"; + X_LUT4 \vga/charload8_SW0_SW01 ( + .ADR0(\vga/N224_0 ), + .ADR1(\vga/rom_addr_char [2]), + .ADR2(\vga/rom_addr_char [3]), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(N3259) + ); + defparam \N3150/G .INIT = 16'hFFFF; + defparam \N3150/G .LOC = "CLB_R11C5.S1"; + X_LUT4 \N3150/G ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\N3150/GROM ) + ); + defparam \N3150/XUSED .LOC = "CLB_R11C5.S1"; + X_BUF \N3150/XUSED ( + .I(N3150), + .O(N3150_0) + ); + defparam \vga/rom_addr_char<2>_f5 .LOC = "CLB_R19C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5 ( + .IA(\vga/N1101 ), + .IB(\vga/N01 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5_85 ) + ); + defparam \vga/rom_addr_char<1> .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1> .LOC = "CLB_R19C3.S1"; + X_LUT4 \vga/rom_addr_char<1> ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N15_0 ), + .ADR3(\vga/N14 ), + .O(\vga/N01 ) + ); + defparam \vga/rom_addr_char<1>1 .INIT = 16'hA0A0; + defparam \vga/rom_addr_char<1>1 .LOC = "CLB_R19C3.S1"; + X_LUT4 \vga/rom_addr_char<1>1 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N13_0 ), + .ADR3(VCC), + .O(\vga/N1101 ) + ); + defparam \vga/rom_addr_char<3>_f6/YUSED .LOC = "CLB_R19C3.S1"; + X_BUF \vga/rom_addr_char<3>_f6/YUSED ( + .I(\vga/rom_addr_char<3>_f6_80 ), + .O(\vga/rom_addr_char<3>_f6_0_6 ) + ); + defparam \vga/rom_addr_char<3>_f6 .LOC = "CLB_R19C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6 ( + .IA(\vga/rom_addr_char<2>_f51_0 ), + .IB(\vga/rom_addr_char<2>_f5_85 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6_80 ) + ); + defparam \vga/rom_addr_char<3>_f5 .LOC = "CLB_R3C5.S0"; + X_MUX2 \vga/rom_addr_char<3>_f5 ( + .IA(\vga/N1812345 ), + .IB(\vga/N1712345 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f5_86 ) + ); + defparam \vga/rom_addr_char<2>5 .INIT = 16'hCCF0; + defparam \vga/rom_addr_char<2>5 .LOC = "CLB_R3C5.S0"; + X_LUT4 \vga/rom_addr_char<2>5 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char<1>_mmx_out_0 ), + .ADR2(\vga/rom_addr_char<1>112_0 ), + .ADR3(\vga/rom_addr_char [2]), + .O(\vga/N1712345 ) + ); + defparam \vga/rom_addr_char<2>13 .INIT = 16'hF0AA; + defparam \vga/rom_addr_char<2>13 .LOC = "CLB_R3C5.S0"; + X_LUT4 \vga/rom_addr_char<2>13 ( + .ADR0(\vga/rom_addr_char<1>2_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char<1>_mmx_out_0 ), + .ADR3(\vga/rom_addr_char [2]), + .O(\vga/N1812345 ) + ); + defparam \vga/rom_addr_char<3>_f5/XUSED .LOC = "CLB_R3C5.S0"; + X_BUF \vga/rom_addr_char<3>_f5/XUSED ( + .I(\vga/rom_addr_char<3>_f5_86 ), + .O(\vga/rom_addr_char<3>_f5_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1291_SW0 .LOC = "CLB_R16C33.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<0>1291_SW0 ( + .IA(N3188), + .IB(N3189), + .SEL(\vga/scancode_convert/sc [2]), + .O(N3104) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1291_SW0_G .INIT = 16'h2A0A; + defparam \vga/scancode_convert/scancode_rom/data<0>1291_SW0_G .LOC = "CLB_R16C33.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1291_SW0_G ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/scancode_rom/data<0>1_map1475_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<0>1_map1461_0 ), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3189) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1291_SW0_F .INIT = 16'h80CC; + defparam \vga/scancode_convert/scancode_rom/data<0>1291_SW0_F .LOC = "CLB_R16C33.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1291_SW0_F ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [5]), + .ADR2(\vga/scancode_convert/scancode_rom/N7 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<0>1_map1449_0 ), + .O(N3188) + ); + defparam \N3104/XUSED .LOC = "CLB_R16C33.S0"; + X_BUF \N3104/XUSED ( + .I(N3104), + .O(N3104_0) + ); + defparam \vga/rom_addr_char<4>_f5 .LOC = "CLB_R14C2.S0"; + X_MUX2 \vga/rom_addr_char<4>_f5 ( + .IA(\vga/N2211 ), + .IB(\vga/N1911 ), + .SEL(\vga/rom_addr_char [4]), + .O(\vga/rom_addr_char<4>_f5_87 ) + ); + defparam \vga/rom_addr_char<3> .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<3> .LOC = "CLB_R14C2.S0"; + X_LUT4 \vga/rom_addr_char<3> ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char<2>11_0 ), + .ADR2(\vga/rom_addr_char [3]), + .ADR3(\vga/rom_addr_char<2>_f58_0 ), + .O(\vga/N1911 ) + ); + defparam \vga/rom_addr_char<3>1 .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<3>1 .LOC = "CLB_R14C2.S0"; + X_LUT4 \vga/rom_addr_char<3>1 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char<2>2_0 ), + .ADR2(\vga/rom_addr_char [3]), + .ADR3(\vga/rom_addr_char<2>_f59_0 ), + .O(\vga/N2211 ) + ); + defparam \vga/rom_addr_char<4>_f5/XUSED .LOC = "CLB_R14C2.S0"; + X_BUF \vga/rom_addr_char<4>_f5/XUSED ( + .I(\vga/rom_addr_char<4>_f5_87 ), + .O(\vga/rom_addr_char<4>_f5_0 ) + ); + defparam \vga/rom_addr_char<5>_f5 .LOC = "CLB_R26C12.S1"; + X_MUX2 \vga/rom_addr_char<5>_f5 ( + .IA(\vga/N251 ), + .IB(\vga/N1612 ), + .SEL(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f5_88 ) + ); + defparam \vga/rom_addr_char<4>3 .INIT = 16'hF0AA; + defparam \vga/rom_addr_char<4>3 .LOC = "CLB_R26C12.S1"; + X_LUT4 \vga/rom_addr_char<4>3 ( + .ADR0(\vga/rom_addr_char<3>_f621_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char<3>_f631_0 ), + .ADR3(\vga/rom_addr_char [4]), + .O(\vga/N1612 ) + ); + defparam \vga/rom_addr_char<4>11 .INIT = 16'hAFA0; + defparam \vga/rom_addr_char<4>11 .LOC = "CLB_R26C12.S1"; + X_LUT4 \vga/rom_addr_char<4>11 ( + .ADR0(\vga/rom_addr_char<3>_f65_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char [4]), + .ADR3(\vga/rom_addr_char<3>_f64_0 ), + .O(\vga/N251 ) + ); + defparam \vga/rom_addr_char<5>_f5/XUSED .LOC = "CLB_R26C12.S1"; + X_BUF \vga/rom_addr_char<5>_f5/XUSED ( + .I(\vga/rom_addr_char<5>_f5_88 ), + .O(\vga/rom_addr_char<5>_f5_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1410_SW0_f5 .LOC = "CLB_R16C36.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<2>1410_SW0_f5 ( + .IA(N3255), + .IB(N3254), + .SEL(\vga/scancode_convert/sc [4]), + .O(N3126) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1410_SW01 .INIT = 16'hFFFC; + defparam \vga/scancode_convert/scancode_rom/data<2>1410_SW01 .LOC = "CLB_R16C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1410_SW01 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/scancode_rom/N12 ), + .O(N3254) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1410_SW02 .INIT = 16'hFFF5; + defparam \vga/scancode_convert/scancode_rom/data<2>1410_SW02 .LOC = "CLB_R16C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1410_SW02 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(VCC), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3255) + ); + defparam \N3126/XUSED .LOC = "CLB_R16C36.S1"; + X_BUF \N3126/XUSED ( + .I(N3126), + .O(N3126_0) + ); + defparam \vga/crt/state_FFd2-In_f5 .LOC = "CLB_R15C18.S0"; + X_MUX2 \vga/crt/state_FFd2-In_f5 ( + .IA(N3227), + .IB(N3226), + .SEL(\vga/crt/state_FFd3_11 ), + .O(\vga/crt/state_FFd2-In ) + ); + defparam \vga/crt/state_FFd2-In1 .INIT = 16'hFFF7; + defparam \vga/crt/state_FFd2-In1 .LOC = "CLB_R15C18.S0"; + X_LUT4 \vga/crt/state_FFd2-In1 ( + .ADR0(\vga/crt/state_FFd2_12 ), + .ADR1(\vga/scancode_convert/strobe_out_15 ), + .ADR2(\vga/scancode_convert/key_up_14 ), + .ADR3(\vga/crt/state_FFd1_13 ), + .O(N3226) + ); + defparam \vga/crt/state_FFd2-In2 .INIT = 16'hEC00; + defparam \vga/crt/state_FFd2-In2 .LOC = "CLB_R15C18.S0"; + X_LUT4 \vga/crt/state_FFd2-In2 ( + .ADR0(\vga/crt/eol_0 ), + .ADR1(\vga/crt/state_FFd1_13 ), + .ADR2(\vga/crt/scroll_0 ), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(N3227) + ); + defparam \vga/ps2/bitcnt_x<2>1 .LOC = "CLB_R7C19.S0"; + X_MUX2 \vga/ps2/bitcnt_x<2>1 ( + .IA(N3206), + .IB(N3207), + .SEL(\vga/ps2/ps2_clk_fall_edge_0 ), + .O(\vga/ps2/bitcnt_x [2]) + ); + defparam \vga/ps2/bitcnt_x<2>1_G .INIT = 16'h7788; + defparam \vga/ps2/bitcnt_x<2>1_G .LOC = "CLB_R7C19.S0"; + X_LUT4 \vga/ps2/bitcnt_x<2>1_G ( + .ADR0(\vga/ps2/bitcnt_r [0]), + .ADR1(\vga/ps2/bitcnt_r [1]), + .ADR2(VCC), + .ADR3(\vga/ps2/bitcnt_r [2]), + .O(N3207) + ); + defparam \vga/ps2/bitcnt_x<2>1_F .INIT = 16'h1050; + defparam \vga/ps2/bitcnt_x<2>1_F .LOC = "CLB_R7C19.S0"; + X_LUT4 \vga/ps2/bitcnt_x<2>1_F ( + .ADR0(\vga/ps2/error_r_16 ), + .ADR1(\vga/ps2/_cmp_eq0001 ), + .ADR2(\vga/ps2/bitcnt_r [2]), + .ADR3(\vga/ps2/ps2_clk_r [1]), + .O(N3206) + ); + defparam \vga/ps2/bitcnt_r_2 .LOC = "CLB_R7C19.S0"; + defparam \vga/ps2/bitcnt_r_2 .INIT = 1'b0; + X_FF \vga/ps2/bitcnt_r_2 ( + .I(\vga/ps2/bitcnt_x [2]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/bitcnt_r<2>/FFX/RST ), + .O(\vga/ps2/bitcnt_r [2]) + ); + defparam \vga/ps2/bitcnt_r<2>/FFX/RSTOR .LOC = "CLB_R7C19.S0"; + X_INV \vga/ps2/bitcnt_r<2>/FFX/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/bitcnt_r<2>/FFX/RST ) + ); + defparam \vga/ps2/bitcnt_x<0>1_f5 .LOC = "CLB_R7C18.S0"; + X_MUX2 \vga/ps2/bitcnt_x<0>1_f5 ( + .IA(N3225), + .IB(N3224), + .SEL(\vga/ps2/_cmp_eq0001 ), + .O(\vga/ps2/bitcnt_x [0]) + ); + defparam \vga/ps2/bitcnt_x<0>11 .INIT = 16'h3304; + defparam \vga/ps2/bitcnt_x<0>11 .LOC = "CLB_R7C18.S0"; + X_LUT4 \vga/ps2/bitcnt_x<0>11 ( + .ADR0(\vga/ps2/ps2_clk_r [1]), + .ADR1(\vga/ps2/bitcnt_r [0]), + .ADR2(\vga/ps2/error_r_16 ), + .ADR3(\vga/ps2/ps2_clk_fall_edge_0 ), + .O(N3224) + ); + defparam \vga/ps2/bitcnt_x<0>12 .INIT = 16'h303C; + defparam \vga/ps2/bitcnt_x<0>12 .LOC = "CLB_R7C18.S0"; + X_LUT4 \vga/ps2/bitcnt_x<0>12 ( + .ADR0(VCC), + .ADR1(\vga/ps2/bitcnt_r [0]), + .ADR2(\vga/ps2/ps2_clk_fall_edge_0 ), + .ADR3(\vga/ps2/error_r_16 ), + .O(N3225) + ); + defparam \vga/ps2/bitcnt_r_0 .LOC = "CLB_R7C18.S0"; + defparam \vga/ps2/bitcnt_r_0 .INIT = 1'b0; + X_FF \vga/ps2/bitcnt_r_0 ( + .I(\vga/ps2/bitcnt_x [0]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/bitcnt_r<0>/FFX/RST ), + .O(\vga/ps2/bitcnt_r [0]) + ); + defparam \vga/ps2/bitcnt_r<0>/FFX/RSTOR .LOC = "CLB_R7C18.S0"; + X_INV \vga/ps2/bitcnt_r<0>/FFX/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/bitcnt_r<0>/FFX/RST ) + ); + defparam \vga/ps2/bitcnt_x<1>1_f5 .LOC = "CLB_R7C18.S1"; + X_MUX2 \vga/ps2/bitcnt_x<1>1_f5 ( + .IA(N3231), + .IB(N3230), + .SEL(\vga/ps2/ps2_clk_fall_edge_0 ), + .O(\vga/ps2/bitcnt_x [1]) + ); + defparam \vga/ps2/bitcnt_x<1>11 .INIT = 16'h0FF0; + defparam \vga/ps2/bitcnt_x<1>11 .LOC = "CLB_R7C18.S1"; + X_LUT4 \vga/ps2/bitcnt_x<1>11 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/bitcnt_r [0]), + .ADR3(\vga/ps2/bitcnt_r [1]), + .O(N3230) + ); + defparam \vga/ps2/bitcnt_x<1>12 .INIT = 16'h004C; + defparam \vga/ps2/bitcnt_x<1>12 .LOC = "CLB_R7C18.S1"; + X_LUT4 \vga/ps2/bitcnt_x<1>12 ( + .ADR0(\vga/ps2/_cmp_eq0001 ), + .ADR1(\vga/ps2/bitcnt_r [1]), + .ADR2(\vga/ps2/ps2_clk_r [1]), + .ADR3(\vga/ps2/error_r_16 ), + .O(N3231) + ); + defparam \vga/ps2/bitcnt_r_1 .LOC = "CLB_R7C18.S1"; + defparam \vga/ps2/bitcnt_r_1 .INIT = 1'b0; + X_FF \vga/ps2/bitcnt_r_1 ( + .I(\vga/ps2/bitcnt_x [1]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/bitcnt_r<1>/FFX/RST ), + .O(\vga/ps2/bitcnt_r [1]) + ); + defparam \vga/ps2/bitcnt_r<1>/FFX/RSTOR .LOC = "CLB_R7C18.S1"; + X_INV \vga/ps2/bitcnt_r<1>/FFX/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/bitcnt_r<1>/FFX/RST ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>111_f5 .LOC = "CLB_R16C37.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<2>111_f5 ( + .IA(N3243), + .IB(N3242), + .SEL(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1056 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1111 .INIT = 16'h0800; + defparam \vga/scancode_convert/scancode_rom/data<2>1111 .LOC = "CLB_R16C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1111 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3242) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1112 .INIT = 16'hAA00; + defparam \vga/scancode_convert/scancode_rom/data<2>1112 .LOC = "CLB_R16C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1112 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/sc [2]), + .O(N3243) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1_map1056/XUSED .LOC = "CLB_R16C37.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<2>1_map1056/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<2>1_map1056 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1056_0 ) + ); + defparam \vga/rom_addr_char<1>_mmx_out1_f5 .LOC = "CLB_R2C5.S0"; + X_MUX2 \vga/rom_addr_char<1>_mmx_out1_f5 ( + .IA(N3262), + .IB(N3261), + .SEL(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/rom_addr_char<1>_mmx_out ) + ); + defparam \vga/rom_addr_char<1>_mmx_out11 .INIT = 16'h373F; + defparam \vga/rom_addr_char<1>_mmx_out11 .LOC = "CLB_R2C5.S0"; + X_LUT4 \vga/rom_addr_char<1>_mmx_out11 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(N3261) + ); + defparam \vga/rom_addr_char<1>_mmx_out12 .INIT = 16'hFDFF; + defparam \vga/rom_addr_char<1>_mmx_out12 .LOC = "CLB_R2C5.S0"; + X_LUT4 \vga/rom_addr_char<1>_mmx_out12 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(N3262) + ); + defparam \vga/rom_addr_char<1>_mmx_out/XUSED .LOC = "CLB_R2C5.S0"; + X_BUF \vga/rom_addr_char<1>_mmx_out/XUSED ( + .I(\vga/rom_addr_char<1>_mmx_out ), + .O(\vga/rom_addr_char<1>_mmx_out_0 ) + ); + defparam \vga/charload237_f5 .LOC = "CLB_R13C8.S0"; + X_MUX2 \vga/charload237_f5 ( + .IA(N3229), + .IB(N3228), + .SEL(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [7]) + ); + defparam \vga/charload2371 .INIT = 16'hF000; + defparam \vga/charload2371 .LOC = "CLB_R13C8.S0"; + X_LUT4 \vga/charload2371 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/charload_19 ), + .ADR3(\vga/cursor_match_0 ), + .O(N3228) + ); + defparam \vga/charload2372 .INIT = 16'hF800; + defparam \vga/charload2372 .LOC = "CLB_R13C8.S0"; + X_LUT4 \vga/charload2372 ( + .ADR0(\vga/rom_addr_char [5]), + .ADR1(\vga/charload2_map865_0 ), + .ADR2(\vga/cursor_match_0 ), + .ADR3(\vga/charload_19 ), + .O(N3229) + ); + defparam \vga/rom_addr_char<2>_f51 .LOC = "CLB_R20C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f51 ( + .IA(\vga/N111234 ), + .IB(\vga/N01123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f512 ) + ); + defparam \vga/rom_addr_char<1>20 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>20 .LOC = "CLB_R20C3.S1"; + X_LUT4 \vga/rom_addr_char<1>20 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N143_0 ), + .ADR3(\vga/N142_0 ), + .O(\vga/N01123 ) + ); + defparam \vga/rom_addr_char<1>110 .INIT = 16'hCCF0; + defparam \vga/rom_addr_char<1>110 .LOC = "CLB_R20C3.S1"; + X_LUT4 \vga/rom_addr_char<1>110 ( + .ADR0(VCC), + .ADR1(\vga/N13_0 ), + .ADR2(\vga/N25_0 ), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N111234 ) + ); + defparam \vga/rom_addr_char<3>_f612/YUSED .LOC = "CLB_R20C3.S1"; + X_BUF \vga/rom_addr_char<3>_f612/YUSED ( + .I(\vga/rom_addr_char<3>_f612 ), + .O(\vga/rom_addr_char<3>_f612_0 ) + ); + defparam \vga/rom_addr_char<3>_f61 .LOC = "CLB_R20C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f61 ( + .IA(\vga/rom_addr_char<2>_f511_0 ), + .IB(\vga/rom_addr_char<2>_f512 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f612 ) + ); + defparam \vga/vgacore/vblank2_f5 .LOC = "CLB_R16C9.S0"; + X_MUX2 \vga/vgacore/vblank2_f5 ( + .IA(N3244), + .IB(\vga/vgacore/N51/FROM ), + .SEL(\vga/vgacore/vcnt [8]), + .O(\vga/vgacore/N51 ) + ); + defparam \vga/vgacore/N51/F .INIT = 16'h0000; + defparam \vga/vgacore/N51/F .LOC = "CLB_R16C9.S0"; + X_LUT4 \vga/vgacore/N51/F ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/vgacore/N51/FROM ) + ); + defparam \vga/vgacore/vblank21 .INIT = 16'h0001; + defparam \vga/vgacore/vblank21 .LOC = "CLB_R16C9.S0"; + X_LUT4 \vga/vgacore/vblank21 ( + .ADR0(\vga/vgacore/vcnt [5]), + .ADR1(\vga/vgacore/vcnt [7]), + .ADR2(\vga/vgacore/vcnt [6]), + .ADR3(\vga/vgacore/vcnt [4]), + .O(N3244) + ); + defparam \vga/vgacore/N51/XUSED .LOC = "CLB_R16C9.S0"; + X_BUF \vga/vgacore/N51/XUSED ( + .I(\vga/vgacore/N51 ), + .O(\vga/vgacore/N51_0 ) + ); + defparam \vga/rom_addr_char<2>_f52 .LOC = "CLB_R24C6.S1"; + X_MUX2 \vga/rom_addr_char<2>_f52 ( + .IA(\vga/N1112345 ), + .IB(\vga/N011234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5123 ) + ); + defparam \vga/rom_addr_char<1>24 .INIT = 16'hFC30; + defparam \vga/rom_addr_char<1>24 .LOC = "CLB_R24C6.S1"; + X_LUT4 \vga/rom_addr_char<1>24 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(\vga/N14 ), + .ADR3(\vga/N53_0 ), + .O(\vga/N011234 ) + ); + defparam \vga/rom_addr_char<1>112 .INIT = 16'hF000; + defparam \vga/rom_addr_char<1>112 .LOC = "CLB_R24C6.S1"; + X_LUT4 \vga/rom_addr_char<1>112 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/N40_0 ), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N1112345 ) + ); + defparam \vga/rom_addr_char<3>_f6123/YUSED .LOC = "CLB_R24C6.S1"; + X_BUF \vga/rom_addr_char<3>_f6123/YUSED ( + .I(\vga/rom_addr_char<3>_f6123 ), + .O(\vga/rom_addr_char<3>_f6123_0 ) + ); + defparam \vga/rom_addr_char<3>_f62 .LOC = "CLB_R24C6.S1"; + X_MUX2 \vga/rom_addr_char<3>_f62 ( + .IA(\vga/rom_addr_char<2>_f5112_0 ), + .IB(\vga/rom_addr_char<2>_f5123 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6123 ) + ); + defparam \vga/rom_addr_char<2>_f53 .LOC = "CLB_R9C1.S0"; + X_MUX2 \vga/rom_addr_char<2>_f53 ( + .IA(\vga/N11123456 ), + .IB(\vga/N0112345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51234 ) + ); + defparam \vga/rom_addr_char<1>26 .INIT = 16'hEE22; + defparam \vga/rom_addr_char<1>26 .LOC = "CLB_R9C1.S0"; + X_LUT4 \vga/rom_addr_char<1>26 ( + .ADR0(\vga/N94_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N95_0 ), + .O(\vga/N0112345 ) + ); + defparam \vga/rom_addr_char<1>114 .INIT = 16'h0C0C; + defparam \vga/rom_addr_char<1>114 .LOC = "CLB_R9C1.S0"; + X_LUT4 \vga/rom_addr_char<1>114 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(N3166_0), + .ADR3(VCC), + .O(\vga/N11123456 ) + ); + defparam \vga/rom_addr_char<2>_f51234/XUSED .LOC = "CLB_R9C1.S0"; + X_BUF \vga/rom_addr_char<2>_f51234/XUSED ( + .I(\vga/rom_addr_char<2>_f51234 ), + .O(\vga/rom_addr_char<2>_f51234_0 ) + ); + defparam \vga/rom_addr_char<2>_f54 .LOC = "CLB_R23C5.S1"; + X_MUX2 \vga/rom_addr_char<2>_f54 ( + .IA(\vga/N111234567 ), + .IB(\vga/N01123456 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f512345 ) + ); + defparam \vga/rom_addr_char<1>28 .INIT = 16'hF0CC; + defparam \vga/rom_addr_char<1>28 .LOC = "CLB_R23C5.S1"; + X_LUT4 \vga/rom_addr_char<1>28 ( + .ADR0(VCC), + .ADR1(\vga/N14 ), + .ADR2(\vga/N2_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N01123456 ) + ); + defparam \vga/rom_addr_char<1>116 .INIT = 16'hA0A0; + defparam \vga/rom_addr_char<1>116 .LOC = "CLB_R23C5.S1"; + X_LUT4 \vga/rom_addr_char<1>116 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N186_0 ), + .ADR3(VCC), + .O(\vga/N111234567 ) + ); + defparam \vga/rom_addr_char<3>_f612345/YUSED .LOC = "CLB_R23C5.S1"; + X_BUF \vga/rom_addr_char<3>_f612345/YUSED ( + .I(\vga/rom_addr_char<3>_f612345 ), + .O(\vga/rom_addr_char<3>_f612345_0 ) + ); + defparam \vga/rom_addr_char<3>_f64 .LOC = "CLB_R23C5.S1"; + X_MUX2 \vga/rom_addr_char<3>_f64 ( + .IA(\vga/rom_addr_char<2>_f511234_0 ), + .IB(\vga/rom_addr_char<2>_f512345 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f612345 ) + ); + defparam \vga/charload354_f5 .LOC = "CLB_R13C7.S0"; + X_MUX2 \vga/charload354_f5 ( + .IA(\vga/pixel_hold<0>_rt_89 ), + .IB(N3233), + .SEL(\vga/charload_19 ), + .O(\vga/_mux0002 [6]) + ); + defparam \vga/charload3541 .INIT = 16'hFF08; + defparam \vga/charload3541 .LOC = "CLB_R13C7.S0"; + X_LUT4 \vga/charload3541 ( + .ADR0(\vga/rom_addr_char [5]), + .ADR1(\vga/charload3_map953_0 ), + .ADR2(\vga/rom_addr_char [6]), + .ADR3(\vga/cursor_match_0 ), + .O(N3233) + ); + defparam \vga/pixel_hold<0>_rt .INIT = 16'hF0F0; + defparam \vga/pixel_hold<0>_rt .LOC = "CLB_R13C7.S0"; + X_LUT4 \vga/pixel_hold<0>_rt ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/pixel_hold [0]), + .ADR3(VCC), + .O(\vga/pixel_hold<0>_rt_89 ) + ); + defparam \vga/rom_addr_char<2>_f5_101 .LOC = "CLB_R27C12.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_101 ( + .IA(\vga/N2412 ), + .IB(\vga/N231 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51112 ) + ); + defparam \vga/rom_addr_char<1>22 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>22 .LOC = "CLB_R27C12.S0"; + X_LUT4 \vga/rom_addr_char<1>22 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N71_0 ), + .ADR3(\vga/N70_0 ), + .O(\vga/N231 ) + ); + defparam \vga/rom_addr_char<1>231 .INIT = 16'hEE44; + defparam \vga/rom_addr_char<1>231 .LOC = "CLB_R27C12.S0"; + X_LUT4 \vga/rom_addr_char<1>231 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N68_0 ), + .ADR2(VCC), + .ADR3(\vga/N69_0 ), + .O(\vga/N2412 ) + ); + defparam \vga/rom_addr_char<2>_f51112/F5USED .LOC = "CLB_R27C12.S0"; + X_BUF \vga/rom_addr_char<2>_f51112/F5USED ( + .I(\vga/rom_addr_char<2>_f51112 ), + .O(\vga/rom_addr_char<2>_f51112_0 ) + ); + defparam \vga/charload458_f5 .LOC = "CLB_R13C9.S0"; + X_MUX2 \vga/charload458_f5 ( + .IA(N3237), + .IB(N3236), + .SEL(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [2]) + ); + defparam \vga/charload4581 .INIT = 16'hFCAA; + defparam \vga/charload4581 .LOC = "CLB_R13C9.S0"; + X_LUT4 \vga/charload4581 ( + .ADR0(\vga/pixel_hold [4]), + .ADR1(\vga/rom_addr_char<5>_f5_0 ), + .ADR2(\vga/cursor_match_0 ), + .ADR3(\vga/charload_19 ), + .O(N3236) + ); + defparam \vga/charload4582 .INIT = 16'hFCB8; + defparam \vga/charload4582 .LOC = "CLB_R13C9.S0"; + X_LUT4 \vga/charload4582 ( + .ADR0(\vga/cursor_match_0 ), + .ADR1(\vga/charload_19 ), + .ADR2(\vga/pixel_hold [4]), + .ADR3(\vga/charload4_map979_0 ), + .O(N3237) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2319_f5 .LOC = "CLB_R17C36.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<1>2319_f5 ( + .IA(N3250), + .IB(N3249), + .SEL(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1751 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>23191 .INIT = 16'hAAAE; + defparam \vga/scancode_convert/scancode_rom/data<1>23191 .LOC = "CLB_R17C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>23191 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3249) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>23192 .INIT = 16'hCEFC; + defparam \vga/scancode_convert/scancode_rom/data<1>23192 .LOC = "CLB_R17C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>23192 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3250) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2_map1751/XUSED .LOC = "CLB_R17C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<1>2_map1751/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2_map1751 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1751_0 ) + ); + defparam \vga/rom_addr_char<5>_f51 .LOC = "CLB_R25C10.S1"; + X_MUX2 \vga/rom_addr_char<5>_f51 ( + .IA(\vga/N2512 ), + .IB(\vga/N16123 ), + .SEL(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f51_90 ) + ); + defparam \vga/rom_addr_char<4>4 .INIT = 16'hF0CC; + defparam \vga/rom_addr_char<4>4 .LOC = "CLB_R25C10.S1"; + X_LUT4 \vga/rom_addr_char<4>4 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char<3>_f6212_0 ), + .ADR2(\vga/rom_addr_char<3>_f6312_0 ), + .ADR3(\vga/rom_addr_char [4]), + .O(\vga/N16123 ) + ); + defparam \vga/rom_addr_char<4>12 .INIT = 16'hAACC; + defparam \vga/rom_addr_char<4>12 .LOC = "CLB_R25C10.S1"; + X_LUT4 \vga/rom_addr_char<4>12 ( + .ADR0(\vga/rom_addr_char<3>_f651_0 ), + .ADR1(\vga/rom_addr_char<3>_f641_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char [4]), + .O(\vga/N2512 ) + ); + defparam \vga/rom_addr_char<5>_f51/XUSED .LOC = "CLB_R25C10.S1"; + X_BUF \vga/rom_addr_char<5>_f51/XUSED ( + .I(\vga/rom_addr_char<5>_f51_90 ), + .O(\vga/rom_addr_char<5>_f51_0 ) + ); + defparam \vga/rom_addr_char<5>_f52 .LOC = "CLB_R26C9.S0"; + X_MUX2 \vga/rom_addr_char<5>_f52 ( + .IA(\vga/N23123 ), + .IB(\vga/N141234 ), + .SEL(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f512 ) + ); + defparam \vga/rom_addr_char<4>5 .INIT = 16'hCACA; + defparam \vga/rom_addr_char<4>5 .LOC = "CLB_R26C9.S0"; + X_LUT4 \vga/rom_addr_char<4>5 ( + .ADR0(\vga/rom_addr_char<3>_f61123_0 ), + .ADR1(\vga/rom_addr_char<3>_f62123_0 ), + .ADR2(\vga/rom_addr_char [4]), + .ADR3(VCC), + .O(\vga/N141234 ) + ); + defparam \vga/rom_addr_char<4>13 .INIT = 16'hFC0C; + defparam \vga/rom_addr_char<4>13 .LOC = "CLB_R26C9.S0"; + X_LUT4 \vga/rom_addr_char<4>13 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char<3>_f63123_0 ), + .ADR2(\vga/rom_addr_char [4]), + .ADR3(\vga/rom_addr_char<3>_f6412_0 ), + .O(\vga/N23123 ) + ); + defparam \vga/rom_addr_char<5>_f512/XUSED .LOC = "CLB_R26C9.S0"; + X_BUF \vga/rom_addr_char<5>_f512/XUSED ( + .I(\vga/rom_addr_char<5>_f512 ), + .O(\vga/rom_addr_char<5>_f512_0 ) + ); + defparam \vga/rom_addr_char<5>_f53 .LOC = "CLB_R8C3.S1"; + X_MUX2 \vga/rom_addr_char<5>_f53 ( + .IA(\vga/N231234 ), + .IB(\vga/N1612345 ), + .SEL(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f5123 ) + ); + defparam \vga/rom_addr_char<4>6 .INIT = 16'hDD88; + defparam \vga/rom_addr_char<4>6 .LOC = "CLB_R8C3.S1"; + X_LUT4 \vga/rom_addr_char<4>6 ( + .ADR0(\vga/rom_addr_char [4]), + .ADR1(\vga/rom_addr_char<3>_f631234_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char<3>_f621234_0 ), + .O(\vga/N1612345 ) + ); + defparam \vga/rom_addr_char<4>14 .INIT = 16'hE4E4; + defparam \vga/rom_addr_char<4>14 .LOC = "CLB_R8C3.S1"; + X_LUT4 \vga/rom_addr_char<4>14 ( + .ADR0(\vga/rom_addr_char [4]), + .ADR1(\vga/rom_addr_char<3>_f5_0 ), + .ADR2(\vga/rom_addr_char<3>_f64123_0 ), + .ADR3(VCC), + .O(\vga/N231234 ) + ); + defparam \vga/rom_addr_char<5>_f5123/XUSED .LOC = "CLB_R8C3.S1"; + X_BUF \vga/rom_addr_char<5>_f5123/XUSED ( + .I(\vga/rom_addr_char<5>_f5123 ), + .O(\vga/rom_addr_char<5>_f5123_0 ) + ); + defparam \vga/charload558_f5 .LOC = "CLB_R13C8.S1"; + X_MUX2 \vga/charload558_f5 ( + .IA(N3235), + .IB(N3234), + .SEL(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [4]) + ); + defparam \vga/charload5581 .INIT = 16'hFBC8; + defparam \vga/charload5581 .LOC = "CLB_R13C8.S1"; + X_LUT4 \vga/charload5581 ( + .ADR0(\vga/rom_addr_char<5>_f51_0 ), + .ADR1(\vga/charload_19 ), + .ADR2(\vga/cursor_match_0 ), + .ADR3(\vga/pixel_hold [2]), + .O(N3234) + ); + defparam \vga/charload5582 .INIT = 16'hFCB8; + defparam \vga/charload5582 .LOC = "CLB_R13C8.S1"; + X_LUT4 \vga/charload5582 ( + .ADR0(\vga/cursor_match_0 ), + .ADR1(\vga/charload_19 ), + .ADR2(\vga/pixel_hold [2]), + .ADR3(\vga/charload5_map965_0 ), + .O(N3235) + ); + defparam \vga/ps2/bitcnt_x<3> .LOC = "CLB_R7C19.S1"; + X_MUX2 \vga/ps2/bitcnt_x<3> ( + .IA(N3204), + .IB(N3205), + .SEL(\vga/ps2/ps2_clk_fall_edge_0 ), + .O(\vga/ps2/bitcnt_x [3]) + ); + defparam \vga/ps2/bitcnt_x<3>_G .INIT = 16'h6CCC; + defparam \vga/ps2/bitcnt_x<3>_G .LOC = "CLB_R7C19.S1"; + X_LUT4 \vga/ps2/bitcnt_x<3>_G ( + .ADR0(\vga/ps2/bitcnt_r [2]), + .ADR1(\vga/ps2/bitcnt_r [3]), + .ADR2(\vga/ps2/bitcnt_r [1]), + .ADR3(\vga/ps2/bitcnt_r [0]), + .O(N3205) + ); + defparam \vga/ps2/bitcnt_x<3>_F .INIT = 16'h020A; + defparam \vga/ps2/bitcnt_x<3>_F .LOC = "CLB_R7C19.S1"; + X_LUT4 \vga/ps2/bitcnt_x<3>_F ( + .ADR0(\vga/ps2/bitcnt_r [3]), + .ADR1(\vga/ps2/ps2_clk_r [1]), + .ADR2(\vga/ps2/error_r_16 ), + .ADR3(\vga/ps2/_cmp_eq0001 ), + .O(N3204) + ); + defparam \vga/ps2/bitcnt_r_3 .LOC = "CLB_R7C19.S1"; + defparam \vga/ps2/bitcnt_r_3 .INIT = 1'b0; + X_FF \vga/ps2/bitcnt_r_3 ( + .I(\vga/ps2/bitcnt_x [3]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/bitcnt_r<3>/FFX/RST ), + .O(\vga/ps2/bitcnt_r [3]) + ); + defparam \vga/ps2/bitcnt_r<3>/FFX/RSTOR .LOC = "CLB_R7C19.S1"; + X_INV \vga/ps2/bitcnt_r<3>/FFX/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/bitcnt_r<3>/FFX/RST ) + ); + defparam \vga/charload758_f5 .LOC = "CLB_R12C6.S0"; + X_MUX2 \vga/charload758_f5 ( + .IA(N3239), + .IB(N3238), + .SEL(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [1]) + ); + defparam \vga/charload7581 .INIT = 16'hFCAA; + defparam \vga/charload7581 .LOC = "CLB_R12C6.S0"; + X_LUT4 \vga/charload7581 ( + .ADR0(\vga/pixel_hold [5]), + .ADR1(\vga/cursor_match_0 ), + .ADR2(\vga/rom_addr_char<5>_f5123_0 ), + .ADR3(\vga/charload_19 ), + .O(N3238) + ); + defparam \vga/charload7582 .INIT = 16'hEEF0; + defparam \vga/charload7582 .LOC = "CLB_R12C6.S0"; + X_LUT4 \vga/charload7582 ( + .ADR0(\vga/charload7_map993_0 ), + .ADR1(\vga/cursor_match_0 ), + .ADR2(\vga/pixel_hold [5]), + .ADR3(\vga/charload_19 ), + .O(N3239) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>172_f5 .LOC = "CLB_R18C35.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<3>172_f5 ( + .IA(N3257), + .IB(N3256), + .SEL(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1171 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1721 .INIT = 16'hFCFA; + defparam \vga/scancode_convert/scancode_rom/data<3>1721 .LOC = "CLB_R18C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1721 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [2]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3256) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1722 .INIT = 16'hF0F4; + defparam \vga/scancode_convert/scancode_rom/data<3>1722 .LOC = "CLB_R18C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1722 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [2]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3257) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1_map1171/XUSED .LOC = "CLB_R18C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>1_map1171/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>1_map1171 ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1171_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>122_f5 .LOC = "CLB_R12C35.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<4>122_f5 ( + .IA(\vga/scancode_convert/sc<3>_rt_91 ), + .IB(N3248), + .SEL(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1548 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1221 .INIT = 16'hCDEF; + defparam \vga/scancode_convert/scancode_rom/data<4>1221 .LOC = "CLB_R12C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1221 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/scancode_rom/N12 ), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3248) + ); + defparam \vga/scancode_convert/sc<3>_rt .INIT = 16'hFF00; + defparam \vga/scancode_convert/sc<3>_rt .LOC = "CLB_R12C35.S1"; + X_LUT4 \vga/scancode_convert/sc<3>_rt ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/sc<3>_rt_91 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1_map1548/XUSED .LOC = "CLB_R12C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>1_map1548/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1_map1548 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1548_0 ) + ); + defparam \vga/ram_addr_mux<4>_f5 .LOC = "CLB_R15C4.S0"; + X_MUX2 \vga/ram_addr_mux<4>_f5 ( + .IA(N3220), + .IB(N3219), + .SEL(\vga/vgacore/vcnt [3]), + .O(\vga/ram_addr_mux [4]) + ); + defparam \vga/ram_addr_mux<4>1 .INIT = 16'h353A; + defparam \vga/ram_addr_mux<4>1 .LOC = "CLB_R15C4.S0"; + X_LUT4 \vga/ram_addr_mux<4>1 ( + .ADR0(\vga/crt/cursor_v [0]), + .ADR1(\vga/vgacore/hcnt [7]), + .ADR2(\vga/ram_we_n ), + .ADR3(\vga/crt/cursor_h [4]), + .O(N3219) + ); + defparam \vga/ram_addr_mux<4>2 .INIT = 16'hCC5A; + defparam \vga/ram_addr_mux<4>2 .LOC = "CLB_R15C4.S0"; + X_LUT4 \vga/ram_addr_mux<4>2 ( + .ADR0(\vga/crt/cursor_h [4]), + .ADR1(\vga/vgacore/hcnt [7]), + .ADR2(\vga/crt/cursor_v [0]), + .ADR3(\vga/ram_we_n ), + .O(N3220) + ); + defparam \vga/video_ram/ram_addr_w<4>/XUSED .LOC = "CLB_R15C4.S0"; + X_BUF \vga/video_ram/ram_addr_w<4>/XUSED ( + .I(\vga/ram_addr_mux [4]), + .O(\vga/ram_addr_mux<4>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_4 .LOC = "CLB_R15C4.S0"; + defparam \vga/video_ram/ram_addr_w_4 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_4 ( + .I(\vga/ram_addr_mux [4]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [4]) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2260_SW0 .LOC = "CLB_R14C36.S0"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<1>2260_SW0 ( + .IA(N3184), + .IB(N3185), + .SEL(\vga/scancode_convert/sc [2]), + .O(N3106) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2260_SW0_G .INIT = 16'h2A0A; + defparam \vga/scancode_convert/scancode_rom/data<1>2260_SW0_G .LOC = "CLB_R14C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2260_SW0_G ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/scancode_rom/data<1>2_map1729_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<1>2_map1717_0 ), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3185) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2260_SW0_F .INIT = 16'h0300; + defparam \vga/scancode_convert/scancode_rom/data<1>2260_SW0_F .LOC = "CLB_R14C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2260_SW0_F ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/scancode_rom/data<1>2_map1708_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<1>2_map1701_0 ), + .ADR3(\vga/scancode_convert/sc [5]), + .O(N3184) + ); + defparam \N3106/XUSED .LOC = "CLB_R14C36.S0"; + X_BUF \N3106/XUSED ( + .I(N3106), + .O(N3106_0) + ); + defparam \vga/charload217 .LOC = "CLB_R12C8.S0"; + X_MUX2 \vga/charload217 ( + .IA(N3210), + .IB(N3211), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/charload2_map865 ) + ); + defparam \vga/charload217_G .INIT = 16'h0200; + defparam \vga/charload217_G .LOC = "CLB_R12C8.S0"; + X_LUT4 \vga/charload217_G ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/rom_addr_char [4]), + .ADR2(\vga/rom_addr_char [2]), + .ADR3(\vga/N4 ), + .O(N3211) + ); + defparam \vga/charload217_F .INIT = 16'h0020; + defparam \vga/charload217_F .LOC = "CLB_R12C8.S0"; + X_LUT4 \vga/charload217_F ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(N3164_0), + .ADR2(\vga/rom_addr_char [2]), + .ADR3(\vga/rom_addr_char [4]), + .O(N3210) + ); + defparam \vga/charload2_map865/XUSED .LOC = "CLB_R12C8.S0"; + X_BUF \vga/charload2_map865/XUSED ( + .I(\vga/charload2_map865 ), + .O(\vga/charload2_map865_0 ) + ); + defparam \vga/crt/state_FFd3-In48_SW0 .LOC = "CLB_R16C18.S1"; + X_MUX2 \vga/crt/state_FFd3-In48_SW0 ( + .IA(N3208), + .IB(N3209), + .SEL(\vga/crt/state_FFd2_12 ), + .O(N3144) + ); + defparam \vga/crt/state_FFd3-In48_SW0_G .INIT = 16'hFFF3; + defparam \vga/crt/state_FFd3-In48_SW0_G .LOC = "CLB_R16C18.S1"; + X_LUT4 \vga/crt/state_FFd3-In48_SW0_G ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/strobe_out_15 ), + .ADR2(\vga/crt/state_FFd1_13 ), + .ADR3(\vga/scancode_convert/key_up_14 ), + .O(N3209) + ); + defparam \vga/crt/state_FFd3-In48_SW0_F .INIT = 16'h0020; + defparam \vga/crt/state_FFd3-In48_SW0_F .LOC = "CLB_R16C18.S1"; + X_LUT4 \vga/crt/state_FFd3-In48_SW0_F ( + .ADR0(\vga/crt/state_FFd3_11 ), + .ADR1(\vga/crt/newline_20 ), + .ADR2(\vga/crt/state_FFd1_13 ), + .ADR3(\vga/crt/_cmp_eq0001_0 ), + .O(N3208) + ); + defparam \N3144/XUSED .LOC = "CLB_R16C18.S1"; + X_BUF \N3144/XUSED ( + .I(N3144), + .O(N3144_0) + ); + defparam \vga/rom_addr_char<1>1641 .LOC = "CLB_R4C5.S0"; + X_MUX2 \vga/rom_addr_char<1>1641 ( + .IA(N3194), + .IB(N3195), + .SEL(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/rom_addr_char<1>112_92 ) + ); + defparam \vga/rom_addr_char<1>1641_G .INIT = 16'h21A5; + defparam \vga/rom_addr_char<1>1641_G .LOC = "CLB_R4C5.S0"; + X_LUT4 \vga/rom_addr_char<1>1641_G ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(N3195) + ); + defparam \vga/rom_addr_char<1>1641_F .INIT = 16'hE3E3; + defparam \vga/rom_addr_char<1>1641_F .LOC = "CLB_R4C5.S0"; + X_LUT4 \vga/rom_addr_char<1>1641_F ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(VCC), + .O(N3194) + ); + defparam \vga/rom_addr_char<1>112/XUSED .LOC = "CLB_R4C5.S0"; + X_BUF \vga/rom_addr_char<1>112/XUSED ( + .I(\vga/rom_addr_char<1>112_92 ), + .O(\vga/rom_addr_char<1>112_0 ) + ); + defparam \vga/rom_addr_char<1>1741 .LOC = "CLB_R3C5.S1"; + X_MUX2 \vga/rom_addr_char<1>1741 ( + .IA(N3196), + .IB(N3197), + .SEL(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/rom_addr_char<1>2_93 ) + ); + defparam \vga/rom_addr_char<1>1741_G .INIT = 16'h5775; + defparam \vga/rom_addr_char<1>1741_G .LOC = "CLB_R3C5.S1"; + X_LUT4 \vga/rom_addr_char<1>1741_G ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(N3197) + ); + defparam \vga/rom_addr_char<1>1741_F .INIT = 16'hFFDC; + defparam \vga/rom_addr_char<1>1741_F .LOC = "CLB_R3C5.S1"; + X_LUT4 \vga/rom_addr_char<1>1741_F ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(N3196) + ); + defparam \vga/rom_addr_char<1>2/XUSED .LOC = "CLB_R3C5.S1"; + X_BUF \vga/rom_addr_char<1>2/XUSED ( + .I(\vga/rom_addr_char<1>2_93 ), + .O(\vga/rom_addr_char<1>2_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_01 .LOC = "CLB_R20C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_01 ( + .IA(\vga/N3123 ), + .IB(\vga/N21234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f511 ) + ); + defparam \vga/rom_addr_char<1>21 .INIT = 16'hEE44; + defparam \vga/rom_addr_char<1>21 .LOC = "CLB_R20C3.S0"; + X_LUT4 \vga/rom_addr_char<1>21 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N138_0 ), + .ADR2(VCC), + .ADR3(\vga/N139_0 ), + .O(\vga/N21234 ) + ); + defparam \vga/rom_addr_char<1>31 .INIT = 16'hAACC; + defparam \vga/rom_addr_char<1>31 .LOC = "CLB_R20C3.S0"; + X_LUT4 \vga/rom_addr_char<1>31 ( + .ADR0(\vga/N137_0 ), + .ADR1(\vga/N47_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N3123 ) + ); + defparam \vga/rom_addr_char<2>_f511/F5USED .LOC = "CLB_R20C3.S0"; + X_BUF \vga/rom_addr_char<2>_f511/F5USED ( + .I(\vga/rom_addr_char<2>_f511 ), + .O(\vga/rom_addr_char<2>_f511_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_02 .LOC = "CLB_R24C6.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_02 ( + .IA(\vga/N31234 ), + .IB(\vga/N212345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5112 ) + ); + defparam \vga/rom_addr_char<1>25 .INIT = 16'hFA50; + defparam \vga/rom_addr_char<1>25 .LOC = "CLB_R24C6.S0"; + X_LUT4 \vga/rom_addr_char<1>25 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N49_0 ), + .ADR3(\vga/N50_0 ), + .O(\vga/N212345 ) + ); + defparam \vga/rom_addr_char<1>32 .INIT = 16'hEE22; + defparam \vga/rom_addr_char<1>32 .LOC = "CLB_R24C6.S0"; + X_LUT4 \vga/rom_addr_char<1>32 ( + .ADR0(\vga/N47_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N48_0 ), + .O(\vga/N31234 ) + ); + defparam \vga/rom_addr_char<2>_f5112/F5USED .LOC = "CLB_R24C6.S0"; + X_BUF \vga/rom_addr_char<2>_f5112/F5USED ( + .I(\vga/rom_addr_char<2>_f5112 ), + .O(\vga/rom_addr_char<2>_f5112_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_10 .LOC = "CLB_R27C13.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_10 ( + .IA(\vga/N241 ), + .IB(N3079), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5111 ) + ); + defparam \vga/rom_addr_char<2>_f5_102 .INIT = 16'hF0CC; + defparam \vga/rom_addr_char<2>_f5_102 .LOC = "CLB_R27C13.S0"; + X_LUT4 \vga/rom_addr_char<2>_f5_102 ( + .ADR0(VCC), + .ADR1(\vga/N70_0 ), + .ADR2(\vga/N71_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(N3079) + ); + defparam \vga/rom_addr_char<1>23 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>23 .LOC = "CLB_R27C13.S0"; + X_LUT4 \vga/rom_addr_char<1>23 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N64_0 ), + .ADR3(\vga/N155_0 ), + .O(\vga/N241 ) + ); + defparam \vga/rom_addr_char<2>_f5111/F5USED .LOC = "CLB_R27C13.S0"; + X_BUF \vga/rom_addr_char<2>_f5111/F5USED ( + .I(\vga/rom_addr_char<2>_f5111 ), + .O(\vga/rom_addr_char<2>_f5111_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_03 .LOC = "CLB_R11C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_03 ( + .IA(\vga/N312345 ), + .IB(\vga/N2123456 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51123 ) + ); + defparam \vga/rom_addr_char<1>33 .INIT = 16'hEE22; + defparam \vga/rom_addr_char<1>33 .LOC = "CLB_R11C3.S1"; + X_LUT4 \vga/rom_addr_char<1>33 ( + .ADR0(\vga/N104_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N105_0 ), + .O(\vga/N2123456 ) + ); + defparam \vga/rom_addr_char<1>43 .INIT = 16'h7861; + defparam \vga/rom_addr_char<1>43 .LOC = "CLB_R11C3.S1"; + X_LUT4 \vga/rom_addr_char<1>43 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N312345 ) + ); + defparam \vga/rom_addr_char<3>_f61234/YUSED .LOC = "CLB_R11C3.S1"; + X_BUF \vga/rom_addr_char<3>_f61234/YUSED ( + .I(\vga/rom_addr_char<3>_f61234 ), + .O(\vga/rom_addr_char<3>_f61234_0 ) + ); + defparam \vga/rom_addr_char<3>_f63 .LOC = "CLB_R11C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f63 ( + .IA(\vga/rom_addr_char<2>_f52123_0 ), + .IB(\vga/rom_addr_char<2>_f51123 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f61234 ) + ); + defparam \vga/rom_addr_char<2>_f5_11 .LOC = "CLB_R23C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_11 ( + .IA(\vga/N5 ), + .IB(\vga/N4123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f521 ) + ); + defparam \vga/rom_addr_char<1>41 .INIT = 16'hFA50; + defparam \vga/rom_addr_char<1>41 .LOC = "CLB_R23C3.S1"; + X_LUT4 \vga/rom_addr_char<1>41 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N150_0 ), + .ADR3(\vga/N151_0 ), + .O(\vga/N4123 ) + ); + defparam \vga/rom_addr_char<1>51 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>51 .LOC = "CLB_R23C3.S1"; + X_LUT4 \vga/rom_addr_char<1>51 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N149_0 ), + .ADR3(\vga/N55_0 ), + .O(\vga/N5 ) + ); + defparam \vga/rom_addr_char<3>_f611/YUSED .LOC = "CLB_R23C3.S1"; + X_BUF \vga/rom_addr_char<3>_f611/YUSED ( + .I(\vga/rom_addr_char<3>_f611 ), + .O(\vga/rom_addr_char<3>_f611_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_01 .LOC = "CLB_R23C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_01 ( + .IA(\vga/rom_addr_char<2>_f531_0 ), + .IB(\vga/rom_addr_char<2>_f521 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f611 ) + ); + defparam \vga/rom_addr_char<2>_f5_04 .LOC = "CLB_R23C5.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_04 ( + .IA(\vga/N3123456 ), + .IB(\vga/N21234567 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f511234 ) + ); + defparam \vga/rom_addr_char<1>29 .INIT = 16'hF0CC; + defparam \vga/rom_addr_char<1>29 .LOC = "CLB_R23C5.S0"; + X_LUT4 \vga/rom_addr_char<1>29 ( + .ADR0(VCC), + .ADR1(\vga/N184_0 ), + .ADR2(\vga/N8 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N21234567 ) + ); + defparam \vga/rom_addr_char<1>34 .INIT = 16'hA0A0; + defparam \vga/rom_addr_char<1>34 .LOC = "CLB_R23C5.S0"; + X_LUT4 \vga/rom_addr_char<1>34 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N183_0 ), + .ADR3(VCC), + .O(\vga/N3123456 ) + ); + defparam \vga/rom_addr_char<2>_f511234/F5USED .LOC = "CLB_R23C5.S0"; + X_BUF \vga/rom_addr_char<2>_f511234/F5USED ( + .I(\vga/rom_addr_char<2>_f511234 ), + .O(\vga/rom_addr_char<2>_f511234_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_12 .LOC = "CLB_R24C11.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_12 ( + .IA(\vga/N5123 ), + .IB(\vga/N41234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5212 ) + ); + defparam \vga/rom_addr_char<1>42 .INIT = 16'hFC0C; + defparam \vga/rom_addr_char<1>42 .LOC = "CLB_R24C11.S1"; + X_LUT4 \vga/rom_addr_char<1>42 ( + .ADR0(VCC), + .ADR1(\vga/N59_0 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N60_0 ), + .O(\vga/N41234 ) + ); + defparam \vga/rom_addr_char<1>52 .INIT = 16'h0A0A; + defparam \vga/rom_addr_char<1>52 .LOC = "CLB_R24C11.S1"; + X_LUT4 \vga/rom_addr_char<1>52 ( + .ADR0(\vga/N58_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(VCC), + .O(\vga/N5123 ) + ); + defparam \vga/rom_addr_char<3>_f6112/YUSED .LOC = "CLB_R24C11.S1"; + X_BUF \vga/rom_addr_char<3>_f6112/YUSED ( + .I(\vga/rom_addr_char<3>_f6112 ), + .O(\vga/rom_addr_char<3>_f6112_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_02 .LOC = "CLB_R24C11.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_02 ( + .IA(\vga/rom_addr_char<2>_f5312_0 ), + .IB(\vga/rom_addr_char<2>_f5212 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6112 ) + ); + defparam \vga/rom_addr_char<2>_f5_13 .LOC = "CLB_R11C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_13 ( + .IA(\vga/N51234 ), + .IB(\vga/N412345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f52123 ) + ); + defparam \vga/rom_addr_char<1>53 .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<1>53 .LOC = "CLB_R11C3.S0"; + X_LUT4 \vga/rom_addr_char<1>53 ( + .ADR0(VCC), + .ADR1(\vga/N102_0 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N101_0 ), + .O(\vga/N412345 ) + ); + defparam \vga/rom_addr_char<1>63 .INIT = 16'hFA0A; + defparam \vga/rom_addr_char<1>63 .LOC = "CLB_R11C3.S0"; + X_LUT4 \vga/rom_addr_char<1>63 ( + .ADR0(\vga/N99_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N55_0 ), + .O(\vga/N51234 ) + ); + defparam \vga/rom_addr_char<2>_f52123/F5USED .LOC = "CLB_R11C3.S0"; + X_BUF \vga/rom_addr_char<2>_f52123/F5USED ( + .I(\vga/rom_addr_char<2>_f52123 ), + .O(\vga/rom_addr_char<2>_f52123_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_21 .LOC = "CLB_R23C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_21 ( + .IA(\vga/N7123 ), + .IB(\vga/N6123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f531 ) + ); + defparam \vga/rom_addr_char<1>61 .INIT = 16'hAAF0; + defparam \vga/rom_addr_char<1>61 .LOC = "CLB_R23C3.S0"; + X_LUT4 \vga/rom_addr_char<1>61 ( + .ADR0(\vga/N147_0 ), + .ADR1(VCC), + .ADR2(\vga/N146_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N6123 ) + ); + defparam \vga/rom_addr_char<1>71 .INIT = 16'hCCAA; + defparam \vga/rom_addr_char<1>71 .LOC = "CLB_R23C3.S0"; + X_LUT4 \vga/rom_addr_char<1>71 ( + .ADR0(\vga/N144_0 ), + .ADR1(\vga/N145_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N7123 ) + ); + defparam \vga/rom_addr_char<2>_f531/F5USED .LOC = "CLB_R23C3.S0"; + X_BUF \vga/rom_addr_char<2>_f531/F5USED ( + .I(\vga/rom_addr_char<2>_f531 ), + .O(\vga/rom_addr_char<2>_f531_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_14 .LOC = "CLB_R16C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_14 ( + .IA(\vga/N512345 ), + .IB(\vga/N4123456 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f521234 ) + ); + defparam \vga/rom_addr_char<1>44 .INIT = 16'hFC0C; + defparam \vga/rom_addr_char<1>44 .LOC = "CLB_R16C3.S1"; + X_LUT4 \vga/rom_addr_char<1>44 ( + .ADR0(VCC), + .ADR1(\vga/N194_0 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N15_0 ), + .O(\vga/N4123456 ) + ); + defparam \vga/rom_addr_char<1>54 .INIT = 16'h00F0; + defparam \vga/rom_addr_char<1>54 .LOC = "CLB_R16C3.S1"; + X_LUT4 \vga/rom_addr_char<1>54 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/N193_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N512345 ) + ); + defparam \vga/rom_addr_char<3>_f611234/YUSED .LOC = "CLB_R16C3.S1"; + X_BUF \vga/rom_addr_char<3>_f611234/YUSED ( + .I(\vga/rom_addr_char<3>_f611234 ), + .O(\vga/rom_addr_char<3>_f611234_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_04 .LOC = "CLB_R16C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_04 ( + .IA(\vga/rom_addr_char<2>_f531234_0 ), + .IB(\vga/rom_addr_char<2>_f521234 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f611234 ) + ); + defparam \vga/rom_addr_char<2>_f5_22 .LOC = "CLB_R24C11.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_22 ( + .IA(\vga/N71234 ), + .IB(\vga/N61234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5312 ) + ); + defparam \vga/rom_addr_char<1>62 .INIT = 16'hB8B8; + defparam \vga/rom_addr_char<1>62 .LOC = "CLB_R24C11.S0"; + X_LUT4 \vga/rom_addr_char<1>62 ( + .ADR0(\vga/N57_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(\vga/N56_0 ), + .ADR3(VCC), + .O(\vga/N61234 ) + ); + defparam \vga/rom_addr_char<1>72 .INIT = 16'hBB88; + defparam \vga/rom_addr_char<1>72 .LOC = "CLB_R24C11.S0"; + X_LUT4 \vga/rom_addr_char<1>72 ( + .ADR0(\vga/N55_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N54_0 ), + .O(\vga/N71234 ) + ); + defparam \vga/rom_addr_char<2>_f5312/F5USED .LOC = "CLB_R24C11.S0"; + X_BUF \vga/rom_addr_char<2>_f5312/F5USED ( + .I(\vga/rom_addr_char<2>_f5312 ), + .O(\vga/rom_addr_char<2>_f5312_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_23 .LOC = "CLB_R26C5.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_23 ( + .IA(\vga/N712345 ), + .IB(\vga/N612345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f53123 ) + ); + defparam \vga/rom_addr_char<1>73 .INIT = 16'hACAC; + defparam \vga/rom_addr_char<1>73 .LOC = "CLB_R26C5.S1"; + X_LUT4 \vga/rom_addr_char<1>73 ( + .ADR0(\vga/N128_0 ), + .ADR1(\vga/N127_0 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(VCC), + .O(\vga/N612345 ) + ); + defparam \vga/rom_addr_char<1>83 .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<1>83 .LOC = "CLB_R26C5.S1"; + X_LUT4 \vga/rom_addr_char<1>83 ( + .ADR0(VCC), + .ADR1(\vga/N126_0 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N125_0 ), + .O(\vga/N712345 ) + ); + defparam \vga/rom_addr_char<3>_f61123/YUSED .LOC = "CLB_R26C5.S1"; + X_BUF \vga/rom_addr_char<3>_f61123/YUSED ( + .I(\vga/rom_addr_char<3>_f61123 ), + .O(\vga/rom_addr_char<3>_f61123_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_03 .LOC = "CLB_R26C5.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_03 ( + .IA(\vga/rom_addr_char<2>_f54123_0 ), + .IB(\vga/rom_addr_char<2>_f53123 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f61123 ) + ); + defparam \vga/rom_addr_char<2>_f5_31 .LOC = "CLB_R27C5.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_31 ( + .IA(\vga/N9 ), + .IB(\vga/N8123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f541 ) + ); + defparam \vga/rom_addr_char<1>81 .INIT = 16'hEE44; + defparam \vga/rom_addr_char<1>81 .LOC = "CLB_R27C5.S1"; + X_LUT4 \vga/rom_addr_char<1>81 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N53_0 ), + .ADR2(VCC), + .ADR3(\vga/N128_0 ), + .O(\vga/N8123 ) + ); + defparam \vga/rom_addr_char<1>91 .INIT = 16'hF0AA; + defparam \vga/rom_addr_char<1>91 .LOC = "CLB_R27C5.S1"; + X_LUT4 \vga/rom_addr_char<1>91 ( + .ADR0(\vga/N171_0 ), + .ADR1(VCC), + .ADR2(\vga/N172_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N9 ) + ); + defparam \vga/rom_addr_char<3>_f621/YUSED .LOC = "CLB_R27C5.S1"; + X_BUF \vga/rom_addr_char<3>_f621/YUSED ( + .I(\vga/rom_addr_char<3>_f621 ), + .O(\vga/rom_addr_char<3>_f621_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_11 .LOC = "CLB_R27C5.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_11 ( + .IA(\vga/rom_addr_char<2>_f551_0 ), + .IB(\vga/rom_addr_char<2>_f541 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f621 ) + ); + defparam \vga/rom_addr_char<2>_f5_24 .LOC = "CLB_R16C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_24 ( + .IA(\vga/N7123456 ), + .IB(\vga/N6123456 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f531234 ) + ); + defparam \vga/rom_addr_char<1>64 .INIT = 16'hFA50; + defparam \vga/rom_addr_char<1>64 .LOC = "CLB_R16C3.S0"; + X_LUT4 \vga/rom_addr_char<1>64 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N191_0 ), + .ADR3(\vga/N192_0 ), + .O(\vga/N6123456 ) + ); + defparam \vga/rom_addr_char<1>74 .INIT = 16'hBB88; + defparam \vga/rom_addr_char<1>74 .LOC = "CLB_R16C3.S0"; + X_LUT4 \vga/rom_addr_char<1>74 ( + .ADR0(\vga/N190_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N16_0 ), + .O(\vga/N7123456 ) + ); + defparam \vga/rom_addr_char<2>_f531234/F5USED .LOC = "CLB_R16C3.S0"; + X_BUF \vga/rom_addr_char<2>_f531234/F5USED ( + .I(\vga/rom_addr_char<2>_f531234 ), + .O(\vga/rom_addr_char<2>_f531234_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_32 .LOC = "CLB_R26C8.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_32 ( + .IA(\vga/N91 ), + .IB(\vga/N81234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5412 ) + ); + defparam \vga/rom_addr_char<1>82 .INIT = 16'hDD88; + defparam \vga/rom_addr_char<1>82 .LOC = "CLB_R26C8.S1"; + X_LUT4 \vga/rom_addr_char<1>82 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N83_0 ), + .ADR2(VCC), + .ADR3(\vga/N82_0 ), + .O(\vga/N81234 ) + ); + defparam \vga/rom_addr_char<1>92 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>92 .LOC = "CLB_R26C8.S1"; + X_LUT4 \vga/rom_addr_char<1>92 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(VCC), + .ADR2(\vga/N81_0 ), + .ADR3(\vga/N80_0 ), + .O(\vga/N91 ) + ); + defparam \vga/rom_addr_char<3>_f6212/YUSED .LOC = "CLB_R26C8.S1"; + X_BUF \vga/rom_addr_char<3>_f6212/YUSED ( + .I(\vga/rom_addr_char<3>_f6212 ), + .O(\vga/rom_addr_char<3>_f6212_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_12 .LOC = "CLB_R26C8.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_12 ( + .IA(\vga/rom_addr_char<2>_f5512_0 ), + .IB(\vga/rom_addr_char<2>_f5412 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6212 ) + ); + defparam \vga/rom_addr_char<2>_f5_33 .LOC = "CLB_R26C5.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_33 ( + .IA(\vga/N9123 ), + .IB(\vga/N10123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f54123 ) + ); + defparam \vga/rom_addr_char<1>102 .INIT = 16'hEE44; + defparam \vga/rom_addr_char<1>102 .LOC = "CLB_R26C5.S0"; + X_LUT4 \vga/rom_addr_char<1>102 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/N78_0 ), + .ADR2(VCC), + .ADR3(\vga/N79_0 ), + .O(\vga/N10123 ) + ); + defparam \vga/rom_addr_char<1>103 .INIT = 16'h5D08; + defparam \vga/rom_addr_char<1>103 .LOC = "CLB_R26C5.S0"; + X_LUT4 \vga/rom_addr_char<1>103 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/N121_0 ), + .O(\vga/N9123 ) + ); + defparam \vga/rom_addr_char<2>_f54123/F5USED .LOC = "CLB_R26C5.S0"; + X_BUF \vga/rom_addr_char<2>_f54123/F5USED ( + .I(\vga/rom_addr_char<2>_f54123 ), + .O(\vga/rom_addr_char<2>_f54123_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_41 .LOC = "CLB_R27C5.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_41 ( + .IA(\vga/N11112 ), + .IB(\vga/N1012 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f551 ) + ); + defparam \vga/rom_addr_char<1>101 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>101 .LOC = "CLB_R27C5.S0"; + X_LUT4 \vga/rom_addr_char<1>101 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N170_0 ), + .ADR3(\vga/N78_0 ), + .O(\vga/N1012 ) + ); + defparam \vga/rom_addr_char<1>111 .INIT = 16'h7250; + defparam \vga/rom_addr_char<1>111 .LOC = "CLB_R27C5.S0"; + X_LUT4 \vga/rom_addr_char<1>111 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/N167_0 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N11112 ) + ); + defparam \vga/rom_addr_char<2>_f551/F5USED .LOC = "CLB_R27C5.S0"; + X_BUF \vga/rom_addr_char<2>_f551/F5USED ( + .I(\vga/rom_addr_char<2>_f551 ), + .O(\vga/rom_addr_char<2>_f551_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_34 .LOC = "CLB_R5C3.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_34 ( + .IA(\vga/N91234 ), + .IB(\vga/N8123456 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f541234 ) + ); + defparam \vga/rom_addr_char<1>84 .INIT = 16'hAACC; + defparam \vga/rom_addr_char<1>84 .LOC = "CLB_R5C3.S1"; + X_LUT4 \vga/rom_addr_char<1>84 ( + .ADR0(\vga/N213_0 ), + .ADR1(\vga/N41_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N8123456 ) + ); + defparam \vga/rom_addr_char<1>94 .INIT = 16'hE4E4; + defparam \vga/rom_addr_char<1>94 .LOC = "CLB_R5C3.S1"; + X_LUT4 \vga/rom_addr_char<1>94 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N27_0 ), + .ADR2(\vga/N29_0 ), + .ADR3(VCC), + .O(\vga/N91234 ) + ); + defparam \vga/rom_addr_char<3>_f621234/YUSED .LOC = "CLB_R5C3.S1"; + X_BUF \vga/rom_addr_char<3>_f621234/YUSED ( + .I(\vga/rom_addr_char<3>_f621234 ), + .O(\vga/rom_addr_char<3>_f621234_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_14 .LOC = "CLB_R5C3.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_14 ( + .IA(\vga/rom_addr_char<2>_f551234_0 ), + .IB(\vga/rom_addr_char<2>_f541234 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f621234 ) + ); + defparam \vga/rom_addr_char<2>_f5_42 .LOC = "CLB_R26C8.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_42 ( + .IA(\vga/N111123 ), + .IB(N3080), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5512 ) + ); + defparam \vga/rom_addr_char<2>_f5_421 .INIT = 16'hEE22; + defparam \vga/rom_addr_char<2>_f5_421 .LOC = "CLB_R26C8.S0"; + X_LUT4 \vga/rom_addr_char<2>_f5_421 ( + .ADR0(\vga/N78_0 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N79_0 ), + .O(N3080) + ); + defparam \vga/rom_addr_char<1>113 .INIT = 16'h00D8; + defparam \vga/rom_addr_char<1>113 .LOC = "CLB_R26C8.S0"; + X_LUT4 \vga/rom_addr_char<1>113 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(N3170_0), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N111123 ) + ); + defparam \vga/rom_addr_char<2>_f5512/F5USED .LOC = "CLB_R26C8.S0"; + X_BUF \vga/rom_addr_char<2>_f5512/F5USED ( + .I(\vga/rom_addr_char<2>_f5512 ), + .O(\vga/rom_addr_char<2>_f5512_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_43 .LOC = "CLB_R22C2.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_43 ( + .IA(\vga/N1110 ), + .IB(\vga/N101234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f55123 ) + ); + defparam \vga/rom_addr_char<1>115 .INIT = 16'hEE44; + defparam \vga/rom_addr_char<1>115 .LOC = "CLB_R22C2.S1"; + X_LUT4 \vga/rom_addr_char<1>115 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/N133_0 ), + .ADR2(VCC), + .ADR3(\vga/N134_0 ), + .O(\vga/N101234 ) + ); + defparam \vga/rom_addr_char<1>123 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>123 .LOC = "CLB_R22C2.S1"; + X_LUT4 \vga/rom_addr_char<1>123 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N132_0 ), + .ADR3(\vga/N131_0 ), + .O(\vga/N1110 ) + ); + defparam \vga/rom_addr_char<3>_f62123/YUSED .LOC = "CLB_R22C2.S1"; + X_BUF \vga/rom_addr_char<3>_f62123/YUSED ( + .I(\vga/rom_addr_char<3>_f62123 ), + .O(\vga/rom_addr_char<3>_f62123_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_13 .LOC = "CLB_R22C2.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_13 ( + .IA(\vga/rom_addr_char<2>_f56123_0 ), + .IB(\vga/rom_addr_char<2>_f55123 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f62123 ) + ); + defparam \vga/rom_addr_char<2>_f5_51 .LOC = "CLB_R25C12.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_51 ( + .IA(\vga/N1312 ), + .IB(\vga/N1212 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f561 ) + ); + defparam \vga/rom_addr_char<1>121 .INIT = 16'h0033; + defparam \vga/rom_addr_char<1>121 .LOC = "CLB_R25C12.S1"; + X_LUT4 \vga/rom_addr_char<1>121 ( + .ADR0(VCC), + .ADR1(N3160_0), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N1212 ) + ); + defparam \vga/rom_addr_char<1>131 .INIT = 16'hACAC; + defparam \vga/rom_addr_char<1>131 .LOC = "CLB_R25C12.S1"; + X_LUT4 \vga/rom_addr_char<1>131 ( + .ADR0(\vga/N179_0 ), + .ADR1(\vga/N178_0 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(VCC), + .O(\vga/N1312 ) + ); + defparam \vga/rom_addr_char<3>_f631/YUSED .LOC = "CLB_R25C12.S1"; + X_BUF \vga/rom_addr_char<3>_f631/YUSED ( + .I(\vga/rom_addr_char<3>_f631 ), + .O(\vga/rom_addr_char<3>_f631_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_21 .LOC = "CLB_R25C12.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_21 ( + .IA(\vga/rom_addr_char<2>_f571_0 ), + .IB(\vga/rom_addr_char<2>_f561 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f631 ) + ); + defparam \vga/rom_addr_char<2>_f5_44 .LOC = "CLB_R5C3.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_44 ( + .IA(\vga/N1111234 ), + .IB(\vga/N1012345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f551234 ) + ); + defparam \vga/rom_addr_char<1>104 .INIT = 16'h0388; + defparam \vga/rom_addr_char<1>104 .LOC = "CLB_R5C3.S0"; + X_LUT4 \vga/rom_addr_char<1>104 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(N3148_0), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N1012345 ) + ); + defparam \vga/rom_addr_char<1>117 .INIT = 16'hAFA0; + defparam \vga/rom_addr_char<1>117 .LOC = "CLB_R5C3.S0"; + X_LUT4 \vga/rom_addr_char<1>117 ( + .ADR0(\vga/N208_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N2_0 ), + .O(\vga/N1111234 ) + ); + defparam \vga/rom_addr_char<2>_f551234/F5USED .LOC = "CLB_R5C3.S0"; + X_BUF \vga/rom_addr_char<2>_f551234/F5USED ( + .I(\vga/rom_addr_char<2>_f551234 ), + .O(\vga/rom_addr_char<2>_f551234_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_52 .LOC = "CLB_R21C11.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_52 ( + .IA(\vga/N13123 ), + .IB(\vga/N12123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5612 ) + ); + defparam \vga/rom_addr_char<1>122 .INIT = 16'hE2E2; + defparam \vga/rom_addr_char<1>122 .LOC = "CLB_R21C11.S1"; + X_LUT4 \vga/rom_addr_char<1>122 ( + .ADR0(\vga/N89_0 ), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N90_0 ), + .ADR3(VCC), + .O(\vga/N12123 ) + ); + defparam \vga/rom_addr_char<1>132 .INIT = 16'hE2E2; + defparam \vga/rom_addr_char<1>132 .LOC = "CLB_R21C11.S1"; + X_LUT4 \vga/rom_addr_char<1>132 ( + .ADR0(\vga/N87_0 ), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N88_0 ), + .ADR3(VCC), + .O(\vga/N13123 ) + ); + defparam \vga/rom_addr_char<3>_f6312/YUSED .LOC = "CLB_R21C11.S1"; + X_BUF \vga/rom_addr_char<3>_f6312/YUSED ( + .I(\vga/rom_addr_char<3>_f6312 ), + .O(\vga/rom_addr_char<3>_f6312_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_22 .LOC = "CLB_R21C11.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_22 ( + .IA(\vga/rom_addr_char<2>_f5712_0 ), + .IB(\vga/rom_addr_char<2>_f5612 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6312 ) + ); + defparam \vga/rom_addr_char<2>_f5_53 .LOC = "CLB_R22C2.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_53 ( + .IA(\vga/N131234 ), + .IB(\vga/N121234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f56123 ) + ); + defparam \vga/rom_addr_char<1>133 .INIT = 16'hF0AA; + defparam \vga/rom_addr_char<1>133 .LOC = "CLB_R22C2.S0"; + X_LUT4 \vga/rom_addr_char<1>133 ( + .ADR0(\vga/N129_0 ), + .ADR1(VCC), + .ADR2(\vga/N130_0 ), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N121234 ) + ); + defparam \vga/rom_addr_char<1>143 .INIT = 16'hCC0A; + defparam \vga/rom_addr_char<1>143 .LOC = "CLB_R22C2.S0"; + X_LUT4 \vga/rom_addr_char<1>143 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/N78_0 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N131234 ) + ); + defparam \vga/rom_addr_char<2>_f56123/F5USED .LOC = "CLB_R22C2.S0"; + X_BUF \vga/rom_addr_char<2>_f56123/F5USED ( + .I(\vga/rom_addr_char<2>_f56123 ), + .O(\vga/rom_addr_char<2>_f56123_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_61 .LOC = "CLB_R25C12.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_61 ( + .IA(\vga/N1512 ), + .IB(\vga/N1412 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f571 ) + ); + defparam \vga/rom_addr_char<1>141 .INIT = 16'hCCAA; + defparam \vga/rom_addr_char<1>141 .LOC = "CLB_R25C12.S0"; + X_LUT4 \vga/rom_addr_char<1>141 ( + .ADR0(\vga/N176_0 ), + .ADR1(\vga/N86_0 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N1412 ) + ); + defparam \vga/rom_addr_char<1>151 .INIT = 16'hD1C0; + defparam \vga/rom_addr_char<1>151 .LOC = "CLB_R25C12.S0"; + X_LUT4 \vga/rom_addr_char<1>151 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N175_0 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N1512 ) + ); + defparam \vga/rom_addr_char<2>_f571/F5USED .LOC = "CLB_R25C12.S0"; + X_BUF \vga/rom_addr_char<2>_f571/F5USED ( + .I(\vga/rom_addr_char<2>_f571 ), + .O(\vga/rom_addr_char<2>_f571_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_54 .LOC = "CLB_R3C2.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_54 ( + .IA(\vga/N1312345 ), + .IB(\vga/N1212345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f561234 ) + ); + defparam \vga/rom_addr_char<1>124 .INIT = 16'hF000; + defparam \vga/rom_addr_char<1>124 .LOC = "CLB_R3C2.S1"; + X_LUT4 \vga/rom_addr_char<1>124 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N134_0 ), + .O(\vga/N1212345 ) + ); + defparam \vga/rom_addr_char<1>134 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>134 .LOC = "CLB_R3C2.S1"; + X_LUT4 \vga/rom_addr_char<1>134 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N219_0 ), + .ADR3(\vga/N218_0 ), + .O(\vga/N1312345 ) + ); + defparam \vga/rom_addr_char<3>_f631234/YUSED .LOC = "CLB_R3C2.S1"; + X_BUF \vga/rom_addr_char<3>_f631234/YUSED ( + .I(\vga/rom_addr_char<3>_f631234 ), + .O(\vga/rom_addr_char<3>_f631234_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_24 .LOC = "CLB_R3C2.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_24 ( + .IA(\vga/rom_addr_char<2>_f571234_0 ), + .IB(\vga/rom_addr_char<2>_f561234 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f631234 ) + ); + defparam \vga/rom_addr_char<2>_f5_62 .LOC = "CLB_R21C11.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_62 ( + .IA(\vga/N15123 ), + .IB(\vga/N14123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5712 ) + ); + defparam \vga/rom_addr_char<1>142 .INIT = 16'hFC0C; + defparam \vga/rom_addr_char<1>142 .LOC = "CLB_R21C11.S0"; + X_LUT4 \vga/rom_addr_char<1>142 ( + .ADR0(VCC), + .ADR1(\vga/N85_0 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N86_0 ), + .O(\vga/N14123 ) + ); + defparam \vga/rom_addr_char<1>152 .INIT = 16'h1310; + defparam \vga/rom_addr_char<1>152 .LOC = "CLB_R21C11.S0"; + X_LUT4 \vga/rom_addr_char<1>152 ( + .ADR0(N3172_0), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N15123 ) + ); + defparam \vga/rom_addr_char<2>_f5712/F5USED .LOC = "CLB_R21C11.S0"; + X_BUF \vga/rom_addr_char<2>_f5712/F5USED ( + .I(\vga/rom_addr_char<2>_f5712 ), + .O(\vga/rom_addr_char<2>_f5712_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_63 .LOC = "CLB_R26C15.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_63 ( + .IA(\vga/N161234 ), + .IB(\vga/N151234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f57123 ) + ); + defparam \vga/rom_addr_char<1>153 .INIT = 16'hDD88; + defparam \vga/rom_addr_char<1>153 .LOC = "CLB_R26C15.S1"; + X_LUT4 \vga/rom_addr_char<1>153 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/N113_0 ), + .ADR2(VCC), + .ADR3(\vga/N82_0 ), + .O(\vga/N151234 ) + ); + defparam \vga/rom_addr_char<1>163 .INIT = 16'hFA0A; + defparam \vga/rom_addr_char<1>163 .LOC = "CLB_R26C15.S1"; + X_LUT4 \vga/rom_addr_char<1>163 ( + .ADR0(\vga/N110_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N111_0 ), + .O(\vga/N161234 ) + ); + defparam \vga/rom_addr_char<3>_f63123/YUSED .LOC = "CLB_R26C15.S1"; + X_BUF \vga/rom_addr_char<3>_f63123/YUSED ( + .I(\vga/rom_addr_char<3>_f63123 ), + .O(\vga/rom_addr_char<3>_f63123_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_23 .LOC = "CLB_R26C15.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_23 ( + .IA(\vga/rom_addr_char<2>_f58123_0 ), + .IB(\vga/rom_addr_char<2>_f57123 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f63123 ) + ); + defparam \vga/rom_addr_char<2>_f5_71 .LOC = "CLB_R25C13.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_71 ( + .IA(\vga/N1812 ), + .IB(\vga/N1712 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f581 ) + ); + defparam \vga/rom_addr_char<1>161 .INIT = 16'hF3C0; + defparam \vga/rom_addr_char<1>161 .LOC = "CLB_R25C13.S1"; + X_LUT4 \vga/rom_addr_char<1>161 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N159_0 ), + .ADR3(\vga/N67_0 ), + .O(\vga/N1712 ) + ); + defparam \vga/rom_addr_char<1>171 .INIT = 16'hFC0C; + defparam \vga/rom_addr_char<1>171 .LOC = "CLB_R25C13.S1"; + X_LUT4 \vga/rom_addr_char<1>171 ( + .ADR0(VCC), + .ADR1(\vga/N65_0 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N157_0 ), + .O(\vga/N1812 ) + ); + defparam \vga/rom_addr_char<3>_f64/YUSED .LOC = "CLB_R25C13.S1"; + X_BUF \vga/rom_addr_char<3>_f64/YUSED ( + .I(\vga/rom_addr_char<3>_f64_94 ), + .O(\vga/rom_addr_char<3>_f64_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_3 .LOC = "CLB_R25C13.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_3 ( + .IA(\vga/rom_addr_char<2>_f591_0 ), + .IB(\vga/rom_addr_char<2>_f581 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f64_94 ) + ); + defparam \vga/rom_addr_char<2>_f5_64 .LOC = "CLB_R3C2.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_64 ( + .IA(\vga/N1512345 ), + .IB(\vga/N1412345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f571234 ) + ); + defparam \vga/rom_addr_char<1>144 .INIT = 16'hF3C0; + defparam \vga/rom_addr_char<1>144 .LOC = "CLB_R3C2.S0"; + X_LUT4 \vga/rom_addr_char<1>144 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N45_0 ), + .ADR3(\vga/N216_0 ), + .O(\vga/N1412345 ) + ); + defparam \vga/rom_addr_char<1>154 .INIT = 16'hBB88; + defparam \vga/rom_addr_char<1>154 .LOC = "CLB_R3C2.S0"; + X_LUT4 \vga/rom_addr_char<1>154 ( + .ADR0(\vga/N215_0 ), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(VCC), + .ADR3(\vga/N214_0 ), + .O(\vga/N1512345 ) + ); + defparam \vga/rom_addr_char<2>_f571234/F5USED .LOC = "CLB_R3C2.S0"; + X_BUF \vga/rom_addr_char<2>_f571234/F5USED ( + .I(\vga/rom_addr_char<2>_f571234 ), + .O(\vga/rom_addr_char<2>_f571234_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_72 .LOC = "CLB_R25C15.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_72 ( + .IA(\vga/N18123 ), + .IB(\vga/N17123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5812 ) + ); + defparam \vga/rom_addr_char<1>162 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>162 .LOC = "CLB_R25C15.S1"; + X_LUT4 \vga/rom_addr_char<1>162 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N65_0 ), + .ADR3(\vga/N67_0 ), + .O(\vga/N17123 ) + ); + defparam \vga/rom_addr_char<1>172 .INIT = 16'hCCF0; + defparam \vga/rom_addr_char<1>172 .LOC = "CLB_R25C15.S1"; + X_LUT4 \vga/rom_addr_char<1>172 ( + .ADR0(VCC), + .ADR1(\vga/N66_0 ), + .ADR2(\vga/N65_0 ), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N18123 ) + ); + defparam \vga/rom_addr_char<3>_f641/YUSED .LOC = "CLB_R25C15.S1"; + X_BUF \vga/rom_addr_char<3>_f641/YUSED ( + .I(\vga/rom_addr_char<3>_f641 ), + .O(\vga/rom_addr_char<3>_f641_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_31 .LOC = "CLB_R25C15.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_31 ( + .IA(\vga/rom_addr_char<2>_f5912_0 ), + .IB(\vga/rom_addr_char<2>_f5812 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f641 ) + ); + defparam \vga/rom_addr_char<2>_f5_73 .LOC = "CLB_R26C15.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_73 ( + .IA(\vga/N181234 ), + .IB(\vga/N19123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f58123 ) + ); + defparam \vga/rom_addr_char<1>182 .INIT = 16'hF5A0; + defparam \vga/rom_addr_char<1>182 .LOC = "CLB_R26C15.S0"; + X_LUT4 \vga/rom_addr_char<1>182 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(VCC), + .ADR2(\vga/N64_0 ), + .ADR3(\vga/N63_0 ), + .O(\vga/N19123 ) + ); + defparam \vga/rom_addr_char<1>183 .INIT = 16'hCCF0; + defparam \vga/rom_addr_char<1>183 .LOC = "CLB_R26C15.S0"; + X_LUT4 \vga/rom_addr_char<1>183 ( + .ADR0(VCC), + .ADR1(\vga/N62_0 ), + .ADR2(\vga/N106_0 ), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N181234 ) + ); + defparam \vga/rom_addr_char<2>_f58123/F5USED .LOC = "CLB_R26C15.S0"; + X_BUF \vga/rom_addr_char<2>_f58123/F5USED ( + .I(\vga/rom_addr_char<2>_f58123 ), + .O(\vga/rom_addr_char<2>_f58123_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_81 .LOC = "CLB_R25C13.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_81 ( + .IA(\vga/N2012 ), + .IB(\vga/N1912 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f591 ) + ); + defparam \vga/rom_addr_char<1>181 .INIT = 16'hACAC; + defparam \vga/rom_addr_char<1>181 .LOC = "CLB_R25C13.S0"; + X_LUT4 \vga/rom_addr_char<1>181 ( + .ADR0(\vga/N155_0 ), + .ADR1(\vga/N63_0 ), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(VCC), + .O(\vga/N1912 ) + ); + defparam \vga/rom_addr_char<1>191 .INIT = 16'hF3C0; + defparam \vga/rom_addr_char<1>191 .LOC = "CLB_R25C13.S0"; + X_LUT4 \vga/rom_addr_char<1>191 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N62_0 ), + .ADR3(\vga/N152_0 ), + .O(\vga/N2012 ) + ); + defparam \vga/rom_addr_char<2>_f591/F5USED .LOC = "CLB_R25C13.S0"; + X_BUF \vga/rom_addr_char<2>_f591/F5USED ( + .I(\vga/rom_addr_char<2>_f591 ), + .O(\vga/rom_addr_char<2>_f591_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_74 .LOC = "CLB_R9C2.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_74 ( + .IA(\vga/N2012345 ), + .IB(\vga/N1912345 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f581234 ) + ); + defparam \vga/rom_addr_char<1>184 .INIT = 16'hE2E2; + defparam \vga/rom_addr_char<1>184 .LOC = "CLB_R9C2.S1"; + X_LUT4 \vga/rom_addr_char<1>184 ( + .ADR0(\vga/N134_0 ), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N37_0 ), + .ADR3(VCC), + .O(\vga/N1912345 ) + ); + defparam \vga/rom_addr_char<1>194 .INIT = 16'hAFA0; + defparam \vga/rom_addr_char<1>194 .LOC = "CLB_R9C2.S1"; + X_LUT4 \vga/rom_addr_char<1>194 ( + .ADR0(\vga/N205_0 ), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N35_0 ), + .O(\vga/N2012345 ) + ); + defparam \vga/rom_addr_char<3>_f64123/YUSED .LOC = "CLB_R9C2.S1"; + X_BUF \vga/rom_addr_char<3>_f64123/YUSED ( + .I(\vga/rom_addr_char<3>_f64123 ), + .O(\vga/rom_addr_char<3>_f64123_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_33 .LOC = "CLB_R9C2.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_33 ( + .IA(\vga/rom_addr_char<2>_f591234_0 ), + .IB(\vga/rom_addr_char<2>_f581234 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f64123 ) + ); + defparam \vga/rom_addr_char<2>_f5_82 .LOC = "CLB_R25C15.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_82 ( + .IA(\vga/N20123 ), + .IB(N3081), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5912 ) + ); + defparam \vga/rom_addr_char<2>_f5_821 .INIT = 16'hDD88; + defparam \vga/rom_addr_char<2>_f5_821 .LOC = "CLB_R25C15.S0"; + X_LUT4 \vga/rom_addr_char<2>_f5_821 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N64_0 ), + .ADR2(VCC), + .ADR3(\vga/N63_0 ), + .O(N3081) + ); + defparam \vga/rom_addr_char<1>192 .INIT = 16'hDD88; + defparam \vga/rom_addr_char<1>192 .LOC = "CLB_R25C15.S0"; + X_LUT4 \vga/rom_addr_char<1>192 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/N62_0 ), + .ADR2(VCC), + .ADR3(\vga/N61_0 ), + .O(\vga/N20123 ) + ); + defparam \vga/rom_addr_char<2>_f5912/F5USED .LOC = "CLB_R25C15.S0"; + X_BUF \vga/rom_addr_char<2>_f5912/F5USED ( + .I(\vga/rom_addr_char<2>_f5912 ), + .O(\vga/rom_addr_char<2>_f5912_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_83 .LOC = "CLB_R26C13.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_83 ( + .IA(\vga/N201234 ), + .IB(\vga/N191234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f59123 ) + ); + defparam \vga/rom_addr_char<1>193 .INIT = 16'hE4E4; + defparam \vga/rom_addr_char<1>193 .LOC = "CLB_R26C13.S1"; + X_LUT4 \vga/rom_addr_char<1>193 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/N65_0 ), + .ADR2(\vga/N120_0 ), + .ADR3(VCC), + .O(\vga/N191234 ) + ); + defparam \vga/rom_addr_char<1>203 .INIT = 16'hFC0C; + defparam \vga/rom_addr_char<1>203 .LOC = "CLB_R26C13.S1"; + X_LUT4 \vga/rom_addr_char<1>203 ( + .ADR0(VCC), + .ADR1(\vga/N117_0 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N118_0 ), + .O(\vga/N201234 ) + ); + defparam \vga/rom_addr_char<3>_f6412/YUSED .LOC = "CLB_R26C13.S1"; + X_BUF \vga/rom_addr_char<3>_f6412/YUSED ( + .I(\vga/rom_addr_char<3>_f6412 ), + .O(\vga/rom_addr_char<3>_f6412_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_32 .LOC = "CLB_R26C13.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_32 ( + .IA(\vga/rom_addr_char<2>_f51012_0 ), + .IB(\vga/rom_addr_char<2>_f59123 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6412 ) + ); + defparam \vga/rom_addr_char<2>_f5_91 .LOC = "CLB_R27C12.S1"; + X_MUX2 \vga/rom_addr_char<2>_f5_91 ( + .IA(\vga/N22123 ), + .IB(\vga/N21123 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5101 ) + ); + defparam \vga/rom_addr_char<1>202 .INIT = 16'hCCF0; + defparam \vga/rom_addr_char<1>202 .LOC = "CLB_R27C12.S1"; + X_LUT4 \vga/rom_addr_char<1>202 ( + .ADR0(VCC), + .ADR1(\vga/N75_0 ), + .ADR2(\vga/N74_0 ), + .ADR3(\vga/rom_addr_char [1]), + .O(\vga/N21123 ) + ); + defparam \vga/rom_addr_char<1>212 .INIT = 16'hF0AA; + defparam \vga/rom_addr_char<1>212 .LOC = "CLB_R27C12.S1"; + X_LUT4 \vga/rom_addr_char<1>212 ( + .ADR0(\vga/N72_0 ), + .ADR1(VCC), + .ADR2(\vga/N73_0 ), + .ADR3(\vga/rom_addr_char_1_1_7 ), + .O(\vga/N22123 ) + ); + defparam \vga/rom_addr_char<3>_f651/YUSED .LOC = "CLB_R27C12.S1"; + X_BUF \vga/rom_addr_char<3>_f651/YUSED ( + .I(\vga/rom_addr_char<3>_f651 ), + .O(\vga/rom_addr_char<3>_f651_0 ) + ); + defparam \vga/rom_addr_char<3>_f6_41 .LOC = "CLB_R27C12.S1"; + X_MUX2 \vga/rom_addr_char<3>_f6_41 ( + .IA(\vga/rom_addr_char<2>_f51112_0 ), + .IB(\vga/rom_addr_char<2>_f5101 ), + .SEL(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f651 ) + ); + defparam \vga/rom_addr_char<2>_f5_84 .LOC = "CLB_R9C2.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_84 ( + .IA(\vga/N2212345 ), + .IB(\vga/N1511 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f591234 ) + ); + defparam \vga/rom_addr_char<1>14 .INIT = 16'hB8B8; + defparam \vga/rom_addr_char<1>14 .LOC = "CLB_R9C2.S0"; + X_LUT4 \vga/rom_addr_char<1>14 ( + .ADR0(\vga/N34_0 ), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/N33_0 ), + .ADR3(VCC), + .O(\vga/N1511 ) + ); + defparam \vga/rom_addr_char<1>214 .INIT = 16'hD8D8; + defparam \vga/rom_addr_char<1>214 .LOC = "CLB_R9C2.S0"; + X_LUT4 \vga/rom_addr_char<1>214 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N201_0 ), + .ADR2(\vga/N30_0 ), + .ADR3(VCC), + .O(\vga/N2212345 ) + ); + defparam \vga/rom_addr_char<2>_f591234/F5USED .LOC = "CLB_R9C2.S0"; + X_BUF \vga/rom_addr_char<2>_f591234/F5USED ( + .I(\vga/rom_addr_char<2>_f591234 ), + .O(\vga/rom_addr_char<2>_f591234_0 ) + ); + defparam \vga/rom_addr_char<2>_f5_92 .LOC = "CLB_R26C13.S0"; + X_MUX2 \vga/rom_addr_char<2>_f5_92 ( + .IA(\vga/N221234 ), + .IB(\vga/N211234 ), + .SEL(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51012 ) + ); + defparam \vga/rom_addr_char<1>213 .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<1>213 .LOC = "CLB_R26C13.S0"; + X_LUT4 \vga/rom_addr_char<1>213 ( + .ADR0(VCC), + .ADR1(\vga/N116_0 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N115_0 ), + .O(\vga/N211234 ) + ); + defparam \vga/rom_addr_char<1>222 .INIT = 16'hE4E4; + defparam \vga/rom_addr_char<1>222 .LOC = "CLB_R26C13.S0"; + X_LUT4 \vga/rom_addr_char<1>222 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/N114_0 ), + .ADR2(\vga/N64_0 ), + .ADR3(VCC), + .O(\vga/N221234 ) + ); + defparam \vga/rom_addr_char<2>_f51012/F5USED .LOC = "CLB_R26C13.S0"; + X_BUF \vga/rom_addr_char<2>_f51012/F5USED ( + .I(\vga/rom_addr_char<2>_f51012 ), + .O(\vga/rom_addr_char<2>_f51012_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1217_f5 .LOC = "CLB_R18C34.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<3>1217_f5 ( + .IA(N3265), + .IB(N3264), + .SEL(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1201 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>12171 .INIT = 16'hFCCC; + defparam \vga/scancode_convert/scancode_rom/data<3>12171 .LOC = "CLB_R18C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>12171 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3264) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>12172 .INIT = 16'hFFFC; + defparam \vga/scancode_convert/scancode_rom/data<3>12172 .LOC = "CLB_R18C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>12172 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3265) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1_map1201/XUSED .LOC = "CLB_R18C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>1_map1201/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>1_map1201 ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1201_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3159_SW0 .LOC = "CLB_R12C33.S1"; + X_MUX2 \vga/scancode_convert/scancode_rom/data<5>3159_SW0 ( + .IA(N3212), + .IB(N3213), + .SEL(\vga/scancode_convert/sc [2]), + .O(N3112) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3159_SW0_G .INIT = 16'h3F55; + defparam \vga/scancode_convert/scancode_rom/data<5>3159_SW0_G .LOC = "CLB_R12C33.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3159_SW0_G ( + .ADR0(\vga/scancode_convert/scancode_rom/data<5>3_map1245_0 ), + .ADR1(\vga/scancode_convert/scancode_rom/data<5>3_map1260_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<5>3_map1249_0 ), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3213) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3159_SW0_F .INIT = 16'hDFDF; + defparam \vga/scancode_convert/scancode_rom/data<5>3159_SW0_F .LOC = "CLB_R12C33.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3159_SW0_F ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/scancode_rom/N12 ), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(VCC), + .O(N3212) + ); + defparam \N3112/XUSED .LOC = "CLB_R12C33.S1"; + X_BUF \N3112/XUSED ( + .I(N3112), + .O(N3112_0) + ); + defparam \vga/ram_addr_write<5>/LOGIC_ZERO .LOC = "CLB_R16C10.S1"; + X_ZERO \vga/ram_addr_write<5>/LOGIC_ZERO ( + .O(\vga/ram_addr_write<5>/LOGIC_ZERO_95 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_cy<5> .LOC = "CLB_R16C10.S1"; + X_MUX2 \vga/crt/Madd_ram_addr_Madd_cy<5> ( + .IA(\vga/crt/Madd_ram_addrC_mand1 ), + .IB(\vga/ram_addr_write<5>/LOGIC_ZERO_95 ), + .SEL(\vga/ram_addr_write [5]), + .O(\vga/crt/Madd_ram_addr_Madd_cy[5] ) + ); + defparam \vga/crt/Madd_ram_addrC_mand .LOC = "CLB_R16C10.S1"; + X_AND2 \vga/crt/Madd_ram_addrC_mand ( + .I0(\vga/crt/cursor_v [0]), + .I1(\vga/crt/cursor_h [4]), + .O(\vga/crt/Madd_ram_addrC_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<5> .INIT = 16'h8778; + defparam \vga/crt/Madd_ram_addr_Madd_lut<5> .LOC = "CLB_R16C10.S1"; + X_LUT4 \vga/crt/Madd_ram_addr_Madd_lut<5> ( + .ADR0(\vga/crt/cursor_h [4]), + .ADR1(\vga/crt/cursor_v [0]), + .ADR2(\vga/crt/cursor_h [5]), + .ADR3(\vga/crt/cursor_v [1]), + .O(\vga/ram_addr_write [5]) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<6> .INIT = 16'h7788; + defparam \vga/crt/Madd_ram_addr_Madd_lut<6> .LOC = "CLB_R16C10.S1"; + X_LUT4 \vga/crt/Madd_ram_addr_Madd_lut<6> ( + .ADR0(\vga/crt/cursor_h [5]), + .ADR1(\vga/crt/cursor_v [1]), + .ADR2(VCC), + .ADR3(\vga/crt/Madd_ram_addrR2_0 ), + .O(\vga/crt/N8 ) + ); + defparam \vga/ram_addr_write<5>/XUSED .LOC = "CLB_R16C10.S1"; + X_BUF \vga/ram_addr_write<5>/XUSED ( + .I(\vga/ram_addr_write [5]), + .O(\vga/ram_addr_write<5>_0 ) + ); + defparam \vga/ram_addr_write<5>/YUSED .LOC = "CLB_R16C10.S1"; + X_BUF \vga/ram_addr_write<5>/YUSED ( + .I(\vga/ram_addr_write [6]), + .O(\vga/ram_addr_write<6>_0 ) + ); + defparam \vga/crt/Madd_ram_addrC1_mand .LOC = "CLB_R16C10.S1"; + X_AND2 \vga/crt/Madd_ram_addrC1_mand ( + .I0(\vga/crt/cursor_v [1]), + .I1(\vga/crt/cursor_h [5]), + .O(\vga/crt/Madd_ram_addrC1_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_cy<6> .LOC = "CLB_R16C10.S1"; + X_MUX2 \vga/crt/Madd_ram_addr_Madd_cy<6> ( + .IA(\vga/crt/Madd_ram_addrC1_mand1 ), + .IB(\vga/crt/Madd_ram_addr_Madd_cy[5] ), + .SEL(\vga/crt/N8 ), + .O(\vga/ram_addr_write<5>/CYMUXG ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_xor<6> .LOC = "CLB_R16C10.S1"; + X_XOR2 \vga/crt/Madd_ram_addr_Madd_xor<6> ( + .I0(\vga/crt/Madd_ram_addr_Madd_cy[5] ), + .I1(\vga/crt/N8 ), + .O(\vga/ram_addr_write [6]) + ); + defparam \vga/crt/Madd_ram_addr_Madd_cy<8> .LOC = "CLB_R14C10.S1"; + X_MUX2 \vga/crt/Madd_ram_addr_Madd_cy<8> ( + .IA(\vga/crt/Madd_ram_addrC3_mand1 ), + .IB(\vga/ram_addr_write<8>/CYINIT_96 ), + .SEL(\vga/crt/N10 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy[8] ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_xor<8> .LOC = "CLB_R14C10.S1"; + X_XOR2 \vga/crt/Madd_ram_addr_Madd_xor<8> ( + .I0(\vga/ram_addr_write<8>/CYINIT_96 ), + .I1(\vga/crt/N10 ), + .O(\vga/ram_addr_write [8]) + ); + defparam \vga/crt/Madd_ram_addrC3_mand .LOC = "CLB_R14C10.S1"; + X_AND2 \vga/crt/Madd_ram_addrC3_mand ( + .I0(\vga/crt/cursor_v [3]), + .I1(\vga/crt/cursor_v [1]), + .O(\vga/crt/Madd_ram_addrC3_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<8> .INIT = 16'h8778; + defparam \vga/crt/Madd_ram_addr_Madd_lut<8> .LOC = "CLB_R14C10.S1"; + X_LUT4 \vga/crt/Madd_ram_addr_Madd_lut<8> ( + .ADR0(\vga/crt/cursor_v [1]), + .ADR1(\vga/crt/cursor_v [3]), + .ADR2(\vga/crt/cursor_v [4]), + .ADR3(\vga/crt/cursor_v [2]), + .O(\vga/crt/N10 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<9> .INIT = 16'h8778; + defparam \vga/crt/Madd_ram_addr_Madd_lut<9> .LOC = "CLB_R14C10.S1"; + X_LUT4 \vga/crt/Madd_ram_addr_Madd_lut<9> ( + .ADR0(\vga/crt/cursor_v [2]), + .ADR1(\vga/crt/cursor_v [4]), + .ADR2(\vga/crt/cursor_v [3]), + .ADR3(\vga/crt/cursor_v [5]), + .O(\vga/crt/N11 ) + ); + defparam \vga/ram_addr_write<8>/XUSED .LOC = "CLB_R14C10.S1"; + X_BUF \vga/ram_addr_write<8>/XUSED ( + .I(\vga/ram_addr_write [8]), + .O(\vga/ram_addr_write<8>_0 ) + ); + defparam \vga/ram_addr_write<8>/YUSED .LOC = "CLB_R14C10.S1"; + X_BUF \vga/ram_addr_write<8>/YUSED ( + .I(\vga/ram_addr_write [9]), + .O(\vga/ram_addr_write<9>_0 ) + ); + defparam \vga/crt/Madd_ram_addrC4_mand .LOC = "CLB_R14C10.S1"; + X_AND2 \vga/crt/Madd_ram_addrC4_mand ( + .I0(\vga/crt/cursor_v [4]), + .I1(\vga/crt/cursor_v [2]), + .O(\vga/crt/Madd_ram_addrC4_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_cy<9> .LOC = "CLB_R14C10.S1"; + X_MUX2 \vga/crt/Madd_ram_addr_Madd_cy<9> ( + .IA(\vga/crt/Madd_ram_addrC4_mand1 ), + .IB(\vga/crt/Madd_ram_addr_Madd_cy[8] ), + .SEL(\vga/crt/N11 ), + .O(\vga/ram_addr_write<8>/CYMUXG ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_xor<9> .LOC = "CLB_R14C10.S1"; + X_XOR2 \vga/crt/Madd_ram_addr_Madd_xor<9> ( + .I0(\vga/crt/Madd_ram_addr_Madd_cy[8] ), + .I1(\vga/crt/N11 ), + .O(\vga/ram_addr_write [9]) + ); + defparam \vga/ram_addr_write<8>/CYINIT .LOC = "CLB_R14C10.S1"; + X_BUF \vga/ram_addr_write<8>/CYINIT ( + .I(\vga/ram_addr_write<7>/CYMUXG ), + .O(\vga/ram_addr_write<8>/CYINIT_96 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_cy<10> .LOC = "CLB_R13C10.S1"; + X_MUX2 \vga/crt/Madd_ram_addr_Madd_cy<10> ( + .IA(\vga/crt/cursor_v [4]), + .IB(\vga/ram_addr_write<10>/CYINIT_98 ), + .SEL(\vga/crt/N12 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy[10] ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_xor<10> .LOC = "CLB_R13C10.S1"; + X_XOR2 \vga/crt/Madd_ram_addr_Madd_xor<10> ( + .I0(\vga/ram_addr_write<10>/CYINIT_98 ), + .I1(\vga/crt/N12 ), + .O(\vga/ram_addr_write [10]) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<10> .INIT = 16'h66AA; + defparam \vga/crt/Madd_ram_addr_Madd_lut<10> .LOC = "CLB_R13C10.S1"; + X_LUT4 \vga/crt/Madd_ram_addr_Madd_lut<10> ( + .ADR0(\vga/crt/cursor_v [4]), + .ADR1(\vga/crt/cursor_v [3]), + .ADR2(VCC), + .ADR3(\vga/crt/cursor_v [5]), + .O(\vga/crt/N12 ) + ); + defparam \vga/crt/cursor_v<5>_rt .INIT = 16'hAAAA; + defparam \vga/crt/cursor_v<5>_rt .LOC = "CLB_R13C10.S1"; + X_LUT4 \vga/crt/cursor_v<5>_rt ( + .ADR0(\vga/crt/cursor_v [5]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/cursor_v<5>_rt_97 ) + ); + defparam \vga/ram_addr_write<10>/XUSED .LOC = "CLB_R13C10.S1"; + X_BUF \vga/ram_addr_write<10>/XUSED ( + .I(\vga/ram_addr_write [10]), + .O(\vga/ram_addr_write<10>_0 ) + ); + defparam \vga/ram_addr_write<10>/YUSED .LOC = "CLB_R13C10.S1"; + X_BUF \vga/ram_addr_write<10>/YUSED ( + .I(\vga/ram_addr_write [11]), + .O(\vga/ram_addr_write<11>_0 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_xor<11> .LOC = "CLB_R13C10.S1"; + X_XOR2 \vga/crt/Madd_ram_addr_Madd_xor<11> ( + .I0(\vga/crt/Madd_ram_addr_Madd_cy[10] ), + .I1(\vga/crt/cursor_v<5>_rt_97 ), + .O(\vga/ram_addr_write [11]) + ); + defparam \vga/ram_addr_write<10>/CYINIT .LOC = "CLB_R13C10.S1"; + X_BUF \vga/ram_addr_write<10>/CYINIT ( + .I(\vga/ram_addr_write<8>/CYMUXG ), + .O(\vga/ram_addr_write<10>/CYINIT_98 ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ONE .LOC = "CLB_R18C7.S0"; + X_ONE \vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ONE ( + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ONE_101 ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ZERO .LOC = "CLB_R18C7.S0"; + X_ZERO \vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ZERO ( + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ZERO_100 ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<0> .LOC = "CLB_R18C7.S0"; + X_MUX2 \vga/vgacore/Mcompar__cmp_lt0000_cy<0> ( + .IA(\vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ZERO_100 ), + .IB(\vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ONE_101 ), + .SEL(\vga/vgacore/N4 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy[0] ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<0> .INIT = 16'h8000; + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<0> .LOC = "CLB_R18C7.S0"; + X_LUT4 \vga/vgacore/Mcompar__cmp_lt0000_lut<0> ( + .ADR0(\vga/vgacore/hcnt [1]), + .ADR1(\vga/vgacore/hcnt [3]), + .ADR2(\vga/vgacore/hcnt [0]), + .ADR3(\vga/vgacore/hcnt [2]), + .O(\vga/vgacore/N4 ) + ); + defparam \vga/vgacore/hcnt<4>_rt .INIT = 16'hF0F0; + defparam \vga/vgacore/hcnt<4>_rt .LOC = "CLB_R18C7.S0"; + X_LUT4 \vga/vgacore/hcnt<4>_rt ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [4]), + .ADR3(VCC), + .O(\vga/vgacore/hcnt<4>_rt_99 ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<1> .LOC = "CLB_R18C7.S0"; + X_MUX2 \vga/vgacore/Mcompar__cmp_lt0000_cy<1> ( + .IA(\vga/vgacore/Mcompar__cmp_lt0000_cy<1>/LOGIC_ZERO_100 ), + .IB(\vga/vgacore/Mcompar__cmp_lt0000_cy[0] ), + .SEL(\vga/vgacore/hcnt<4>_rt_99 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy<1>/CYMUXG ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<2> .LOC = "CLB_R17C7.S0"; + X_MUX2 \vga/vgacore/Mcompar__cmp_lt0000_cy<2> ( + .IA(GLOBAL_LOGIC1), + .IB(\vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYINIT_102 ), + .SEL(\vga/vgacore/N5 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy[2] ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<2> .INIT = 16'h0003; + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<2> .LOC = "CLB_R17C7.S0"; + X_LUT4 \vga/vgacore/Mcompar__cmp_lt0000_lut<2> ( + .ADR0(GLOBAL_LOGIC1), + .ADR1(\vga/vgacore/hcnt [6]), + .ADR2(\vga/vgacore/hcnt [5]), + .ADR3(\vga/vgacore/hcnt [7]), + .O(\vga/vgacore/N5 ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<3> .INIT = 16'hF000; + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<3> .LOC = "CLB_R17C7.S0"; + X_LUT4 \vga/vgacore/Mcompar__cmp_lt0000_lut<3> ( + .ADR0(GLOBAL_LOGIC0), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [8]), + .ADR3(\vga/vgacore/hcnt [9]), + .O(\vga/vgacore/N6 ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<3> .LOC = "CLB_R17C7.S0"; + X_MUX2 \vga/vgacore/Mcompar__cmp_lt0000_cy<3> ( + .IA(GLOBAL_LOGIC0), + .IB(\vga/vgacore/Mcompar__cmp_lt0000_cy[2] ), + .SEL(\vga/vgacore/N6 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYMUXG ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYINIT .LOC = "CLB_R17C7.S0"; + X_BUF \vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYINIT ( + .I(\vga/vgacore/Mcompar__cmp_lt0000_cy<1>/CYMUXG ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYINIT_102 ) + ); + defparam \vga/vgacore/hblank/LOGIC_ONE .LOC = "CLB_R16C7.S0"; + X_ONE \vga/vgacore/hblank/LOGIC_ONE ( + .O(\vga/vgacore/hblank/LOGIC_ONE_103 ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<4> .LOC = "CLB_R16C7.S0"; + X_MUX2 \vga/vgacore/Mcompar__cmp_lt0000_cy<4> ( + .IA(\vga/vgacore/hblank/LOGIC_ONE_103 ), + .IB(\vga/vgacore/hblank/CYINIT_104 ), + .SEL(\vga/vgacore/N7 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy[4] ) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<4>_INV_0 .INIT = 16'h00FF; + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<4>_INV_0 .LOC = "CLB_R16C7.S0"; + X_LUT4 \vga/vgacore/Mcompar__cmp_lt0000_lut<4>_INV_0 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/vgacore/hcnt [10]), + .O(\vga/vgacore/N7 ) + ); + defparam \vga/vgacore/_mux00021 .INIT = 16'hFEF0; + defparam \vga/vgacore/_mux00021 .LOC = "CLB_R16C7.S0"; + X_LUT4 \vga/vgacore/_mux00021 ( + .ADR0(\vga/vgacore/hcnt [7]), + .ADR1(\vga/vgacore/hcnt [8]), + .ADR2(\vga/vgacore/hcnt [10]), + .ADR3(\vga/vgacore/hcnt [9]), + .O(\vga/vgacore/_mux0002 ) + ); + defparam \vga/vgacore/hblank/XBUSED .LOC = "CLB_R16C7.S0"; + X_BUF \vga/vgacore/hblank/XBUSED ( + .I(\vga/vgacore/Mcompar__cmp_lt0000_cy[4] ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy<4>_0 ) + ); + defparam \vga/vgacore/hblank/CYINIT .LOC = "CLB_R16C7.S0"; + X_BUF \vga/vgacore/hblank/CYINIT ( + .I(\vga/vgacore/Mcompar__cmp_lt0000_cy<3>/CYMUXG ), + .O(\vga/vgacore/hblank/CYINIT_104 ) + ); + defparam \vga/ram_addr_video<5>/LOGIC_ZERO .LOC = "CLB_R17C5.S0"; + X_ZERO \vga/ram_addr_video<5>/LOGIC_ZERO ( + .O(\vga/ram_addr_video<5>/LOGIC_ZERO_105 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_cy<5> .LOC = "CLB_R17C5.S0"; + X_MUX2 \vga/Madd_ram_addr_video_Madd_cy<5> ( + .IA(\vga/Madd_ram_addr_videoC_mand1 ), + .IB(\vga/ram_addr_video<5>/LOGIC_ZERO_105 ), + .SEL(\vga/ram_addr_video [5]), + .O(\vga/Madd_ram_addr_video_Madd_cy[5] ) + ); + defparam \vga/Madd_ram_addr_videoC_mand .LOC = "CLB_R17C5.S0"; + X_AND2 \vga/Madd_ram_addr_videoC_mand ( + .I0(\vga/vgacore/vcnt [3]), + .I1(\vga/vgacore/hcnt [7]), + .O(\vga/Madd_ram_addr_videoC_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<5> .INIT = 16'h8778; + defparam \vga/Madd_ram_addr_video_Madd_lut<5> .LOC = "CLB_R17C5.S0"; + X_LUT4 \vga/Madd_ram_addr_video_Madd_lut<5> ( + .ADR0(\vga/vgacore/hcnt [7]), + .ADR1(\vga/vgacore/vcnt [3]), + .ADR2(\vga/vgacore/vcnt [4]), + .ADR3(\vga/vgacore/hcnt [8]), + .O(\vga/ram_addr_video [5]) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<6> .INIT = 16'h7878; + defparam \vga/Madd_ram_addr_video_Madd_lut<6> .LOC = "CLB_R17C5.S0"; + X_LUT4 \vga/Madd_ram_addr_video_Madd_lut<6> ( + .ADR0(\vga/vgacore/hcnt [8]), + .ADR1(\vga/vgacore/vcnt [4]), + .ADR2(\vga/Madd_ram_addr_videoR2_0 ), + .ADR3(VCC), + .O(\vga/N229 ) + ); + defparam \vga/ram_addr_video<5>/XUSED .LOC = "CLB_R17C5.S0"; + X_BUF \vga/ram_addr_video<5>/XUSED ( + .I(\vga/ram_addr_video [5]), + .O(\vga/ram_addr_video<5>_0 ) + ); + defparam \vga/ram_addr_video<5>/YUSED .LOC = "CLB_R17C5.S0"; + X_BUF \vga/ram_addr_video<5>/YUSED ( + .I(\vga/ram_addr_video [6]), + .O(\vga/ram_addr_video<6>_0 ) + ); + defparam \vga/Madd_ram_addr_videoC1_mand .LOC = "CLB_R17C5.S0"; + X_AND2 \vga/Madd_ram_addr_videoC1_mand ( + .I0(\vga/vgacore/vcnt [4]), + .I1(\vga/vgacore/hcnt [8]), + .O(\vga/Madd_ram_addr_videoC1_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_cy<6> .LOC = "CLB_R17C5.S0"; + X_MUX2 \vga/Madd_ram_addr_video_Madd_cy<6> ( + .IA(\vga/Madd_ram_addr_videoC1_mand1 ), + .IB(\vga/Madd_ram_addr_video_Madd_cy[5] ), + .SEL(\vga/N229 ), + .O(\vga/ram_addr_video<5>/CYMUXG ) + ); + defparam \vga/Madd_ram_addr_video_Madd_xor<6> .LOC = "CLB_R17C5.S0"; + X_XOR2 \vga/Madd_ram_addr_video_Madd_xor<6> ( + .I0(\vga/Madd_ram_addr_video_Madd_cy[5] ), + .I1(\vga/N229 ), + .O(\vga/ram_addr_video [6]) + ); + defparam \vga/Madd_ram_addr_video_Madd_cy<8> .LOC = "CLB_R15C5.S0"; + X_MUX2 \vga/Madd_ram_addr_video_Madd_cy<8> ( + .IA(\vga/Madd_ram_addr_videoC3_mand1 ), + .IB(\vga/ram_addr_video<8>/CYINIT_106 ), + .SEL(\vga/N2313 ), + .O(\vga/Madd_ram_addr_video_Madd_cy[8] ) + ); + defparam \vga/Madd_ram_addr_video_Madd_xor<8> .LOC = "CLB_R15C5.S0"; + X_XOR2 \vga/Madd_ram_addr_video_Madd_xor<8> ( + .I0(\vga/ram_addr_video<8>/CYINIT_106 ), + .I1(\vga/N2313 ), + .O(\vga/ram_addr_video [8]) + ); + defparam \vga/Madd_ram_addr_videoC3_mand .LOC = "CLB_R15C5.S0"; + X_AND2 \vga/Madd_ram_addr_videoC3_mand ( + .I0(\vga/vgacore/vcnt [6]), + .I1(\vga/vgacore/vcnt [4]), + .O(\vga/Madd_ram_addr_videoC3_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<8> .INIT = 16'h8778; + defparam \vga/Madd_ram_addr_video_Madd_lut<8> .LOC = "CLB_R15C5.S0"; + X_LUT4 \vga/Madd_ram_addr_video_Madd_lut<8> ( + .ADR0(\vga/vgacore/vcnt [4]), + .ADR1(\vga/vgacore/vcnt [6]), + .ADR2(\vga/vgacore/vcnt [7]), + .ADR3(\vga/vgacore/vcnt [5]), + .O(\vga/N2313 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<9> .INIT = 16'h8778; + defparam \vga/Madd_ram_addr_video_Madd_lut<9> .LOC = "CLB_R15C5.S0"; + X_LUT4 \vga/Madd_ram_addr_video_Madd_lut<9> ( + .ADR0(\vga/vgacore/vcnt [5]), + .ADR1(\vga/vgacore/vcnt [7]), + .ADR2(\vga/vgacore/vcnt [8]), + .ADR3(\vga/vgacore/vcnt [6]), + .O(\vga/N232 ) + ); + defparam \vga/ram_addr_video<8>/XUSED .LOC = "CLB_R15C5.S0"; + X_BUF \vga/ram_addr_video<8>/XUSED ( + .I(\vga/ram_addr_video [8]), + .O(\vga/ram_addr_video<8>_0 ) + ); + defparam \vga/ram_addr_video<8>/YUSED .LOC = "CLB_R15C5.S0"; + X_BUF \vga/ram_addr_video<8>/YUSED ( + .I(\vga/ram_addr_video [9]), + .O(\vga/ram_addr_video<9>_0 ) + ); + defparam \vga/Madd_ram_addr_videoC4_mand .LOC = "CLB_R15C5.S0"; + X_AND2 \vga/Madd_ram_addr_videoC4_mand ( + .I0(\vga/vgacore/vcnt [7]), + .I1(\vga/vgacore/vcnt [5]), + .O(\vga/Madd_ram_addr_videoC4_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_cy<9> .LOC = "CLB_R15C5.S0"; + X_MUX2 \vga/Madd_ram_addr_video_Madd_cy<9> ( + .IA(\vga/Madd_ram_addr_videoC4_mand1 ), + .IB(\vga/Madd_ram_addr_video_Madd_cy[8] ), + .SEL(\vga/N232 ), + .O(\vga/ram_addr_video<8>/CYMUXG ) + ); + defparam \vga/Madd_ram_addr_video_Madd_xor<9> .LOC = "CLB_R15C5.S0"; + X_XOR2 \vga/Madd_ram_addr_video_Madd_xor<9> ( + .I0(\vga/Madd_ram_addr_video_Madd_cy[8] ), + .I1(\vga/N232 ), + .O(\vga/ram_addr_video [9]) + ); + defparam \vga/ram_addr_video<8>/CYINIT .LOC = "CLB_R15C5.S0"; + X_BUF \vga/ram_addr_video<8>/CYINIT ( + .I(\vga/ram_addr_video<7>/CYMUXG ), + .O(\vga/ram_addr_video<8>/CYINIT_106 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_cy<10> .LOC = "CLB_R14C5.S0"; + X_MUX2 \vga/Madd_ram_addr_video_Madd_cy<10> ( + .IA(\vga/vgacore/vcnt [7]), + .IB(\vga/ram_addr_video<10>/CYINIT_108 ), + .SEL(\vga/N233 ), + .O(\vga/Madd_ram_addr_video_Madd_cy[10] ) + ); + defparam \vga/Madd_ram_addr_video_Madd_xor<10> .LOC = "CLB_R14C5.S0"; + X_XOR2 \vga/Madd_ram_addr_video_Madd_xor<10> ( + .I0(\vga/ram_addr_video<10>/CYINIT_108 ), + .I1(\vga/N233 ), + .O(\vga/ram_addr_video [10]) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<10> .INIT = 16'h6A6A; + defparam \vga/Madd_ram_addr_video_Madd_lut<10> .LOC = "CLB_R14C5.S0"; + X_LUT4 \vga/Madd_ram_addr_video_Madd_lut<10> ( + .ADR0(\vga/vgacore/vcnt [7]), + .ADR1(\vga/vgacore/vcnt [6]), + .ADR2(\vga/vgacore/vcnt [8]), + .ADR3(VCC), + .O(\vga/N233 ) + ); + defparam \vga/vgacore/vcnt<8>_rt .INIT = 16'hAAAA; + defparam \vga/vgacore/vcnt<8>_rt .LOC = "CLB_R14C5.S0"; + X_LUT4 \vga/vgacore/vcnt<8>_rt ( + .ADR0(\vga/vgacore/vcnt [8]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/vgacore/vcnt<8>_rt_107 ) + ); + defparam \vga/ram_addr_video<10>/XUSED .LOC = "CLB_R14C5.S0"; + X_BUF \vga/ram_addr_video<10>/XUSED ( + .I(\vga/ram_addr_video [10]), + .O(\vga/ram_addr_video<10>_0 ) + ); + defparam \vga/ram_addr_video<10>/YUSED .LOC = "CLB_R14C5.S0"; + X_BUF \vga/ram_addr_video<10>/YUSED ( + .I(\vga/ram_addr_video [11]), + .O(\vga/ram_addr_video<11>_0 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_xor<11> .LOC = "CLB_R14C5.S0"; + X_XOR2 \vga/Madd_ram_addr_video_Madd_xor<11> ( + .I0(\vga/Madd_ram_addr_video_Madd_cy[10] ), + .I1(\vga/vgacore/vcnt<8>_rt_107 ), + .O(\vga/ram_addr_video [11]) + ); + defparam \vga/ram_addr_video<10>/CYINIT .LOC = "CLB_R14C5.S0"; + X_BUF \vga/ram_addr_video<10>/CYINIT ( + .I(\vga/ram_addr_video<8>/CYMUXG ), + .O(\vga/ram_addr_video<10>/CYINIT_108 ) + ); + defparam \vga/ps2/_addsub0000<1>/LOGIC_ZERO .LOC = "CLB_R11C16.S1"; + X_ZERO \vga/ps2/_addsub0000<1>/LOGIC_ZERO ( + .O(\vga/ps2/_addsub0000<1>/LOGIC_ZERO_109 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<0> .LOC = "CLB_R11C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<0> ( + .IA(GLOBAL_LOGIC1), + .IB(\vga/ps2/_addsub0000<1>/LOGIC_ZERO_109 ), + .SEL(\vga/ps2/N5 ), + .O(\vga/ps2/Madd__addsub0000_cy[0] ) + ); + defparam \vga/ps2/Madd__addsub0000_lut<0>_INV_0 .INIT = 16'h0F0F; + defparam \vga/ps2/Madd__addsub0000_lut<0>_INV_0 .LOC = "CLB_R11C16.S1"; + X_LUT4 \vga/ps2/Madd__addsub0000_lut<0>_INV_0 ( + .ADR0(GLOBAL_LOGIC1), + .ADR1(VCC), + .ADR2(\vga/ps2/timer_r [0]), + .ADR3(VCC), + .O(\vga/ps2/N5 ) + ); + defparam \vga/ps2/_addsub0000<1>/G .INIT = 16'hFF00; + defparam \vga/ps2/_addsub0000<1>/G .LOC = "CLB_R11C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<1>/G ( + .ADR0(GLOBAL_LOGIC0), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/timer_r [1]), + .O(\vga/ps2/_addsub0000<1>/GROM ) + ); + defparam \vga/ps2/_addsub0000<1>/YUSED .LOC = "CLB_R11C16.S1"; + X_BUF \vga/ps2/_addsub0000<1>/YUSED ( + .I(\vga/ps2/_addsub0000 [1]), + .O(\vga/ps2/_addsub0000<1>_0 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<1> .LOC = "CLB_R11C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<1> ( + .IA(GLOBAL_LOGIC0), + .IB(\vga/ps2/Madd__addsub0000_cy[0] ), + .SEL(\vga/ps2/_addsub0000<1>/GROM ), + .O(\vga/ps2/_addsub0000<1>/CYMUXG ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<1> .LOC = "CLB_R11C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<1> ( + .I0(\vga/ps2/Madd__addsub0000_cy[0] ), + .I1(\vga/ps2/_addsub0000<1>/GROM ), + .O(\vga/ps2/_addsub0000 [1]) + ); + defparam \vga/ps2/_addsub0000<2>/LOGIC_ZERO .LOC = "CLB_R10C16.S1"; + X_ZERO \vga/ps2/_addsub0000<2>/LOGIC_ZERO ( + .O(\vga/ps2/_addsub0000<2>/LOGIC_ZERO_110 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<2> .LOC = "CLB_R10C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<2> ( + .IA(\vga/ps2/_addsub0000<2>/LOGIC_ZERO_110 ), + .IB(\vga/ps2/_addsub0000<2>/CYINIT_111 ), + .SEL(\vga/ps2/_addsub0000<2>/FROM ), + .O(\vga/ps2/Madd__addsub0000_cy[2] ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<2> .LOC = "CLB_R10C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<2> ( + .I0(\vga/ps2/_addsub0000<2>/CYINIT_111 ), + .I1(\vga/ps2/_addsub0000<2>/FROM ), + .O(\vga/ps2/_addsub0000 [2]) + ); + defparam \vga/ps2/_addsub0000<2>/F .INIT = 16'hFF00; + defparam \vga/ps2/_addsub0000<2>/F .LOC = "CLB_R10C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<2>/F ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/timer_r [2]), + .O(\vga/ps2/_addsub0000<2>/FROM ) + ); + defparam \vga/ps2/_addsub0000<2>/G .INIT = 16'hFF00; + defparam \vga/ps2/_addsub0000<2>/G .LOC = "CLB_R10C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<2>/G ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/timer_r [3]), + .O(\vga/ps2/_addsub0000<2>/GROM ) + ); + defparam \vga/ps2/_addsub0000<2>/XUSED .LOC = "CLB_R10C16.S1"; + X_BUF \vga/ps2/_addsub0000<2>/XUSED ( + .I(\vga/ps2/_addsub0000 [2]), + .O(\vga/ps2/_addsub0000<2>_0 ) + ); + defparam \vga/ps2/_addsub0000<2>/YUSED .LOC = "CLB_R10C16.S1"; + X_BUF \vga/ps2/_addsub0000<2>/YUSED ( + .I(\vga/ps2/_addsub0000 [3]), + .O(\vga/ps2/_addsub0000<3>_0 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<3> .LOC = "CLB_R10C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<3> ( + .IA(\vga/ps2/_addsub0000<2>/LOGIC_ZERO_110 ), + .IB(\vga/ps2/Madd__addsub0000_cy[2] ), + .SEL(\vga/ps2/_addsub0000<2>/GROM ), + .O(\vga/ps2/_addsub0000<2>/CYMUXG ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<3> .LOC = "CLB_R10C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<3> ( + .I0(\vga/ps2/Madd__addsub0000_cy[2] ), + .I1(\vga/ps2/_addsub0000<2>/GROM ), + .O(\vga/ps2/_addsub0000 [3]) + ); + defparam \vga/ps2/_addsub0000<2>/CYINIT .LOC = "CLB_R10C16.S1"; + X_BUF \vga/ps2/_addsub0000<2>/CYINIT ( + .I(\vga/ps2/_addsub0000<1>/CYMUXG ), + .O(\vga/ps2/_addsub0000<2>/CYINIT_111 ) + ); + defparam \vga/ps2/_addsub0000<4>/LOGIC_ZERO .LOC = "CLB_R9C16.S1"; + X_ZERO \vga/ps2/_addsub0000<4>/LOGIC_ZERO ( + .O(\vga/ps2/_addsub0000<4>/LOGIC_ZERO_112 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<4> .LOC = "CLB_R9C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<4> ( + .IA(\vga/ps2/_addsub0000<4>/LOGIC_ZERO_112 ), + .IB(\vga/ps2/_addsub0000<4>/CYINIT_113 ), + .SEL(\vga/ps2/_addsub0000<4>/FROM ), + .O(\vga/ps2/Madd__addsub0000_cy[4] ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<4> .LOC = "CLB_R9C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<4> ( + .I0(\vga/ps2/_addsub0000<4>/CYINIT_113 ), + .I1(\vga/ps2/_addsub0000<4>/FROM ), + .O(\vga/ps2/_addsub0000 [4]) + ); + defparam \vga/ps2/_addsub0000<4>/F .INIT = 16'hFF00; + defparam \vga/ps2/_addsub0000<4>/F .LOC = "CLB_R9C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<4>/F ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/timer_r [4]), + .O(\vga/ps2/_addsub0000<4>/FROM ) + ); + defparam \vga/ps2/_addsub0000<4>/G .INIT = 16'hF0F0; + defparam \vga/ps2/_addsub0000<4>/G .LOC = "CLB_R9C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<4>/G ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/timer_r [5]), + .ADR3(VCC), + .O(\vga/ps2/_addsub0000<4>/GROM ) + ); + defparam \vga/ps2/_addsub0000<4>/XUSED .LOC = "CLB_R9C16.S1"; + X_BUF \vga/ps2/_addsub0000<4>/XUSED ( + .I(\vga/ps2/_addsub0000 [4]), + .O(\vga/ps2/_addsub0000<4>_0 ) + ); + defparam \vga/ps2/_addsub0000<4>/YUSED .LOC = "CLB_R9C16.S1"; + X_BUF \vga/ps2/_addsub0000<4>/YUSED ( + .I(\vga/ps2/_addsub0000 [5]), + .O(\vga/ps2/_addsub0000<5>_0 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<5> .LOC = "CLB_R9C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<5> ( + .IA(\vga/ps2/_addsub0000<4>/LOGIC_ZERO_112 ), + .IB(\vga/ps2/Madd__addsub0000_cy[4] ), + .SEL(\vga/ps2/_addsub0000<4>/GROM ), + .O(\vga/ps2/_addsub0000<4>/CYMUXG ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<5> .LOC = "CLB_R9C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<5> ( + .I0(\vga/ps2/Madd__addsub0000_cy[4] ), + .I1(\vga/ps2/_addsub0000<4>/GROM ), + .O(\vga/ps2/_addsub0000 [5]) + ); + defparam \vga/ps2/_addsub0000<4>/CYINIT .LOC = "CLB_R9C16.S1"; + X_BUF \vga/ps2/_addsub0000<4>/CYINIT ( + .I(\vga/ps2/_addsub0000<2>/CYMUXG ), + .O(\vga/ps2/_addsub0000<4>/CYINIT_113 ) + ); + defparam \vga/ps2/_addsub0000<6>/LOGIC_ZERO .LOC = "CLB_R8C16.S1"; + X_ZERO \vga/ps2/_addsub0000<6>/LOGIC_ZERO ( + .O(\vga/ps2/_addsub0000<6>/LOGIC_ZERO_114 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<6> .LOC = "CLB_R8C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<6> ( + .IA(\vga/ps2/_addsub0000<6>/LOGIC_ZERO_114 ), + .IB(\vga/ps2/_addsub0000<6>/CYINIT_115 ), + .SEL(\vga/ps2/_addsub0000<6>/FROM ), + .O(\vga/ps2/Madd__addsub0000_cy[6] ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<6> .LOC = "CLB_R8C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<6> ( + .I0(\vga/ps2/_addsub0000<6>/CYINIT_115 ), + .I1(\vga/ps2/_addsub0000<6>/FROM ), + .O(\vga/ps2/_addsub0000 [6]) + ); + defparam \vga/ps2/_addsub0000<6>/F .INIT = 16'hCCCC; + defparam \vga/ps2/_addsub0000<6>/F .LOC = "CLB_R8C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<6>/F ( + .ADR0(VCC), + .ADR1(\vga/ps2/timer_r [6]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/_addsub0000<6>/FROM ) + ); + defparam \vga/ps2/_addsub0000<6>/G .INIT = 16'hF0F0; + defparam \vga/ps2/_addsub0000<6>/G .LOC = "CLB_R8C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<6>/G ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/timer_r [7]), + .ADR3(VCC), + .O(\vga/ps2/_addsub0000<6>/GROM ) + ); + defparam \vga/ps2/_addsub0000<6>/XUSED .LOC = "CLB_R8C16.S1"; + X_BUF \vga/ps2/_addsub0000<6>/XUSED ( + .I(\vga/ps2/_addsub0000 [6]), + .O(\vga/ps2/_addsub0000<6>_0 ) + ); + defparam \vga/ps2/_addsub0000<6>/YUSED .LOC = "CLB_R8C16.S1"; + X_BUF \vga/ps2/_addsub0000<6>/YUSED ( + .I(\vga/ps2/_addsub0000 [7]), + .O(\vga/ps2/_addsub0000<7>_0 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<7> .LOC = "CLB_R8C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<7> ( + .IA(\vga/ps2/_addsub0000<6>/LOGIC_ZERO_114 ), + .IB(\vga/ps2/Madd__addsub0000_cy[6] ), + .SEL(\vga/ps2/_addsub0000<6>/GROM ), + .O(\vga/ps2/_addsub0000<6>/CYMUXG ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<7> .LOC = "CLB_R8C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<7> ( + .I0(\vga/ps2/Madd__addsub0000_cy[6] ), + .I1(\vga/ps2/_addsub0000<6>/GROM ), + .O(\vga/ps2/_addsub0000 [7]) + ); + defparam \vga/ps2/_addsub0000<6>/CYINIT .LOC = "CLB_R8C16.S1"; + X_BUF \vga/ps2/_addsub0000<6>/CYINIT ( + .I(\vga/ps2/_addsub0000<4>/CYMUXG ), + .O(\vga/ps2/_addsub0000<6>/CYINIT_115 ) + ); + defparam \vga/ps2/_addsub0000<8>/LOGIC_ZERO .LOC = "CLB_R7C16.S1"; + X_ZERO \vga/ps2/_addsub0000<8>/LOGIC_ZERO ( + .O(\vga/ps2/_addsub0000<8>/LOGIC_ZERO_116 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<8> .LOC = "CLB_R7C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<8> ( + .IA(\vga/ps2/_addsub0000<8>/LOGIC_ZERO_116 ), + .IB(\vga/ps2/_addsub0000<8>/CYINIT_117 ), + .SEL(\vga/ps2/_addsub0000<8>/FROM ), + .O(\vga/ps2/Madd__addsub0000_cy[8] ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<8> .LOC = "CLB_R7C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<8> ( + .I0(\vga/ps2/_addsub0000<8>/CYINIT_117 ), + .I1(\vga/ps2/_addsub0000<8>/FROM ), + .O(\vga/ps2/_addsub0000 [8]) + ); + defparam \vga/ps2/_addsub0000<8>/F .INIT = 16'hAAAA; + defparam \vga/ps2/_addsub0000<8>/F .LOC = "CLB_R7C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<8>/F ( + .ADR0(\vga/ps2/timer_r [8]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/_addsub0000<8>/FROM ) + ); + defparam \vga/ps2/_addsub0000<8>/G .INIT = 16'hCCCC; + defparam \vga/ps2/_addsub0000<8>/G .LOC = "CLB_R7C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<8>/G ( + .ADR0(VCC), + .ADR1(\vga/ps2/timer_r [9]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/_addsub0000<8>/GROM ) + ); + defparam \vga/ps2/_addsub0000<8>/XUSED .LOC = "CLB_R7C16.S1"; + X_BUF \vga/ps2/_addsub0000<8>/XUSED ( + .I(\vga/ps2/_addsub0000 [8]), + .O(\vga/ps2/_addsub0000<8>_0 ) + ); + defparam \vga/ps2/_addsub0000<8>/YUSED .LOC = "CLB_R7C16.S1"; + X_BUF \vga/ps2/_addsub0000<8>/YUSED ( + .I(\vga/ps2/_addsub0000 [9]), + .O(\vga/ps2/_addsub0000<9>_0 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<9> .LOC = "CLB_R7C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<9> ( + .IA(\vga/ps2/_addsub0000<8>/LOGIC_ZERO_116 ), + .IB(\vga/ps2/Madd__addsub0000_cy[8] ), + .SEL(\vga/ps2/_addsub0000<8>/GROM ), + .O(\vga/ps2/_addsub0000<8>/CYMUXG ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<9> .LOC = "CLB_R7C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<9> ( + .I0(\vga/ps2/Madd__addsub0000_cy[8] ), + .I1(\vga/ps2/_addsub0000<8>/GROM ), + .O(\vga/ps2/_addsub0000 [9]) + ); + defparam \vga/ps2/_addsub0000<8>/CYINIT .LOC = "CLB_R7C16.S1"; + X_BUF \vga/ps2/_addsub0000<8>/CYINIT ( + .I(\vga/ps2/_addsub0000<6>/CYMUXG ), + .O(\vga/ps2/_addsub0000<8>/CYINIT_117 ) + ); + defparam \vga/ps2/_addsub0000<10>/LOGIC_ZERO .LOC = "CLB_R6C16.S1"; + X_ZERO \vga/ps2/_addsub0000<10>/LOGIC_ZERO ( + .O(\vga/ps2/_addsub0000<10>/LOGIC_ZERO_118 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<10> .LOC = "CLB_R6C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<10> ( + .IA(\vga/ps2/_addsub0000<10>/LOGIC_ZERO_118 ), + .IB(\vga/ps2/_addsub0000<10>/CYINIT_119 ), + .SEL(\vga/ps2/_addsub0000<10>/FROM ), + .O(\vga/ps2/Madd__addsub0000_cy[10] ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<10> .LOC = "CLB_R6C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<10> ( + .I0(\vga/ps2/_addsub0000<10>/CYINIT_119 ), + .I1(\vga/ps2/_addsub0000<10>/FROM ), + .O(\vga/ps2/_addsub0000 [10]) + ); + defparam \vga/ps2/_addsub0000<10>/F .INIT = 16'hCCCC; + defparam \vga/ps2/_addsub0000<10>/F .LOC = "CLB_R6C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<10>/F ( + .ADR0(VCC), + .ADR1(\vga/ps2/timer_r [10]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/_addsub0000<10>/FROM ) + ); + defparam \vga/ps2/_addsub0000<10>/G .INIT = 16'hAAAA; + defparam \vga/ps2/_addsub0000<10>/G .LOC = "CLB_R6C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<10>/G ( + .ADR0(\vga/ps2/timer_r [11]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/_addsub0000<10>/GROM ) + ); + defparam \vga/ps2/_addsub0000<10>/XUSED .LOC = "CLB_R6C16.S1"; + X_BUF \vga/ps2/_addsub0000<10>/XUSED ( + .I(\vga/ps2/_addsub0000 [10]), + .O(\vga/ps2/_addsub0000<10>_0 ) + ); + defparam \vga/ps2/_addsub0000<10>/YUSED .LOC = "CLB_R6C16.S1"; + X_BUF \vga/ps2/_addsub0000<10>/YUSED ( + .I(\vga/ps2/_addsub0000 [11]), + .O(\vga/ps2/_addsub0000<11>_0 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<11> .LOC = "CLB_R6C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<11> ( + .IA(\vga/ps2/_addsub0000<10>/LOGIC_ZERO_118 ), + .IB(\vga/ps2/Madd__addsub0000_cy[10] ), + .SEL(\vga/ps2/_addsub0000<10>/GROM ), + .O(\vga/ps2/_addsub0000<10>/CYMUXG ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<11> .LOC = "CLB_R6C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<11> ( + .I0(\vga/ps2/Madd__addsub0000_cy[10] ), + .I1(\vga/ps2/_addsub0000<10>/GROM ), + .O(\vga/ps2/_addsub0000 [11]) + ); + defparam \vga/ps2/_addsub0000<10>/CYINIT .LOC = "CLB_R6C16.S1"; + X_BUF \vga/ps2/_addsub0000<10>/CYINIT ( + .I(\vga/ps2/_addsub0000<8>/CYMUXG ), + .O(\vga/ps2/_addsub0000<10>/CYINIT_119 ) + ); + defparam \vga/ps2/_addsub0000<12>/LOGIC_ZERO .LOC = "CLB_R5C16.S1"; + X_ZERO \vga/ps2/_addsub0000<12>/LOGIC_ZERO ( + .O(\vga/ps2/_addsub0000<12>/LOGIC_ZERO_120 ) + ); + defparam \vga/ps2/Madd__addsub0000_cy<12> .LOC = "CLB_R5C16.S1"; + X_MUX2 \vga/ps2/Madd__addsub0000_cy<12> ( + .IA(\vga/ps2/_addsub0000<12>/LOGIC_ZERO_120 ), + .IB(\vga/ps2/_addsub0000<12>/CYINIT_122 ), + .SEL(\vga/ps2/_addsub0000<12>/FROM ), + .O(\vga/ps2/Madd__addsub0000_cy[12] ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<12> .LOC = "CLB_R5C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<12> ( + .I0(\vga/ps2/_addsub0000<12>/CYINIT_122 ), + .I1(\vga/ps2/_addsub0000<12>/FROM ), + .O(\vga/ps2/_addsub0000 [12]) + ); + defparam \vga/ps2/_addsub0000<12>/F .INIT = 16'hFF00; + defparam \vga/ps2/_addsub0000<12>/F .LOC = "CLB_R5C16.S1"; + X_LUT4 \vga/ps2/_addsub0000<12>/F ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/timer_r [12]), + .O(\vga/ps2/_addsub0000<12>/FROM ) + ); + defparam \vga/ps2/timer_r<13>_rt .INIT = 16'hAAAA; + defparam \vga/ps2/timer_r<13>_rt .LOC = "CLB_R5C16.S1"; + X_LUT4 \vga/ps2/timer_r<13>_rt ( + .ADR0(\vga/ps2/timer_r [13]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/timer_r<13>_rt_121 ) + ); + defparam \vga/ps2/_addsub0000<12>/XUSED .LOC = "CLB_R5C16.S1"; + X_BUF \vga/ps2/_addsub0000<12>/XUSED ( + .I(\vga/ps2/_addsub0000 [12]), + .O(\vga/ps2/_addsub0000<12>_0 ) + ); + defparam \vga/ps2/_addsub0000<12>/YUSED .LOC = "CLB_R5C16.S1"; + X_BUF \vga/ps2/_addsub0000<12>/YUSED ( + .I(\vga/ps2/_addsub0000 [13]), + .O(\vga/ps2/_addsub0000<13>_0 ) + ); + defparam \vga/ps2/Madd__addsub0000_xor<13> .LOC = "CLB_R5C16.S1"; + X_XOR2 \vga/ps2/Madd__addsub0000_xor<13> ( + .I0(\vga/ps2/Madd__addsub0000_cy[12] ), + .I1(\vga/ps2/timer_r<13>_rt_121 ), + .O(\vga/ps2/_addsub0000 [13]) + ); + defparam \vga/ps2/_addsub0000<12>/CYINIT .LOC = "CLB_R5C16.S1"; + X_BUF \vga/ps2/_addsub0000<12>/CYINIT ( + .I(\vga/ps2/_addsub0000<10>/CYMUXG ), + .O(\vga/ps2/_addsub0000<12>/CYINIT_122 ) + ); + defparam \vga/crt/Result<1>/LOGIC_ZERO .LOC = "CLB_R16C12.S1"; + X_ZERO \vga/crt/Result<1>/LOGIC_ZERO ( + .O(\vga/crt/Result<1>/LOGIC_ZERO_123 ) + ); + defparam \vga/crt/Mcount_cursor_v_cy<0> .LOC = "CLB_R16C12.S1"; + X_MUX2 \vga/crt/Mcount_cursor_v_cy<0> ( + .IA(GLOBAL_LOGIC1), + .IB(\vga/crt/Result<1>/LOGIC_ZERO_123 ), + .SEL(\vga/crt/Result [0]), + .O(\vga/crt/Mcount_cursor_v_cy[0] ) + ); + defparam \vga/crt/Mcount_cursor_v_lut<0>_INV_0 .INIT = 16'h3333; + defparam \vga/crt/Mcount_cursor_v_lut<0>_INV_0 .LOC = "CLB_R16C12.S1"; + X_LUT4 \vga/crt/Mcount_cursor_v_lut<0>_INV_0 ( + .ADR0(GLOBAL_LOGIC1), + .ADR1(\vga/crt/cursor_v [0]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/Result [0]) + ); + defparam \vga/crt/Result<1>/G .INIT = 16'hFF00; + defparam \vga/crt/Result<1>/G .LOC = "CLB_R16C12.S1"; + X_LUT4 \vga/crt/Result<1>/G ( + .ADR0(GLOBAL_LOGIC0), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/crt/cursor_v [1]), + .O(\vga/crt/Result<1>/GROM ) + ); + defparam \vga/crt/Result<1>/YUSED .LOC = "CLB_R16C12.S1"; + X_BUF \vga/crt/Result<1>/YUSED ( + .I(\vga/crt/Result [1]), + .O(\vga/crt/Result<1>_0 ) + ); + defparam \vga/crt/Mcount_cursor_v_cy<1> .LOC = "CLB_R16C12.S1"; + X_MUX2 \vga/crt/Mcount_cursor_v_cy<1> ( + .IA(GLOBAL_LOGIC0), + .IB(\vga/crt/Mcount_cursor_v_cy[0] ), + .SEL(\vga/crt/Result<1>/GROM ), + .O(\vga/crt/Result<1>/CYMUXG ) + ); + defparam \vga/crt/Mcount_cursor_v_xor<1> .LOC = "CLB_R16C12.S1"; + X_XOR2 \vga/crt/Mcount_cursor_v_xor<1> ( + .I0(\vga/crt/Mcount_cursor_v_cy[0] ), + .I1(\vga/crt/Result<1>/GROM ), + .O(\vga/crt/Result [1]) + ); + defparam \vga/crt/Result<2>/LOGIC_ZERO .LOC = "CLB_R15C12.S1"; + X_ZERO \vga/crt/Result<2>/LOGIC_ZERO ( + .O(\vga/crt/Result<2>/LOGIC_ZERO_124 ) + ); + defparam \vga/crt/Mcount_cursor_v_cy<2> .LOC = "CLB_R15C12.S1"; + X_MUX2 \vga/crt/Mcount_cursor_v_cy<2> ( + .IA(\vga/crt/Result<2>/LOGIC_ZERO_124 ), + .IB(\vga/crt/Result<2>/CYINIT_125 ), + .SEL(\vga/crt/Result<2>/FROM ), + .O(\vga/crt/Mcount_cursor_v_cy[2] ) + ); + defparam \vga/crt/Mcount_cursor_v_xor<2> .LOC = "CLB_R15C12.S1"; + X_XOR2 \vga/crt/Mcount_cursor_v_xor<2> ( + .I0(\vga/crt/Result<2>/CYINIT_125 ), + .I1(\vga/crt/Result<2>/FROM ), + .O(\vga/crt/Result [2]) + ); + defparam \vga/crt/Result<2>/F .INIT = 16'hAAAA; + defparam \vga/crt/Result<2>/F .LOC = "CLB_R15C12.S1"; + X_LUT4 \vga/crt/Result<2>/F ( + .ADR0(\vga/crt/cursor_v [2]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/Result<2>/FROM ) + ); + defparam \vga/crt/Result<2>/G .INIT = 16'hCCCC; + defparam \vga/crt/Result<2>/G .LOC = "CLB_R15C12.S1"; + X_LUT4 \vga/crt/Result<2>/G ( + .ADR0(VCC), + .ADR1(\vga/crt/cursor_v [3]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/Result<2>/GROM ) + ); + defparam \vga/crt/Result<2>/XUSED .LOC = "CLB_R15C12.S1"; + X_BUF \vga/crt/Result<2>/XUSED ( + .I(\vga/crt/Result [2]), + .O(\vga/crt/Result<2>_0 ) + ); + defparam \vga/crt/Result<2>/YUSED .LOC = "CLB_R15C12.S1"; + X_BUF \vga/crt/Result<2>/YUSED ( + .I(\vga/crt/Result [3]), + .O(\vga/crt/Result<3>_0 ) + ); + defparam \vga/crt/Mcount_cursor_v_cy<3> .LOC = "CLB_R15C12.S1"; + X_MUX2 \vga/crt/Mcount_cursor_v_cy<3> ( + .IA(\vga/crt/Result<2>/LOGIC_ZERO_124 ), + .IB(\vga/crt/Mcount_cursor_v_cy[2] ), + .SEL(\vga/crt/Result<2>/GROM ), + .O(\vga/crt/Result<2>/CYMUXG ) + ); + defparam \vga/crt/Mcount_cursor_v_xor<3> .LOC = "CLB_R15C12.S1"; + X_XOR2 \vga/crt/Mcount_cursor_v_xor<3> ( + .I0(\vga/crt/Mcount_cursor_v_cy[2] ), + .I1(\vga/crt/Result<2>/GROM ), + .O(\vga/crt/Result [3]) + ); + defparam \vga/crt/Result<2>/CYINIT .LOC = "CLB_R15C12.S1"; + X_BUF \vga/crt/Result<2>/CYINIT ( + .I(\vga/crt/Result<1>/CYMUXG ), + .O(\vga/crt/Result<2>/CYINIT_125 ) + ); + defparam \vga/crt/Result<4>/LOGIC_ZERO .LOC = "CLB_R14C12.S1"; + X_ZERO \vga/crt/Result<4>/LOGIC_ZERO ( + .O(\vga/crt/Result<4>/LOGIC_ZERO_126 ) + ); + defparam \vga/crt/Mcount_cursor_v_cy<4> .LOC = "CLB_R14C12.S1"; + X_MUX2 \vga/crt/Mcount_cursor_v_cy<4> ( + .IA(\vga/crt/Result<4>/LOGIC_ZERO_126 ), + .IB(\vga/crt/Result<4>/CYINIT_127 ), + .SEL(\vga/crt/Result<4>/FROM ), + .O(\vga/crt/Mcount_cursor_v_cy[4] ) + ); + defparam \vga/crt/Mcount_cursor_v_xor<4> .LOC = "CLB_R14C12.S1"; + X_XOR2 \vga/crt/Mcount_cursor_v_xor<4> ( + .I0(\vga/crt/Result<4>/CYINIT_127 ), + .I1(\vga/crt/Result<4>/FROM ), + .O(\vga/crt/Result [4]) + ); + defparam \vga/crt/Result<4>/F .INIT = 16'hCCCC; + defparam \vga/crt/Result<4>/F .LOC = "CLB_R14C12.S1"; + X_LUT4 \vga/crt/Result<4>/F ( + .ADR0(VCC), + .ADR1(\vga/crt/cursor_v [4]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/Result<4>/FROM ) + ); + defparam \vga/crt/cursor_v<5>_rt.1 .INIT = 16'hF0F0; + defparam \vga/crt/cursor_v<5>_rt.1 .LOC = "CLB_R14C12.S1"; + X_LUT4 \vga/crt/cursor_v<5>_rt.1 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_v [5]), + .ADR3(VCC), + .O(\vga/crt/Result<4>/GROM ) + ); + defparam \vga/crt/Result<4>/XUSED .LOC = "CLB_R14C12.S1"; + X_BUF \vga/crt/Result<4>/XUSED ( + .I(\vga/crt/Result [4]), + .O(\vga/crt/Result<4>_0 ) + ); + defparam \vga/crt/Result<4>/YUSED .LOC = "CLB_R14C12.S1"; + X_BUF \vga/crt/Result<4>/YUSED ( + .I(\vga/crt/Result [5]), + .O(\vga/crt/Result<5>_0 ) + ); + defparam \vga/crt/Mcount_cursor_v_xor<5> .LOC = "CLB_R14C12.S1"; + X_XOR2 \vga/crt/Mcount_cursor_v_xor<5> ( + .I0(\vga/crt/Mcount_cursor_v_cy[4] ), + .I1(\vga/crt/Result<4>/GROM ), + .O(\vga/crt/Result [5]) + ); + defparam \vga/crt/Result<4>/CYINIT .LOC = "CLB_R14C12.S1"; + X_BUF \vga/crt/Result<4>/CYINIT ( + .I(\vga/crt/Result<2>/CYMUXG ), + .O(\vga/crt/Result<4>/CYINIT_127 ) + ); + defparam \vga/crt/Result<1>1/LOGIC_ZERO .LOC = "CLB_R19C12.S0"; + X_ZERO \vga/crt/Result<1>1/LOGIC_ZERO ( + .O(\vga/crt/Result<1>1/LOGIC_ZERO_128 ) + ); + defparam \vga/crt/Mcount_cursor_h_cy<0> .LOC = "CLB_R19C12.S0"; + X_MUX2 \vga/crt/Mcount_cursor_h_cy<0> ( + .IA(GLOBAL_LOGIC1), + .IB(\vga/crt/Result<1>1/LOGIC_ZERO_128 ), + .SEL(\vga/crt/Result<0>1 ), + .O(\vga/crt/Mcount_cursor_h_cy[0] ) + ); + defparam \vga/crt/Mcount_cursor_h_lut<0>_INV_0 .INIT = 16'h0F0F; + defparam \vga/crt/Mcount_cursor_h_lut<0>_INV_0 .LOC = "CLB_R19C12.S0"; + X_LUT4 \vga/crt/Mcount_cursor_h_lut<0>_INV_0 ( + .ADR0(GLOBAL_LOGIC1), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_h [0]), + .ADR3(VCC), + .O(\vga/crt/Result<0>1 ) + ); + defparam \vga/crt/Result<1>1/G .INIT = 16'hF0F0; + defparam \vga/crt/Result<1>1/G .LOC = "CLB_R19C12.S0"; + X_LUT4 \vga/crt/Result<1>1/G ( + .ADR0(GLOBAL_LOGIC0), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_h [1]), + .ADR3(VCC), + .O(\vga/crt/Result<1>1/GROM ) + ); + defparam \vga/crt/Result<1>1/YUSED .LOC = "CLB_R19C12.S0"; + X_BUF \vga/crt/Result<1>1/YUSED ( + .I(\vga/crt/Result<1>1 ), + .O(\vga/crt/Result<1>1_0 ) + ); + defparam \vga/crt/Mcount_cursor_h_cy<1> .LOC = "CLB_R19C12.S0"; + X_MUX2 \vga/crt/Mcount_cursor_h_cy<1> ( + .IA(GLOBAL_LOGIC0), + .IB(\vga/crt/Mcount_cursor_h_cy[0] ), + .SEL(\vga/crt/Result<1>1/GROM ), + .O(\vga/crt/Result<1>1/CYMUXG ) + ); + defparam \vga/crt/Mcount_cursor_h_xor<1> .LOC = "CLB_R19C12.S0"; + X_XOR2 \vga/crt/Mcount_cursor_h_xor<1> ( + .I0(\vga/crt/Mcount_cursor_h_cy[0] ), + .I1(\vga/crt/Result<1>1/GROM ), + .O(\vga/crt/Result<1>1 ) + ); + defparam \vga/crt/Result<2>1/LOGIC_ZERO .LOC = "CLB_R18C12.S0"; + X_ZERO \vga/crt/Result<2>1/LOGIC_ZERO ( + .O(\vga/crt/Result<2>1/LOGIC_ZERO_129 ) + ); + defparam \vga/crt/Mcount_cursor_h_cy<2> .LOC = "CLB_R18C12.S0"; + X_MUX2 \vga/crt/Mcount_cursor_h_cy<2> ( + .IA(\vga/crt/Result<2>1/LOGIC_ZERO_129 ), + .IB(\vga/crt/Result<2>1/CYINIT_130 ), + .SEL(\vga/crt/Result<2>1/FROM ), + .O(\vga/crt/Mcount_cursor_h_cy[2] ) + ); + defparam \vga/crt/Mcount_cursor_h_xor<2> .LOC = "CLB_R18C12.S0"; + X_XOR2 \vga/crt/Mcount_cursor_h_xor<2> ( + .I0(\vga/crt/Result<2>1/CYINIT_130 ), + .I1(\vga/crt/Result<2>1/FROM ), + .O(\vga/crt/Result<2>1 ) + ); + defparam \vga/crt/Result<2>1/F .INIT = 16'hCCCC; + defparam \vga/crt/Result<2>1/F .LOC = "CLB_R18C12.S0"; + X_LUT4 \vga/crt/Result<2>1/F ( + .ADR0(VCC), + .ADR1(\vga/crt/cursor_h [2]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/Result<2>1/FROM ) + ); + defparam \vga/crt/Result<2>1/G .INIT = 16'hAAAA; + defparam \vga/crt/Result<2>1/G .LOC = "CLB_R18C12.S0"; + X_LUT4 \vga/crt/Result<2>1/G ( + .ADR0(\vga/crt/cursor_h [3]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/Result<2>1/GROM ) + ); + defparam \vga/crt/Result<2>1/XUSED .LOC = "CLB_R18C12.S0"; + X_BUF \vga/crt/Result<2>1/XUSED ( + .I(\vga/crt/Result<2>1 ), + .O(\vga/crt/Result<2>1_0 ) + ); + defparam \vga/crt/Result<2>1/YUSED .LOC = "CLB_R18C12.S0"; + X_BUF \vga/crt/Result<2>1/YUSED ( + .I(\vga/crt/Result<3>1 ), + .O(\vga/crt/Result<3>1_0 ) + ); + defparam \vga/crt/Mcount_cursor_h_cy<3> .LOC = "CLB_R18C12.S0"; + X_MUX2 \vga/crt/Mcount_cursor_h_cy<3> ( + .IA(\vga/crt/Result<2>1/LOGIC_ZERO_129 ), + .IB(\vga/crt/Mcount_cursor_h_cy[2] ), + .SEL(\vga/crt/Result<2>1/GROM ), + .O(\vga/crt/Result<2>1/CYMUXG ) + ); + defparam \vga/crt/Mcount_cursor_h_xor<3> .LOC = "CLB_R18C12.S0"; + X_XOR2 \vga/crt/Mcount_cursor_h_xor<3> ( + .I0(\vga/crt/Mcount_cursor_h_cy[2] ), + .I1(\vga/crt/Result<2>1/GROM ), + .O(\vga/crt/Result<3>1 ) + ); + defparam \vga/crt/Result<2>1/CYINIT .LOC = "CLB_R18C12.S0"; + X_BUF \vga/crt/Result<2>1/CYINIT ( + .I(\vga/crt/Result<1>1/CYMUXG ), + .O(\vga/crt/Result<2>1/CYINIT_130 ) + ); + defparam \vga/crt/Result<4>1/LOGIC_ZERO .LOC = "CLB_R17C12.S0"; + X_ZERO \vga/crt/Result<4>1/LOGIC_ZERO ( + .O(\vga/crt/Result<4>1/LOGIC_ZERO_131 ) + ); + defparam \vga/crt/Mcount_cursor_h_cy<4> .LOC = "CLB_R17C12.S0"; + X_MUX2 \vga/crt/Mcount_cursor_h_cy<4> ( + .IA(\vga/crt/Result<4>1/LOGIC_ZERO_131 ), + .IB(\vga/crt/Result<4>1/CYINIT_132 ), + .SEL(\vga/crt/Result<4>1/FROM ), + .O(\vga/crt/Mcount_cursor_h_cy[4] ) + ); + defparam \vga/crt/Mcount_cursor_h_xor<4> .LOC = "CLB_R17C12.S0"; + X_XOR2 \vga/crt/Mcount_cursor_h_xor<4> ( + .I0(\vga/crt/Result<4>1/CYINIT_132 ), + .I1(\vga/crt/Result<4>1/FROM ), + .O(\vga/crt/Result<4>1 ) + ); + defparam \vga/crt/Result<4>1/F .INIT = 16'hF0F0; + defparam \vga/crt/Result<4>1/F .LOC = "CLB_R17C12.S0"; + X_LUT4 \vga/crt/Result<4>1/F ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_h [4]), + .ADR3(VCC), + .O(\vga/crt/Result<4>1/FROM ) + ); + defparam \vga/crt/Result<4>1/G .INIT = 16'hFF00; + defparam \vga/crt/Result<4>1/G .LOC = "CLB_R17C12.S0"; + X_LUT4 \vga/crt/Result<4>1/G ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/crt/cursor_h [5]), + .O(\vga/crt/Result<4>1/GROM ) + ); + defparam \vga/crt/Result<4>1/XUSED .LOC = "CLB_R17C12.S0"; + X_BUF \vga/crt/Result<4>1/XUSED ( + .I(\vga/crt/Result<4>1 ), + .O(\vga/crt/Result<4>1_0 ) + ); + defparam \vga/crt/Result<4>1/YUSED .LOC = "CLB_R17C12.S0"; + X_BUF \vga/crt/Result<4>1/YUSED ( + .I(\vga/crt/Result<5>1 ), + .O(\vga/crt/Result<5>1_0 ) + ); + defparam \vga/crt/Mcount_cursor_h_cy<5> .LOC = "CLB_R17C12.S0"; + X_MUX2 \vga/crt/Mcount_cursor_h_cy<5> ( + .IA(\vga/crt/Result<4>1/LOGIC_ZERO_131 ), + .IB(\vga/crt/Mcount_cursor_h_cy[4] ), + .SEL(\vga/crt/Result<4>1/GROM ), + .O(\vga/crt/Result<4>1/CYMUXG ) + ); + defparam \vga/crt/Mcount_cursor_h_xor<5> .LOC = "CLB_R17C12.S0"; + X_XOR2 \vga/crt/Mcount_cursor_h_xor<5> ( + .I0(\vga/crt/Mcount_cursor_h_cy[4] ), + .I1(\vga/crt/Result<4>1/GROM ), + .O(\vga/crt/Result<5>1 ) + ); + defparam \vga/crt/Result<4>1/CYINIT .LOC = "CLB_R17C12.S0"; + X_BUF \vga/crt/Result<4>1/CYINIT ( + .I(\vga/crt/Result<2>1/CYMUXG ), + .O(\vga/crt/Result<4>1/CYINIT_132 ) + ); + defparam \vga/crt/Mcount_cursor_h_xor<6> .LOC = "CLB_R16C12.S0"; + X_XOR2 \vga/crt/Mcount_cursor_h_xor<6> ( + .I0(\vga/crt/Result<6>/CYINIT_134 ), + .I1(\vga/crt/cursor_h<6>_rt_133 ), + .O(\vga/crt/Result [6]) + ); + defparam \vga/crt/cursor_h<6>_rt .INIT = 16'hF0F0; + defparam \vga/crt/cursor_h<6>_rt .LOC = "CLB_R16C12.S0"; + X_LUT4 \vga/crt/cursor_h<6>_rt ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_h [6]), + .ADR3(VCC), + .O(\vga/crt/cursor_h<6>_rt_133 ) + ); + defparam \vga/crt/Result<6>/XUSED .LOC = "CLB_R16C12.S0"; + X_BUF \vga/crt/Result<6>/XUSED ( + .I(\vga/crt/Result [6]), + .O(\vga/crt/Result<6>_0 ) + ); + defparam \vga/crt/Result<6>/CYINIT .LOC = "CLB_R16C12.S0"; + X_BUF \vga/crt/Result<6>/CYINIT ( + .I(\vga/crt/Result<4>1/CYMUXG ), + .O(\vga/crt/Result<6>/CYINIT_134 ) + ); + defparam \vga/vgacore/hcnt<1>/LOGIC_ZERO .LOC = "CLB_R19C7.S1"; + X_ZERO \vga/vgacore/hcnt<1>/LOGIC_ZERO ( + .O(\vga/vgacore/hcnt<1>/LOGIC_ZERO_135 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<1> .LOC = "CLB_R19C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<1> ( + .IA(\vga/vgacore/hcnt<1>/LOGIC_ZERO_135 ), + .IB(\vga/vgacore/hcnt<1>/CYINIT_136 ), + .SEL(\vga/vgacore/hcnt_Eqn_1 ), + .O(\vga/vgacore/Mcount_hcnt_cy[1] ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<1> .LOC = "CLB_R19C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<1> ( + .I0(\vga/vgacore/hcnt<1>/CYINIT_136 ), + .I1(\vga/vgacore/hcnt_Eqn_1 ), + .O(\vga/vgacore/Result [1]) + ); + defparam \vga/vgacore/hcnt_Eqn_11 .INIT = 16'hF000; + defparam \vga/vgacore/hcnt_Eqn_11 .LOC = "CLB_R19C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_11 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [1]), + .ADR3(\vga/vgacore/hcnt_Eqn_bis_0 ), + .O(\vga/vgacore/hcnt_Eqn_1 ) + ); + defparam \vga/vgacore/hcnt_Eqn_21 .INIT = 16'hF000; + defparam \vga/vgacore/hcnt_Eqn_21 .LOC = "CLB_R19C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_21 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt_Eqn_bis_0 ), + .ADR3(\vga/vgacore/hcnt [2]), + .O(\vga/vgacore/hcnt_Eqn_2 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<2> .LOC = "CLB_R19C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<2> ( + .IA(\vga/vgacore/hcnt<1>/LOGIC_ZERO_135 ), + .IB(\vga/vgacore/Mcount_hcnt_cy[1] ), + .SEL(\vga/vgacore/hcnt_Eqn_2 ), + .O(\vga/vgacore/hcnt<1>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<2> .LOC = "CLB_R19C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<2> ( + .I0(\vga/vgacore/Mcount_hcnt_cy[1] ), + .I1(\vga/vgacore/hcnt_Eqn_2 ), + .O(\vga/vgacore/Result [2]) + ); + defparam \vga/vgacore/hcnt<1>/SRMUX .LOC = "CLB_R19C7.S1"; + X_INV \vga/vgacore/hcnt<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hcnt<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/hcnt<1>/CYINIT .LOC = "CLB_R19C7.S1"; + X_BUF \vga/vgacore/hcnt<1>/CYINIT ( + .I(\vga/vgacore/hcnt<0>/CYMUXG ), + .O(\vga/vgacore/hcnt<1>/CYINIT_136 ) + ); + defparam \vga/vgacore/hcnt_1 .LOC = "CLB_R19C7.S1"; + defparam \vga/vgacore/hcnt_1 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_1 ( + .I(\vga/vgacore/Result [1]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<1>/FFX/RST ), + .O(\vga/vgacore/hcnt [1]) + ); + defparam \vga/vgacore/hcnt<1>/FFX/RSTOR .LOC = "CLB_R19C7.S1"; + X_BUF \vga/vgacore/hcnt<1>/FFX/RSTOR ( + .I(\vga/vgacore/hcnt<1>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<1>/FFX/RST ) + ); + defparam \vga/vgacore/hcnt<3>/LOGIC_ZERO .LOC = "CLB_R18C7.S1"; + X_ZERO \vga/vgacore/hcnt<3>/LOGIC_ZERO ( + .O(\vga/vgacore/hcnt<3>/LOGIC_ZERO_137 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<3> .LOC = "CLB_R18C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<3> ( + .IA(\vga/vgacore/hcnt<3>/LOGIC_ZERO_137 ), + .IB(\vga/vgacore/hcnt<3>/CYINIT_138 ), + .SEL(\vga/vgacore/hcnt_Eqn_3 ), + .O(\vga/vgacore/Mcount_hcnt_cy[3] ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<3> .LOC = "CLB_R18C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<3> ( + .I0(\vga/vgacore/hcnt<3>/CYINIT_138 ), + .I1(\vga/vgacore/hcnt_Eqn_3 ), + .O(\vga/vgacore/Result [3]) + ); + defparam \vga/vgacore/hcnt_Eqn_31 .INIT = 16'hCC00; + defparam \vga/vgacore/hcnt_Eqn_31 .LOC = "CLB_R18C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_31 ( + .ADR0(VCC), + .ADR1(\vga/vgacore/hcnt [3]), + .ADR2(VCC), + .ADR3(\vga/vgacore/hcnt_Eqn_bis_0 ), + .O(\vga/vgacore/hcnt_Eqn_3 ) + ); + defparam \vga/vgacore/hcnt_Eqn_41 .INIT = 16'h8888; + defparam \vga/vgacore/hcnt_Eqn_41 .LOC = "CLB_R18C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_41 ( + .ADR0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .ADR1(\vga/vgacore/hcnt [4]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/vgacore/hcnt_Eqn_4 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<4> .LOC = "CLB_R18C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<4> ( + .IA(\vga/vgacore/hcnt<3>/LOGIC_ZERO_137 ), + .IB(\vga/vgacore/Mcount_hcnt_cy[3] ), + .SEL(\vga/vgacore/hcnt_Eqn_4 ), + .O(\vga/vgacore/hcnt<3>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<4> .LOC = "CLB_R18C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<4> ( + .I0(\vga/vgacore/Mcount_hcnt_cy[3] ), + .I1(\vga/vgacore/hcnt_Eqn_4 ), + .O(\vga/vgacore/Result [4]) + ); + defparam \vga/vgacore/hcnt<3>/SRMUX .LOC = "CLB_R18C7.S1"; + X_INV \vga/vgacore/hcnt<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hcnt<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/hcnt<3>/CYINIT .LOC = "CLB_R18C7.S1"; + X_BUF \vga/vgacore/hcnt<3>/CYINIT ( + .I(\vga/vgacore/hcnt<1>/CYMUXG ), + .O(\vga/vgacore/hcnt<3>/CYINIT_138 ) + ); + defparam \vga/vgacore/hcnt<5>/LOGIC_ZERO .LOC = "CLB_R17C7.S1"; + X_ZERO \vga/vgacore/hcnt<5>/LOGIC_ZERO ( + .O(\vga/vgacore/hcnt<5>/LOGIC_ZERO_139 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<5> .LOC = "CLB_R17C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<5> ( + .IA(\vga/vgacore/hcnt<5>/LOGIC_ZERO_139 ), + .IB(\vga/vgacore/hcnt<5>/CYINIT_140 ), + .SEL(\vga/vgacore/hcnt_Eqn_5 ), + .O(\vga/vgacore/Mcount_hcnt_cy[5] ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<5> .LOC = "CLB_R17C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<5> ( + .I0(\vga/vgacore/hcnt<5>/CYINIT_140 ), + .I1(\vga/vgacore/hcnt_Eqn_5 ), + .O(\vga/vgacore/Result [5]) + ); + defparam \vga/vgacore/hcnt_Eqn_51 .INIT = 16'hF000; + defparam \vga/vgacore/hcnt_Eqn_51 .LOC = "CLB_R17C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_51 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt_Eqn_bis_0 ), + .ADR3(\vga/vgacore/hcnt [5]), + .O(\vga/vgacore/hcnt_Eqn_5 ) + ); + defparam \vga/vgacore/hcnt_Eqn_61 .INIT = 16'hAA00; + defparam \vga/vgacore/hcnt_Eqn_61 .LOC = "CLB_R17C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_61 ( + .ADR0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/vgacore/hcnt [6]), + .O(\vga/vgacore/hcnt_Eqn_6 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<6> .LOC = "CLB_R17C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<6> ( + .IA(\vga/vgacore/hcnt<5>/LOGIC_ZERO_139 ), + .IB(\vga/vgacore/Mcount_hcnt_cy[5] ), + .SEL(\vga/vgacore/hcnt_Eqn_6 ), + .O(\vga/vgacore/hcnt<5>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<6> .LOC = "CLB_R17C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<6> ( + .I0(\vga/vgacore/Mcount_hcnt_cy[5] ), + .I1(\vga/vgacore/hcnt_Eqn_6 ), + .O(\vga/vgacore/Result [6]) + ); + defparam \vga/vgacore/hcnt<5>/SRMUX .LOC = "CLB_R17C7.S1"; + X_INV \vga/vgacore/hcnt<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hcnt<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/hcnt<5>/CYINIT .LOC = "CLB_R17C7.S1"; + X_BUF \vga/vgacore/hcnt<5>/CYINIT ( + .I(\vga/vgacore/hcnt<3>/CYMUXG ), + .O(\vga/vgacore/hcnt<5>/CYINIT_140 ) + ); + defparam \vga/vgacore/hcnt<7>/LOGIC_ZERO .LOC = "CLB_R16C7.S1"; + X_ZERO \vga/vgacore/hcnt<7>/LOGIC_ZERO ( + .O(\vga/vgacore/hcnt<7>/LOGIC_ZERO_141 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<7> .LOC = "CLB_R16C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<7> ( + .IA(\vga/vgacore/hcnt<7>/LOGIC_ZERO_141 ), + .IB(\vga/vgacore/hcnt<7>/CYINIT_142 ), + .SEL(\vga/vgacore/hcnt_Eqn_7 ), + .O(\vga/vgacore/Mcount_hcnt_cy[7] ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<7> .LOC = "CLB_R16C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<7> ( + .I0(\vga/vgacore/hcnt<7>/CYINIT_142 ), + .I1(\vga/vgacore/hcnt_Eqn_7 ), + .O(\vga/vgacore/Result [7]) + ); + defparam \vga/vgacore/hcnt_Eqn_71 .INIT = 16'hA0A0; + defparam \vga/vgacore/hcnt_Eqn_71 .LOC = "CLB_R16C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_71 ( + .ADR0(\vga/vgacore/hcnt [7]), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt_Eqn_bis_0 ), + .ADR3(VCC), + .O(\vga/vgacore/hcnt_Eqn_7 ) + ); + defparam \vga/vgacore/hcnt_Eqn_81 .INIT = 16'hF000; + defparam \vga/vgacore/hcnt_Eqn_81 .LOC = "CLB_R16C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_81 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [8]), + .ADR3(\vga/vgacore/hcnt_Eqn_bis_0 ), + .O(\vga/vgacore/hcnt_Eqn_8 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<8> .LOC = "CLB_R16C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<8> ( + .IA(\vga/vgacore/hcnt<7>/LOGIC_ZERO_141 ), + .IB(\vga/vgacore/Mcount_hcnt_cy[7] ), + .SEL(\vga/vgacore/hcnt_Eqn_8 ), + .O(\vga/vgacore/hcnt<7>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<8> .LOC = "CLB_R16C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<8> ( + .I0(\vga/vgacore/Mcount_hcnt_cy[7] ), + .I1(\vga/vgacore/hcnt_Eqn_8 ), + .O(\vga/vgacore/Result [8]) + ); + defparam \vga/vgacore/hcnt<7>/SRMUX .LOC = "CLB_R16C7.S1"; + X_INV \vga/vgacore/hcnt<7>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hcnt<7>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/hcnt<7>/CYINIT .LOC = "CLB_R16C7.S1"; + X_BUF \vga/vgacore/hcnt<7>/CYINIT ( + .I(\vga/vgacore/hcnt<5>/CYMUXG ), + .O(\vga/vgacore/hcnt<7>/CYINIT_142 ) + ); + defparam \vga/vgacore/hcnt<9>/LOGIC_ZERO .LOC = "CLB_R15C7.S1"; + X_ZERO \vga/vgacore/hcnt<9>/LOGIC_ZERO ( + .O(\vga/vgacore/hcnt<9>/LOGIC_ZERO_143 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<9> .LOC = "CLB_R15C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<9> ( + .IA(\vga/vgacore/hcnt<9>/LOGIC_ZERO_143 ), + .IB(\vga/vgacore/hcnt<9>/CYINIT_144 ), + .SEL(\vga/vgacore/hcnt_Eqn_9 ), + .O(\vga/vgacore/Mcount_hcnt_cy[9] ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<9> .LOC = "CLB_R15C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<9> ( + .I0(\vga/vgacore/hcnt<9>/CYINIT_144 ), + .I1(\vga/vgacore/hcnt_Eqn_9 ), + .O(\vga/vgacore/Result [9]) + ); + defparam \vga/vgacore/hcnt_Eqn_91 .INIT = 16'hCC00; + defparam \vga/vgacore/hcnt_Eqn_91 .LOC = "CLB_R15C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_91 ( + .ADR0(VCC), + .ADR1(\vga/vgacore/hcnt [9]), + .ADR2(VCC), + .ADR3(\vga/vgacore/hcnt_Eqn_bis_0 ), + .O(\vga/vgacore/hcnt_Eqn_9 ) + ); + defparam \vga/vgacore/hcnt_Eqn_101 .INIT = 16'hF000; + defparam \vga/vgacore/hcnt_Eqn_101 .LOC = "CLB_R15C7.S1"; + X_LUT4 \vga/vgacore/hcnt_Eqn_101 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [10]), + .ADR3(\vga/vgacore/hcnt_Eqn_bis_0 ), + .O(\vga/vgacore/hcnt_Eqn_10 ) + ); + defparam \vga/vgacore/Mcount_hcnt_xor<10> .LOC = "CLB_R15C7.S1"; + X_XOR2 \vga/vgacore/Mcount_hcnt_xor<10> ( + .I0(\vga/vgacore/Mcount_hcnt_cy[9] ), + .I1(\vga/vgacore/hcnt_Eqn_10 ), + .O(\vga/vgacore/Result [10]) + ); + defparam \vga/vgacore/hcnt<9>/SRMUX .LOC = "CLB_R15C7.S1"; + X_INV \vga/vgacore/hcnt<9>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hcnt<9>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/hcnt<9>/CYINIT .LOC = "CLB_R15C7.S1"; + X_BUF \vga/vgacore/hcnt<9>/CYINIT ( + .I(\vga/vgacore/hcnt<7>/CYMUXG ), + .O(\vga/vgacore/hcnt<9>/CYINIT_144 ) + ); + defparam \vga/vgacore/hcnt_9 .LOC = "CLB_R15C7.S1"; + defparam \vga/vgacore/hcnt_9 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_9 ( + .I(\vga/vgacore/Result [9]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<9>/FFX/RST ), + .O(\vga/vgacore/hcnt [9]) + ); + defparam \vga/vgacore/hcnt<9>/FFX/RSTOR .LOC = "CLB_R15C7.S1"; + X_BUF \vga/vgacore/hcnt<9>/FFX/RSTOR ( + .I(\vga/vgacore/hcnt<9>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<9>/FFX/RST ) + ); + defparam \vga/vgacore/vcnt<0>/LOGIC_ONE .LOC = "CLB_R19C9.S1"; + X_ONE \vga/vgacore/vcnt<0>/LOGIC_ONE ( + .O(\vga/vgacore/vcnt<0>/LOGIC_ONE_145 ) + ); + defparam \vga/vgacore/vcnt<0>/LOGIC_ZERO .LOC = "CLB_R19C9.S1"; + X_ZERO \vga/vgacore/vcnt<0>/LOGIC_ZERO ( + .O(\vga/vgacore/vcnt<0>/LOGIC_ZERO_147 ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<0> .LOC = "CLB_R19C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<0> ( + .IA(\vga/vgacore/vcnt_Eqn_0_mand1 ), + .IB(\vga/vgacore/vcnt<0>/LOGIC_ZERO_147 ), + .SEL(\vga/vgacore/Result<0>1 ), + .O(\vga/vgacore/Mcount_vcnt_cy<0>_rt_146 ) + ); + defparam \vga/vgacore/vcnt_Eqn_0_mand .LOC = "CLB_R19C9.S1"; + X_AND2 \vga/vgacore/vcnt_Eqn_0_mand ( + .I0(\vga/vgacore/vcnt_Eqn_bis_0_0 ), + .I1(\vga/vgacore/vcnt [0]), + .O(\vga/vgacore/vcnt_Eqn_0_mand1 ) + ); + defparam \vga/vgacore/Mcount_vcnt_lut<0> .INIT = 16'h4444; + defparam \vga/vgacore/Mcount_vcnt_lut<0> .LOC = "CLB_R19C9.S1"; + X_LUT4 \vga/vgacore/Mcount_vcnt_lut<0> ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt_Eqn_bis_0_0 ), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/vgacore/Result<0>1 ) + ); + defparam \vga/vgacore/Mcount_vcnt_lut<0>_1 .INIT = 16'h4444; + defparam \vga/vgacore/Mcount_vcnt_lut<0>_1 .LOC = "CLB_R19C9.S1"; + X_LUT4 \vga/vgacore/Mcount_vcnt_lut<0>_1 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt_Eqn_bis_0_0 ), + .ADR2(VCC), + .ADR3(VCC), + .O(N3216) + ); + defparam \vga/vgacore/vcnt<0>/CKINV .LOC = "CLB_R19C9.S1"; + X_INV \vga/vgacore/vcnt<0>/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt<0>/CKMUXNOT ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<0>_rt .LOC = "CLB_R19C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<0>_rt ( + .IA(\NLW_vga/vgacore/Mcount_vcnt_cy<0>_rt_IA_UNCONNECTED ), + .IB(\vga/vgacore/Mcount_vcnt_cy<0>_rt_146 ), + .SEL(\vga/vgacore/vcnt<0>/LOGIC_ONE_145 ), + .O(\vga/vgacore/vcnt<0>/CYMUXG ) + ); + defparam \vga/vgacore/vcnt<0>/SRMUX .LOC = "CLB_R19C9.S1"; + X_INV \vga/vgacore/vcnt<0>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt<0>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/vcnt_0 .LOC = "CLB_R19C9.S1"; + defparam \vga/vgacore/vcnt_0 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_0 ( + .I(\vga/vgacore/Result<0>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<0>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<0>/FFX/RST ), + .O(\vga/vgacore/vcnt [0]) + ); + defparam \vga/vgacore/vcnt<0>/FFX/RSTOR .LOC = "CLB_R19C9.S1"; + X_BUF \vga/vgacore/vcnt<0>/FFX/RSTOR ( + .I(\vga/vgacore/vcnt<0>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<0>/FFX/RST ) + ); + defparam \vga/vgacore/vcnt<1>/LOGIC_ZERO .LOC = "CLB_R18C9.S1"; + X_ZERO \vga/vgacore/vcnt<1>/LOGIC_ZERO ( + .O(\vga/vgacore/vcnt<1>/LOGIC_ZERO_149 ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<1> .LOC = "CLB_R18C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<1> ( + .IA(\vga/vgacore/vcnt<1>/LOGIC_ZERO_149 ), + .IB(\vga/vgacore/vcnt<1>/CYINIT_150 ), + .SEL(\vga/vgacore/vcnt_Eqn_1_148 ), + .O(\vga/vgacore/Mcount_vcnt_cy[1] ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<1> .LOC = "CLB_R18C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<1> ( + .I0(\vga/vgacore/vcnt<1>/CYINIT_150 ), + .I1(\vga/vgacore/vcnt_Eqn_1_148 ), + .O(\vga/vgacore/Result<1>1 ) + ); + defparam \vga/vgacore/vcnt_Eqn_1 .INIT = 16'h08CC; + defparam \vga/vgacore/vcnt_Eqn_1 .LOC = "CLB_R18C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_1 ( + .ADR0(\vga/vgacore/N51_0 ), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(N839_0), + .ADR3(\vga/vgacore/vcnt [9]), + .O(\vga/vgacore/vcnt_Eqn_1_148 ) + ); + defparam \vga/vgacore/vcnt_Eqn_21 .INIT = 16'h20AA; + defparam \vga/vgacore/vcnt_Eqn_21 .LOC = "CLB_R18C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_21 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [3]), + .ADR2(\vga/vgacore/N51_0 ), + .ADR3(\vga/vgacore/vcnt [9]), + .O(\vga/vgacore/vcnt_Eqn_2 ) + ); + defparam \vga/vgacore/vcnt<1>/XUSED .LOC = "CLB_R18C9.S1"; + X_BUF \vga/vgacore/vcnt<1>/XUSED ( + .I(\vga/vgacore/Result<1>1 ), + .O(\vga/vgacore/Result<1>1_0 ) + ); + defparam \vga/vgacore/vcnt<1>/CKINV .LOC = "CLB_R18C9.S1"; + X_INV \vga/vgacore/vcnt<1>/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt<1>/CKMUXNOT ) + ); + defparam \vga/vgacore/vcnt<1>/YUSED .LOC = "CLB_R18C9.S1"; + X_BUF \vga/vgacore/vcnt<1>/YUSED ( + .I(\vga/vgacore/Result<2>1 ), + .O(\vga/vgacore/Result<2>1_0 ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<2> .LOC = "CLB_R18C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<2> ( + .IA(\vga/vgacore/vcnt<1>/LOGIC_ZERO_149 ), + .IB(\vga/vgacore/Mcount_vcnt_cy[1] ), + .SEL(\vga/vgacore/vcnt_Eqn_2 ), + .O(\vga/vgacore/vcnt<1>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<2> .LOC = "CLB_R18C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<2> ( + .I0(\vga/vgacore/Mcount_vcnt_cy[1] ), + .I1(\vga/vgacore/vcnt_Eqn_2 ), + .O(\vga/vgacore/Result<2>1 ) + ); + defparam \vga/vgacore/vcnt<1>/SRMUX .LOC = "CLB_R18C9.S1"; + X_INV \vga/vgacore/vcnt<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/vcnt<1>/CYINIT .LOC = "CLB_R18C9.S1"; + X_BUF \vga/vgacore/vcnt<1>/CYINIT ( + .I(\vga/vgacore/vcnt<0>/CYMUXG ), + .O(\vga/vgacore/vcnt<1>/CYINIT_150 ) + ); + defparam \vga/vgacore/vcnt<3>/LOGIC_ZERO .LOC = "CLB_R17C9.S1"; + X_ZERO \vga/vgacore/vcnt<3>/LOGIC_ZERO ( + .O(\vga/vgacore/vcnt<3>/LOGIC_ZERO_152 ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<3> .LOC = "CLB_R17C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<3> ( + .IA(\vga/vgacore/vcnt<3>/LOGIC_ZERO_152 ), + .IB(\vga/vgacore/vcnt<3>/CYINIT_153 ), + .SEL(\vga/vgacore/vcnt_Eqn_3_151 ), + .O(\vga/vgacore/Mcount_vcnt_cy[3] ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<3> .LOC = "CLB_R17C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<3> ( + .I0(\vga/vgacore/vcnt<3>/CYINIT_153 ), + .I1(\vga/vgacore/vcnt_Eqn_3_151 ), + .O(\vga/vgacore/Result<3>1 ) + ); + defparam \vga/vgacore/vcnt_Eqn_3 .INIT = 16'h2A0A; + defparam \vga/vgacore/vcnt_Eqn_3 .LOC = "CLB_R17C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_3 ( + .ADR0(\vga/vgacore/vcnt [3]), + .ADR1(N786_0), + .ADR2(\vga/vgacore/vcnt [9]), + .ADR3(\vga/vgacore/N51_0 ), + .O(\vga/vgacore/vcnt_Eqn_3_151 ) + ); + defparam \vga/vgacore/vcnt_Eqn_41 .INIT = 16'h3030; + defparam \vga/vgacore/vcnt_Eqn_41 .LOC = "CLB_R17C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_41 ( + .ADR0(VCC), + .ADR1(\vga/vgacore/vcnt [9]), + .ADR2(\vga/vgacore/vcnt [4]), + .ADR3(VCC), + .O(\vga/vgacore/vcnt_Eqn_4 ) + ); + defparam \vga/vgacore/vcnt<3>/CKINV .LOC = "CLB_R17C9.S1"; + X_INV \vga/vgacore/vcnt<3>/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt<3>/CKMUXNOT ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<4> .LOC = "CLB_R17C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<4> ( + .IA(\vga/vgacore/vcnt<3>/LOGIC_ZERO_152 ), + .IB(\vga/vgacore/Mcount_vcnt_cy[3] ), + .SEL(\vga/vgacore/vcnt_Eqn_4 ), + .O(\vga/vgacore/vcnt<3>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<4> .LOC = "CLB_R17C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<4> ( + .I0(\vga/vgacore/Mcount_vcnt_cy[3] ), + .I1(\vga/vgacore/vcnt_Eqn_4 ), + .O(\vga/vgacore/Result<4>1 ) + ); + defparam \vga/vgacore/vcnt<3>/SRMUX .LOC = "CLB_R17C9.S1"; + X_INV \vga/vgacore/vcnt<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/vcnt<3>/CYINIT .LOC = "CLB_R17C9.S1"; + X_BUF \vga/vgacore/vcnt<3>/CYINIT ( + .I(\vga/vgacore/vcnt<1>/CYMUXG ), + .O(\vga/vgacore/vcnt<3>/CYINIT_153 ) + ); + defparam \vga/vgacore/vcnt<5>/LOGIC_ZERO .LOC = "CLB_R16C9.S1"; + X_ZERO \vga/vgacore/vcnt<5>/LOGIC_ZERO ( + .O(\vga/vgacore/vcnt<5>/LOGIC_ZERO_154 ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<5> .LOC = "CLB_R16C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<5> ( + .IA(\vga/vgacore/vcnt<5>/LOGIC_ZERO_154 ), + .IB(\vga/vgacore/vcnt<5>/CYINIT_155 ), + .SEL(\vga/vgacore/vcnt_Eqn_5 ), + .O(\vga/vgacore/Mcount_vcnt_cy[5] ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<5> .LOC = "CLB_R16C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<5> ( + .I0(\vga/vgacore/vcnt<5>/CYINIT_155 ), + .I1(\vga/vgacore/vcnt_Eqn_5 ), + .O(\vga/vgacore/Result<5>1 ) + ); + defparam \vga/vgacore/vcnt_Eqn_51 .INIT = 16'h5500; + defparam \vga/vgacore/vcnt_Eqn_51 .LOC = "CLB_R16C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_51 ( + .ADR0(\vga/vgacore/vcnt [9]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt [5]), + .O(\vga/vgacore/vcnt_Eqn_5 ) + ); + defparam \vga/vgacore/vcnt_Eqn_61 .INIT = 16'h0A0A; + defparam \vga/vgacore/vcnt_Eqn_61 .LOC = "CLB_R16C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_61 ( + .ADR0(\vga/vgacore/vcnt [6]), + .ADR1(VCC), + .ADR2(\vga/vgacore/vcnt [9]), + .ADR3(VCC), + .O(\vga/vgacore/vcnt_Eqn_6 ) + ); + defparam \vga/vgacore/vcnt<5>/CKINV .LOC = "CLB_R16C9.S1"; + X_INV \vga/vgacore/vcnt<5>/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt<5>/CKMUXNOT ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<6> .LOC = "CLB_R16C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<6> ( + .IA(\vga/vgacore/vcnt<5>/LOGIC_ZERO_154 ), + .IB(\vga/vgacore/Mcount_vcnt_cy[5] ), + .SEL(\vga/vgacore/vcnt_Eqn_6 ), + .O(\vga/vgacore/vcnt<5>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<6> .LOC = "CLB_R16C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<6> ( + .I0(\vga/vgacore/Mcount_vcnt_cy[5] ), + .I1(\vga/vgacore/vcnt_Eqn_6 ), + .O(\vga/vgacore/Result<6>1 ) + ); + defparam \vga/vgacore/vcnt<5>/SRMUX .LOC = "CLB_R16C9.S1"; + X_INV \vga/vgacore/vcnt<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/vcnt<5>/CYINIT .LOC = "CLB_R16C9.S1"; + X_BUF \vga/vgacore/vcnt<5>/CYINIT ( + .I(\vga/vgacore/vcnt<3>/CYMUXG ), + .O(\vga/vgacore/vcnt<5>/CYINIT_155 ) + ); + defparam \vga/vgacore/vcnt<7>/LOGIC_ZERO .LOC = "CLB_R15C9.S1"; + X_ZERO \vga/vgacore/vcnt<7>/LOGIC_ZERO ( + .O(\vga/vgacore/vcnt<7>/LOGIC_ZERO_156 ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<7> .LOC = "CLB_R15C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<7> ( + .IA(\vga/vgacore/vcnt<7>/LOGIC_ZERO_156 ), + .IB(\vga/vgacore/vcnt<7>/CYINIT_157 ), + .SEL(\vga/vgacore/vcnt_Eqn_7 ), + .O(\vga/vgacore/Mcount_vcnt_cy[7] ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<7> .LOC = "CLB_R15C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<7> ( + .I0(\vga/vgacore/vcnt<7>/CYINIT_157 ), + .I1(\vga/vgacore/vcnt_Eqn_7 ), + .O(\vga/vgacore/Result<7>1 ) + ); + defparam \vga/vgacore/vcnt_Eqn_71 .INIT = 16'h5500; + defparam \vga/vgacore/vcnt_Eqn_71 .LOC = "CLB_R15C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_71 ( + .ADR0(\vga/vgacore/vcnt [9]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt [7]), + .O(\vga/vgacore/vcnt_Eqn_7 ) + ); + defparam \vga/vgacore/vcnt_Eqn_81 .INIT = 16'h0F00; + defparam \vga/vgacore/vcnt_Eqn_81 .LOC = "CLB_R15C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_81 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/vgacore/vcnt [9]), + .ADR3(\vga/vgacore/vcnt [8]), + .O(\vga/vgacore/vcnt_Eqn_8 ) + ); + defparam \vga/vgacore/vcnt<7>/CKINV .LOC = "CLB_R15C9.S1"; + X_INV \vga/vgacore/vcnt<7>/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt<7>/CKMUXNOT ) + ); + defparam \vga/vgacore/Mcount_vcnt_cy<8> .LOC = "CLB_R15C9.S1"; + X_MUX2 \vga/vgacore/Mcount_vcnt_cy<8> ( + .IA(\vga/vgacore/vcnt<7>/LOGIC_ZERO_156 ), + .IB(\vga/vgacore/Mcount_vcnt_cy[7] ), + .SEL(\vga/vgacore/vcnt_Eqn_8 ), + .O(\vga/vgacore/vcnt<7>/CYMUXG ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<8> .LOC = "CLB_R15C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<8> ( + .I0(\vga/vgacore/Mcount_vcnt_cy[7] ), + .I1(\vga/vgacore/vcnt_Eqn_8 ), + .O(\vga/vgacore/Result<8>1 ) + ); + defparam \vga/vgacore/vcnt<7>/SRMUX .LOC = "CLB_R15C9.S1"; + X_INV \vga/vgacore/vcnt<7>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt<7>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/vgacore/vcnt<7>/CYINIT .LOC = "CLB_R15C9.S1"; + X_BUF \vga/vgacore/vcnt<7>/CYINIT ( + .I(\vga/vgacore/vcnt<5>/CYMUXG ), + .O(\vga/vgacore/vcnt<7>/CYINIT_157 ) + ); + defparam \vga/vgacore/Mcount_vcnt_xor<9> .LOC = "CLB_R14C9.S1"; + X_XOR2 \vga/vgacore/Mcount_vcnt_xor<9> ( + .I0(\vga/vgacore/vcnt<9>/CYINIT_158 ), + .I1(\vga/vgacore/vcnt_Eqn_9 ), + .O(\vga/vgacore/Result<9>1 ) + ); + defparam \vga/vgacore/vcnt_Eqn_92 .INIT = 16'h8800; + defparam \vga/vgacore/vcnt_Eqn_92 .LOC = "CLB_R14C9.S1"; + X_LUT4 \vga/vgacore/vcnt_Eqn_92 ( + .ADR0(\vga/vgacore/vcnt [9]), + .ADR1(\vga/vgacore/N0 ), + .ADR2(VCC), + .ADR3(\vga/vgacore/N51_0 ), + .O(\vga/vgacore/vcnt_Eqn_9 ) + ); + defparam \vga/vgacore/vcnt<9>/CKINV .LOC = "CLB_R14C9.S1"; + X_INV \vga/vgacore/vcnt<9>/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt<9>/CKMUXNOT ) + ); + defparam \vga/vgacore/vcnt<9>/CYINIT .LOC = "CLB_R14C9.S1"; + X_BUF \vga/vgacore/vcnt<9>/CYINIT ( + .I(\vga/vgacore/vcnt<7>/CYMUXG ), + .O(\vga/vgacore/vcnt<9>/CYINIT_158 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1437 .INIT = 16'h0F1B; + defparam \vga/scancode_convert/scancode_rom/data<0>1437 .LOC = "CLB_R16C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1437 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<0>1437/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1492 .INIT = 16'hF3B3; + defparam \vga/scancode_convert/scancode_rom/data<0>1492 .LOC = "CLB_R16C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1492 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/scancode_rom/data<0>1_map1526_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<0>1437/O ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1529 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1437/O/XUSED .LOC = "CLB_R16C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1437/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1437/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1437/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1437/O/YUSED .LOC = "CLB_R16C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1437/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1529 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1529_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1110 .INIT = 16'h3332; + defparam \vga/scancode_convert/scancode_rom/data<0>1110 .LOC = "CLB_R13C33.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1110 ( + .ADR0(\vga/scancode_convert/shift_24 ), + .ADR1(\vga/scancode_convert/sc_1_1_23 ), + .ADR2(\vga/scancode_convert/capslock_25 ), + .ADR3(\vga/scancode_convert/ctrl_22 ), + .O(\vga/scancode_convert/scancode_rom/N9_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1469 .INIT = 16'h3337; + defparam \vga/scancode_convert/scancode_rom/data<0>1469 .LOC = "CLB_R13C33.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1469 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/scancode_rom/N9 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1526 ) + ); + defparam \vga/scancode_convert/scancode_rom/N9/XUSED .LOC = "CLB_R13C33.S1"; + X_BUF \vga/scancode_convert/scancode_rom/N9/XUSED ( + .I(\vga/scancode_convert/scancode_rom/N9_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/N9 ) + ); + defparam \vga/scancode_convert/scancode_rom/N9/YUSED .LOC = "CLB_R13C33.S1"; + X_BUF \vga/scancode_convert/scancode_rom/N9/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1526 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1526_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1539 .INIT = 16'hEA00; + defparam \vga/scancode_convert/scancode_rom/data<0>1539 .LOC = "CLB_R16C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1539 ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/scancode_rom/data<0>1_map1529_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<0>1_map1503_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<0>1_map1534_0 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1539/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1569 .INIT = 16'hF404; + defparam \vga/scancode_convert/scancode_rom/data<0>1569 .LOC = "CLB_R16C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1569 ( + .ADR0(N3104_0), + .ADR1(\vga/scancode_convert/scancode_rom/data<0>1_map1445_0 ), + .ADR2(\vga/scancode_convert/sc [6]), + .ADR3(\vga/scancode_convert/scancode_rom/data<0>1539/O ), + .O(\vga/scancode_convert/rom_data [0]) + ); + defparam \vga/scancode_convert/ascii<0>/XUSED .LOC = "CLB_R16C34.S0"; + X_BUF \vga/scancode_convert/ascii<0>/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1539/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1539/O ) + ); + defparam \vga/scancode_convert/ascii_0 .LOC = "CLB_R16C34.S0"; + defparam \vga/scancode_convert/ascii_0 .INIT = 1'b0; + X_FF \vga/scancode_convert/ascii_0 ( + .I(\vga/scancode_convert/rom_data [0]), + .CE(\vga/scancode_convert/_or0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/ascii [0]) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1181 .INIT = 16'h15FF; + defparam \vga/scancode_convert/scancode_rom/data<6>1181 .LOC = "CLB_R11C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1181 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1831_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW1 .INIT = 16'hF575; + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW1 .LOC = "CLB_R11C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1201_SW1 ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/scancode_rom/data<6>1_map1808_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<6>1_map1831 ), + .O(N3085) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1_map1831/XUSED .LOC = "CLB_R11C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<6>1_map1831/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1_map1831_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1831 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1_map1831/YUSED .LOC = "CLB_R11C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<6>1_map1831/YUSED ( + .I(N3085), + .O(N3085_0) + ); + defparam \vga/scancode_convert/_cmp_eq00041_SW0 .INIT = 16'hFAFF; + defparam \vga/scancode_convert/_cmp_eq00041_SW0 .LOC = "CLB_R11C28.S0"; + X_LUT4 \vga/scancode_convert/_cmp_eq00041_SW0 ( + .ADR0(\vga/ps2/sc_r [3]), + .ADR1(VCC), + .ADR2(\vga/ps2/sc_r [0]), + .ADR3(\vga/ps2/sc_r [4]), + .O(\vga/scancode_convert/_cmp_eq00041_SW0/O_pack_1 ) + ); + defparam \vga/scancode_convert/_cmp_eq00041 .INIT = 16'h0001; + defparam \vga/scancode_convert/_cmp_eq00041 .LOC = "CLB_R11C28.S0"; + X_LUT4 \vga/scancode_convert/_cmp_eq00041 ( + .ADR0(\vga/ps2/sc_r [6]), + .ADR1(\vga/ps2/sc_r [5]), + .ADR2(\vga/ps2/sc_r [7]), + .ADR3(\vga/scancode_convert/_cmp_eq00041_SW0/O ), + .O(\vga/scancode_convert/N10 ) + ); + defparam \vga/scancode_convert/_cmp_eq00041_SW0/O/XUSED .LOC = "CLB_R11C28.S0"; + X_BUF \vga/scancode_convert/_cmp_eq00041_SW0/O/XUSED ( + .I(\vga/scancode_convert/_cmp_eq00041_SW0/O_pack_1 ), + .O(\vga/scancode_convert/_cmp_eq00041_SW0/O ) + ); + defparam \vga/scancode_convert/_cmp_eq00041_SW0/O/YUSED .LOC = "CLB_R11C28.S0"; + X_BUF \vga/scancode_convert/_cmp_eq00041_SW0/O/YUSED ( + .I(\vga/scancode_convert/N10 ), + .O(\vga/scancode_convert/N10_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2465 .INIT = 16'hA888; + defparam \vga/scancode_convert/scancode_rom/data<1>2465 .LOC = "CLB_R15C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2465 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<0>1_map1534_0 ), + .ADR1(\vga/scancode_convert/sc [5]), + .ADR2(\vga/scancode_convert/scancode_rom/data<1>2_map1751_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<1>2_map1774_0 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2465/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2497 .INIT = 16'hAE04; + defparam \vga/scancode_convert/scancode_rom/data<1>2497 .LOC = "CLB_R15C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2497 ( + .ADR0(\vga/scancode_convert/sc [6]), + .ADR1(\vga/scancode_convert/scancode_rom/data<1>2_map1690_0 ), + .ADR2(N3106_0), + .ADR3(\vga/scancode_convert/scancode_rom/data<1>2465/O ), + .O(\vga/scancode_convert/rom_data [1]) + ); + defparam \vga/scancode_convert/ascii<1>/XUSED .LOC = "CLB_R15C36.S1"; + X_BUF \vga/scancode_convert/ascii<1>/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2465/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2465/O ) + ); + defparam \vga/scancode_convert/ascii_1 .LOC = "CLB_R15C36.S1"; + defparam \vga/scancode_convert/ascii_1 .INIT = 1'b0; + X_FF \vga/scancode_convert/ascii_1 ( + .I(\vga/scancode_convert/rom_data [1]), + .CE(\vga/scancode_convert/_or0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/ascii [1]) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1264 .INIT = 16'h0109; + defparam \vga/scancode_convert/scancode_rom/data<2>1264 .LOC = "CLB_R15C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1264 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<2>1264/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1329 .INIT = 16'hF3B3; + defparam \vga/scancode_convert/scancode_rom/data<2>1329 .LOC = "CLB_R15C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1329 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/scancode_rom/data<2>1_map1121_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<2>1264/O ), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1124 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1264/O/XUSED .LOC = "CLB_R15C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<2>1264/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<2>1264/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1264/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1264/O/YUSED .LOC = "CLB_R15C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<2>1264/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<2>1_map1124 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1124_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1410 .INIT = 16'h3323; + defparam \vga/scancode_convert/scancode_rom/data<2>1410 .LOC = "CLB_R15C37.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1410 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [5]), + .ADR2(N3126_0), + .ADR3(\vga/scancode_convert/scancode_rom/data<2>1_map1129_0 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1410/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1458 .INIT = 16'hE222; + defparam \vga/scancode_convert/scancode_rom/data<2>1458 .LOC = "CLB_R15C37.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1458 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<2>1_map1098_0 ), + .ADR1(\vga/scancode_convert/sc [6]), + .ADR2(\vga/scancode_convert/scancode_rom/data<2>1_map1124_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<2>1410/O ), + .O(\vga/scancode_convert/rom_data [2]) + ); + defparam \vga/scancode_convert/ascii<2>/XUSED .LOC = "CLB_R15C37.S1"; + X_BUF \vga/scancode_convert/ascii<2>/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<2>1410/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1410/O ) + ); + defparam \vga/scancode_convert/ascii_2 .LOC = "CLB_R15C37.S1"; + defparam \vga/scancode_convert/ascii_2 .INIT = 1'b0; + X_FF \vga/scancode_convert/ascii_2 ( + .I(\vga/scancode_convert/rom_data [2]), + .CE(\vga/scancode_convert/_or0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/ascii [2]) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>199 .INIT = 16'h4A00; + defparam \vga/scancode_convert/scancode_rom/data<3>199 .LOC = "CLB_R18C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>199 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/raise ), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<3>199/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1125 .INIT = 16'h7F73; + defparam \vga/scancode_convert/scancode_rom/data<3>1125 .LOC = "CLB_R18C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>1125 ( + .ADR0(\vga/scancode_convert/scancode_rom/N7 ), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/scancode_rom/data<3>199/O ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1185 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>199/O/XUSED .LOC = "CLB_R18C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>199/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>199/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<3>199/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>199/O/YUSED .LOC = "CLB_R18C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>199/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>1_map1185 ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1185_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW1 .INIT = 16'hEF95; + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW1 .LOC = "CLB_R12C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1308_SW1 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<4>1308_SW1/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308 .INIT = 16'h57F7; + defparam \vga/scancode_convert/scancode_rom/data<4>1308 .LOC = "CLB_R12C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1308 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(N3174_0), + .ADR2(\vga/scancode_convert/raise ), + .ADR3(\vga/scancode_convert/scancode_rom/data<4>1308_SW1/O ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1609 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW1/O/XUSED .LOC = "CLB_R12C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>1308_SW1/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1308_SW1/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1308_SW1/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW1/O/YUSED .LOC = "CLB_R12C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>1308_SW1/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1_map1609 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1609_0 ) + ); + defparam \vga/scancode_convert/_cmp_eq000211 .INIT = 16'h0008; + defparam \vga/scancode_convert/_cmp_eq000211 .LOC = "CLB_R10C29.S0"; + X_LUT4 \vga/scancode_convert/_cmp_eq000211 ( + .ADR0(\vga/ps2/sc_r [4]), + .ADR1(\vga/ps2/sc_r [6]), + .ADR2(\vga/ps2/sc_r [1]), + .ADR3(\vga/ps2/sc_r [2]), + .O(\vga/scancode_convert/N31_pack_1 ) + ); + defparam \vga/scancode_convert/_cmp_eq000221 .INIT = 16'h0200; + defparam \vga/scancode_convert/_cmp_eq000221 .LOC = "CLB_R10C29.S0"; + X_LUT4 \vga/scancode_convert/_cmp_eq000221 ( + .ADR0(\vga/ps2/sc_r [3]), + .ADR1(\vga/ps2/sc_r [5]), + .ADR2(\vga/ps2/sc_r [7]), + .ADR3(\vga/scancode_convert/N31 ), + .O(\vga/scancode_convert/N11 ) + ); + defparam \vga/scancode_convert/N31/XUSED .LOC = "CLB_R10C29.S0"; + X_BUF \vga/scancode_convert/N31/XUSED ( + .I(\vga/scancode_convert/N31_pack_1 ), + .O(\vga/scancode_convert/N31 ) + ); + defparam \vga/scancode_convert/N31/YUSED .LOC = "CLB_R10C29.S0"; + X_BUF \vga/scancode_convert/N31/YUSED ( + .I(\vga/scancode_convert/N11 ), + .O(\vga/scancode_convert/N11_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1392_SW0 .INIT = 16'hFFF7; + defparam \vga/scancode_convert/scancode_rom/data<4>1392_SW0 .LOC = "CLB_R10C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1392_SW0 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/scancode_rom/N9 ), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<4>1392_SW0/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1620 .INIT = 16'hFB0B; + defparam \vga/scancode_convert/scancode_rom/data<4>1620 .LOC = "CLB_R10C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1620 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<4>1_map1633_0 ), + .ADR1(\vga/scancode_convert/scancode_rom/data<4>1392_SW0/O ), + .ADR2(\vga/scancode_convert/sc [2]), + .ADR3(\vga/scancode_convert/scancode_rom/data<4>1_map1666_0 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1669 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1392_SW0/O/XUSED .LOC = "CLB_R10C36.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>1392_SW0/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1392_SW0/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1392_SW0/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1392_SW0/O/YUSED .LOC = "CLB_R10C36.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>1392_SW0/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1_map1669 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1669_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1247 .INIT = 16'hA808; + defparam \vga/scancode_convert/scancode_rom/data<6>1247 .LOC = "CLB_R11C37.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1247 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<6>1_map1803_0 ), + .ADR1(N3084_0), + .ADR2(\vga/scancode_convert/scancode_rom/data<6>1_map1820_0 ), + .ADR3(N3085_0), + .O(\vga/scancode_convert/scancode_rom/data<6>1247/O_pack_1 ) + ); + defparam \vga/scancode_convert/_mux0008<6>1 .INIT = 16'h5A78; + defparam \vga/scancode_convert/_mux0008<6>1 .LOC = "CLB_R11C37.S1"; + X_LUT4 \vga/scancode_convert/_mux0008<6>1 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<6>1_map1863_0 ), + .ADR1(\vga/scancode_convert/sc [6]), + .ADR2(\vga/scancode_convert/ctrl_22 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<6>1247/O ), + .O(\vga/scancode_convert/_mux0008 [6]) + ); + defparam \vga/scancode_convert/ascii<6>/XUSED .LOC = "CLB_R11C37.S1"; + X_BUF \vga/scancode_convert/ascii<6>/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1247/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1247/O ) + ); + defparam \vga/scancode_convert/ascii_6 .LOC = "CLB_R11C37.S1"; + defparam \vga/scancode_convert/ascii_6 .INIT = 1'b0; + X_FF \vga/scancode_convert/ascii_6 ( + .I(\vga/scancode_convert/_mux0008 [6]), + .CE(\vga/scancode_convert/_or0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/ascii [6]) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3247 .INIT = 16'h550C; + defparam \vga/scancode_convert/scancode_rom/data<5>3247 .LOC = "CLB_R11C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3247 ( + .ADR0(\vga/scancode_convert/raise ), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<5>3247/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3282 .INIT = 16'hFABA; + defparam \vga/scancode_convert/scancode_rom/data<5>3282 .LOC = "CLB_R11C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3282 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/scancode_rom/data<5>3_map1276_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<5>3247/O ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1295 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3247/O/XUSED .LOC = "CLB_R11C34.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3247/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3247/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3247/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3247/O/YUSED .LOC = "CLB_R11C34.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3247/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1295 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1295_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>152 .INIT = 16'hFFFB; + defparam \vga/scancode_convert/scancode_rom/data<0>152 .LOC = "CLB_R12C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>152 ( + .ADR0(\vga/scancode_convert/capslock_25 ), + .ADR1(\vga/scancode_convert/sc_1_1_23 ), + .ADR2(\vga/scancode_convert/shift_24 ), + .ADR3(\vga/scancode_convert/ctrl_22 ), + .O(\vga/scancode_convert/scancode_rom/N12_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1141 .INIT = 16'h2B21; + defparam \vga/scancode_convert/scancode_rom/data<6>1141 .LOC = "CLB_R12C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1141 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/scancode_rom/N12 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1820 ) + ); + defparam \vga/scancode_convert/scancode_rom/N12/XUSED .LOC = "CLB_R12C34.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N12/XUSED ( + .I(\vga/scancode_convert/scancode_rom/N12_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/N12 ) + ); + defparam \vga/scancode_convert/scancode_rom/N12/YUSED .LOC = "CLB_R12C34.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N12/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1_map1820 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1820_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3359 .INIT = 16'h134F; + defparam \vga/scancode_convert/scancode_rom/data<5>3359 .LOC = "CLB_R11C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3359 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/raise ), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<5>3359/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3483 .INIT = 16'hBBB3; + defparam \vga/scancode_convert/scancode_rom/data<5>3483 .LOC = "CLB_R11C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3483 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<5>3_map1337_0 ), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/scancode_rom/data<5>3359/O ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1340 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3359/O/XUSED .LOC = "CLB_R11C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3359/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3359/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3359/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3359/O/YUSED .LOC = "CLB_R11C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3359/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1340 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1340_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1333 .INIT = 16'h00AE; + defparam \vga/scancode_convert/scancode_rom/data<6>1333 .LOC = "CLB_R12C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1333 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(N3130_0), + .ADR3(\vga/scancode_convert/sc [5]), + .O(\vga/scancode_convert/scancode_rom/data<6>1333/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1360 .INIT = 16'hBB33; + defparam \vga/scancode_convert/scancode_rom/data<6>1360 .LOC = "CLB_R12C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1360 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<6>1_map1850_0 ), + .ADR1(\vga/scancode_convert/sc [6]), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/scancode_rom/data<6>1333/O ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1863 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1333/O/XUSED .LOC = "CLB_R12C37.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<6>1333/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1333/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1333/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1333/O/YUSED .LOC = "CLB_R12C37.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<6>1333/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1_map1863 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1863_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW0 .INIT = 16'h0077; + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW0 .LOC = "CLB_R13C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3852_SW0 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/scancode_rom/data<5>3_map1394_0 ), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/sc [2]), + .O(\vga/scancode_convert/scancode_rom/data<5>3852_SW0/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852 .INIT = 16'h0307; + defparam \vga/scancode_convert/scancode_rom/data<5>3852 .LOC = "CLB_R13C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3852 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/scancode_rom/data<5>3852_SW0/O ), + .ADR2(\vga/scancode_convert/sc [5]), + .ADR3(N3136_0), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1416 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW0/O/XUSED .LOC = "CLB_R13C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3852_SW0/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3852_SW0/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3852_SW0/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW0/O/YUSED .LOC = "CLB_R13C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3852_SW0/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1416 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1416_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3664 .INIT = 16'h4037; + defparam \vga/scancode_convert/scancode_rom/data<5>3664 .LOC = "CLB_R14C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3664 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/raise ), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<5>3664/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3696 .INIT = 16'hFB73; + defparam \vga/scancode_convert/scancode_rom/data<5>3696 .LOC = "CLB_R14C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3696 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/scancode_rom/data<5>3_map1363_0 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<5>3664/O ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1381 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3664/O/XUSED .LOC = "CLB_R14C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3664/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3664/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3664/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3664/O/YUSED .LOC = "CLB_R14C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3664/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1381 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1381_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3895_SW0 .INIT = 16'h7F2A; + defparam \vga/scancode_convert/scancode_rom/data<5>3895_SW0 .LOC = "CLB_R11C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3895_SW0 ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/scancode_rom/data<5>3_map1340_0 ), + .ADR2(\vga/scancode_convert/scancode_rom/data<5>3_map1295_0 ), + .ADR3(N3112_0), + .O(\vga/scancode_convert/scancode_rom/data<5>3895_SW0/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3895 .INIT = 16'h808F; + defparam \vga/scancode_convert/scancode_rom/data<5>3895 .LOC = "CLB_R11C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3895 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<5>3_map1416_0 ), + .ADR1(\vga/scancode_convert/scancode_rom/data<5>3_map1381_0 ), + .ADR2(\vga/scancode_convert/sc [6]), + .ADR3(\vga/scancode_convert/scancode_rom/data<5>3895_SW0/O ), + .O(\vga/scancode_convert/rom_data [5]) + ); + defparam \vga/scancode_convert/ascii<5>/XUSED .LOC = "CLB_R11C35.S1"; + X_BUF \vga/scancode_convert/ascii<5>/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3895_SW0/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3895_SW0/O ) + ); + defparam \vga/vgacore/vcnt_Eqn_911 .INIT = 16'h0F7F; + defparam \vga/vgacore/vcnt_Eqn_911 .LOC = "CLB_R19C9.S0"; + X_LUT4 \vga/vgacore/vcnt_Eqn_911 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [3]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/vgacore/N0_pack_1 ) + ); + defparam \vga/vgacore/vcnt_Eqn_bis_021 .INIT = 16'h3733; + defparam \vga/vgacore/vcnt_Eqn_bis_021 .LOC = "CLB_R19C9.S0"; + X_LUT4 \vga/vgacore/vcnt_Eqn_bis_021 ( + .ADR0(\vga/vgacore/vcnt [8]), + .ADR1(\vga/vgacore/vcnt [9]), + .ADR2(N3108_0), + .ADR3(\vga/vgacore/N0 ), + .O(\vga/vgacore/vcnt_Eqn_bis_0 ) + ); + defparam \vga/vgacore/N0/XUSED .LOC = "CLB_R19C9.S0"; + X_BUF \vga/vgacore/N0/XUSED ( + .I(\vga/vgacore/N0_pack_1 ), + .O(\vga/vgacore/N0 ) + ); + defparam \vga/vgacore/N0/YUSED .LOC = "CLB_R19C9.S0"; + X_BUF \vga/vgacore/N0/YUSED ( + .I(\vga/vgacore/vcnt_Eqn_bis_0 ), + .O(\vga/vgacore/vcnt_Eqn_bis_0_0 ) + ); + defparam \vga/scancode_convert/state_FFd2-In_SW0 .INIT = 16'hF4F8; + defparam \vga/scancode_convert/state_FFd2-In_SW0 .LOC = "CLB_R12C29.S0"; + X_LUT4 \vga/scancode_convert/state_FFd2-In_SW0 ( + .ADR0(\vga/ps2/sc_r [1]), + .ADR1(\vga/scancode_convert/N10_0 ), + .ADR2(\vga/scancode_convert/release_prefix_26 ), + .ADR3(\vga/ps2/sc_r [2]), + .O(\vga/scancode_convert/state_FFd2-In_SW0/O_pack_1 ) + ); + defparam \vga/scancode_convert/state_FFd2-In .INIT = 16'h0010; + defparam \vga/scancode_convert/state_FFd2-In .LOC = "CLB_R12C29.S0"; + X_LUT4 \vga/scancode_convert/state_FFd2-In ( + .ADR0(\vga/scancode_convert/_cmp_eq0000_27 ), + .ADR1(\vga/scancode_convert/N11_0 ), + .ADR2(\vga/scancode_convert/_and0000_0 ), + .ADR3(\vga/scancode_convert/state_FFd2-In_SW0/O ), + .O(\vga/scancode_convert/state_FFd2-In_159 ) + ); + defparam \vga/scancode_convert/state_FFd2/XUSED .LOC = "CLB_R12C29.S0"; + X_BUF \vga/scancode_convert/state_FFd2/XUSED ( + .I(\vga/scancode_convert/state_FFd2-In_SW0/O_pack_1 ), + .O(\vga/scancode_convert/state_FFd2-In_SW0/O ) + ); + defparam \vga/scancode_convert/state_FFd2 .LOC = "CLB_R12C29.S0"; + defparam \vga/scancode_convert/state_FFd2 .INIT = 1'b0; + X_FF \vga/scancode_convert/state_FFd2 ( + .I(\vga/scancode_convert/state_FFd2-In_159 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/state_FFd2/FFY/RST ), + .O(\vga/scancode_convert/state_FFd2_28 ) + ); + defparam \vga/scancode_convert/state_FFd2/FFY/RSTOR .LOC = "CLB_R12C29.S0"; + X_INV \vga/scancode_convert/state_FFd2/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/state_FFd2/FFY/RST ) + ); + defparam \vga/scancode_convert/state_FFd3-In_SW0 .INIT = 16'h8C4C; + defparam \vga/scancode_convert/state_FFd3-In_SW0 .LOC = "CLB_R13C29.S1"; + X_LUT4 \vga/scancode_convert/state_FFd3-In_SW0 ( + .ADR0(\vga/ps2/sc_r [2]), + .ADR1(\vga/scancode_convert/release_prefix_26 ), + .ADR2(\vga/scancode_convert/N10_0 ), + .ADR3(\vga/ps2/sc_r [1]), + .O(\vga/scancode_convert/state_FFd3-In_SW0/O_pack_1 ) + ); + defparam \vga/scancode_convert/state_FFd3-In .INIT = 16'h0200; + defparam \vga/scancode_convert/state_FFd3-In .LOC = "CLB_R13C29.S1"; + X_LUT4 \vga/scancode_convert/state_FFd3-In ( + .ADR0(\vga/scancode_convert/_and0000_0 ), + .ADR1(\vga/scancode_convert/N11_0 ), + .ADR2(\vga/scancode_convert/_cmp_eq0000_27 ), + .ADR3(\vga/scancode_convert/state_FFd3-In_SW0/O ), + .O(\vga/scancode_convert/state_FFd3-In_160 ) + ); + defparam \vga/scancode_convert/state_FFd3/XUSED .LOC = "CLB_R13C29.S1"; + X_BUF \vga/scancode_convert/state_FFd3/XUSED ( + .I(\vga/scancode_convert/state_FFd3-In_SW0/O_pack_1 ), + .O(\vga/scancode_convert/state_FFd3-In_SW0/O ) + ); + defparam \vga/scancode_convert/state_FFd3 .LOC = "CLB_R13C29.S1"; + defparam \vga/scancode_convert/state_FFd3 .INIT = 1'b0; + X_FF \vga/scancode_convert/state_FFd3 ( + .I(\vga/scancode_convert/state_FFd3-In_160 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/state_FFd3/FFY/RST ), + .O(\vga/scancode_convert/state_FFd3_29 ) + ); + defparam \vga/scancode_convert/state_FFd3/FFY/RSTOR .LOC = "CLB_R13C29.S1"; + X_INV \vga/scancode_convert/state_FFd3/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/state_FFd3/FFY/RST ) + ); + defparam \vga/crt/_and0000_SW0 .INIT = 16'h033F; + defparam \vga/crt/_and0000_SW0 .LOC = "CLB_R17C14.S1"; + X_LUT4 \vga/crt/_and0000_SW0 ( + .ADR0(VCC), + .ADR1(\vga/crt/state_FFd2_12 ), + .ADR2(\vga/crt/state_FFd1_13 ), + .ADR3(\vga/crt/eol_0 ), + .O(\vga/crt/_and0000_SW0/O_pack_1 ) + ); + defparam \vga/crt/_and0000 .INIT = 16'h083B; + defparam \vga/crt/_and0000 .LOC = "CLB_R17C14.S1"; + X_LUT4 \vga/crt/_and0000 ( + .ADR0(\vga/crt_data [2]), + .ADR1(\vga/crt/state_FFd3_11 ), + .ADR2(N306_0), + .ADR3(\vga/crt/_and0000_SW0/O ), + .O(\vga/crt/_and0000_161 ) + ); + defparam \vga/crt/_and0000_SW0/O/XUSED .LOC = "CLB_R17C14.S1"; + X_BUF \vga/crt/_and0000_SW0/O/XUSED ( + .I(\vga/crt/_and0000_SW0/O_pack_1 ), + .O(\vga/crt/_and0000_SW0/O ) + ); + defparam \vga/crt/_and0000_SW0/O/YUSED .LOC = "CLB_R17C14.S1"; + X_BUF \vga/crt/_and0000_SW0/O/YUSED ( + .I(\vga/crt/_and0000_161 ), + .O(\vga/crt/_and0000_0 ) + ); + defparam \vga/crt/eol_SW0 .INIT = 16'hDFFF; + defparam \vga/crt/eol_SW0 .LOC = "CLB_R17C13.S1"; + X_LUT4 \vga/crt/eol_SW0 ( + .ADR0(\vga/crt/cursor_h [3]), + .ADR1(\vga/crt/cursor_h [4]), + .ADR2(\vga/crt/cursor_h [2]), + .ADR3(\vga/crt/cursor_h [1]), + .O(\vga/crt/eol_SW0/O_pack_1 ) + ); + defparam \vga/crt/eol .INIT = 16'h0020; + defparam \vga/crt/eol .LOC = "CLB_R17C13.S1"; + X_LUT4 \vga/crt/eol ( + .ADR0(\vga/crt/cursor_h [6]), + .ADR1(\vga/crt/cursor_h [5]), + .ADR2(\vga/crt/cursor_h [0]), + .ADR3(\vga/crt/eol_SW0/O ), + .O(\vga/crt/eol_162 ) + ); + defparam \vga/crt/eol_SW0/O/XUSED .LOC = "CLB_R17C13.S1"; + X_BUF \vga/crt/eol_SW0/O/XUSED ( + .I(\vga/crt/eol_SW0/O_pack_1 ), + .O(\vga/crt/eol_SW0/O ) + ); + defparam \vga/crt/eol_SW0/O/YUSED .LOC = "CLB_R17C13.S1"; + X_BUF \vga/crt/eol_SW0/O/YUSED ( + .I(\vga/crt/eol_162 ), + .O(\vga/crt/eol_0 ) + ); + defparam \vga/scancode_convert/_cmp_eq0000 .INIT = 16'h0010; + defparam \vga/scancode_convert/_cmp_eq0000 .LOC = "CLB_R12C29.S1"; + X_LUT4 \vga/scancode_convert/_cmp_eq0000 ( + .ADR0(\vga/ps2/sc_r [3]), + .ADR1(\vga/ps2/sc_r [0]), + .ADR2(\vga/scancode_convert/N31 ), + .ADR3(N3100_0), + .O(\vga/scancode_convert/_cmp_eq0000_pack_1 ) + ); + defparam \vga/scancode_convert/_not00101 .INIT = 16'hF8F0; + defparam \vga/scancode_convert/_not00101 .LOC = "CLB_R12C29.S1"; + X_LUT4 \vga/scancode_convert/_not00101 ( + .ADR0(\vga/scancode_convert/state_FFd5_31 ), + .ADR1(\vga/ps2/rdy_r_1 ), + .ADR2(\vga/scancode_convert/state_FFd4_30 ), + .ADR3(\vga/scancode_convert/_cmp_eq0000_27 ), + .O(\vga/scancode_convert/_not0010 ) + ); + defparam \vga/scancode_convert/_cmp_eq0000/XUSED .LOC = "CLB_R12C29.S1"; + X_BUF \vga/scancode_convert/_cmp_eq0000/XUSED ( + .I(\vga/scancode_convert/_cmp_eq0000_pack_1 ), + .O(\vga/scancode_convert/_cmp_eq0000_27 ) + ); + defparam \vga/scancode_convert/_cmp_eq0000/YUSED .LOC = "CLB_R12C29.S1"; + X_BUF \vga/scancode_convert/_cmp_eq0000/YUSED ( + .I(\vga/scancode_convert/_not0010 ), + .O(\vga/scancode_convert/_not0010_0 ) + ); + defparam \vga/crt/scroll_SW0 .INIT = 16'hF3FF; + defparam \vga/crt/scroll_SW0 .LOC = "CLB_R15C13.S0"; + X_LUT4 \vga/crt/scroll_SW0 ( + .ADR0(VCC), + .ADR1(\vga/crt/cursor_v [3]), + .ADR2(\vga/crt/cursor_v [2]), + .ADR3(\vga/crt/cursor_v [1]), + .O(\vga/crt/scroll_SW0/O_pack_1 ) + ); + defparam \vga/crt/scroll .INIT = 16'h0080; + defparam \vga/crt/scroll .LOC = "CLB_R15C13.S0"; + X_LUT4 \vga/crt/scroll ( + .ADR0(\vga/crt/cursor_v [4]), + .ADR1(\vga/crt/cursor_v [0]), + .ADR2(\vga/crt/cursor_v [5]), + .ADR3(\vga/crt/scroll_SW0/O ), + .O(\vga/crt/scroll_163 ) + ); + defparam \vga/crt/scroll_SW0/O/XUSED .LOC = "CLB_R15C13.S0"; + X_BUF \vga/crt/scroll_SW0/O/XUSED ( + .I(\vga/crt/scroll_SW0/O_pack_1 ), + .O(\vga/crt/scroll_SW0/O ) + ); + defparam \vga/crt/scroll_SW0/O/YUSED .LOC = "CLB_R15C13.S0"; + X_BUF \vga/crt/scroll_SW0/O/YUSED ( + .I(\vga/crt/scroll_163 ), + .O(\vga/crt/scroll_0 ) + ); + defparam \vga/scancode_convert/state_FFd4-In24 .INIT = 16'hBAEA; + defparam \vga/scancode_convert/state_FFd4-In24 .LOC = "CLB_R13C29.S0"; + X_LUT4 \vga/scancode_convert/state_FFd4-In24 ( + .ADR0(\vga/scancode_convert/N11_0 ), + .ADR1(\vga/ps2/sc_r [1]), + .ADR2(\vga/scancode_convert/N10_0 ), + .ADR3(\vga/ps2/sc_r [2]), + .O(\vga/scancode_convert/state_FFd4-In24/O_pack_1 ) + ); + defparam \vga/scancode_convert/state_FFd4-In34 .INIT = 16'hFEFA; + defparam \vga/scancode_convert/state_FFd4-In34 .LOC = "CLB_R13C29.S0"; + X_LUT4 \vga/scancode_convert/state_FFd4-In34 ( + .ADR0(\vga/scancode_convert/state_FFd3_29 ), + .ADR1(\vga/scancode_convert/_and0000_0 ), + .ADR2(\vga/scancode_convert/state_FFd2_28 ), + .ADR3(\vga/scancode_convert/state_FFd4-In24/O ), + .O(\vga/scancode_convert/state_FFd4-In ) + ); + defparam \vga/scancode_convert/state_FFd4/XUSED .LOC = "CLB_R13C29.S0"; + X_BUF \vga/scancode_convert/state_FFd4/XUSED ( + .I(\vga/scancode_convert/state_FFd4-In24/O_pack_1 ), + .O(\vga/scancode_convert/state_FFd4-In24/O ) + ); + defparam \vga/scancode_convert/state_FFd4 .LOC = "CLB_R13C29.S0"; + defparam \vga/scancode_convert/state_FFd4 .INIT = 1'b0; + X_FF \vga/scancode_convert/state_FFd4 ( + .I(\vga/scancode_convert/state_FFd4-In ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/state_FFd4/FFY/RST ), + .O(\vga/scancode_convert/state_FFd4_30 ) + ); + defparam \vga/scancode_convert/state_FFd4/FFY/RSTOR .LOC = "CLB_R13C29.S0"; + X_INV \vga/scancode_convert/state_FFd4/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/state_FFd4/FFY/RST ) + ); + defparam \vga/crt/_and0001 .INIT = 16'h1000; + defparam \vga/crt/_and0001 .LOC = "CLB_R15C14.S1"; + X_LUT4 \vga/crt/_and0001 ( + .ADR0(\vga/crt/state_FFd3_11 ), + .ADR1(N235_0), + .ADR2(\vga/crt/scroll_0 ), + .ADR3(\vga/crt/eol_0 ), + .O(\vga/crt/_and0001_pack_1 ) + ); + defparam \vga/crt/cursor_v_Eqn_11 .INIT = 16'h00F0; + defparam \vga/crt/cursor_v_Eqn_11 .LOC = "CLB_R15C14.S1"; + X_LUT4 \vga/crt/cursor_v_Eqn_11 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/Result<1>_0 ), + .ADR3(\vga/crt/_and0001_32 ), + .O(\vga/crt/cursor_v_Eqn_1 ) + ); + defparam \vga/crt/cursor_v<1>/XUSED .LOC = "CLB_R15C14.S1"; + X_BUF \vga/crt/cursor_v<1>/XUSED ( + .I(\vga/crt/_and0001_pack_1 ), + .O(\vga/crt/_and0001_32 ) + ); + defparam \vga/crt/cursor_v_1 .LOC = "CLB_R15C14.S1"; + defparam \vga/crt/cursor_v_1 .INIT = 1'b0; + X_FF \vga/crt/cursor_v_1 ( + .I(\vga/crt/cursor_v_Eqn_1 ), + .CE(\vga/crt/_not0007_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_v<1>/FFY/RST ), + .O(\vga/crt/cursor_v [1]) + ); + defparam \vga/crt/cursor_v<1>/FFY/RSTOR .LOC = "CLB_R15C14.S1"; + X_INV \vga/crt/cursor_v<1>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_v<1>/FFY/RST ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>218 .INIT = 16'h5030; + defparam \vga/scancode_convert/scancode_rom/data<1>218 .LOC = "CLB_R15C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>218 ( + .ADR0(\vga/scancode_convert/scancode_rom/N18_0 ), + .ADR1(\vga/scancode_convert/scancode_rom/N28_0 ), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<1>218/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>242 .INIT = 16'hFDCD; + defparam \vga/scancode_convert/scancode_rom/data<1>242 .LOC = "CLB_R15C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>242 ( + .ADR0(\vga/scancode_convert/scancode_rom/N25 ), + .ADR1(\vga/scancode_convert/sc [5]), + .ADR2(\vga/scancode_convert/sc [2]), + .ADR3(\vga/scancode_convert/scancode_rom/data<1>218/O ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1690 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>218/O/XUSED .LOC = "CLB_R15C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<1>218/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>218/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<1>218/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>218/O/YUSED .LOC = "CLB_R15C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<1>218/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2_map1690 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1690_0 ) + ); + defparam \vga/scancode_convert/shift_set6 .INIT = 16'h0088; + defparam \vga/scancode_convert/shift_set6 .LOC = "CLB_R12C31.S0"; + X_LUT4 \vga/scancode_convert/shift_set6 ( + .ADR0(\vga/scancode_convert/N10_0 ), + .ADR1(\vga/ps2/sc_r [1]), + .ADR2(VCC), + .ADR3(\vga/ps2/sc_r [2]), + .O(\vga/scancode_convert/shift_set_map833_pack_1 ) + ); + defparam \vga/scancode_convert/_not0007 .INIT = 16'hAA80; + defparam \vga/scancode_convert/_not0007 .LOC = "CLB_R12C31.S0"; + X_LUT4 \vga/scancode_convert/_not0007 ( + .ADR0(\vga/scancode_convert/_and0000_0 ), + .ADR1(\vga/ps2/sc_r [0]), + .ADR2(\vga/scancode_convert/N11_0 ), + .ADR3(\vga/scancode_convert/shift_set_map833 ), + .O(\vga/scancode_convert/_not0007_164 ) + ); + defparam \vga/scancode_convert/shift_set_map833/XUSED .LOC = "CLB_R12C31.S0"; + X_BUF \vga/scancode_convert/shift_set_map833/XUSED ( + .I(\vga/scancode_convert/shift_set_map833_pack_1 ), + .O(\vga/scancode_convert/shift_set_map833 ) + ); + defparam \vga/scancode_convert/shift_set_map833/YUSED .LOC = "CLB_R12C31.S0"; + X_BUF \vga/scancode_convert/shift_set_map833/YUSED ( + .I(\vga/scancode_convert/_not0007_164 ), + .O(\vga/scancode_convert/_not0007_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>126_SW1 .INIT = 16'hFF5F; + defparam \vga/scancode_convert/scancode_rom/data<3>126_SW1 .LOC = "CLB_R17C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>126_SW1 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(VCC), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<3>126_SW1/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>126 .INIT = 16'h0062; + defparam \vga/scancode_convert/scancode_rom/data<3>126 .LOC = "CLB_R17C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>126 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/raise ), + .ADR3(\vga/scancode_convert/scancode_rom/data<3>126_SW1/O ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1158 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>126_SW1/O/XUSED .LOC = "CLB_R17C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>126_SW1/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>126_SW1/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<3>126_SW1/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>126_SW1/O/YUSED .LOC = "CLB_R17C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<3>126_SW1/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<3>1_map1158 ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1158_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>145 .INIT = 16'h773F; + defparam \vga/scancode_convert/scancode_rom/data<4>145 .LOC = "CLB_R12C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>145 ( + .ADR0(\vga/scancode_convert/scancode_rom/N18_0 ), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/scancode_rom/N43_0 ), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<4>145/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>182 .INIT = 16'h8B03; + defparam \vga/scancode_convert/scancode_rom/data<4>182 .LOC = "CLB_R12C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>182 ( + .ADR0(\vga/scancode_convert/scancode_rom/data<4>1_map1548_0 ), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/scancode_rom/N25 ), + .ADR3(\vga/scancode_convert/scancode_rom/data<4>145/O ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1560 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>145/O/XUSED .LOC = "CLB_R12C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>145/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>145/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<4>145/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>145/O/YUSED .LOC = "CLB_R12C36.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<4>145/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1_map1560 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1560_0 ) + ); + defparam \vga/scancode_convert/raise1_1 .INIT = 16'hFFEE; + defparam \vga/scancode_convert/raise1_1 .LOC = "CLB_R12C33.S0"; + X_LUT4 \vga/scancode_convert/raise1_1 ( + .ADR0(\vga/scancode_convert/ctrl_22 ), + .ADR1(\vga/scancode_convert/shift_24 ), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/capslock_25 ), + .O(\vga/scancode_convert/raise1_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>374 .INIT = 16'h757F; + defparam \vga/scancode_convert/scancode_rom/data<5>374 .LOC = "CLB_R12C33.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>374 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc_0_1_10 ), + .ADR2(\vga/scancode_convert/sc_1_1_23 ), + .ADR3(\vga/scancode_convert/raise1_33 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1260 ) + ); + defparam \vga/scancode_convert/raise1/XUSED .LOC = "CLB_R12C33.S0"; + X_BUF \vga/scancode_convert/raise1/XUSED ( + .I(\vga/scancode_convert/raise1_pack_1 ), + .O(\vga/scancode_convert/raise1_33 ) + ); + defparam \vga/scancode_convert/raise1/YUSED .LOC = "CLB_R12C33.S0"; + X_BUF \vga/scancode_convert/raise1/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1260 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1260_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>111 .INIT = 16'h5FFF; + defparam \vga/scancode_convert/scancode_rom/data<1>111 .LOC = "CLB_R13C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>111 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(VCC), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/N25_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>186 .INIT = 16'hEAFB; + defparam \vga/scancode_convert/scancode_rom/data<6>186 .LOC = "CLB_R13C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>186 ( + .ADR0(\vga/scancode_convert/sc [5]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(N3124_0), + .ADR3(\vga/scancode_convert/scancode_rom/N25 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1803 ) + ); + defparam \vga/scancode_convert/scancode_rom/N25/XUSED .LOC = "CLB_R13C37.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N25/XUSED ( + .I(\vga/scancode_convert/scancode_rom/N25_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/N25 ) + ); + defparam \vga/scancode_convert/scancode_rom/N25/YUSED .LOC = "CLB_R13C37.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N25/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1_map1803 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1803_0 ) + ); + defparam \vga/_and000093 .INIT = 16'h8241; + defparam \vga/_and000093 .LOC = "CLB_R14C9.S0"; + X_LUT4 \vga/_and000093 ( + .ADR0(\vga/vgacore/hcnt [7]), + .ADR1(\vga/crt/cursor_h [5]), + .ADR2(\vga/vgacore/hcnt [8]), + .ADR3(\vga/crt/cursor_h [4]), + .O(\vga/_and000093/O_pack_1 ) + ); + defparam \vga/_and0000238 .INIT = 16'h8000; + defparam \vga/_and0000238 .LOC = "CLB_R14C9.S0"; + X_LUT4 \vga/_and0000238 ( + .ADR0(\vga/_and0000_map879_0 ), + .ADR1(\vga/_and0000_map943_0 ), + .ADR2(\vga/_and0000_map890_0 ), + .ADR3(\vga/_and000093/O ), + .O(\vga/cursor_match ) + ); + defparam \vga/_and000093/O/XUSED .LOC = "CLB_R14C9.S0"; + X_BUF \vga/_and000093/O/XUSED ( + .I(\vga/_and000093/O_pack_1 ), + .O(\vga/_and000093/O ) + ); + defparam \vga/_and000093/O/YUSED .LOC = "CLB_R14C9.S0"; + X_BUF \vga/_and000093/O/YUSED ( + .I(\vga/cursor_match ), + .O(\vga/cursor_match_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>176 .INIT = 16'hCF4F; + defparam \vga/scancode_convert/scancode_rom/data<0>176 .LOC = "CLB_R15C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>176 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/scancode_rom/data<0>1_map1429_0 ), + .ADR2(\vga/scancode_convert/sc [2]), + .ADR3(\vga/scancode_convert/scancode_rom/data<0>1_map1438_0 ), + .O(\vga/scancode_convert/scancode_rom/data<0>176/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1104 .INIT = 16'hFEF0; + defparam \vga/scancode_convert/scancode_rom/data<0>1104 .LOC = "CLB_R15C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1104 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/scancode_rom/data<0>1_map1423_0 ), + .ADR2(\vga/scancode_convert/sc [5]), + .ADR3(\vga/scancode_convert/scancode_rom/data<0>176/O ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1445 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>176/O/XUSED .LOC = "CLB_R15C34.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>176/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>176/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<0>176/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>176/O/YUSED .LOC = "CLB_R15C34.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>176/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1445 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1445_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW1 .INIT = 16'hD710; + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW1 .LOC = "CLB_R16C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1370_SW1 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<0>1370_SW1/O_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370 .INIT = 16'hEEFC; + defparam \vga/scancode_convert/scancode_rom/data<0>1370 .LOC = "CLB_R16C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1370 ( + .ADR0(N3178_0), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/scancode_rom/data<0>1370_SW1/O ), + .ADR3(\vga/scancode_convert/scancode_rom/N12 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1503 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW1/O/XUSED .LOC = "CLB_R16C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1370_SW1/O/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1370_SW1/O_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1370_SW1/O ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW1/O/YUSED .LOC = "CLB_R16C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1370_SW1/O/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1503 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1503_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>31 .INIT = 16'hCFFF; + defparam \vga/scancode_convert/scancode_rom/data<0>31 .LOC = "CLB_R16C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>31 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/N7_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1536 .INIT = 16'h0F2F; + defparam \vga/scancode_convert/scancode_rom/data<0>1536 .LOC = "CLB_R16C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1536 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [5]), + .ADR3(\vga/scancode_convert/scancode_rom/N7 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1534 ) + ); + defparam \vga/scancode_convert/scancode_rom/N7/XUSED .LOC = "CLB_R16C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N7/XUSED ( + .I(\vga/scancode_convert/scancode_rom/N7_pack_1 ), + .O(\vga/scancode_convert/scancode_rom/N7 ) + ); + defparam \vga/scancode_convert/scancode_rom/N7/YUSED .LOC = "CLB_R16C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N7/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1534 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1534_0 ) + ); + defparam \vga/ram_addr_mux<10>1 .INIT = 16'hE2E2; + defparam \vga/ram_addr_mux<10>1 .LOC = "CLB_R12C3.S1"; + X_LUT4 \vga/ram_addr_mux<10>1 ( + .ADR0(\vga/ram_addr_write<10>_0 ), + .ADR1(\vga/ram_we_n ), + .ADR2(\vga/ram_addr_video<10>_0 ), + .ADR3(VCC), + .O(\vga/ram_addr_mux [10]) + ); + defparam \vga/video_ram/ram_addr_w<10>/YUSED .LOC = "CLB_R12C3.S1"; + X_BUF \vga/video_ram/ram_addr_w<10>/YUSED ( + .I(\vga/ram_addr_mux [10]), + .O(\vga/ram_addr_mux<10>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_10 .LOC = "CLB_R12C3.S1"; + defparam \vga/video_ram/ram_addr_w_10 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_10 ( + .I(\vga/ram_addr_mux [10]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [10]) + ); + defparam \vga/crt/Madd_ram_addrR21 .INIT = 16'h9966; + defparam \vga/crt/Madd_ram_addrR21 .LOC = "CLB_R16C13.S0"; + X_LUT4 \vga/crt/Madd_ram_addrR21 ( + .ADR0(\vga/crt/cursor_v [2]), + .ADR1(\vga/crt/cursor_h [6]), + .ADR2(VCC), + .ADR3(\vga/crt/cursor_v [0]), + .O(\vga/crt/Madd_ram_addrR2 ) + ); + defparam \vga/crt/cursor_v_Eqn_01 .INIT = 16'h000F; + defparam \vga/crt/cursor_v_Eqn_01 .LOC = "CLB_R16C13.S0"; + X_LUT4 \vga/crt/cursor_v_Eqn_01 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_v [0]), + .ADR3(\vga/crt/_and0001_32 ), + .O(\vga/crt/cursor_v_Eqn_0 ) + ); + defparam \vga/crt/cursor_v<0>/XUSED .LOC = "CLB_R16C13.S0"; + X_BUF \vga/crt/cursor_v<0>/XUSED ( + .I(\vga/crt/Madd_ram_addrR2 ), + .O(\vga/crt/Madd_ram_addrR2_0 ) + ); + defparam \vga/crt/cursor_v_0 .LOC = "CLB_R16C13.S0"; + defparam \vga/crt/cursor_v_0 .INIT = 1'b0; + X_FF \vga/crt/cursor_v_0 ( + .I(\vga/crt/cursor_v_Eqn_0 ), + .CE(\vga/crt/_not0007_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_v<0>/FFY/RST ), + .O(\vga/crt/cursor_v [0]) + ); + defparam \vga/crt/cursor_v<0>/FFY/RSTOR .LOC = "CLB_R16C13.S0"; + X_INV \vga/crt/cursor_v<0>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_v<0>/FFY/RST ) + ); + defparam \vga/crt/cursor_v_Eqn_31 .INIT = 16'h5050; + defparam \vga/crt/cursor_v_Eqn_31 .LOC = "CLB_R15C13.S1"; + X_LUT4 \vga/crt/cursor_v_Eqn_31 ( + .ADR0(\vga/crt/_and0001_32 ), + .ADR1(VCC), + .ADR2(\vga/crt/Result<3>_0 ), + .ADR3(VCC), + .O(\vga/crt/cursor_v_Eqn_3 ) + ); + defparam \vga/crt/cursor_v_Eqn_21 .INIT = 16'h5500; + defparam \vga/crt/cursor_v_Eqn_21 .LOC = "CLB_R15C13.S1"; + X_LUT4 \vga/crt/cursor_v_Eqn_21 ( + .ADR0(\vga/crt/_and0001_32 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/crt/Result<2>_0 ), + .O(\vga/crt/cursor_v_Eqn_2 ) + ); + defparam \vga/crt/cursor_v<3>/SRMUX .LOC = "CLB_R15C13.S1"; + X_INV \vga/crt/cursor_v<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_v<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/cursor_v_Eqn_51 .INIT = 16'h5500; + defparam \vga/crt/cursor_v_Eqn_51 .LOC = "CLB_R15C14.S0"; + X_LUT4 \vga/crt/cursor_v_Eqn_51 ( + .ADR0(\vga/crt/_and0001_32 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/crt/Result<5>_0 ), + .O(\vga/crt/cursor_v_Eqn_5 ) + ); + defparam \vga/crt/cursor_v_Eqn_41 .INIT = 16'h5500; + defparam \vga/crt/cursor_v_Eqn_41 .LOC = "CLB_R15C14.S0"; + X_LUT4 \vga/crt/cursor_v_Eqn_41 ( + .ADR0(\vga/crt/_and0001_32 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/crt/Result<4>_0 ), + .O(\vga/crt/cursor_v_Eqn_4 ) + ); + defparam \vga/crt/cursor_v<5>/SRMUX .LOC = "CLB_R15C14.S0"; + X_INV \vga/crt/cursor_v<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_v<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/_mux0002<1>1 .INIT = 16'hDF80; + defparam \vga/crt/_mux0002<1>1 .LOC = "CLB_R18C13.S0"; + X_LUT4 \vga/crt/_mux0002<1>1 ( + .ADR0(\vga/crt/state_FFd2_12 ), + .ADR1(\vga/crt_data [1]), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/cursor_h [1]), + .O(\vga/crt/_mux0002 [1]) + ); + defparam \vga/crt/_mux0002<0>1 .INIT = 16'hD8F0; + defparam \vga/crt/_mux0002<0>1 .LOC = "CLB_R18C13.S0"; + X_LUT4 \vga/crt/_mux0002<0>1 ( + .ADR0(\vga/crt/state_FFd2_12 ), + .ADR1(\vga/crt_data [0]), + .ADR2(\vga/crt/cursor_h [0]), + .ADR3(\vga/crt/state_FFd3_11 ), + .O(\vga/crt/_mux0002 [0]) + ); + defparam \vga/crt/ram_data<1>/SRMUX .LOC = "CLB_R18C13.S0"; + X_INV \vga/crt/ram_data<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/ram_data<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/_mux0002<3>1 .INIT = 16'hBF80; + defparam \vga/crt/_mux0002<3>1 .LOC = "CLB_R18C9.S0"; + X_LUT4 \vga/crt/_mux0002<3>1 ( + .ADR0(\vga/crt_data [3]), + .ADR1(\vga/crt/state_FFd2_12 ), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/cursor_h [3]), + .O(\vga/crt/_mux0002 [3]) + ); + defparam \vga/crt/_mux0002<2>1 .INIT = 16'hBF80; + defparam \vga/crt/_mux0002<2>1 .LOC = "CLB_R18C9.S0"; + X_LUT4 \vga/crt/_mux0002<2>1 ( + .ADR0(\vga/crt_data [2]), + .ADR1(\vga/crt/state_FFd2_12 ), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/cursor_h [2]), + .O(\vga/crt/_mux0002 [2]) + ); + defparam \vga/crt/ram_data<3>/SRMUX .LOC = "CLB_R18C9.S0"; + X_INV \vga/crt/ram_data<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/ram_data<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/_mux0002<5>1 .INIT = 16'hB313; + defparam \vga/crt/_mux0002<5>1 .LOC = "CLB_R14C13.S1"; + X_LUT4 \vga/crt/_mux0002<5>1 ( + .ADR0(\vga/crt/state_FFd2_12 ), + .ADR1(\vga/crt/cursor_h [5]), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt_data [5]), + .O(\vga/crt/_mux0002 [5]) + ); + defparam \vga/crt/_mux0002<4>1 .INIT = 16'hCAAA; + defparam \vga/crt/_mux0002<4>1 .LOC = "CLB_R14C13.S1"; + X_LUT4 \vga/crt/_mux0002<4>1 ( + .ADR0(\vga/crt/cursor_h [4]), + .ADR1(\vga/crt_data [4]), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/crt/_mux0002 [4]) + ); + defparam \vga/crt/ram_data<5>/SRMUX .LOC = "CLB_R14C13.S1"; + X_INV \vga/crt/ram_data<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/ram_data<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/scancode_convert/_not00121 .INIT = 16'hFFC0; + defparam \vga/scancode_convert/_not00121 .LOC = "CLB_R14C26.S1"; + X_LUT4 \vga/scancode_convert/_not00121 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/state_FFd1_34 ), + .ADR2(\vga/scancode_convert/_cmp_eq0005 ), + .ADR3(\vga/scancode_convert/state_FFd3_29 ), + .O(\vga/scancode_convert/_not0012 ) + ); + defparam \vga/scancode_convert/state_FFd1-In1 .INIT = 16'hF5F0; + defparam \vga/scancode_convert/state_FFd1-In1 .LOC = "CLB_R14C26.S1"; + X_LUT4 \vga/scancode_convert/state_FFd1-In1 ( + .ADR0(\vga/scancode_convert/_cmp_eq0005 ), + .ADR1(VCC), + .ADR2(\vga/scancode_convert/state_FFd4_30 ), + .ADR3(\vga/scancode_convert/state_FFd1_34 ), + .O(\vga/scancode_convert/state_FFd1-In ) + ); + defparam \vga/scancode_convert/state_FFd1/XUSED .LOC = "CLB_R14C26.S1"; + X_BUF \vga/scancode_convert/state_FFd1/XUSED ( + .I(\vga/scancode_convert/_not0012 ), + .O(\vga/scancode_convert/_not0012_0 ) + ); + defparam \vga/scancode_convert/state_FFd1 .LOC = "CLB_R14C26.S1"; + defparam \vga/scancode_convert/state_FFd1 .INIT = 1'b0; + X_FF \vga/scancode_convert/state_FFd1 ( + .I(\vga/scancode_convert/state_FFd1-In ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/state_FFd1/FFY/RST ), + .O(\vga/scancode_convert/state_FFd1_34 ) + ); + defparam \vga/scancode_convert/state_FFd1/FFY/RSTOR .LOC = "CLB_R14C26.S1"; + X_INV \vga/scancode_convert/state_FFd1/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/state_FFd1/FFY/RST ) + ); + defparam \vga/scancode_convert/state_FFd6/LOGIC_ZERO .LOC = "CLB_R12C28.S0"; + X_ZERO \vga/scancode_convert/state_FFd6/LOGIC_ZERO ( + .O(\vga/scancode_convert/state_FFd6/LOGIC_ZERO_165 ) + ); + defparam \vga/scancode_convert/state_FFd2-In111 .INIT = 16'hC0C0; + defparam \vga/scancode_convert/state_FFd2-In111 .LOC = "CLB_R12C28.S0"; + X_LUT4 \vga/scancode_convert/state_FFd2-In111 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/state_FFd5_31 ), + .ADR2(\vga/ps2/rdy_r_1 ), + .ADR3(VCC), + .O(\vga/scancode_convert/_and0000 ) + ); + defparam \vga/scancode_convert/state_FFd5-In .INIT = 16'hEECE; + defparam \vga/scancode_convert/state_FFd5-In .LOC = "CLB_R12C28.S0"; + X_LUT4 \vga/scancode_convert/state_FFd5-In ( + .ADR0(\vga/scancode_convert/state_FFd5_31 ), + .ADR1(N124_0), + .ADR2(\vga/ps2/rdy_r_1 ), + .ADR3(\vga/scancode_convert/_cmp_eq0000_27 ), + .O(\vga/scancode_convert/state_FFd5-In_166 ) + ); + defparam \vga/scancode_convert/state_FFd6/XUSED .LOC = "CLB_R12C28.S0"; + X_BUF \vga/scancode_convert/state_FFd6/XUSED ( + .I(\vga/scancode_convert/_and0000 ), + .O(\vga/scancode_convert/_and0000_0 ) + ); + defparam \vga/scancode_convert/state_FFd6/SRMUX .LOC = "CLB_R12C28.S0"; + X_INV \vga/scancode_convert/state_FFd6/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/state_FFd6/SRMUX_OUTPUTNOT ) + ); + defparam \vga/scancode_convert/capslock_toggle1 .INIT = 16'h4000; + defparam \vga/scancode_convert/capslock_toggle1 .LOC = "CLB_R12C32.S0"; + X_LUT4 \vga/scancode_convert/capslock_toggle1 ( + .ADR0(\vga/ps2/sc_r [0]), + .ADR1(\vga/scancode_convert/N11_0 ), + .ADR2(\vga/scancode_convert/_and0000_0 ), + .ADR3(\vga/scancode_convert/release_prefix_26 ), + .O(\vga/scancode_convert/capslock_toggle ) + ); + defparam \vga/scancode_convert/shift_set17 .INIT = 16'hEC00; + defparam \vga/scancode_convert/shift_set17 .LOC = "CLB_R12C32.S0"; + X_LUT4 \vga/scancode_convert/shift_set17 ( + .ADR0(\vga/scancode_convert/N11_0 ), + .ADR1(\vga/scancode_convert/shift_set_map833 ), + .ADR2(\vga/ps2/sc_r [0]), + .ADR3(\vga/scancode_convert/shift_set_map836_0 ), + .O(\vga/scancode_convert/shift_set ) + ); + defparam \vga/scancode_convert/shift/XUSED .LOC = "CLB_R12C32.S0"; + X_BUF \vga/scancode_convert/shift/XUSED ( + .I(\vga/scancode_convert/capslock_toggle ), + .O(\vga/scancode_convert/capslock_toggle_0 ) + ); + defparam \vga/scancode_convert/shift .LOC = "CLB_R12C32.S0"; + defparam \vga/scancode_convert/shift .INIT = 1'b0; + X_FF \vga/scancode_convert/shift ( + .I(\vga/scancode_convert/shift_set ), + .CE(\vga/scancode_convert/_not0007_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/shift/FFY/RST ), + .O(\vga/scancode_convert/shift_24 ) + ); + defparam \vga/scancode_convert/shift/FFY/RSTOR .LOC = "CLB_R12C32.S0"; + X_INV \vga/scancode_convert/shift/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/shift/FFY/RST ) + ); + defparam \vga/scancode_convert/shift_set14 .INIT = 16'h0C00; + defparam \vga/scancode_convert/shift_set14 .LOC = "CLB_R12C28.S1"; + X_LUT4 \vga/scancode_convert/shift_set14 ( + .ADR0(VCC), + .ADR1(\vga/ps2/rdy_r_1 ), + .ADR2(\vga/scancode_convert/release_prefix_26 ), + .ADR3(\vga/scancode_convert/state_FFd5_31 ), + .O(\vga/scancode_convert/shift_set_map836 ) + ); + defparam \vga/scancode_convert/release_prefix_set1 .INIT = 16'h8080; + defparam \vga/scancode_convert/release_prefix_set1 .LOC = "CLB_R12C28.S1"; + X_LUT4 \vga/scancode_convert/release_prefix_set1 ( + .ADR0(\vga/scancode_convert/_cmp_eq0000_27 ), + .ADR1(\vga/ps2/rdy_r_1 ), + .ADR2(\vga/scancode_convert/state_FFd5_31 ), + .ADR3(VCC), + .O(\vga/scancode_convert/release_prefix_set ) + ); + defparam \vga/scancode_convert/release_prefix/XUSED .LOC = "CLB_R12C28.S1"; + X_BUF \vga/scancode_convert/release_prefix/XUSED ( + .I(\vga/scancode_convert/shift_set_map836 ), + .O(\vga/scancode_convert/shift_set_map836_0 ) + ); + defparam \vga/scancode_convert/release_prefix .LOC = "CLB_R12C28.S1"; + defparam \vga/scancode_convert/release_prefix .INIT = 1'b0; + X_FF \vga/scancode_convert/release_prefix ( + .I(\vga/scancode_convert/release_prefix_set ), + .CE(\vga/scancode_convert/_not0010_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/release_prefix/FFY/RST ), + .O(\vga/scancode_convert/release_prefix_26 ) + ); + defparam \vga/scancode_convert/release_prefix/FFY/RSTOR .LOC = "CLB_R12C28.S1"; + X_INV \vga/scancode_convert/release_prefix/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/release_prefix/FFY/RST ) + ); + defparam \vga/ps2/timer_x<11>1 .INIT = 16'h3300; + defparam \vga/ps2/timer_x<11>1 .LOC = "CLB_R6C17.S0"; + X_LUT4 \vga/ps2/timer_x<11>1 ( + .ADR0(VCC), + .ADR1(\vga/ps2/ps2_clk_edge ), + .ADR2(VCC), + .ADR3(\vga/ps2/_addsub0000<11>_0 ), + .O(\vga/ps2/timer_x [11]) + ); + defparam \vga/ps2/timer_x<10>1 .INIT = 16'h3030; + defparam \vga/ps2/timer_x<10>1 .LOC = "CLB_R6C17.S0"; + X_LUT4 \vga/ps2/timer_x<10>1 ( + .ADR0(VCC), + .ADR1(\vga/ps2/ps2_clk_edge ), + .ADR2(\vga/ps2/_addsub0000<10>_0 ), + .ADR3(VCC), + .O(\vga/ps2/timer_x [10]) + ); + defparam \vga/ps2/timer_r<11>/SRMUX .LOC = "CLB_R6C17.S0"; + X_INV \vga/ps2/timer_r<11>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<11>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/timer_x<13>1 .INIT = 16'h00AA; + defparam \vga/ps2/timer_x<13>1 .LOC = "CLB_R6C16.S0"; + X_LUT4 \vga/ps2/timer_x<13>1 ( + .ADR0(\vga/ps2/_addsub0000<13>_0 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/ps2_clk_edge ), + .O(\vga/ps2/timer_x [13]) + ); + defparam \vga/ps2/timer_x<12>1 .INIT = 16'h4444; + defparam \vga/ps2/timer_x<12>1 .LOC = "CLB_R6C16.S0"; + X_LUT4 \vga/ps2/timer_x<12>1 ( + .ADR0(\vga/ps2/ps2_clk_edge ), + .ADR1(\vga/ps2/_addsub0000<12>_0 ), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/timer_x [12]) + ); + defparam \vga/ps2/timer_r<13>/SRMUX .LOC = "CLB_R6C16.S0"; + X_INV \vga/ps2/timer_r<13>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<13>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/timer_r_13 .LOC = "CLB_R6C16.S0"; + defparam \vga/ps2/timer_r_13 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_13 ( + .I(\vga/ps2/timer_x [13]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<13>/FFX/RST ), + .O(\vga/ps2/timer_r [13]) + ); + defparam \vga/ps2/timer_r<13>/FFX/RSTOR .LOC = "CLB_R6C16.S0"; + X_BUF \vga/ps2/timer_r<13>/FFX/RSTOR ( + .I(\vga/ps2/timer_r<13>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<13>/FFX/RST ) + ); + defparam \vga/ps2/ps2_clk_edge11 .INIT = 16'h0400; + defparam \vga/ps2/ps2_clk_edge11 .LOC = "CLB_R10C18.S0"; + X_LUT4 \vga/ps2/ps2_clk_edge11 ( + .ADR0(\vga/ps2/ps2_clk_r [2]), + .ADR1(\vga/ps2/ps2_clk_r [3]), + .ADR2(\vga/ps2/ps2_clk_r [1]), + .ADR3(\vga/ps2/ps2_clk_r [4]), + .O(\vga/ps2/ps2_clk_fall_edge ) + ); + defparam \vga/ps2/error_x24 .INIT = 16'hEFCC; + defparam \vga/ps2/error_x24 .LOC = "CLB_R10C18.S0"; + X_LUT4 \vga/ps2/error_x24 ( + .ADR0(\vga/ps2/error_x_map855_0 ), + .ADR1(\vga/ps2/error_r_16 ), + .ADR2(\vga/ps2/ps2_clk_r [1]), + .ADR3(\vga/ps2/_cmp_eq0001 ), + .O(\vga/ps2/error_x ) + ); + defparam \vga/ps2/error_r/XUSED .LOC = "CLB_R10C18.S0"; + X_BUF \vga/ps2/error_r/XUSED ( + .I(\vga/ps2/ps2_clk_fall_edge ), + .O(\vga/ps2/ps2_clk_fall_edge_0 ) + ); + defparam \vga/ps2/error_r .LOC = "CLB_R10C18.S0"; + defparam \vga/ps2/error_r .INIT = 1'b0; + X_FF \vga/ps2/error_r ( + .I(\vga/ps2/error_x ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/error_r/FFY/RST ), + .O(\vga/ps2/error_r_16 ) + ); + defparam \vga/ps2/error_r/FFY/RSTOR .LOC = "CLB_R10C18.S0"; + X_INV \vga/ps2/error_r/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/error_r/FFY/RST ) + ); + defparam \vga/charload1 .INIT = 16'hFBC8; + defparam \vga/charload1 .LOC = "CLB_R12C7.S0"; + X_LUT4 \vga/charload1 ( + .ADR0(N560_0), + .ADR1(\vga/charload_19 ), + .ADR2(\vga/cursor_match_0 ), + .ADR3(\vga/pixel_hold [1]), + .O(\vga/_mux0002 [5]) + ); + defparam \vga/pixel_hold_2 .LOC = "CLB_R12C7.S0"; + defparam \vga/pixel_hold_2 .INIT = 1'b0; + X_FF \vga/pixel_hold_2 ( + .I(\vga/_mux0002 [5]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [2]) + ); + defparam \vga/ram_addr_mux<1>1 .INIT = 16'hF0AA; + defparam \vga/ram_addr_mux<1>1 .LOC = "CLB_R19C4.S0"; + X_LUT4 \vga/ram_addr_mux<1>1 ( + .ADR0(\vga/crt/cursor_h [1]), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [4]), + .ADR3(\vga/ram_we_n ), + .O(\vga/ram_addr_mux [1]) + ); + defparam \vga/ram_addr_mux<0>1 .INIT = 16'hF0AA; + defparam \vga/ram_addr_mux<0>1 .LOC = "CLB_R19C4.S0"; + X_LUT4 \vga/ram_addr_mux<0>1 ( + .ADR0(\vga/crt/cursor_h [0]), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [3]), + .ADR3(\vga/ram_we_n ), + .O(\vga/ram_addr_mux [0]) + ); + defparam \vga/video_ram/ram_addr_w<1>/XUSED .LOC = "CLB_R19C4.S0"; + X_BUF \vga/video_ram/ram_addr_w<1>/XUSED ( + .I(\vga/ram_addr_mux [1]), + .O(\vga/ram_addr_mux<1>_0 ) + ); + defparam \vga/video_ram/ram_addr_w<1>/YUSED .LOC = "CLB_R19C4.S0"; + X_BUF \vga/video_ram/ram_addr_w<1>/YUSED ( + .I(\vga/ram_addr_mux [0]), + .O(\vga/ram_addr_mux<0>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_0 .LOC = "CLB_R19C4.S0"; + defparam \vga/video_ram/ram_addr_w_0 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_0 ( + .I(\vga/ram_addr_mux [0]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [0]) + ); + defparam \vga/ram_addr_mux<3>1 .INIT = 16'hF5A0; + defparam \vga/ram_addr_mux<3>1 .LOC = "CLB_R15C2.S0"; + X_LUT4 \vga/ram_addr_mux<3>1 ( + .ADR0(\vga/ram_we_n ), + .ADR1(VCC), + .ADR2(\vga/vgacore/hcnt [6]), + .ADR3(\vga/crt/cursor_h [3]), + .O(\vga/ram_addr_mux [3]) + ); + defparam \vga/ram_addr_mux<2>1 .INIT = 16'hCCF0; + defparam \vga/ram_addr_mux<2>1 .LOC = "CLB_R15C2.S0"; + X_LUT4 \vga/ram_addr_mux<2>1 ( + .ADR0(VCC), + .ADR1(\vga/vgacore/hcnt [5]), + .ADR2(\vga/crt/cursor_h [2]), + .ADR3(\vga/ram_we_n ), + .O(\vga/ram_addr_mux [2]) + ); + defparam \vga/video_ram/ram_addr_w<3>/XUSED .LOC = "CLB_R15C2.S0"; + X_BUF \vga/video_ram/ram_addr_w<3>/XUSED ( + .I(\vga/ram_addr_mux [3]), + .O(\vga/ram_addr_mux<3>_0 ) + ); + defparam \vga/video_ram/ram_addr_w<3>/YUSED .LOC = "CLB_R15C2.S0"; + X_BUF \vga/video_ram/ram_addr_w<3>/YUSED ( + .I(\vga/ram_addr_mux [2]), + .O(\vga/ram_addr_mux<2>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_2 .LOC = "CLB_R15C2.S0"; + defparam \vga/video_ram/ram_addr_w_2 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_2 ( + .I(\vga/ram_addr_mux [2]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [2]) + ); + defparam \vga/ram_addr_mux<5>1 .INIT = 16'hCFC0; + defparam \vga/ram_addr_mux<5>1 .LOC = "CLB_R18C3.S1"; + X_LUT4 \vga/ram_addr_mux<5>1 ( + .ADR0(VCC), + .ADR1(\vga/ram_addr_video<5>_0 ), + .ADR2(\vga/ram_we_n ), + .ADR3(\vga/ram_addr_write<5>_0 ), + .O(\vga/ram_addr_mux [5]) + ); + defparam \vga/video_ram/ram_addr_w<5>/YUSED .LOC = "CLB_R18C3.S1"; + X_BUF \vga/video_ram/ram_addr_w<5>/YUSED ( + .I(\vga/ram_addr_mux [5]), + .O(\vga/ram_addr_mux<5>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_5 .LOC = "CLB_R18C3.S1"; + defparam \vga/video_ram/ram_addr_w_5 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_5 ( + .I(\vga/ram_addr_mux [5]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [5]) + ); + defparam \vga/ram_addr_mux<7>1 .INIT = 16'hCCF0; + defparam \vga/ram_addr_mux<7>1 .LOC = "CLB_R15C2.S1"; + X_LUT4 \vga/ram_addr_mux<7>1 ( + .ADR0(VCC), + .ADR1(\vga/ram_addr_video<7>_0 ), + .ADR2(\vga/ram_addr_write<7>_0 ), + .ADR3(\vga/ram_we_n ), + .O(\vga/ram_addr_mux [7]) + ); + defparam \vga/ram_addr_mux<6>1 .INIT = 16'hE4E4; + defparam \vga/ram_addr_mux<6>1 .LOC = "CLB_R15C2.S1"; + X_LUT4 \vga/ram_addr_mux<6>1 ( + .ADR0(\vga/ram_we_n ), + .ADR1(\vga/ram_addr_write<6>_0 ), + .ADR2(\vga/ram_addr_video<6>_0 ), + .ADR3(VCC), + .O(\vga/ram_addr_mux [6]) + ); + defparam \vga/video_ram/ram_addr_w<7>/XUSED .LOC = "CLB_R15C2.S1"; + X_BUF \vga/video_ram/ram_addr_w<7>/XUSED ( + .I(\vga/ram_addr_mux [7]), + .O(\vga/ram_addr_mux<7>_0 ) + ); + defparam \vga/video_ram/ram_addr_w<7>/YUSED .LOC = "CLB_R15C2.S1"; + X_BUF \vga/video_ram/ram_addr_w<7>/YUSED ( + .I(\vga/ram_addr_mux [6]), + .O(\vga/ram_addr_mux<6>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_6 .LOC = "CLB_R15C2.S1"; + defparam \vga/video_ram/ram_addr_w_6 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_6 ( + .I(\vga/ram_addr_mux [6]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [6]) + ); + defparam \vga/ram_addr_mux<9>1 .INIT = 16'hAAF0; + defparam \vga/ram_addr_mux<9>1 .LOC = "CLB_R15C4.S1"; + X_LUT4 \vga/ram_addr_mux<9>1 ( + .ADR0(\vga/ram_addr_video<9>_0 ), + .ADR1(VCC), + .ADR2(\vga/ram_addr_write<9>_0 ), + .ADR3(\vga/ram_we_n ), + .O(\vga/ram_addr_mux [9]) + ); + defparam \vga/ram_addr_mux<8>1 .INIT = 16'hCCF0; + defparam \vga/ram_addr_mux<8>1 .LOC = "CLB_R15C4.S1"; + X_LUT4 \vga/ram_addr_mux<8>1 ( + .ADR0(VCC), + .ADR1(\vga/ram_addr_video<8>_0 ), + .ADR2(\vga/ram_addr_write<8>_0 ), + .ADR3(\vga/ram_we_n ), + .O(\vga/ram_addr_mux [8]) + ); + defparam \vga/video_ram/ram_addr_w<9>/XUSED .LOC = "CLB_R15C4.S1"; + X_BUF \vga/video_ram/ram_addr_w<9>/XUSED ( + .I(\vga/ram_addr_mux [9]), + .O(\vga/ram_addr_mux<9>_0 ) + ); + defparam \vga/video_ram/ram_addr_w<9>/YUSED .LOC = "CLB_R15C4.S1"; + X_BUF \vga/video_ram/ram_addr_w<9>/YUSED ( + .I(\vga/ram_addr_mux [8]), + .O(\vga/ram_addr_mux<8>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_8 .LOC = "CLB_R15C4.S1"; + defparam \vga/video_ram/ram_addr_w_8 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_8 ( + .I(\vga/ram_addr_mux [8]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [8]) + ); + defparam \vga/scancode_convert/hold_count__mux0000<1>1 .INIT = 16'h6600; + defparam \vga/scancode_convert/hold_count__mux0000<1>1 .LOC = "CLB_R14C26.S0"; + X_LUT4 \vga/scancode_convert/hold_count__mux0000<1>1 ( + .ADR0(\vga/scancode_convert/hold_count [0]), + .ADR1(\vga/scancode_convert/hold_count [1]), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/state_FFd1_34 ), + .O(\vga/scancode_convert/hold_count__mux0000 [1]) + ); + defparam \vga/scancode_convert/hold_count__mux0000<0>1 .INIT = 16'h0C0C; + defparam \vga/scancode_convert/hold_count__mux0000<0>1 .LOC = "CLB_R14C26.S0"; + X_LUT4 \vga/scancode_convert/hold_count__mux0000<0>1 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/state_FFd1_34 ), + .ADR2(\vga/scancode_convert/hold_count [0]), + .ADR3(VCC), + .O(\vga/scancode_convert/hold_count__mux0000 [0]) + ); + defparam \vga/scancode_convert/hold_count<1>/SRMUX .LOC = "CLB_R14C26.S0"; + X_INV \vga/scancode_convert/hold_count<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/hold_count<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/scancode_convert/_not00111 .INIT = 16'hFEFC; + defparam \vga/scancode_convert/_not00111 .LOC = "CLB_R13C26.S0"; + X_LUT4 \vga/scancode_convert/_not00111 ( + .ADR0(\vga/scancode_convert/_cmp_eq0005 ), + .ADR1(\vga/scancode_convert/state_FFd3_29 ), + .ADR2(\vga/scancode_convert/state_FFd2_28 ), + .ADR3(\vga/scancode_convert/state_FFd1_34 ), + .O(\vga/scancode_convert/_not0011 ) + ); + defparam \vga/scancode_convert/hold_count__mux0000<2>1 .INIT = 16'h60C0; + defparam \vga/scancode_convert/hold_count__mux0000<2>1 .LOC = "CLB_R13C26.S0"; + X_LUT4 \vga/scancode_convert/hold_count__mux0000<2>1 ( + .ADR0(\vga/scancode_convert/hold_count [0]), + .ADR1(\vga/scancode_convert/hold_count [2]), + .ADR2(\vga/scancode_convert/state_FFd1_34 ), + .ADR3(\vga/scancode_convert/hold_count [1]), + .O(\vga/scancode_convert/hold_count__mux0000 [2]) + ); + defparam \vga/scancode_convert/hold_count<2>/XUSED .LOC = "CLB_R13C26.S0"; + X_BUF \vga/scancode_convert/hold_count<2>/XUSED ( + .I(\vga/scancode_convert/_not0011 ), + .O(\vga/scancode_convert/_not0011_0 ) + ); + defparam \vga/scancode_convert/hold_count_2 .LOC = "CLB_R13C26.S0"; + defparam \vga/scancode_convert/hold_count_2 .INIT = 1'b0; + X_FF \vga/scancode_convert/hold_count_2 ( + .I(\vga/scancode_convert/hold_count__mux0000 [2]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/hold_count<2>/FFY/RST ), + .O(\vga/scancode_convert/hold_count [2]) + ); + defparam \vga/scancode_convert/hold_count<2>/FFY/RSTOR .LOC = "CLB_R13C26.S0"; + X_INV \vga/scancode_convert/hold_count<2>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/hold_count<2>/FFY/RST ) + ); + defparam \vga/ps2/_cmp_eq000142 .INIT = 16'h0002; + defparam \vga/ps2/_cmp_eq000142 .LOC = "CLB_R11C16.S0"; + X_LUT4 \vga/ps2/_cmp_eq000142 ( + .ADR0(\vga/ps2/timer_r [2]), + .ADR1(\vga/ps2/timer_r [0]), + .ADR2(\vga/ps2/timer_r [1]), + .ADR3(\vga/ps2/timer_r [3]), + .O(\vga/ps2/_cmp_eq0001_map1047 ) + ); + defparam \vga/ps2/timer_x<0>1 .INIT = 16'h000F; + defparam \vga/ps2/timer_x<0>1 .LOC = "CLB_R11C16.S0"; + X_LUT4 \vga/ps2/timer_x<0>1 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/timer_r [0]), + .ADR3(\vga/ps2/ps2_clk_edge ), + .O(\vga/ps2/timer_x [0]) + ); + defparam \vga/ps2/timer_r<0>/XUSED .LOC = "CLB_R11C16.S0"; + X_BUF \vga/ps2/timer_r<0>/XUSED ( + .I(\vga/ps2/_cmp_eq0001_map1047 ), + .O(\vga/ps2/_cmp_eq0001_map1047_0 ) + ); + defparam \vga/ps2/timer_r_0 .LOC = "CLB_R11C16.S0"; + defparam \vga/ps2/timer_r_0 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_0 ( + .I(\vga/ps2/timer_x [0]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<0>/FFY/RST ), + .O(\vga/ps2/timer_r [0]) + ); + defparam \vga/ps2/timer_r<0>/FFY/RSTOR .LOC = "CLB_R11C16.S0"; + X_INV \vga/ps2/timer_r<0>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<0>/FFY/RST ) + ); + defparam \vga/ps2/timer_x<3>1 .INIT = 16'h00F0; + defparam \vga/ps2/timer_x<3>1 .LOC = "CLB_R9C16.S0"; + X_LUT4 \vga/ps2/timer_x<3>1 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/_addsub0000<3>_0 ), + .ADR3(\vga/ps2/ps2_clk_edge ), + .O(\vga/ps2/timer_x [3]) + ); + defparam \vga/ps2/timer_x<2>1 .INIT = 16'h00AA; + defparam \vga/ps2/timer_x<2>1 .LOC = "CLB_R9C16.S0"; + X_LUT4 \vga/ps2/timer_x<2>1 ( + .ADR0(\vga/ps2/_addsub0000<2>_0 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/ps2_clk_edge ), + .O(\vga/ps2/timer_x [2]) + ); + defparam \vga/ps2/timer_r<3>/SRMUX .LOC = "CLB_R9C16.S0"; + X_INV \vga/ps2/timer_r<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/timer_x<5>1 .INIT = 16'h00F0; + defparam \vga/ps2/timer_x<5>1 .LOC = "CLB_R8C16.S0"; + X_LUT4 \vga/ps2/timer_x<5>1 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/_addsub0000<5>_0 ), + .ADR3(\vga/ps2/ps2_clk_edge ), + .O(\vga/ps2/timer_x [5]) + ); + defparam \vga/ps2/timer_x<4>1 .INIT = 16'h00AA; + defparam \vga/ps2/timer_x<4>1 .LOC = "CLB_R8C16.S0"; + X_LUT4 \vga/ps2/timer_x<4>1 ( + .ADR0(\vga/ps2/_addsub0000<4>_0 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/ps2_clk_edge ), + .O(\vga/ps2/timer_x [4]) + ); + defparam \vga/ps2/timer_r<5>/SRMUX .LOC = "CLB_R8C16.S0"; + X_INV \vga/ps2/timer_r<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/timer_x<7>1 .INIT = 16'h2222; + defparam \vga/ps2/timer_x<7>1 .LOC = "CLB_R8C15.S1"; + X_LUT4 \vga/ps2/timer_x<7>1 ( + .ADR0(\vga/ps2/_addsub0000<7>_0 ), + .ADR1(\vga/ps2/ps2_clk_edge ), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/ps2/timer_x [7]) + ); + defparam \vga/ps2/timer_x<6>1 .INIT = 16'h5050; + defparam \vga/ps2/timer_x<6>1 .LOC = "CLB_R8C15.S1"; + X_LUT4 \vga/ps2/timer_x<6>1 ( + .ADR0(\vga/ps2/ps2_clk_edge ), + .ADR1(VCC), + .ADR2(\vga/ps2/_addsub0000<6>_0 ), + .ADR3(VCC), + .O(\vga/ps2/timer_x [6]) + ); + defparam \vga/ps2/timer_r<7>/SRMUX .LOC = "CLB_R8C15.S1"; + X_INV \vga/ps2/timer_r<7>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<7>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/timer_r_7 .LOC = "CLB_R8C15.S1"; + defparam \vga/ps2/timer_r_7 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_7 ( + .I(\vga/ps2/timer_x [7]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<7>/FFX/RST ), + .O(\vga/ps2/timer_r [7]) + ); + defparam \vga/ps2/timer_r<7>/FFX/RSTOR .LOC = "CLB_R8C15.S1"; + X_BUF \vga/ps2/timer_r<7>/FFX/RSTOR ( + .I(\vga/ps2/timer_r<7>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<7>/FFX/RST ) + ); + defparam \vga/ps2/timer_x<9>1 .INIT = 16'h0C0C; + defparam \vga/ps2/timer_x<9>1 .LOC = "CLB_R7C17.S0"; + X_LUT4 \vga/ps2/timer_x<9>1 ( + .ADR0(VCC), + .ADR1(\vga/ps2/_addsub0000<9>_0 ), + .ADR2(\vga/ps2/ps2_clk_edge ), + .ADR3(VCC), + .O(\vga/ps2/timer_x [9]) + ); + defparam \vga/ps2/timer_x<8>1 .INIT = 16'h0A0A; + defparam \vga/ps2/timer_x<8>1 .LOC = "CLB_R7C17.S0"; + X_LUT4 \vga/ps2/timer_x<8>1 ( + .ADR0(\vga/ps2/_addsub0000<8>_0 ), + .ADR1(VCC), + .ADR2(\vga/ps2/ps2_clk_edge ), + .ADR3(VCC), + .O(\vga/ps2/timer_x [8]) + ); + defparam \vga/ps2/timer_r<9>/SRMUX .LOC = "CLB_R7C17.S0"; + X_INV \vga/ps2/timer_r<9>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<9>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/write_ctrl .INIT = 16'h1144; + defparam \vga/write_ctrl .LOC = "CLB_R16C14.S1"; + X_LUT4 \vga/write_ctrl ( + .ADR0(\vga/crt/state_FFd2_12 ), + .ADR1(\vga/crt/state_FFd3_11 ), + .ADR2(VCC), + .ADR3(\vga/crt/state_FFd1_13 ), + .O(\vga/N226 ) + ); + defparam \vga/crt/write_delay__mux0000<0>1 .INIT = 16'h0010; + defparam \vga/crt/write_delay__mux0000<0>1 .LOC = "CLB_R16C14.S1"; + X_LUT4 \vga/crt/write_delay__mux0000<0>1 ( + .ADR0(\vga/crt/write_delay [0]), + .ADR1(\vga/crt/state_FFd3_11 ), + .ADR2(\vga/crt/state_FFd1_13 ), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/crt/write_delay__mux0000 [0]) + ); + defparam \vga/crt/write_delay<0>/XUSED .LOC = "CLB_R16C14.S1"; + X_BUF \vga/crt/write_delay<0>/XUSED ( + .I(\vga/N226 ), + .O(\vga/N226_0 ) + ); + defparam \vga/crt/write_delay_0 .LOC = "CLB_R16C14.S1"; + defparam \vga/crt/write_delay_0 .INIT = 1'b0; + X_FF \vga/crt/write_delay_0 ( + .I(\vga/crt/write_delay__mux0000 [0]), + .CE(VCC), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/write_delay<0>/FFY/RST ), + .O(\vga/crt/write_delay [0]) + ); + defparam \vga/crt/write_delay<0>/FFY/RSTOR .LOC = "CLB_R16C14.S1"; + X_INV \vga/crt/write_delay<0>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/write_delay<0>/FFY/RST ) + ); + defparam \vga/crt/write_delay__mux0000<2>1 .INIT = 16'h28A0; + defparam \vga/crt/write_delay__mux0000<2>1 .LOC = "CLB_R16C15.S0"; + X_LUT4 \vga/crt/write_delay__mux0000<2>1 ( + .ADR0(\vga/crt/_cmp_eq0004 ), + .ADR1(\vga/crt/write_delay [1]), + .ADR2(\vga/crt/write_delay [2]), + .ADR3(\vga/crt/write_delay [0]), + .O(\vga/crt/write_delay__mux0000 [2]) + ); + defparam \vga/crt/write_delay_2 .LOC = "CLB_R16C15.S0"; + defparam \vga/crt/write_delay_2 .INIT = 1'b0; + X_FF \vga/crt/write_delay_2 ( + .I(\vga/crt/write_delay__mux0000 [2]), + .CE(VCC), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/write_delay<2>/FFY/RST ), + .O(\vga/crt/write_delay [2]) + ); + defparam \vga/crt/write_delay<2>/FFY/RSTOR .LOC = "CLB_R16C15.S0"; + X_INV \vga/crt/write_delay<2>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/write_delay<2>/FFY/RST ) + ); + defparam \vga/_cmp_eq00001 .INIT = 16'hA000; + defparam \vga/_cmp_eq00001 .LOC = "CLB_R13C6.S0"; + X_LUT4 \vga/_cmp_eq00001 ( + .ADR0(\vga/pclk [2]), + .ADR1(VCC), + .ADR2(\vga/pclk [1]), + .ADR3(\vga/pclk [0]), + .O(\vga/_cmp_eq0000 ) + ); + defparam \vga/charload/CKINV .LOC = "CLB_R13C6.S0"; + X_INV \vga/charload/CKINV ( + .I(gray_cnt_FFd1_0), + .O(\vga/charload/CKMUXNOT ) + ); + defparam \vga/charload .LOC = "CLB_R13C6.S0"; + defparam \vga/charload .INIT = 1'b0; + X_FF \vga/charload ( + .I(\vga/_cmp_eq0000 ), + .CE(VCC), + .CLK(\vga/charload/CKMUXNOT ), + .SET(GND), + .RST(\vga/charload/FFY/RST ), + .O(\vga/charload_19 ) + ); + defparam \vga/charload/FFY/RSTOR .LOC = "CLB_R13C6.S0"; + X_INV \vga/charload/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/charload/FFY/RST ) + ); + defparam \vga/crt/_not00101 .INIT = 16'hF008; + defparam \vga/crt/_not00101 .LOC = "CLB_R15C17.S0"; + X_LUT4 \vga/crt/_not00101 ( + .ADR0(\vga/crt/state_FFd1_13 ), + .ADR1(\vga/crt/eol_0 ), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/crt/_not0010_pack_1 ) + ); + defparam \vga/crt/Mrom_set_newline1 .INIT = 16'h0040; + defparam \vga/crt/Mrom_set_newline1 .LOC = "CLB_R15C17.S0"; + X_LUT4 \vga/crt/Mrom_set_newline1 ( + .ADR0(\vga/crt/state_FFd3_11 ), + .ADR1(\vga/crt/eol_0 ), + .ADR2(\vga/crt/state_FFd1_13 ), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/crt/N3 ) + ); + defparam \vga/crt/newline/XUSED .LOC = "CLB_R15C17.S0"; + X_BUF \vga/crt/newline/XUSED ( + .I(\vga/crt/_not0010_pack_1 ), + .O(\vga/crt/_not0010 ) + ); + defparam \vga/crt/newline .LOC = "CLB_R15C17.S0"; + defparam \vga/crt/newline .INIT = 1'b0; + X_FF \vga/crt/newline ( + .I(\vga/crt/N3 ), + .CE(\vga/crt/_not0010 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/newline/FFY/RST ), + .O(\vga/crt/newline_20 ) + ); + defparam \vga/crt/newline/FFY/RSTOR .LOC = "CLB_R15C17.S0"; + X_INV \vga/crt/newline/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/newline/FFY/RST ) + ); + defparam \vga/pclk__mux0000<1>1 .INIT = 16'hFDFE; + defparam \vga/pclk__mux0000<1>1 .LOC = "CLB_R14C6.S1"; + X_LUT4 \vga/pclk__mux0000<1>1 ( + .ADR0(\vga/pclk [0]), + .ADR1(\vga/clearing ), + .ADR2(\vga/vgacore/hblank_21 ), + .ADR3(\vga/pclk [1]), + .O(\vga/pclk__mux0000 [1]) + ); + defparam \vga/pclk__mux0000<0>1 .INIT = 16'hDDFD; + defparam \vga/pclk__mux0000<0>1 .LOC = "CLB_R14C6.S1"; + X_LUT4 \vga/pclk__mux0000<0>1 ( + .ADR0(\vga/pclk [0]), + .ADR1(\vga/vgacore/hblank_21 ), + .ADR2(\vga/crt/N91 ), + .ADR3(\vga/crt/state_FFd1_13 ), + .O(\vga/pclk__mux0000 [0]) + ); + defparam \vga/pclk<1>/SRMUX .LOC = "CLB_R14C6.S1"; + X_INV \vga/pclk<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/pclk<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/cursor_h_Eqn_11 .INIT = 16'h5050; + defparam \vga/crt/cursor_h_Eqn_11 .LOC = "CLB_R18C13.S1"; + X_LUT4 \vga/crt/cursor_h_Eqn_11 ( + .ADR0(\vga/crt/_and0000_0 ), + .ADR1(VCC), + .ADR2(\vga/crt/Result<1>1_0 ), + .ADR3(VCC), + .O(\vga/crt/cursor_h_Eqn_1 ) + ); + defparam \vga/crt/cursor_h_Eqn_01 .INIT = 16'h000F; + defparam \vga/crt/cursor_h_Eqn_01 .LOC = "CLB_R18C13.S1"; + X_LUT4 \vga/crt/cursor_h_Eqn_01 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_h [0]), + .ADR3(\vga/crt/_and0000_0 ), + .O(\vga/crt/cursor_h_Eqn_0 ) + ); + defparam \vga/crt/cursor_h<1>/SRMUX .LOC = "CLB_R18C13.S1"; + X_INV \vga/crt/cursor_h<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_h<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/cursor_h_Eqn_31 .INIT = 16'h00F0; + defparam \vga/crt/cursor_h_Eqn_31 .LOC = "CLB_R17C13.S0"; + X_LUT4 \vga/crt/cursor_h_Eqn_31 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/Result<3>1_0 ), + .ADR3(\vga/crt/_and0000_0 ), + .O(\vga/crt/cursor_h_Eqn_3 ) + ); + defparam \vga/crt/cursor_h_Eqn_21 .INIT = 16'h00F0; + defparam \vga/crt/cursor_h_Eqn_21 .LOC = "CLB_R17C13.S0"; + X_LUT4 \vga/crt/cursor_h_Eqn_21 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/Result<2>1_0 ), + .ADR3(\vga/crt/_and0000_0 ), + .O(\vga/crt/cursor_h_Eqn_2 ) + ); + defparam \vga/crt/cursor_h<3>/SRMUX .LOC = "CLB_R17C13.S0"; + X_INV \vga/crt/cursor_h<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_h<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/cursor_h_Eqn_51 .INIT = 16'h3030; + defparam \vga/crt/cursor_h_Eqn_51 .LOC = "CLB_R17C14.S0"; + X_LUT4 \vga/crt/cursor_h_Eqn_51 ( + .ADR0(VCC), + .ADR1(\vga/crt/_and0000_0 ), + .ADR2(\vga/crt/Result<5>1_0 ), + .ADR3(VCC), + .O(\vga/crt/cursor_h_Eqn_5 ) + ); + defparam \vga/crt/cursor_h_Eqn_41 .INIT = 16'h2222; + defparam \vga/crt/cursor_h_Eqn_41 .LOC = "CLB_R17C14.S0"; + X_LUT4 \vga/crt/cursor_h_Eqn_41 ( + .ADR0(\vga/crt/Result<4>1_0 ), + .ADR1(\vga/crt/_and0000_0 ), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/crt/cursor_h_Eqn_4 ) + ); + defparam \vga/crt/cursor_h<5>/SRMUX .LOC = "CLB_R17C14.S0"; + X_INV \vga/crt/cursor_h<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_h<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt/cursor_h_Eqn_61 .INIT = 16'h00F0; + defparam \vga/crt/cursor_h_Eqn_61 .LOC = "CLB_R16C13.S1"; + X_LUT4 \vga/crt/cursor_h_Eqn_61 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/crt/Result<6>_0 ), + .ADR3(\vga/crt/_and0000_0 ), + .O(\vga/crt/cursor_h_Eqn_6 ) + ); + defparam \vga/crt/cursor_h_6 .LOC = "CLB_R16C13.S1"; + defparam \vga/crt/cursor_h_6 .INIT = 1'b0; + X_FF \vga/crt/cursor_h_6 ( + .I(\vga/crt/cursor_h_Eqn_6 ), + .CE(\vga/crt/_not0006_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_h<6>/FFY/RST ), + .O(\vga/crt/cursor_h [6]) + ); + defparam \vga/crt/cursor_h<6>/FFY/RSTOR .LOC = "CLB_R16C13.S1"; + X_INV \vga/crt/cursor_h<6>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/cursor_h<6>/FFY/RST ) + ); + defparam \vga/ps2/ps2_clk_r<2>/SRMUX .LOC = "CLB_R11C8.S1"; + X_INV \vga/ps2/ps2_clk_r<2>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/ps2_clk_r<2>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/ps2_clk_r_1 .LOC = "CLB_R11C8.S1"; + defparam \vga/ps2/ps2_clk_r_1 .INIT = 1'b1; + X_FF \vga/ps2/ps2_clk_r_1 ( + .I(\vga/ps2/ps2_clk_r [0]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/ps2/ps2_clk_r<2>/FFY/SET ), + .RST(GND), + .O(\vga/ps2/ps2_clk_r [1]) + ); + defparam \vga/ps2/ps2_clk_r<2>/FFY/SETOR .LOC = "CLB_R11C8.S1"; + X_BUF \vga/ps2/ps2_clk_r<2>/FFY/SETOR ( + .I(\vga/ps2/ps2_clk_r<2>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/ps2_clk_r<2>/FFY/SET ) + ); + defparam \vga/ps2/ps2_clk_r<4>/SRMUX .LOC = "CLB_R10C13.S0"; + X_INV \vga/ps2/ps2_clk_r<4>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/ps2_clk_r<4>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/ps2_clk_r_3 .LOC = "CLB_R10C13.S0"; + defparam \vga/ps2/ps2_clk_r_3 .INIT = 1'b1; + X_FF \vga/ps2/ps2_clk_r_3 ( + .I(\vga/ps2/ps2_clk_r [2]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/ps2/ps2_clk_r<4>/FFY/SET ), + .RST(GND), + .O(\vga/ps2/ps2_clk_r [3]) + ); + defparam \vga/ps2/ps2_clk_r<4>/FFY/SETOR .LOC = "CLB_R10C13.S0"; + X_BUF \vga/ps2/ps2_clk_r<4>/FFY/SETOR ( + .I(\vga/ps2/ps2_clk_r<4>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/ps2_clk_r<4>/FFY/SET ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1354 .INIT = 16'hD0C0; + defparam \vga/scancode_convert/scancode_rom/data<2>1354 .LOC = "CLB_R14C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1354 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1129 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2109 .INIT = 16'h8A00; + defparam \vga/scancode_convert/scancode_rom/data<1>2109 .LOC = "CLB_R14C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2109 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1708 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1_map1129/XUSED .LOC = "CLB_R14C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<2>1_map1129/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<2>1_map1129 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1129_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1_map1129/YUSED .LOC = "CLB_R14C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<2>1_map1129/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2_map1708 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1708_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW2 .INIT = 16'hA02A; + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW2 .LOC = "CLB_R16C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1370_SW2 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [4]), + .O(N3178) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2147 .INIT = 16'hCFCE; + defparam \vga/scancode_convert/scancode_rom/data<1>2147 .LOC = "CLB_R16C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2147 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1717 ) + ); + defparam \N3178/XUSED .LOC = "CLB_R16C36.S0"; + X_BUF \N3178/XUSED ( + .I(N3178), + .O(N3178_0) + ); + defparam \N3178/YUSED .LOC = "CLB_R16C36.S0"; + X_BUF \N3178/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2_map1717 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1717_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW1 .INIT = 16'hEC2F; + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW1 .LOC = "CLB_R13C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3852_SW1 ( + .ADR0(\vga/scancode_convert/raise ), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3136) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2184 .INIT = 16'h0F80; + defparam \vga/scancode_convert/scancode_rom/data<1>2184 .LOC = "CLB_R13C36.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>2184 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/raise ), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1729 ) + ); + defparam \N3136/XUSED .LOC = "CLB_R13C36.S0"; + X_BUF \N3136/XUSED ( + .I(N3136), + .O(N3136_0) + ); + defparam \N3136/YUSED .LOC = "CLB_R13C36.S0"; + X_BUF \N3136/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2_map1729 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1729_0 ) + ); + defparam \vga/scancode_convert/_cmp_eq00051 .INIT = 16'h1010; + defparam \vga/scancode_convert/_cmp_eq00051 .LOC = "CLB_R13C26.S1"; + X_LUT4 \vga/scancode_convert/_cmp_eq00051 ( + .ADR0(\vga/scancode_convert/hold_count [0]), + .ADR1(\vga/scancode_convert/hold_count [1]), + .ADR2(\vga/scancode_convert/hold_count [2]), + .ADR3(VCC), + .O(\vga/scancode_convert/_cmp_eq0005_pack_1 ) + ); + defparam \vga/scancode_convert/state_FFd5-In_SW0 .INIT = 16'hFCF0; + defparam \vga/scancode_convert/state_FFd5-In_SW0 .LOC = "CLB_R13C26.S1"; + X_LUT4 \vga/scancode_convert/state_FFd5-In_SW0 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/state_FFd1_34 ), + .ADR2(\vga/scancode_convert/state_FFd6_35 ), + .ADR3(\vga/scancode_convert/_cmp_eq0005 ), + .O(N124) + ); + defparam \vga/scancode_convert/_cmp_eq0005/XUSED .LOC = "CLB_R13C26.S1"; + X_BUF \vga/scancode_convert/_cmp_eq0005/XUSED ( + .I(\vga/scancode_convert/_cmp_eq0005_pack_1 ), + .O(\vga/scancode_convert/_cmp_eq0005 ) + ); + defparam \vga/scancode_convert/_cmp_eq0005/YUSED .LOC = "CLB_R13C26.S1"; + X_BUF \vga/scancode_convert/_cmp_eq0005/YUSED ( + .I(N124), + .O(N124_0) + ); + defparam \vga/crt/_not00071 .INIT = 16'hC0E0; + defparam \vga/crt/_not00071 .LOC = "CLB_R16C14.S0"; + X_LUT4 \vga/crt/_not00071 ( + .ADR0(\vga/crt/eol_0 ), + .ADR1(\vga/crt/state_FFd1_13 ), + .ADR2(\vga/crt/state_FFd2_12 ), + .ADR3(\vga/crt/state_FFd3_11 ), + .O(\vga/crt/_not0007 ) + ); + defparam \vga/crt/_not00061 .INIT = 16'hAEAC; + defparam \vga/crt/_not00061 .LOC = "CLB_R16C14.S0"; + X_LUT4 \vga/crt/_not00061 ( + .ADR0(\vga/crt/state_FFd1_13 ), + .ADR1(\vga/crt/state_FFd2_12 ), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/eol_0 ), + .O(\vga/crt/_not0006 ) + ); + defparam \vga/crt/_not0007/XUSED .LOC = "CLB_R16C14.S0"; + X_BUF \vga/crt/_not0007/XUSED ( + .I(\vga/crt/_not0007 ), + .O(\vga/crt/_not0007_0 ) + ); + defparam \vga/crt/_not0007/YUSED .LOC = "CLB_R16C14.S0"; + X_BUF \vga/crt/_not0007/YUSED ( + .I(\vga/crt/_not0006 ), + .O(\vga/crt/_not0006_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1123 .INIT = 16'hCCDC; + defparam \vga/scancode_convert/scancode_rom/data<0>1123 .LOC = "CLB_R15C33.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1123 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [3]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1449 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1308 .INIT = 16'h24FF; + defparam \vga/scancode_convert/scancode_rom/data<2>1308 .LOC = "CLB_R15C33.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1308 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1121 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1_map1449/XUSED .LOC = "CLB_R15C33.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1_map1449/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1449 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1449_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1_map1449/YUSED .LOC = "CLB_R15C33.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1_map1449/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<2>1_map1121 ), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1121_0 ) + ); + defparam \vga/crt/_and0001_SW0 .INIT = 16'hFF55; + defparam \vga/crt/_and0001_SW0 .LOC = "CLB_R15C15.S0"; + X_LUT4 \vga/crt/_and0001_SW0 ( + .ADR0(\vga/crt/state_FFd2_12 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/crt/state_FFd1_13 ), + .O(N235) + ); + defparam \vga/crt/_not00081 .INIT = 16'h0D00; + defparam \vga/crt/_not00081 .LOC = "CLB_R15C15.S0"; + X_LUT4 \vga/crt/_not00081 ( + .ADR0(\vga/crt/state_FFd3_11 ), + .ADR1(\vga/insert_crt_data ), + .ADR2(\vga/crt/state_FFd1_13 ), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/crt/_not0008 ) + ); + defparam \N235/XUSED .LOC = "CLB_R15C15.S0"; + X_BUF \N235/XUSED ( + .I(N235), + .O(N235_0) + ); + defparam \N235/YUSED .LOC = "CLB_R15C15.S0"; + X_BUF \N235/YUSED ( + .I(\vga/crt/_not0008 ), + .O(\vga/crt/_not0008_0 ) + ); + defparam \vga/char_rom/Mrom_data216 .INIT = 16'h8000; + defparam \vga/char_rom/Mrom_data216 .LOC = "CLB_R11C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data216 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N224 ) + ); + defparam \vga/char_rom/Mrom_data10 .INIT = 16'h2034; + defparam \vga/char_rom/Mrom_data10 .LOC = "CLB_R11C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data10 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N13 ) + ); + defparam \vga/N224/XUSED .LOC = "CLB_R11C5.S0"; + X_BUF \vga/N224/XUSED ( + .I(\vga/N224 ), + .O(\vga/N224_0 ) + ); + defparam \vga/N224/YUSED .LOC = "CLB_R11C5.S0"; + X_BUF \vga/N224/YUSED ( + .I(\vga/N13 ), + .O(\vga/N13_0 ) + ); + defparam \vga/char_rom/Mrom_data11 .INIT = 16'h0080; + defparam \vga/char_rom/Mrom_data11 .LOC = "CLB_R19C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data11 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N14_pack_1 ) + ); + defparam \vga/rom_addr_char<2>4 .INIT = 16'h0A00; + defparam \vga/rom_addr_char<2>4 .LOC = "CLB_R19C2.S0"; + X_LUT4 \vga/rom_addr_char<2>4 ( + .ADR0(\vga/rom_addr_char [2]), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N14 ), + .O(\vga/rom_addr_char<2>11_167 ) + ); + defparam \vga/N14/XUSED .LOC = "CLB_R19C2.S0"; + X_BUF \vga/N14/XUSED ( + .I(\vga/N14_pack_1 ), + .O(\vga/N14 ) + ); + defparam \vga/N14/YUSED .LOC = "CLB_R19C2.S0"; + X_BUF \vga/N14/YUSED ( + .I(\vga/rom_addr_char<2>11_167 ), + .O(\vga/rom_addr_char<2>11_0 ) + ); + defparam \vga/char_rom/Mrom_data214 .INIT = 16'h0004; + defparam \vga/char_rom/Mrom_data214 .LOC = "CLB_R1C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data214 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N222 ) + ); + defparam \vga/char_rom/Mrom_data20 .INIT = 16'h3BBC; + defparam \vga/char_rom/Mrom_data20 .LOC = "CLB_R1C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data20 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N23 ) + ); + defparam \vga/N222/XUSED .LOC = "CLB_R1C3.S1"; + X_BUF \vga/N222/XUSED ( + .I(\vga/N222 ), + .O(\vga/N222_0 ) + ); + defparam \vga/N222/YUSED .LOC = "CLB_R1C3.S1"; + X_BUF \vga/N222/YUSED ( + .I(\vga/N23 ), + .O(\vga/N23_0 ) + ); + defparam \vga/char_rom/Mrom_data213 .INIT = 16'h2418; + defparam \vga/char_rom/Mrom_data213 .LOC = "CLB_R13C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data213 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N221 ) + ); + defparam \vga/char_rom/Mrom_data12 .INIT = 16'h0400; + defparam \vga/char_rom/Mrom_data12 .LOC = "CLB_R13C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data12 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N15 ) + ); + defparam \vga/N221/XUSED .LOC = "CLB_R13C3.S1"; + X_BUF \vga/N221/XUSED ( + .I(\vga/N221 ), + .O(\vga/N221_0 ) + ); + defparam \vga/N221/YUSED .LOC = "CLB_R13C3.S1"; + X_BUF \vga/N221/YUSED ( + .I(\vga/N15 ), + .O(\vga/N15_0 ) + ); + defparam \vga/char_rom/Mrom_data212 .INIT = 16'h1282; + defparam \vga/char_rom/Mrom_data212 .LOC = "CLB_R3C1.S0"; + X_LUT4 \vga/char_rom/Mrom_data212 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N219 ) + ); + defparam \vga/char_rom/Mrom_data21 .INIT = 16'h2326; + defparam \vga/char_rom/Mrom_data21 .LOC = "CLB_R3C1.S0"; + X_LUT4 \vga/char_rom/Mrom_data21 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N24 ) + ); + defparam \vga/N219/XUSED .LOC = "CLB_R3C1.S0"; + X_BUF \vga/N219/XUSED ( + .I(\vga/N219 ), + .O(\vga/N219_0 ) + ); + defparam \vga/N219/YUSED .LOC = "CLB_R3C1.S0"; + X_BUF \vga/N219/YUSED ( + .I(\vga/N24 ), + .O(\vga/N24_0 ) + ); + defparam \vga/char_rom/Mrom_data211 .INIT = 16'h9C6C; + defparam \vga/char_rom/Mrom_data211 .LOC = "CLB_R2C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data211 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N218 ) + ); + defparam \vga/char_rom/Mrom_data13 .INIT = 16'h030E; + defparam \vga/char_rom/Mrom_data13 .LOC = "CLB_R2C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data13 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N16 ) + ); + defparam \vga/N218/XUSED .LOC = "CLB_R2C2.S1"; + X_BUF \vga/N218/XUSED ( + .I(\vga/N218 ), + .O(\vga/N218_0 ) + ); + defparam \vga/N218/YUSED .LOC = "CLB_R2C2.S1"; + X_BUF \vga/N218/YUSED ( + .I(\vga/N16 ), + .O(\vga/N16_0 ) + ); + defparam \vga/char_rom/Mrom_data99 .INIT = 16'h4250; + defparam \vga/char_rom/Mrom_data99 .LOC = "CLB_R10C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data99 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N104 ) + ); + defparam \vga/char_rom/Mrom_data30 .INIT = 16'h7701; + defparam \vga/char_rom/Mrom_data30 .LOC = "CLB_R10C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data30 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N33 ) + ); + defparam \vga/N104/XUSED .LOC = "CLB_R10C3.S1"; + X_BUF \vga/N104/XUSED ( + .I(\vga/N104 ), + .O(\vga/N104_0 ) + ); + defparam \vga/N104/YUSED .LOC = "CLB_R10C3.S1"; + X_BUF \vga/N104/YUSED ( + .I(\vga/N33 ), + .O(\vga/N33_0 ) + ); + defparam \vga/char_rom/Mrom_data209 .INIT = 16'h282C; + defparam \vga/char_rom/Mrom_data209 .LOC = "CLB_R2C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data209 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N216 ) + ); + defparam \vga/char_rom/Mrom_data22 .INIT = 16'h1596; + defparam \vga/char_rom/Mrom_data22 .LOC = "CLB_R2C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data22 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N25 ) + ); + defparam \vga/N216/XUSED .LOC = "CLB_R2C2.S0"; + X_BUF \vga/N216/XUSED ( + .I(\vga/N216 ), + .O(\vga/N216_0 ) + ); + defparam \vga/N216/YUSED .LOC = "CLB_R2C2.S0"; + X_BUF \vga/N216/YUSED ( + .I(\vga/N25 ), + .O(\vga/N25_0 ) + ); + defparam \vga/char_rom/Mrom_data208 .INIT = 16'h4030; + defparam \vga/char_rom/Mrom_data208 .LOC = "CLB_R3C1.S1"; + X_LUT4 \vga/char_rom/Mrom_data208 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N215 ) + ); + defparam \vga/char_rom/Mrom_data14 .INIT = 16'h0D78; + defparam \vga/char_rom/Mrom_data14 .LOC = "CLB_R3C1.S1"; + X_LUT4 \vga/char_rom/Mrom_data14 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N17 ) + ); + defparam \vga/N215/XUSED .LOC = "CLB_R3C1.S1"; + X_BUF \vga/N215/XUSED ( + .I(\vga/N215 ), + .O(\vga/N215_0 ) + ); + defparam \vga/N215/YUSED .LOC = "CLB_R3C1.S1"; + X_BUF \vga/N215/YUSED ( + .I(\vga/N17 ), + .O(\vga/N17_0 ) + ); + defparam \vga/char_rom/Mrom_data97 .INIT = 16'h4611; + defparam \vga/char_rom/Mrom_data97 .LOC = "CLB_R11C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data97 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N102 ) + ); + defparam \vga/char_rom/Mrom_data31 .INIT = 16'h7757; + defparam \vga/char_rom/Mrom_data31 .LOC = "CLB_R11C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data31 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N34 ) + ); + defparam \vga/N102/XUSED .LOC = "CLB_R11C2.S0"; + X_BUF \vga/N102/XUSED ( + .I(\vga/N102 ), + .O(\vga/N102_0 ) + ); + defparam \vga/N102/YUSED .LOC = "CLB_R11C2.S0"; + X_BUF \vga/N102/YUSED ( + .I(\vga/N34 ), + .O(\vga/N34_0 ) + ); + defparam \vga/char_rom/Mrom_data207 .INIT = 16'h64EE; + defparam \vga/char_rom/Mrom_data207 .LOC = "CLB_R1C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data207 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N214 ) + ); + defparam \vga/char_rom/Mrom_data23 .INIT = 16'h7C01; + defparam \vga/char_rom/Mrom_data23 .LOC = "CLB_R1C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data23 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N26 ) + ); + defparam \vga/N214/XUSED .LOC = "CLB_R1C3.S0"; + X_BUF \vga/N214/XUSED ( + .I(\vga/N214 ), + .O(\vga/N214_0 ) + ); + defparam \vga/N214/YUSED .LOC = "CLB_R1C3.S0"; + X_BUF \vga/N214/YUSED ( + .I(\vga/N26 ), + .O(\vga/N26_0 ) + ); + defparam \vga/char_rom/Mrom_data96 .INIT = 16'h0992; + defparam \vga/char_rom/Mrom_data96 .LOC = "CLB_R10C1.S1"; + X_LUT4 \vga/char_rom/Mrom_data96 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N101 ) + ); + defparam \vga/char_rom/Mrom_data40 .INIT = 16'hDAD8; + defparam \vga/char_rom/Mrom_data40 .LOC = "CLB_R10C1.S1"; + X_LUT4 \vga/char_rom/Mrom_data40 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N43 ) + ); + defparam \vga/N101/XUSED .LOC = "CLB_R10C1.S1"; + X_BUF \vga/N101/XUSED ( + .I(\vga/N101 ), + .O(\vga/N101_0 ) + ); + defparam \vga/N101/YUSED .LOC = "CLB_R10C1.S1"; + X_BUF \vga/N101/YUSED ( + .I(\vga/N43 ), + .O(\vga/N43_0 ) + ); + defparam \vga/char_rom/Mrom_data94 .INIT = 16'h4EED; + defparam \vga/char_rom/Mrom_data94 .LOC = "CLB_R11C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data94 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N99 ) + ); + defparam \vga/char_rom/Mrom_data32 .INIT = 16'h0675; + defparam \vga/char_rom/Mrom_data32 .LOC = "CLB_R11C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data32 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N35 ) + ); + defparam \vga/N99/XUSED .LOC = "CLB_R11C2.S1"; + X_BUF \vga/N99/XUSED ( + .I(\vga/N99 ), + .O(\vga/N99_0 ) + ); + defparam \vga/N99/YUSED .LOC = "CLB_R11C2.S1"; + X_BUF \vga/N99/YUSED ( + .I(\vga/N35 ), + .O(\vga/N35_0 ) + ); + defparam \vga/char_rom/Mrom_data206 .INIT = 16'h1FD0; + defparam \vga/char_rom/Mrom_data206 .LOC = "CLB_R6C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data206 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N213 ) + ); + defparam \vga/char_rom/Mrom_data24 .INIT = 16'h070F; + defparam \vga/char_rom/Mrom_data24 .LOC = "CLB_R6C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data24 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N27 ) + ); + defparam \vga/N213/XUSED .LOC = "CLB_R6C3.S1"; + X_BUF \vga/N213/XUSED ( + .I(\vga/N213 ), + .O(\vga/N213_0 ) + ); + defparam \vga/N213/YUSED .LOC = "CLB_R6C3.S1"; + X_BUF \vga/N213/YUSED ( + .I(\vga/N27 ), + .O(\vga/N27_0 ) + ); + defparam \vga/char_rom/Mrom_data93 .INIT = 16'h1280; + defparam \vga/char_rom/Mrom_data93 .LOC = "CLB_R8C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data93 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N98 ) + ); + defparam \vga/char_rom/Mrom_data41 .INIT = 16'h0480; + defparam \vga/char_rom/Mrom_data41 .LOC = "CLB_R8C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data41 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N44 ) + ); + defparam \vga/N98/XUSED .LOC = "CLB_R8C2.S1"; + X_BUF \vga/N98/XUSED ( + .I(\vga/N98 ), + .O(\vga/N98_0 ) + ); + defparam \vga/N98/YUSED .LOC = "CLB_R8C2.S1"; + X_BUF \vga/N98/YUSED ( + .I(\vga/N44 ), + .O(\vga/N44_0 ) + ); + defparam \vga/char_rom/Mrom_data201 .INIT = 16'h5B3B; + defparam \vga/char_rom/Mrom_data201 .LOC = "CLB_R2C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data201 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N208 ) + ); + defparam \vga/char_rom/Mrom_data25 .INIT = 16'h1597; + defparam \vga/char_rom/Mrom_data25 .LOC = "CLB_R2C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data25 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N28 ) + ); + defparam \vga/N208/XUSED .LOC = "CLB_R2C3.S1"; + X_BUF \vga/N208/XUSED ( + .I(\vga/N208 ), + .O(\vga/N208_0 ) + ); + defparam \vga/N208/YUSED .LOC = "CLB_R2C3.S1"; + X_BUF \vga/N208/YUSED ( + .I(\vga/N28 ), + .O(\vga/N28_0 ) + ); + defparam \vga/char_rom/Mrom_data198 .INIT = 16'h0071; + defparam \vga/char_rom/Mrom_data198 .LOC = "CLB_R4C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data198 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N205 ) + ); + defparam \vga/char_rom/Mrom_data17 .INIT = 16'h07BC; + defparam \vga/char_rom/Mrom_data17 .LOC = "CLB_R4C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data17 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N20 ) + ); + defparam \vga/N205/XUSED .LOC = "CLB_R4C2.S0"; + X_BUF \vga/N205/XUSED ( + .I(\vga/N205 ), + .O(\vga/N205_0 ) + ); + defparam \vga/N205/YUSED .LOC = "CLB_R4C2.S0"; + X_BUF \vga/N205/YUSED ( + .I(\vga/N20 ), + .O(\vga/N20_0 ) + ); + defparam \vga/char_rom/Mrom_data91 .INIT = 16'h46C9; + defparam \vga/char_rom/Mrom_data91 .LOC = "CLB_R11C7.S0"; + X_LUT4 \vga/char_rom/Mrom_data91 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N96 ) + ); + defparam \vga/char_rom/Mrom_data50 .INIT = 16'h0B01; + defparam \vga/char_rom/Mrom_data50 .LOC = "CLB_R11C7.S0"; + X_LUT4 \vga/char_rom/Mrom_data50 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N54 ) + ); + defparam \vga/N96/XUSED .LOC = "CLB_R11C7.S0"; + X_BUF \vga/N96/XUSED ( + .I(\vga/N96 ), + .O(\vga/N96_0 ) + ); + defparam \vga/N96/YUSED .LOC = "CLB_R11C7.S0"; + X_BUF \vga/N96/YUSED ( + .I(\vga/N54 ), + .O(\vga/N54_0 ) + ); + defparam \vga/char_rom/Mrom_data90 .INIT = 16'h0345; + defparam \vga/char_rom/Mrom_data90 .LOC = "CLB_R7C1.S0"; + X_LUT4 \vga/char_rom/Mrom_data90 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N95 ) + ); + defparam \vga/char_rom/Mrom_data42 .INIT = 16'h31CC; + defparam \vga/char_rom/Mrom_data42 .LOC = "CLB_R7C1.S0"; + X_LUT4 \vga/char_rom/Mrom_data42 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N45 ) + ); + defparam \vga/N95/XUSED .LOC = "CLB_R7C1.S0"; + X_BUF \vga/N95/XUSED ( + .I(\vga/N95 ), + .O(\vga/N95_0 ) + ); + defparam \vga/N95/YUSED .LOC = "CLB_R7C1.S0"; + X_BUF \vga/N95/YUSED ( + .I(\vga/N45 ), + .O(\vga/N45_0 ) + ); + defparam \vga/char_rom/Mrom_data89 .INIT = 16'h1B3B; + defparam \vga/char_rom/Mrom_data89 .LOC = "CLB_R9C1.S1"; + X_LUT4 \vga/char_rom/Mrom_data89 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N94 ) + ); + defparam \vga/char_rom/Mrom_data34 .INIT = 16'h8010; + defparam \vga/char_rom/Mrom_data34 .LOC = "CLB_R9C1.S1"; + X_LUT4 \vga/char_rom/Mrom_data34 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N37 ) + ); + defparam \vga/N94/XUSED .LOC = "CLB_R9C1.S1"; + X_BUF \vga/N94/XUSED ( + .I(\vga/N94 ), + .O(\vga/N94_0 ) + ); + defparam \vga/N94/YUSED .LOC = "CLB_R9C1.S1"; + X_BUF \vga/N94/YUSED ( + .I(\vga/N37 ), + .O(\vga/N37_0 ) + ); + defparam \vga/char_rom/Mrom_data28 .INIT = 16'h3E12; + defparam \vga/char_rom/Mrom_data28 .LOC = "CLB_R5C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data28 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N31 ) + ); + defparam \vga/char_rom/Mrom_data26 .INIT = 16'h7F08; + defparam \vga/char_rom/Mrom_data26 .LOC = "CLB_R5C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data26 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N29 ) + ); + defparam \vga/N31/XUSED .LOC = "CLB_R5C2.S0"; + X_BUF \vga/N31/XUSED ( + .I(\vga/N31 ), + .O(\vga/N31_0 ) + ); + defparam \vga/N31/YUSED .LOC = "CLB_R5C2.S0"; + X_BUF \vga/N31/YUSED ( + .I(\vga/N29 ), + .O(\vga/N29_0 ) + ); + defparam \vga/char_rom/Mrom_data194 .INIT = 16'h17F3; + defparam \vga/char_rom/Mrom_data194 .LOC = "CLB_R4C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data194 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N201 ) + ); + defparam \vga/char_rom/Mrom_data18 .INIT = 16'h1080; + defparam \vga/char_rom/Mrom_data18 .LOC = "CLB_R4C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data18 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N21 ) + ); + defparam \vga/N201/XUSED .LOC = "CLB_R4C2.S1"; + X_BUF \vga/N201/XUSED ( + .I(\vga/N201 ), + .O(\vga/N201_0 ) + ); + defparam \vga/N201/YUSED .LOC = "CLB_R4C2.S1"; + X_BUF \vga/N201/YUSED ( + .I(\vga/N21 ), + .O(\vga/N21_0 ) + ); + defparam \vga/pixel<8>27 .INIT = 16'h00A0; + defparam \vga/pixel<8>27 .LOC = "CLB_R15C8.S0"; + X_LUT4 \vga/pixel<8>27 ( + .ADR0(\vga/pixelData [0]), + .ADR1(VCC), + .ADR2(\vga/pixel<8>_map785_0 ), + .ADR3(\vga/vgacore/hblank_21 ), + .O(pixel[8]) + ); + defparam \pixel<8>/YUSED .LOC = "CLB_R15C8.S0"; + X_BUF \pixel<8>/YUSED ( + .I(pixel[8]), + .O(\pixel<8>_0 ) + ); + defparam \vga/rom_addr_char<1>114_SW0 .INIT = 16'hE788; + defparam \vga/rom_addr_char<1>114_SW0 .LOC = "CLB_R10C1.S0"; + X_LUT4 \vga/rom_addr_char<1>114_SW0 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char [1]), + .O(N3166) + ); + defparam \vga/char_rom/Mrom_data51 .INIT = 16'h30C3; + defparam \vga/char_rom/Mrom_data51 .LOC = "CLB_R10C1.S0"; + X_LUT4 \vga/char_rom/Mrom_data51 ( + .ADR0(VCC), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N55 ) + ); + defparam \N3166/XUSED .LOC = "CLB_R10C1.S0"; + X_BUF \N3166/XUSED ( + .I(N3166), + .O(N3166_0) + ); + defparam \N3166/YUSED .LOC = "CLB_R10C1.S0"; + X_BUF \N3166/YUSED ( + .I(\vga/N55 ), + .O(\vga/N55_0 ) + ); + defparam \vga/char_rom/Mrom_data86 .INIT = 16'h0001; + defparam \vga/char_rom/Mrom_data86 .LOC = "CLB_R21C6.S0"; + X_LUT4 \vga/char_rom/Mrom_data86 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N90 ) + ); + defparam \vga/char_rom/Mrom_data43 .INIT = 16'h1020; + defparam \vga/char_rom/Mrom_data43 .LOC = "CLB_R21C6.S0"; + X_LUT4 \vga/char_rom/Mrom_data43 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N47 ) + ); + defparam \vga/N90/XUSED .LOC = "CLB_R21C6.S0"; + X_BUF \vga/N90/XUSED ( + .I(\vga/N90 ), + .O(\vga/N90_0 ) + ); + defparam \vga/N90/YUSED .LOC = "CLB_R21C6.S0"; + X_BUF \vga/N90/YUSED ( + .I(\vga/N47 ), + .O(\vga/N47_0 ) + ); + defparam \vga/char_rom/Mrom_data85 .INIT = 16'h0AA8; + defparam \vga/char_rom/Mrom_data85 .LOC = "CLB_R21C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data85 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N89 ) + ); + defparam \vga/char_rom/Mrom_data35 .INIT = 16'h60A0; + defparam \vga/char_rom/Mrom_data35 .LOC = "CLB_R21C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data35 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N38 ) + ); + defparam \vga/N89/XUSED .LOC = "CLB_R21C5.S0"; + X_BUF \vga/N89/XUSED ( + .I(\vga/N89 ), + .O(\vga/N89_0 ) + ); + defparam \vga/N89/YUSED .LOC = "CLB_R21C5.S0"; + X_BUF \vga/N89/YUSED ( + .I(\vga/N38 ), + .O(\vga/N38_0 ) + ); + defparam \vga/rom_addr_char<1>6_SW0 .INIT = 16'h9873; + defparam \vga/rom_addr_char<1>6_SW0 .LOC = "CLB_R2C3.S0"; + X_LUT4 \vga/rom_addr_char<1>6_SW0 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(N3146) + ); + defparam \vga/char_rom/Mrom_data27 .INIT = 16'h57FB; + defparam \vga/char_rom/Mrom_data27 .LOC = "CLB_R2C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data27 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N30 ) + ); + defparam \N3146/XUSED .LOC = "CLB_R2C3.S0"; + X_BUF \N3146/XUSED ( + .I(N3146), + .O(N3146_0) + ); + defparam \N3146/YUSED .LOC = "CLB_R2C3.S0"; + X_BUF \N3146/YUSED ( + .I(\vga/N30 ), + .O(\vga/N30_0 ) + ); + defparam \vga/char_rom/Mrom_data187 .INIT = 16'h4220; + defparam \vga/char_rom/Mrom_data187 .LOC = "CLB_R8C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data187 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N194 ) + ); + defparam \vga/char_rom/Mrom_data19 .INIT = 16'h0068; + defparam \vga/char_rom/Mrom_data19 .LOC = "CLB_R8C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data19 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N22 ) + ); + defparam \vga/N194/XUSED .LOC = "CLB_R8C3.S0"; + X_BUF \vga/N194/XUSED ( + .I(\vga/N194 ), + .O(\vga/N194_0 ) + ); + defparam \vga/N194/YUSED .LOC = "CLB_R8C3.S0"; + X_BUF \vga/N194/YUSED ( + .I(\vga/N22 ), + .O(\vga/N22_0 ) + ); + defparam \vga/char_rom/Mrom_data84 .INIT = 16'h1D02; + defparam \vga/char_rom/Mrom_data84 .LOC = "CLB_R25C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data84 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N88 ) + ); + defparam \vga/char_rom/Mrom_data60 .INIT = 16'h6211; + defparam \vga/char_rom/Mrom_data60 .LOC = "CLB_R25C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data60 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N64 ) + ); + defparam \vga/N88/XUSED .LOC = "CLB_R25C18.S0"; + X_BUF \vga/N88/XUSED ( + .I(\vga/N88 ), + .O(\vga/N88_0 ) + ); + defparam \vga/N88/YUSED .LOC = "CLB_R25C18.S0"; + X_BUF \vga/N88/YUSED ( + .I(\vga/N64 ), + .O(\vga/N64_0 ) + ); + defparam \vga/char_rom/Mrom_data83 .INIT = 16'h36CC; + defparam \vga/char_rom/Mrom_data83 .LOC = "CLB_R23C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data83 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N87 ) + ); + defparam \vga/char_rom/Mrom_data52 .INIT = 16'h497F; + defparam \vga/char_rom/Mrom_data52 .LOC = "CLB_R23C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data52 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N56 ) + ); + defparam \vga/N87/XUSED .LOC = "CLB_R23C11.S0"; + X_BUF \vga/N87/XUSED ( + .I(\vga/N87 ), + .O(\vga/N87_0 ) + ); + defparam \vga/N87/YUSED .LOC = "CLB_R23C11.S0"; + X_BUF \vga/N87/YUSED ( + .I(\vga/N56 ), + .O(\vga/N56_0 ) + ); + defparam \vga/char_rom/Mrom_data82 .INIT = 16'h6020; + defparam \vga/char_rom/Mrom_data82 .LOC = "CLB_R24C8.S1"; + X_LUT4 \vga/char_rom/Mrom_data82 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N86 ) + ); + defparam \vga/char_rom/Mrom_data44 .INIT = 16'h7E13; + defparam \vga/char_rom/Mrom_data44 .LOC = "CLB_R24C8.S1"; + X_LUT4 \vga/char_rom/Mrom_data44 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N48 ) + ); + defparam \vga/N86/XUSED .LOC = "CLB_R24C8.S1"; + X_BUF \vga/N86/XUSED ( + .I(\vga/N86 ), + .O(\vga/N86_0 ) + ); + defparam \vga/N86/YUSED .LOC = "CLB_R24C8.S1"; + X_BUF \vga/N86/YUSED ( + .I(\vga/N48 ), + .O(\vga/N48_0 ) + ); + defparam \vga/char_rom/Mrom_data81 .INIT = 16'h7A42; + defparam \vga/char_rom/Mrom_data81 .LOC = "CLB_R21C6.S1"; + X_LUT4 \vga/char_rom/Mrom_data81 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N85 ) + ); + defparam \vga/char_rom/Mrom_data36 .INIT = 16'h4588; + defparam \vga/char_rom/Mrom_data36 .LOC = "CLB_R21C6.S1"; + X_LUT4 \vga/char_rom/Mrom_data36 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N39 ) + ); + defparam \vga/N85/XUSED .LOC = "CLB_R21C6.S1"; + X_BUF \vga/N85/XUSED ( + .I(\vga/N85 ), + .O(\vga/N85_0 ) + ); + defparam \vga/N85/YUSED .LOC = "CLB_R21C6.S1"; + X_BUF \vga/N85/YUSED ( + .I(\vga/N39 ), + .O(\vga/N39_0 ) + ); + defparam \vga/char_rom/Mrom_data79 .INIT = 16'h560C; + defparam \vga/char_rom/Mrom_data79 .LOC = "CLB_R26C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data79 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N83 ) + ); + defparam \vga/char_rom/Mrom_data61 .INIT = 16'h0940; + defparam \vga/char_rom/Mrom_data61 .LOC = "CLB_R26C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data61 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N65 ) + ); + defparam \vga/N83/XUSED .LOC = "CLB_R26C18.S0"; + X_BUF \vga/N83/XUSED ( + .I(\vga/N83 ), + .O(\vga/N83_0 ) + ); + defparam \vga/N83/YUSED .LOC = "CLB_R26C18.S0"; + X_BUF \vga/N83/YUSED ( + .I(\vga/N65 ), + .O(\vga/N65_0 ) + ); + defparam \vga/char_rom/Mrom_data78 .INIT = 16'h1040; + defparam \vga/char_rom/Mrom_data78 .LOC = "CLB_R26C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data78 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N82 ) + ); + defparam \vga/char_rom/Mrom_data53 .INIT = 16'h1161; + defparam \vga/char_rom/Mrom_data53 .LOC = "CLB_R26C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data53 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N57 ) + ); + defparam \vga/N82/XUSED .LOC = "CLB_R26C11.S0"; + X_BUF \vga/N82/XUSED ( + .I(\vga/N82 ), + .O(\vga/N82_0 ) + ); + defparam \vga/N82/YUSED .LOC = "CLB_R26C11.S0"; + X_BUF \vga/N82/YUSED ( + .I(\vga/N57 ), + .O(\vga/N57_0 ) + ); + defparam \vga/char_rom/Mrom_data77 .INIT = 16'h447D; + defparam \vga/char_rom/Mrom_data77 .LOC = "CLB_R26C7.S1"; + X_LUT4 \vga/char_rom/Mrom_data77 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N81 ) + ); + defparam \vga/char_rom/Mrom_data45 .INIT = 16'h3058; + defparam \vga/char_rom/Mrom_data45 .LOC = "CLB_R26C7.S1"; + X_LUT4 \vga/char_rom/Mrom_data45 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N49 ) + ); + defparam \vga/N81/XUSED .LOC = "CLB_R26C7.S1"; + X_BUF \vga/N81/XUSED ( + .I(\vga/N81 ), + .O(\vga/N81_0 ) + ); + defparam \vga/N81/YUSED .LOC = "CLB_R26C7.S1"; + X_BUF \vga/N81/YUSED ( + .I(\vga/N49 ), + .O(\vga/N49_0 ) + ); + defparam \vga/char_rom/Mrom_data76 .INIT = 16'h14D0; + defparam \vga/char_rom/Mrom_data76 .LOC = "CLB_R26C6.S1"; + X_LUT4 \vga/char_rom/Mrom_data76 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N80 ) + ); + defparam \vga/char_rom/Mrom_data37 .INIT = 16'h1B33; + defparam \vga/char_rom/Mrom_data37 .LOC = "CLB_R26C6.S1"; + X_LUT4 \vga/char_rom/Mrom_data37 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N40 ) + ); + defparam \vga/N80/XUSED .LOC = "CLB_R26C6.S1"; + X_BUF \vga/N80/XUSED ( + .I(\vga/N80 ), + .O(\vga/N80_0 ) + ); + defparam \vga/N80/YUSED .LOC = "CLB_R26C6.S1"; + X_BUF \vga/N80/YUSED ( + .I(\vga/N40 ), + .O(\vga/N40_0 ) + ); + defparam \vga/char_rom/Mrom_data75 .INIT = 16'h9481; + defparam \vga/char_rom/Mrom_data75 .LOC = "CLB_R21C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data75 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N79 ) + ); + defparam \vga/char_rom/Mrom_data29 .INIT = 16'h0F58; + defparam \vga/char_rom/Mrom_data29 .LOC = "CLB_R21C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data29 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N32 ) + ); + defparam \vga/N79/XUSED .LOC = "CLB_R21C2.S0"; + X_BUF \vga/N79/XUSED ( + .I(\vga/N79 ), + .O(\vga/N79_0 ) + ); + defparam \vga/N79/YUSED .LOC = "CLB_R21C2.S0"; + X_BUF \vga/N79/YUSED ( + .I(\vga/N32 ), + .O(\vga/N32_0 ) + ); + defparam \vga/rom_addr_char<2>15_SW0 .INIT = 16'hE50F; + defparam \vga/rom_addr_char<2>15_SW0 .LOC = "CLB_R14C2.S1"; + X_LUT4 \vga/rom_addr_char<2>15_SW0 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(N3162_pack_1) + ); + defparam \vga/rom_addr_char<2>15 .INIT = 16'h00C0; + defparam \vga/rom_addr_char<2>15 .LOC = "CLB_R14C2.S1"; + X_LUT4 \vga/rom_addr_char<2>15 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/rom_addr_char [2]), + .ADR3(N3162), + .O(\vga/rom_addr_char<2>2 ) + ); + defparam \N3162/XUSED .LOC = "CLB_R14C2.S1"; + X_BUF \N3162/XUSED ( + .I(N3162_pack_1), + .O(N3162) + ); + defparam \N3162/YUSED .LOC = "CLB_R14C2.S1"; + X_BUF \N3162/YUSED ( + .I(\vga/rom_addr_char<2>2 ), + .O(\vga/rom_addr_char<2>2_0 ) + ); + defparam \vga/char_rom/Mrom_data74 .INIT = 16'h00EC; + defparam \vga/char_rom/Mrom_data74 .LOC = "CLB_R27C8.S0"; + X_LUT4 \vga/char_rom/Mrom_data74 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N78 ) + ); + defparam \vga/char_rom/Mrom_data70 .INIT = 16'h4CCE; + defparam \vga/char_rom/Mrom_data70 .LOC = "CLB_R27C8.S0"; + X_LUT4 \vga/char_rom/Mrom_data70 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N74 ) + ); + defparam \vga/N78/XUSED .LOC = "CLB_R27C8.S0"; + X_BUF \vga/N78/XUSED ( + .I(\vga/N78 ), + .O(\vga/N78_0 ) + ); + defparam \vga/N78/YUSED .LOC = "CLB_R27C8.S0"; + X_BUF \vga/N78/YUSED ( + .I(\vga/N74 ), + .O(\vga/N74_0 ) + ); + defparam \vga/char_rom/Mrom_data71 .INIT = 16'h8002; + defparam \vga/char_rom/Mrom_data71 .LOC = "CLB_R27C18.S1"; + X_LUT4 \vga/char_rom/Mrom_data71 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N75 ) + ); + defparam \vga/char_rom/Mrom_data62 .INIT = 16'h1088; + defparam \vga/char_rom/Mrom_data62 .LOC = "CLB_R27C18.S1"; + X_LUT4 \vga/char_rom/Mrom_data62 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N66 ) + ); + defparam \vga/N75/XUSED .LOC = "CLB_R27C18.S1"; + X_BUF \vga/N75/XUSED ( + .I(\vga/N75 ), + .O(\vga/N75_0 ) + ); + defparam \vga/N75/YUSED .LOC = "CLB_R27C18.S1"; + X_BUF \vga/N75/YUSED ( + .I(\vga/N66 ), + .O(\vga/N66_0 ) + ); + defparam \vga/char_rom/Mrom_data69 .INIT = 16'h3007; + defparam \vga/char_rom/Mrom_data69 .LOC = "CLB_R25C11.S1"; + X_LUT4 \vga/char_rom/Mrom_data69 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N73 ) + ); + defparam \vga/char_rom/Mrom_data54 .INIT = 16'h24C3; + defparam \vga/char_rom/Mrom_data54 .LOC = "CLB_R25C11.S1"; + X_LUT4 \vga/char_rom/Mrom_data54 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N58 ) + ); + defparam \vga/N73/XUSED .LOC = "CLB_R25C11.S1"; + X_BUF \vga/N73/XUSED ( + .I(\vga/N73 ), + .O(\vga/N73_0 ) + ); + defparam \vga/N73/YUSED .LOC = "CLB_R25C11.S1"; + X_BUF \vga/N73/YUSED ( + .I(\vga/N58 ), + .O(\vga/N58_0 ) + ); + defparam \vga/char_rom/Mrom_data68 .INIT = 16'h2006; + defparam \vga/char_rom/Mrom_data68 .LOC = "CLB_R27C6.S0"; + X_LUT4 \vga/char_rom/Mrom_data68 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N72 ) + ); + defparam \vga/char_rom/Mrom_data46 .INIT = 16'h0508; + defparam \vga/char_rom/Mrom_data46 .LOC = "CLB_R27C6.S0"; + X_LUT4 \vga/char_rom/Mrom_data46 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N50 ) + ); + defparam \vga/N72/XUSED .LOC = "CLB_R27C6.S0"; + X_BUF \vga/N72/XUSED ( + .I(\vga/N72 ), + .O(\vga/N72_0 ) + ); + defparam \vga/N72/YUSED .LOC = "CLB_R27C6.S0"; + X_BUF \vga/N72/YUSED ( + .I(\vga/N50 ), + .O(\vga/N50_0 ) + ); + defparam \vga/char_rom/Mrom_data67 .INIT = 16'h2008; + defparam \vga/char_rom/Mrom_data67 .LOC = "CLB_R21C8.S0"; + X_LUT4 \vga/char_rom/Mrom_data67 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N71 ) + ); + defparam \vga/char_rom/Mrom_data38 .INIT = 16'h2AA0; + defparam \vga/char_rom/Mrom_data38 .LOC = "CLB_R21C8.S0"; + X_LUT4 \vga/char_rom/Mrom_data38 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N41 ) + ); + defparam \vga/N71/XUSED .LOC = "CLB_R21C8.S0"; + X_BUF \vga/N71/XUSED ( + .I(\vga/N71 ), + .O(\vga/N71_0 ) + ); + defparam \vga/N71/YUSED .LOC = "CLB_R21C8.S0"; + X_BUF \vga/N71/YUSED ( + .I(\vga/N41 ), + .O(\vga/N41_0 ) + ); + defparam \vga/char_rom/Mrom_data66 .INIT = 16'h2001; + defparam \vga/char_rom/Mrom_data66 .LOC = "CLB_R28C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data66 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N70 ) + ); + defparam \vga/char_rom/Mrom_data63 .INIT = 16'h1008; + defparam \vga/char_rom/Mrom_data63 .LOC = "CLB_R28C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data63 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N67 ) + ); + defparam \vga/N70/XUSED .LOC = "CLB_R28C18.S0"; + X_BUF \vga/N70/XUSED ( + .I(\vga/N70 ), + .O(\vga/N70_0 ) + ); + defparam \vga/N70/YUSED .LOC = "CLB_R28C18.S0"; + X_BUF \vga/N70/YUSED ( + .I(\vga/N67 ), + .O(\vga/N67_0 ) + ); + defparam \vga/char_rom/Mrom_data65 .INIT = 16'h09A5; + defparam \vga/char_rom/Mrom_data65 .LOC = "CLB_R26C11.S1"; + X_LUT4 \vga/char_rom/Mrom_data65 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N69 ) + ); + defparam \vga/char_rom/Mrom_data55 .INIT = 16'h2049; + defparam \vga/char_rom/Mrom_data55 .LOC = "CLB_R26C11.S1"; + X_LUT4 \vga/char_rom/Mrom_data55 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N59 ) + ); + defparam \vga/N69/XUSED .LOC = "CLB_R26C11.S1"; + X_BUF \vga/N69/XUSED ( + .I(\vga/N69 ), + .O(\vga/N69_0 ) + ); + defparam \vga/N69/YUSED .LOC = "CLB_R26C11.S1"; + X_BUF \vga/N69/YUSED ( + .I(\vga/N59 ), + .O(\vga/N59_0 ) + ); + defparam \vga/char_rom/Mrom_data59 .INIT = 16'h2909; + defparam \vga/char_rom/Mrom_data59 .LOC = "CLB_R27C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data59 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N63 ) + ); + defparam \vga/char_rom/Mrom_data64 .INIT = 16'h4025; + defparam \vga/char_rom/Mrom_data64 .LOC = "CLB_R27C18.S0"; + X_LUT4 \vga/char_rom/Mrom_data64 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N68 ) + ); + defparam \vga/N63/XUSED .LOC = "CLB_R27C18.S0"; + X_BUF \vga/N63/XUSED ( + .I(\vga/N63 ), + .O(\vga/N63_0 ) + ); + defparam \vga/N63/YUSED .LOC = "CLB_R27C18.S0"; + X_BUF \vga/N63/YUSED ( + .I(\vga/N68 ), + .O(\vga/N68_0 ) + ); + defparam \vga/char_rom/Mrom_data58 .INIT = 16'h0929; + defparam \vga/char_rom/Mrom_data58 .LOC = "CLB_R25C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data58 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N62 ) + ); + defparam \vga/char_rom/Mrom_data56 .INIT = 16'h2106; + defparam \vga/char_rom/Mrom_data56 .LOC = "CLB_R25C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data56 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N60 ) + ); + defparam \vga/N62/XUSED .LOC = "CLB_R25C11.S0"; + X_BUF \vga/N62/XUSED ( + .I(\vga/N62 ), + .O(\vga/N62_0 ) + ); + defparam \vga/N62/YUSED .LOC = "CLB_R25C11.S0"; + X_BUF \vga/N62/YUSED ( + .I(\vga/N60 ), + .O(\vga/N60_0 ) + ); + defparam \vga/rom_addr_char<2>2_SW0 .INIT = 16'hFDAF; + defparam \vga/rom_addr_char<2>2_SW0 .LOC = "CLB_R20C11.S1"; + X_LUT4 \vga/rom_addr_char<2>2_SW0 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(N3164) + ); + defparam \vga/char_rom/Mrom_data57 .INIT = 16'h030F; + defparam \vga/char_rom/Mrom_data57 .LOC = "CLB_R20C11.S1"; + X_LUT4 \vga/char_rom/Mrom_data57 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N61 ) + ); + defparam \N3164/XUSED .LOC = "CLB_R20C11.S1"; + X_BUF \N3164/XUSED ( + .I(N3164), + .O(N3164_0) + ); + defparam \N3164/YUSED .LOC = "CLB_R20C11.S1"; + X_BUF \N3164/YUSED ( + .I(\vga/N61 ), + .O(\vga/N61_0 ) + ); + defparam \vga/char_rom/Mrom_data8 .INIT = 16'h17C0; + defparam \vga/char_rom/Mrom_data8 .LOC = "CLB_R24C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data8 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N11 ) + ); + defparam \vga/char_rom/Mrom_data49 .INIT = 16'h0040; + defparam \vga/char_rom/Mrom_data49 .LOC = "CLB_R24C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data49 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt_1_1_8 ), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_0_1_17 ), + .O(\vga/N53 ) + ); + defparam \vga/N11/XUSED .LOC = "CLB_R24C5.S0"; + X_BUF \vga/N11/XUSED ( + .I(\vga/N11 ), + .O(\vga/N11_0 ) + ); + defparam \vga/N11/YUSED .LOC = "CLB_R24C5.S0"; + X_BUF \vga/N11/YUSED ( + .I(\vga/N53 ), + .O(\vga/N53_0 ) + ); + defparam \vga/scancode_convert/ctrl_set_SW1 .INIT = 16'hBBFF; + defparam \vga/scancode_convert/ctrl_set_SW1 .LOC = "CLB_R12C32.S1"; + X_LUT4 \vga/scancode_convert/ctrl_set_SW1 ( + .ADR0(\vga/scancode_convert/release_prefix_26 ), + .ADR1(\vga/ps2/rdy_r_1 ), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/state_FFd5_31 ), + .O(N3158_pack_1) + ); + defparam \vga/scancode_convert/ctrl_set .INIT = 16'h0040; + defparam \vga/scancode_convert/ctrl_set .LOC = "CLB_R12C32.S1"; + X_LUT4 \vga/scancode_convert/ctrl_set ( + .ADR0(\vga/ps2/sc_r [1]), + .ADR1(\vga/ps2/sc_r [2]), + .ADR2(\vga/scancode_convert/N10_0 ), + .ADR3(N3158), + .O(\vga/scancode_convert/ctrl_set_168 ) + ); + defparam \vga/scancode_convert/ctrl/XUSED .LOC = "CLB_R12C32.S1"; + X_BUF \vga/scancode_convert/ctrl/XUSED ( + .I(N3158_pack_1), + .O(N3158) + ); + defparam \vga/scancode_convert/ctrl .LOC = "CLB_R12C32.S1"; + defparam \vga/scancode_convert/ctrl .INIT = 1'b0; + X_FF \vga/scancode_convert/ctrl ( + .I(\vga/scancode_convert/ctrl_set_168 ), + .CE(\vga/scancode_convert/_not0009_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/ctrl/FFY/RST ), + .O(\vga/scancode_convert/ctrl_22 ) + ); + defparam \vga/scancode_convert/ctrl/FFY/RSTOR .LOC = "CLB_R12C32.S1"; + X_INV \vga/scancode_convert/ctrl/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/ctrl/FFY/RST ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1180_SW1 .INIT = 16'hED4B; + defparam \vga/scancode_convert/scancode_rom/data<2>1180_SW1 .LOC = "CLB_R10C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1180_SW1 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [2]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(N3142) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1118 .INIT = 16'hCDCC; + defparam \vga/scancode_convert/scancode_rom/data<4>1118 .LOC = "CLB_R10C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1118 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [4]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1565 ) + ); + defparam \N3142/XUSED .LOC = "CLB_R10C37.S0"; + X_BUF \N3142/XUSED ( + .I(N3142), + .O(N3142_0) + ); + defparam \N3142/YUSED .LOC = "CLB_R10C37.S0"; + X_BUF \N3142/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<4>1_map1565 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1565_0 ) + ); + defparam \vga/char_rom/Mrom_data186 .INIT = 16'h114E; + defparam \vga/char_rom/Mrom_data186 .LOC = "CLB_R15C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data186 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N193 ) + ); + defparam \vga/char_rom/Mrom_data100 .INIT = 16'h2686; + defparam \vga/char_rom/Mrom_data100 .LOC = "CLB_R15C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data100 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N105 ) + ); + defparam \vga/N193/XUSED .LOC = "CLB_R15C3.S0"; + X_BUF \vga/N193/XUSED ( + .I(\vga/N193 ), + .O(\vga/N193_0 ) + ); + defparam \vga/N193/YUSED .LOC = "CLB_R15C3.S0"; + X_BUF \vga/N193/YUSED ( + .I(\vga/N105 ), + .O(\vga/N105_0 ) + ); + defparam \vga/char_rom/Mrom_data185 .INIT = 16'h1216; + defparam \vga/char_rom/Mrom_data185 .LOC = "CLB_R22C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data185 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N192 ) + ); + defparam \vga/char_rom/Mrom_data101 .INIT = 16'h131B; + defparam \vga/char_rom/Mrom_data101 .LOC = "CLB_R22C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data101 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N106 ) + ); + defparam \vga/N192/XUSED .LOC = "CLB_R22C11.S0"; + X_BUF \vga/N192/XUSED ( + .I(\vga/N192 ), + .O(\vga/N192_0 ) + ); + defparam \vga/N192/YUSED .LOC = "CLB_R22C11.S0"; + X_BUF \vga/N192/YUSED ( + .I(\vga/N106 ), + .O(\vga/N106_0 ) + ); + defparam \vga/char_rom/Mrom_data184 .INIT = 16'h54D2; + defparam \vga/char_rom/Mrom_data184 .LOC = "CLB_R26C10.S1"; + X_LUT4 \vga/char_rom/Mrom_data184 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N191 ) + ); + defparam \vga/char_rom/Mrom_data110 .INIT = 16'h5333; + defparam \vga/char_rom/Mrom_data110 .LOC = "CLB_R26C10.S1"; + X_LUT4 \vga/char_rom/Mrom_data110 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N115 ) + ); + defparam \vga/N191/XUSED .LOC = "CLB_R26C10.S1"; + X_BUF \vga/N191/XUSED ( + .I(\vga/N191 ), + .O(\vga/N191_0 ) + ); + defparam \vga/N191/YUSED .LOC = "CLB_R26C10.S1"; + X_BUF \vga/N191/YUSED ( + .I(\vga/N115 ), + .O(\vga/N115_0 ) + ); + defparam \vga/char_rom/Mrom_data183 .INIT = 16'h3308; + defparam \vga/char_rom/Mrom_data183 .LOC = "CLB_R24C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data183 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N190 ) + ); + defparam \vga/char_rom/Mrom_data111 .INIT = 16'h6068; + defparam \vga/char_rom/Mrom_data111 .LOC = "CLB_R24C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data111 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N116 ) + ); + defparam \vga/N190/XUSED .LOC = "CLB_R24C10.S0"; + X_BUF \vga/N190/XUSED ( + .I(\vga/N190 ), + .O(\vga/N190_0 ) + ); + defparam \vga/N190/YUSED .LOC = "CLB_R24C10.S0"; + X_BUF \vga/N190/YUSED ( + .I(\vga/N116 ), + .O(\vga/N116_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1108 .INIT = 16'hEEFE; + defparam \vga/scancode_convert/scancode_rom/data<6>1108 .LOC = "CLB_R13C37.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1108 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1808 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1180_SW0 .INIT = 16'hB91D; + defparam \vga/scancode_convert/scancode_rom/data<2>1180_SW0 .LOC = "CLB_R13C37.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<2>1180_SW0 ( + .ADR0(\vga/scancode_convert/sc [2]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(N3141) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1_map1808/XUSED .LOC = "CLB_R13C37.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<6>1_map1808/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1_map1808 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1808_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1_map1808/YUSED .LOC = "CLB_R13C37.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<6>1_map1808/YUSED ( + .I(N3141), + .O(N3141_0) + ); + defparam \vga/char_rom/Mrom_data179 .INIT = 16'h1B00; + defparam \vga/char_rom/Mrom_data179 .LOC = "CLB_R25C5.S1"; + X_LUT4 \vga/char_rom/Mrom_data179 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N186 ) + ); + defparam \vga/char_rom/Mrom_data120 .INIT = 16'h2BA2; + defparam \vga/char_rom/Mrom_data120 .LOC = "CLB_R25C5.S1"; + X_LUT4 \vga/char_rom/Mrom_data120 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N125 ) + ); + defparam \vga/N186/XUSED .LOC = "CLB_R25C5.S1"; + X_BUF \vga/N186/XUSED ( + .I(\vga/N186 ), + .O(\vga/N186_0 ) + ); + defparam \vga/N186/YUSED .LOC = "CLB_R25C5.S1"; + X_BUF \vga/N186/YUSED ( + .I(\vga/N125 ), + .O(\vga/N125_0 ) + ); + defparam \vga/char_rom/Mrom_data177 .INIT = 16'h503C; + defparam \vga/char_rom/Mrom_data177 .LOC = "CLB_R24C10.S1"; + X_LUT4 \vga/char_rom/Mrom_data177 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N184 ) + ); + defparam \vga/char_rom/Mrom_data112 .INIT = 16'h4C20; + defparam \vga/char_rom/Mrom_data112 .LOC = "CLB_R24C10.S1"; + X_LUT4 \vga/char_rom/Mrom_data112 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N117 ) + ); + defparam \vga/N184/XUSED .LOC = "CLB_R24C10.S1"; + X_BUF \vga/N184/XUSED ( + .I(\vga/N184 ), + .O(\vga/N184_0 ) + ); + defparam \vga/N184/YUSED .LOC = "CLB_R24C10.S1"; + X_BUF \vga/N184/YUSED ( + .I(\vga/N117 ), + .O(\vga/N117_0 ) + ); + defparam \vga/char_rom/Mrom_data176 .INIT = 16'h4207; + defparam \vga/char_rom/Mrom_data176 .LOC = "CLB_R25C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data176 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N183 ) + ); + defparam \vga/char_rom/Mrom_data121 .INIT = 16'h2890; + defparam \vga/char_rom/Mrom_data121 .LOC = "CLB_R25C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data121 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N126 ) + ); + defparam \vga/N183/XUSED .LOC = "CLB_R25C5.S0"; + X_BUF \vga/N183/XUSED ( + .I(\vga/N183 ), + .O(\vga/N183_0 ) + ); + defparam \vga/N183/YUSED .LOC = "CLB_R25C5.S0"; + X_BUF \vga/N183/YUSED ( + .I(\vga/N126 ), + .O(\vga/N126_0 ) + ); + defparam \vga/char_rom/Mrom_data173 .INIT = 16'h53E2; + defparam \vga/char_rom/Mrom_data173 .LOC = "CLB_R25C16.S0"; + X_LUT4 \vga/char_rom/Mrom_data173 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N179 ) + ); + defparam \vga/char_rom/Mrom_data113 .INIT = 16'h009D; + defparam \vga/char_rom/Mrom_data113 .LOC = "CLB_R25C16.S0"; + X_LUT4 \vga/char_rom/Mrom_data113 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N118 ) + ); + defparam \vga/N179/XUSED .LOC = "CLB_R25C16.S0"; + X_BUF \vga/N179/XUSED ( + .I(\vga/N179 ), + .O(\vga/N179_0 ) + ); + defparam \vga/N179/YUSED .LOC = "CLB_R25C16.S0"; + X_BUF \vga/N179/YUSED ( + .I(\vga/N118 ), + .O(\vga/N118_0 ) + ); + defparam \vga/char_rom/Mrom_data172 .INIT = 16'hC010; + defparam \vga/char_rom/Mrom_data172 .LOC = "CLB_R26C16.S1"; + X_LUT4 \vga/char_rom/Mrom_data172 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N178 ) + ); + defparam \vga/char_rom/Mrom_data105 .INIT = 16'h7F08; + defparam \vga/char_rom/Mrom_data105 .LOC = "CLB_R26C16.S1"; + X_LUT4 \vga/char_rom/Mrom_data105 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N110 ) + ); + defparam \vga/N178/XUSED .LOC = "CLB_R26C16.S1"; + X_BUF \vga/N178/XUSED ( + .I(\vga/N178 ), + .O(\vga/N178_0 ) + ); + defparam \vga/N178/YUSED .LOC = "CLB_R26C16.S1"; + X_BUF \vga/N178/YUSED ( + .I(\vga/N110 ), + .O(\vga/N110_0 ) + ); + defparam \vga/char_rom/Mrom_data170 .INIT = 16'h205E; + defparam \vga/char_rom/Mrom_data170 .LOC = "CLB_R25C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data170 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N176 ) + ); + defparam \vga/char_rom/Mrom_data122 .INIT = 16'h1B73; + defparam \vga/char_rom/Mrom_data122 .LOC = "CLB_R25C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data122 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N127 ) + ); + defparam \vga/N176/XUSED .LOC = "CLB_R25C10.S0"; + X_BUF \vga/N176/XUSED ( + .I(\vga/N176 ), + .O(\vga/N176_0 ) + ); + defparam \vga/N176/YUSED .LOC = "CLB_R25C10.S0"; + X_BUF \vga/N176/YUSED ( + .I(\vga/N127 ), + .O(\vga/N127_0 ) + ); + defparam \vga/char_rom/Mrom_data169 .INIT = 16'h5760; + defparam \vga/char_rom/Mrom_data169 .LOC = "CLB_R25C16.S1"; + X_LUT4 \vga/char_rom/Mrom_data169 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N175 ) + ); + defparam \vga/char_rom/Mrom_data106 .INIT = 16'h1440; + defparam \vga/char_rom/Mrom_data106 .LOC = "CLB_R25C16.S1"; + X_LUT4 \vga/char_rom/Mrom_data106 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N111 ) + ); + defparam \vga/N175/XUSED .LOC = "CLB_R25C16.S1"; + X_BUF \vga/N175/XUSED ( + .I(\vga/N175 ), + .O(\vga/N175_0 ) + ); + defparam \vga/N175/YUSED .LOC = "CLB_R25C16.S1"; + X_BUF \vga/N175/YUSED ( + .I(\vga/N111 ), + .O(\vga/N111_0 ) + ); + defparam \vga/char_rom/Mrom_data166 .INIT = 16'h0820; + defparam \vga/char_rom/Mrom_data166 .LOC = "CLB_R26C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data166 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N172 ) + ); + defparam \vga/char_rom/Mrom_data131 .INIT = 16'h7E05; + defparam \vga/char_rom/Mrom_data131 .LOC = "CLB_R26C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data131 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N137 ) + ); + defparam \vga/N172/XUSED .LOC = "CLB_R26C3.S0"; + X_BUF \vga/N172/XUSED ( + .I(\vga/N172 ), + .O(\vga/N172_0 ) + ); + defparam \vga/N172/YUSED .LOC = "CLB_R26C3.S0"; + X_BUF \vga/N172/YUSED ( + .I(\vga/N137 ), + .O(\vga/N137_0 ) + ); + defparam \vga/char_rom/Mrom_data165 .INIT = 16'h0004; + defparam \vga/char_rom/Mrom_data165 .LOC = "CLB_R28C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data165 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N171 ) + ); + defparam \vga/char_rom/Mrom_data123 .INIT = 16'h2030; + defparam \vga/char_rom/Mrom_data123 .LOC = "CLB_R28C5.S0"; + X_LUT4 \vga/char_rom/Mrom_data123 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N128 ) + ); + defparam \vga/N171/XUSED .LOC = "CLB_R28C5.S0"; + X_BUF \vga/N171/XUSED ( + .I(\vga/N171 ), + .O(\vga/N171_0 ) + ); + defparam \vga/N171/YUSED .LOC = "CLB_R28C5.S0"; + X_BUF \vga/N171/YUSED ( + .I(\vga/N128 ), + .O(\vga/N128_0 ) + ); + defparam \vga/char_rom/Mrom_data164 .INIT = 16'hD33A; + defparam \vga/char_rom/Mrom_data164 .LOC = "CLB_R27C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data164 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N170 ) + ); + defparam \vga/char_rom/Mrom_data115 .INIT = 16'h8001; + defparam \vga/char_rom/Mrom_data115 .LOC = "CLB_R27C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data115 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N120 ) + ); + defparam \vga/N170/XUSED .LOC = "CLB_R27C10.S0"; + X_BUF \vga/N170/XUSED ( + .I(\vga/N170 ), + .O(\vga/N170_0 ) + ); + defparam \vga/N170/YUSED .LOC = "CLB_R27C10.S0"; + X_BUF \vga/N170/YUSED ( + .I(\vga/N120 ), + .O(\vga/N120_0 ) + ); + defparam \vga/char_rom/Mrom_data161 .INIT = 16'h3025; + defparam \vga/char_rom/Mrom_data161 .LOC = "CLB_R27C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data161 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N167 ) + ); + defparam \vga/char_rom/Mrom_data140 .INIT = 16'h6112; + defparam \vga/char_rom/Mrom_data140 .LOC = "CLB_R27C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data140 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N146 ) + ); + defparam \vga/N167/XUSED .LOC = "CLB_R27C3.S0"; + X_BUF \vga/N167/XUSED ( + .I(\vga/N167 ), + .O(\vga/N167_0 ) + ); + defparam \vga/N167/YUSED .LOC = "CLB_R27C3.S0"; + X_BUF \vga/N167/YUSED ( + .I(\vga/N146 ), + .O(\vga/N146_0 ) + ); + defparam \vga/char_rom/Mrom_data153 .INIT = 16'h4012; + defparam \vga/char_rom/Mrom_data153 .LOC = "CLB_R23C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data153 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N159 ) + ); + defparam \vga/char_rom/Mrom_data132 .INIT = 16'h134C; + defparam \vga/char_rom/Mrom_data132 .LOC = "CLB_R23C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data132 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N138 ) + ); + defparam \vga/N159/XUSED .LOC = "CLB_R23C10.S0"; + X_BUF \vga/N159/XUSED ( + .I(\vga/N159 ), + .O(\vga/N159_0 ) + ); + defparam \vga/N159/YUSED .LOC = "CLB_R23C10.S0"; + X_BUF \vga/N159/YUSED ( + .I(\vga/N138 ), + .O(\vga/N138_0 ) + ); + defparam \vga/char_rom/Mrom_data151 .INIT = 16'h4020; + defparam \vga/char_rom/Mrom_data151 .LOC = "CLB_R22C11.S1"; + X_LUT4 \vga/char_rom/Mrom_data151 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N157 ) + ); + defparam \vga/char_rom/Mrom_data124 .INIT = 16'h200C; + defparam \vga/char_rom/Mrom_data124 .LOC = "CLB_R22C11.S1"; + X_LUT4 \vga/char_rom/Mrom_data124 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N129 ) + ); + defparam \vga/N157/XUSED .LOC = "CLB_R22C11.S1"; + X_BUF \vga/N157/XUSED ( + .I(\vga/N157 ), + .O(\vga/N157_0 ) + ); + defparam \vga/N157/YUSED .LOC = "CLB_R22C11.S1"; + X_BUF \vga/N157/YUSED ( + .I(\vga/N129 ), + .O(\vga/N129_0 ) + ); + defparam \vga/char_rom/Mrom_data149 .INIT = 16'h0491; + defparam \vga/char_rom/Mrom_data149 .LOC = "CLB_R27C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data149 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N155 ) + ); + defparam \vga/char_rom/Mrom_data116 .INIT = 16'h0E13; + defparam \vga/char_rom/Mrom_data116 .LOC = "CLB_R27C11.S0"; + X_LUT4 \vga/char_rom/Mrom_data116 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N121 ) + ); + defparam \vga/N155/XUSED .LOC = "CLB_R27C11.S0"; + X_BUF \vga/N155/XUSED ( + .I(\vga/N155 ), + .O(\vga/N155_0 ) + ); + defparam \vga/N155/YUSED .LOC = "CLB_R27C11.S0"; + X_BUF \vga/N155/YUSED ( + .I(\vga/N121 ), + .O(\vga/N121_0 ) + ); + defparam \vga/char_rom/Mrom_data146 .INIT = 16'h0039; + defparam \vga/char_rom/Mrom_data146 .LOC = "CLB_R26C16.S0"; + X_LUT4 \vga/char_rom/Mrom_data146 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N152 ) + ); + defparam \vga/char_rom/Mrom_data108 .INIT = 16'h0806; + defparam \vga/char_rom/Mrom_data108 .LOC = "CLB_R26C16.S0"; + X_LUT4 \vga/char_rom/Mrom_data108 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N113 ) + ); + defparam \vga/N152/XUSED .LOC = "CLB_R26C16.S0"; + X_BUF \vga/N152/XUSED ( + .I(\vga/N152 ), + .O(\vga/N152_0 ) + ); + defparam \vga/N152/YUSED .LOC = "CLB_R26C16.S0"; + X_BUF \vga/N152/YUSED ( + .I(\vga/N113 ), + .O(\vga/N113_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW0 .INIT = 16'hC0C3; + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW0 .LOC = "CLB_R11C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<4>1308_SW0 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3174) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3193 .INIT = 16'hF3F2; + defparam \vga/scancode_convert/scancode_rom/data<5>3193 .LOC = "CLB_R11C36.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3193 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/raise ), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1276 ) + ); + defparam \N3174/XUSED .LOC = "CLB_R11C36.S1"; + X_BUF \N3174/XUSED ( + .I(N3174), + .O(N3174_0) + ); + defparam \N3174/YUSED .LOC = "CLB_R11C36.S1"; + X_BUF \N3174/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1276 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1276_0 ) + ); + defparam \vga/scancode_convert/key_up .LOC = "CLB_R15C26.S0"; + defparam \vga/scancode_convert/key_up .INIT = 1'b0; + X_FF \vga/scancode_convert/key_up ( + .I(\vga/scancode_convert/state_FFd3_29 ), + .CE(\vga/scancode_convert/_not0012_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/key_up/FFY/RST ), + .O(\vga/scancode_convert/key_up_14 ) + ); + defparam \vga/scancode_convert/key_up/FFY/RSTOR .LOC = "CLB_R15C26.S0"; + X_INV \vga/scancode_convert/key_up/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/key_up/FFY/RST ) + ); + defparam \vga/char_rom/Mrom_data145 .INIT = 16'h0141; + defparam \vga/char_rom/Mrom_data145 .LOC = "CLB_R24C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data145 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N151 ) + ); + defparam \vga/char_rom/Mrom_data141 .INIT = 16'h19AC; + defparam \vga/char_rom/Mrom_data141 .LOC = "CLB_R24C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data141 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N147 ) + ); + defparam \vga/N151/XUSED .LOC = "CLB_R24C3.S1"; + X_BUF \vga/N151/XUSED ( + .I(\vga/N151 ), + .O(\vga/N151_0 ) + ); + defparam \vga/N151/YUSED .LOC = "CLB_R24C3.S1"; + X_BUF \vga/N151/YUSED ( + .I(\vga/N147 ), + .O(\vga/N147_0 ) + ); + defparam \vga/char_rom/Mrom_data144 .INIT = 16'h0582; + defparam \vga/char_rom/Mrom_data144 .LOC = "CLB_R21C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data144 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N150 ) + ); + defparam \vga/char_rom/Mrom_data133 .INIT = 16'h1531; + defparam \vga/char_rom/Mrom_data133 .LOC = "CLB_R21C3.S0"; + X_LUT4 \vga/char_rom/Mrom_data133 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N139 ) + ); + defparam \vga/N150/XUSED .LOC = "CLB_R21C3.S0"; + X_BUF \vga/N150/XUSED ( + .I(\vga/N150 ), + .O(\vga/N150_0 ) + ); + defparam \vga/N150/YUSED .LOC = "CLB_R21C3.S0"; + X_BUF \vga/N150/YUSED ( + .I(\vga/N139 ), + .O(\vga/N139_0 ) + ); + defparam \vga/char_rom/Mrom_data143 .INIT = 16'hBFC0; + defparam \vga/char_rom/Mrom_data143 .LOC = "CLB_R23C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data143 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N149 ) + ); + defparam \vga/char_rom/Mrom_data125 .INIT = 16'h10A0; + defparam \vga/char_rom/Mrom_data125 .LOC = "CLB_R23C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data125 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N130 ) + ); + defparam \vga/N149/XUSED .LOC = "CLB_R23C2.S0"; + X_BUF \vga/N149/XUSED ( + .I(\vga/N149 ), + .O(\vga/N149_0 ) + ); + defparam \vga/N149/YUSED .LOC = "CLB_R23C2.S0"; + X_BUF \vga/N149/YUSED ( + .I(\vga/N130 ), + .O(\vga/N130_0 ) + ); + defparam \vga/char_rom/Mrom_data139 .INIT = 16'h2391; + defparam \vga/char_rom/Mrom_data139 .LOC = "CLB_R26C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data139 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N145 ) + ); + defparam \vga/char_rom/Mrom_data109 .INIT = 16'h4521; + defparam \vga/char_rom/Mrom_data109 .LOC = "CLB_R26C10.S0"; + X_LUT4 \vga/char_rom/Mrom_data109 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N114 ) + ); + defparam \vga/N145/XUSED .LOC = "CLB_R26C10.S0"; + X_BUF \vga/N145/XUSED ( + .I(\vga/N145 ), + .O(\vga/N145_0 ) + ); + defparam \vga/N145/YUSED .LOC = "CLB_R26C10.S0"; + X_BUF \vga/N145/YUSED ( + .I(\vga/N114 ), + .O(\vga/N114_0 ) + ); + defparam \vga/char_rom/Mrom_data138 .INIT = 16'h180D; + defparam \vga/char_rom/Mrom_data138 .LOC = "CLB_R23C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data138 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N144 ) + ); + defparam \vga/char_rom/Mrom_data126 .INIT = 16'h4804; + defparam \vga/char_rom/Mrom_data126 .LOC = "CLB_R23C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data126 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N131 ) + ); + defparam \vga/N144/XUSED .LOC = "CLB_R23C2.S1"; + X_BUF \vga/N144/XUSED ( + .I(\vga/N144 ), + .O(\vga/N144_0 ) + ); + defparam \vga/N144/YUSED .LOC = "CLB_R23C2.S1"; + X_BUF \vga/N144/YUSED ( + .I(\vga/N131 ), + .O(\vga/N131_0 ) + ); + defparam \vga/char_rom/Mrom_data137 .INIT = 16'h0448; + defparam \vga/char_rom/Mrom_data137 .LOC = "CLB_R20C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data137 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N143 ) + ); + defparam \vga/char_rom/Mrom_data127 .INIT = 16'h00D6; + defparam \vga/char_rom/Mrom_data127 .LOC = "CLB_R20C2.S0"; + X_LUT4 \vga/char_rom/Mrom_data127 ( + .ADR0(\vga/rom_addr_char [0]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [2]), + .ADR3(\vga/vgacore/vcnt [0]), + .O(\vga/N132 ) + ); + defparam \vga/N143/XUSED .LOC = "CLB_R20C2.S0"; + X_BUF \vga/N143/XUSED ( + .I(\vga/N143 ), + .O(\vga/N143_0 ) + ); + defparam \vga/N143/YUSED .LOC = "CLB_R20C2.S0"; + X_BUF \vga/N143/YUSED ( + .I(\vga/N132 ), + .O(\vga/N132_0 ) + ); + defparam \vga/char_rom/Mrom_data129 .INIT = 16'h0010; + defparam \vga/char_rom/Mrom_data129 .LOC = "CLB_R20C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data129 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/rom_addr_char [0]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [1]), + .O(\vga/N134 ) + ); + defparam \vga/char_rom/Mrom_data136 .INIT = 16'h40A8; + defparam \vga/char_rom/Mrom_data136 .LOC = "CLB_R20C2.S1"; + X_LUT4 \vga/char_rom/Mrom_data136 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [1]), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N142 ) + ); + defparam \vga/N134/XUSED .LOC = "CLB_R20C2.S1"; + X_BUF \vga/N134/XUSED ( + .I(\vga/N134 ), + .O(\vga/N134_0 ) + ); + defparam \vga/N134/YUSED .LOC = "CLB_R20C2.S1"; + X_BUF \vga/N134/YUSED ( + .I(\vga/N142 ), + .O(\vga/N142_0 ) + ); + defparam \vga/char_rom/Mrom_data1 .INIT = 16'h4000; + defparam \vga/char_rom/Mrom_data1 .LOC = "CLB_R22C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data1 ( + .ADR0(\vga/vgacore/vcnt [1]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/rom_addr_char [0]), + .ADR3(\vga/vgacore/vcnt [2]), + .O(\vga/N2 ) + ); + defparam \vga/char_rom/Mrom_data128 .INIT = 16'h415F; + defparam \vga/char_rom/Mrom_data128 .LOC = "CLB_R22C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data128 ( + .ADR0(\vga/vgacore/vcnt [0]), + .ADR1(\vga/vgacore/vcnt [2]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(\vga/rom_addr_char [0]), + .O(\vga/N133 ) + ); + defparam \vga/N2/XUSED .LOC = "CLB_R22C3.S1"; + X_BUF \vga/N2/XUSED ( + .I(\vga/N2 ), + .O(\vga/N2_0 ) + ); + defparam \vga/N2/YUSED .LOC = "CLB_R22C3.S1"; + X_BUF \vga/N2/YUSED ( + .I(\vga/N133 ), + .O(\vga/N133_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1206 .INIT = 16'h112A; + defparam \vga/scancode_convert/scancode_rom/data<0>1206 .LOC = "CLB_R14C33.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1206 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/raise ), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1475 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3614 .INIT = 16'h0E3D; + defparam \vga/scancode_convert/scancode_rom/data<5>3614 .LOC = "CLB_R14C33.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3614 ( + .ADR0(\vga/scancode_convert/raise ), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1363 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1_map1475/XUSED .LOC = "CLB_R14C33.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1_map1475/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1475 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1475_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1_map1475/YUSED .LOC = "CLB_R14C33.S0"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1_map1475/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1363 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1363_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>186_SW0 .INIT = 16'h5420; + defparam \vga/scancode_convert/scancode_rom/data<6>186_SW0 .LOC = "CLB_R14C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>186_SW0 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [4]), + .O(N3124) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1305 .INIT = 16'h3B37; + defparam \vga/scancode_convert/scancode_rom/data<6>1305 .LOC = "CLB_R14C37.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1305 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [2]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1850 ) + ); + defparam \N3124/XUSED .LOC = "CLB_R14C37.S0"; + X_BUF \N3124/XUSED ( + .I(N3124), + .O(N3124_0) + ); + defparam \N3124/YUSED .LOC = "CLB_R14C37.S0"; + X_BUF \N3124/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<6>1_map1850 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1850_0 ) + ); + defparam \vga/ram_addr_write<7>/LOGIC_ONE .LOC = "CLB_R15C10.S1"; + X_ONE \vga/ram_addr_write<7>/LOGIC_ONE ( + .O(\vga/ram_addr_write<7>/LOGIC_ONE_169 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_cy<7> .LOC = "CLB_R15C10.S1"; + X_MUX2 \vga/crt/Madd_ram_addr_Madd_cy<7> ( + .IA(\vga/crt/Madd_ram_addrC2 ), + .IB(\vga/ram_addr_write<7>/CYINIT_171 ), + .SEL(\vga/crt/N9 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy<7>_rt_170 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_xor<7> .LOC = "CLB_R15C10.S1"; + X_XOR2 \vga/crt/Madd_ram_addr_Madd_xor<7> ( + .I0(\vga/ram_addr_write<7>/CYINIT_171 ), + .I1(\vga/crt/N9 ), + .O(\vga/ram_addr_write [7]) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<7> .INIT = 16'h9966; + defparam \vga/crt/Madd_ram_addr_Madd_lut<7> .LOC = "CLB_R15C10.S1"; + X_LUT4 \vga/crt/Madd_ram_addr_Madd_lut<7> ( + .ADR0(\vga/crt/Madd_ram_addrC2 ), + .ADR1(\vga/crt/cursor_v [1]), + .ADR2(VCC), + .ADR3(\vga/crt/cursor_v [3]), + .O(\vga/crt/N9 ) + ); + defparam \vga/crt/Madd_ram_addrC21 .INIT = 16'hFAA0; + defparam \vga/crt/Madd_ram_addrC21 .LOC = "CLB_R15C10.S1"; + X_LUT4 \vga/crt/Madd_ram_addrC21 ( + .ADR0(\vga/crt/cursor_v [0]), + .ADR1(VCC), + .ADR2(\vga/crt/cursor_h [6]), + .ADR3(\vga/crt/cursor_v [2]), + .O(\vga/crt/Madd_ram_addrC2_pack_1 ) + ); + defparam \vga/ram_addr_write<7>/XUSED .LOC = "CLB_R15C10.S1"; + X_BUF \vga/ram_addr_write<7>/XUSED ( + .I(\vga/ram_addr_write [7]), + .O(\vga/ram_addr_write<7>_0 ) + ); + defparam \vga/ram_addr_write<7>/YUSED .LOC = "CLB_R15C10.S1"; + X_BUF \vga/ram_addr_write<7>/YUSED ( + .I(\vga/crt/Madd_ram_addrC2_pack_1 ), + .O(\vga/crt/Madd_ram_addrC2 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_cy<7>_rt .LOC = "CLB_R15C10.S1"; + X_MUX2 \vga/crt/Madd_ram_addr_Madd_cy<7>_rt ( + .IA(\NLW_vga/crt/Madd_ram_addr_Madd_cy<7>_rt_IA_UNCONNECTED ), + .IB(\vga/crt/Madd_ram_addr_Madd_cy<7>_rt_170 ), + .SEL(\vga/ram_addr_write<7>/LOGIC_ONE_169 ), + .O(\vga/ram_addr_write<7>/CYMUXG ) + ); + defparam \vga/ram_addr_write<7>/CYINIT .LOC = "CLB_R15C10.S1"; + X_BUF \vga/ram_addr_write<7>/CYINIT ( + .I(\vga/ram_addr_write<5>/CYMUXG ), + .O(\vga/ram_addr_write<7>/CYINIT_171 ) + ); + defparam \vga/scancode_convert/raise1 .INIT = 16'hFFFC; + defparam \vga/scancode_convert/raise1 .LOC = "CLB_R13C34.S0"; + X_LUT4 \vga/scancode_convert/raise1 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/ctrl_22 ), + .ADR2(\vga/scancode_convert/capslock_25 ), + .ADR3(\vga/scancode_convert/shift_24 ), + .O(\vga/scancode_convert/raise_pack_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>144 .INIT = 16'h0A0E; + defparam \vga/scancode_convert/scancode_rom/data<0>144 .LOC = "CLB_R13C34.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>144 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1438 ) + ); + defparam \vga/scancode_convert/raise/XUSED .LOC = "CLB_R13C34.S0"; + X_BUF \vga/scancode_convert/raise/XUSED ( + .I(\vga/scancode_convert/raise_pack_1 ), + .O(\vga/scancode_convert/raise ) + ); + defparam \vga/scancode_convert/raise/YUSED .LOC = "CLB_R13C34.S0"; + X_BUF \vga/scancode_convert/raise/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1438 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1438_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>81 .INIT = 16'hFF5F; + defparam \vga/scancode_convert/scancode_rom/data<3>81 .LOC = "CLB_R13C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<3>81 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(VCC), + .ADR2(\vga/scancode_convert/raise ), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/N43 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3746 .INIT = 16'h9322; + defparam \vga/scancode_convert/scancode_rom/data<5>3746 .LOC = "CLB_R13C35.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>3746 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/raise ), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1394 ) + ); + defparam \vga/scancode_convert/scancode_rom/N43/XUSED .LOC = "CLB_R13C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/N43/XUSED ( + .I(\vga/scancode_convert/scancode_rom/N43 ), + .O(\vga/scancode_convert/scancode_rom/N43_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/N43/YUSED .LOC = "CLB_R13C35.S1"; + X_BUF \vga/scancode_convert/scancode_rom/N43/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1394 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1394_0 ) + ); + defparam \vga/charload8_SW0 .INIT = 16'h2064; + defparam \vga/charload8_SW0 .LOC = "CLB_R11C7.S1"; + X_LUT4 \vga/charload8_SW0 ( + .ADR0(\vga/rom_addr_char [5]), + .ADR1(\vga/rom_addr_char [6]), + .ADR2(\vga/rom_addr_char<4>11234_0 ), + .ADR3(N3150_0), + .O(N562_pack_1) + ); + defparam \vga/charload8 .INIT = 16'hEEE2; + defparam \vga/charload8 .LOC = "CLB_R11C7.S1"; + X_LUT4 \vga/charload8 ( + .ADR0(\vga/pixel_hold [6]), + .ADR1(\vga/charload_19 ), + .ADR2(\vga/cursor_match_0 ), + .ADR3(N562), + .O(\vga/_mux0002 [0]) + ); + defparam \vga/pixel_hold<7>/XUSED .LOC = "CLB_R11C7.S1"; + X_BUF \vga/pixel_hold<7>/XUSED ( + .I(N562_pack_1), + .O(N562) + ); + defparam \vga/pixel_hold_7 .LOC = "CLB_R11C7.S1"; + defparam \vga/pixel_hold_7 .INIT = 1'b0; + X_FF \vga/pixel_hold_7 ( + .I(\vga/_mux0002 [0]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [7]) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>281 .INIT = 16'h002C; + defparam \vga/scancode_convert/scancode_rom/data<1>281 .LOC = "CLB_R14C37.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>281 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc [0]), + .ADR2(\vga/scancode_convert/sc [1]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1701 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1333_SW0 .INIT = 16'h0FCC; + defparam \vga/scancode_convert/scancode_rom/data<6>1333_SW0 .LOC = "CLB_R14C37.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<6>1333_SW0 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/sc [3]), + .O(N3130) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2_map1701/XUSED .LOC = "CLB_R14C37.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<1>2_map1701/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<1>2_map1701 ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1701_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2_map1701/YUSED .LOC = "CLB_R14C37.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<1>2_map1701/YUSED ( + .I(N3130), + .O(N3130_0) + ); + defparam \vga/crt/state_Out41 .INIT = 16'h0044; + defparam \vga/crt/state_Out41 .LOC = "CLB_R16C15.S1"; + X_LUT4 \vga/crt/state_Out41 ( + .ADR0(\vga/crt/state_FFd3_11 ), + .ADR1(\vga/crt/state_FFd1_13 ), + .ADR2(VCC), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/crt/_cmp_eq0004_pack_1 ) + ); + defparam \vga/crt/write_delay__mux0000<1>1 .INIT = 16'h5A00; + defparam \vga/crt/write_delay__mux0000<1>1 .LOC = "CLB_R16C15.S1"; + X_LUT4 \vga/crt/write_delay__mux0000<1>1 ( + .ADR0(\vga/crt/write_delay [0]), + .ADR1(VCC), + .ADR2(\vga/crt/write_delay [1]), + .ADR3(\vga/crt/_cmp_eq0004 ), + .O(\vga/crt/write_delay__mux0000 [1]) + ); + defparam \vga/crt/write_delay<1>/XUSED .LOC = "CLB_R16C15.S1"; + X_BUF \vga/crt/write_delay<1>/XUSED ( + .I(\vga/crt/_cmp_eq0004_pack_1 ), + .O(\vga/crt/_cmp_eq0004 ) + ); + defparam \vga/crt/write_delay_1 .LOC = "CLB_R16C15.S1"; + defparam \vga/crt/write_delay_1 .INIT = 1'b0; + X_FF \vga/crt/write_delay_1 ( + .I(\vga/crt/write_delay__mux0000 [1]), + .CE(VCC), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/write_delay<1>/FFY/RST ), + .O(\vga/crt/write_delay [1]) + ); + defparam \vga/crt/write_delay<1>/FFY/RSTOR .LOC = "CLB_R16C15.S1"; + X_INV \vga/crt/write_delay<1>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/write_delay<1>/FFY/RST ) + ); + defparam \vga/crt/state_Out92 .INIT = 16'h1155; + defparam \vga/crt/state_Out92 .LOC = "CLB_R15C6.S0"; + X_LUT4 \vga/crt/state_Out92 ( + .ADR0(\vga/crt/state_FFd1_13 ), + .ADR1(\vga/crt/state_FFd3_11 ), + .ADR2(VCC), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/clearing_pack_1 ) + ); + defparam \vga/_mux00001 .INIT = 16'h550C; + defparam \vga/_mux00001 .LOC = "CLB_R15C6.S0"; + X_LUT4 \vga/_mux00001 ( + .ADR0(\vga/crtclk1 ), + .ADR1(\vga/pclk [2]), + .ADR2(\vga/pclk [1]), + .ADR3(\vga/clearing ), + .O(\vga/_mux0000 ) + ); + defparam \vga/ram_wclk/XUSED .LOC = "CLB_R15C6.S0"; + X_BUF \vga/ram_wclk/XUSED ( + .I(\vga/clearing_pack_1 ), + .O(\vga/clearing ) + ); + defparam \gray_cnt_FFd11/BYMUX .LOC = "CLB_R2C21.S0"; + X_INV \gray_cnt_FFd11/BYMUX ( + .I(gray_cnt_FFd1_0), + .O(\gray_cnt_FFd11/BYMUXNOT ) + ); + defparam \gray_cnt_FFd11/SRMUX .LOC = "CLB_R2C21.S0"; + X_INV \gray_cnt_FFd11/SRMUX ( + .I(reset_n_IBUF_0), + .O(\gray_cnt_FFd11/SRMUX_OUTPUTNOT ) + ); + defparam gray_cnt_FFd2.LOC = "CLB_R2C21.S0"; + defparam gray_cnt_FFd2.INIT = 1'b0; + X_FF gray_cnt_FFd2 ( + .I(\gray_cnt_FFd11/BYMUXNOT ), + .CE(VCC), + .CLK(clka_BUFGP), + .SET(GND), + .RST(\gray_cnt_FFd11/FFY/RST ), + .O(gray_cnt_FFd2_36) + ); + defparam \gray_cnt_FFd11/FFY/RSTOR .LOC = "CLB_R2C21.S0"; + X_BUF \gray_cnt_FFd11/FFY/RSTOR ( + .I(\gray_cnt_FFd11/SRMUX_OUTPUTNOT ), + .O(\gray_cnt_FFd11/FFY/RST ) + ); + defparam \vga/crt/ram_we_n1 .INIT = 16'hFCCF; + defparam \vga/crt/ram_we_n1 .LOC = "CLB_R14C3.S0"; + X_LUT4 \vga/crt/ram_we_n1 ( + .ADR0(VCC), + .ADR1(\vga/crt/state_FFd2_12 ), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/state_FFd1_13 ), + .O(\vga/ram_we_n_pack_1 ) + ); + defparam \vga/ram_addr_mux<11>1 .INIT = 16'hCCAA; + defparam \vga/ram_addr_mux<11>1 .LOC = "CLB_R14C3.S0"; + X_LUT4 \vga/ram_addr_mux<11>1 ( + .ADR0(\vga/ram_addr_write<11>_0 ), + .ADR1(\vga/ram_addr_video<11>_0 ), + .ADR2(VCC), + .ADR3(\vga/ram_we_n ), + .O(\vga/ram_addr_mux [11]) + ); + defparam \vga/video_ram/ram_addr_w<11>/XUSED .LOC = "CLB_R14C3.S0"; + X_BUF \vga/video_ram/ram_addr_w<11>/XUSED ( + .I(\vga/ram_we_n_pack_1 ), + .O(\vga/ram_we_n ) + ); + defparam \vga/video_ram/ram_addr_w<11>/YUSED .LOC = "CLB_R14C3.S0"; + X_BUF \vga/video_ram/ram_addr_w<11>/YUSED ( + .I(\vga/ram_addr_mux [11]), + .O(\vga/ram_addr_mux<11>_0 ) + ); + defparam \vga/video_ram/ram_addr_w_11 .LOC = "CLB_R14C3.S0"; + defparam \vga/video_ram/ram_addr_w_11 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_11 ( + .I(\vga/ram_addr_mux [11]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [11]) + ); + defparam \vga/scancode_convert/capslock/BYMUX .LOC = "CLB_R13C32.S0"; + X_INV \vga/scancode_convert/capslock/BYMUX ( + .I(\vga/scancode_convert/capslock_25 ), + .O(\vga/scancode_convert/capslock/BYMUXNOT ) + ); + defparam \vga/scancode_convert/capslock .LOC = "CLB_R13C32.S0"; + defparam \vga/scancode_convert/capslock .INIT = 1'b0; + X_FF \vga/scancode_convert/capslock ( + .I(\vga/scancode_convert/capslock/BYMUXNOT ), + .CE(\vga/scancode_convert/capslock_toggle_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/capslock/FFY/RST ), + .O(\vga/scancode_convert/capslock_25 ) + ); + defparam \vga/scancode_convert/capslock/FFY/RSTOR .LOC = "CLB_R13C32.S0"; + X_INV \vga/scancode_convert/capslock/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/capslock/FFY/RST ) + ); + defparam \vga/ram_addr_video<7>/LOGIC_ONE .LOC = "CLB_R16C5.S0"; + X_ONE \vga/ram_addr_video<7>/LOGIC_ONE ( + .O(\vga/ram_addr_video<7>/LOGIC_ONE_172 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_cy<7> .LOC = "CLB_R16C5.S0"; + X_MUX2 \vga/Madd_ram_addr_video_Madd_cy<7> ( + .IA(\vga/Madd_ram_addr_videoC2 ), + .IB(\vga/ram_addr_video<7>/CYINIT_174 ), + .SEL(\vga/N230 ), + .O(\vga/Madd_ram_addr_video_Madd_cy<7>_rt_173 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_xor<7> .LOC = "CLB_R16C5.S0"; + X_XOR2 \vga/Madd_ram_addr_video_Madd_xor<7> ( + .I0(\vga/ram_addr_video<7>/CYINIT_174 ), + .I1(\vga/N230 ), + .O(\vga/ram_addr_video [7]) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<7> .INIT = 16'h9966; + defparam \vga/Madd_ram_addr_video_Madd_lut<7> .LOC = "CLB_R16C5.S0"; + X_LUT4 \vga/Madd_ram_addr_video_Madd_lut<7> ( + .ADR0(\vga/Madd_ram_addr_videoC2 ), + .ADR1(\vga/vgacore/vcnt [6]), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt [4]), + .O(\vga/N230 ) + ); + defparam \vga/Madd_ram_addr_videoC21 .INIT = 16'hEE88; + defparam \vga/Madd_ram_addr_videoC21 .LOC = "CLB_R16C5.S0"; + X_LUT4 \vga/Madd_ram_addr_videoC21 ( + .ADR0(\vga/vgacore/vcnt [3]), + .ADR1(\vga/vgacore/vcnt [5]), + .ADR2(VCC), + .ADR3(\vga/vgacore/hcnt [9]), + .O(\vga/Madd_ram_addr_videoC2_pack_1 ) + ); + defparam \vga/ram_addr_video<7>/XUSED .LOC = "CLB_R16C5.S0"; + X_BUF \vga/ram_addr_video<7>/XUSED ( + .I(\vga/ram_addr_video [7]), + .O(\vga/ram_addr_video<7>_0 ) + ); + defparam \vga/ram_addr_video<7>/YUSED .LOC = "CLB_R16C5.S0"; + X_BUF \vga/ram_addr_video<7>/YUSED ( + .I(\vga/Madd_ram_addr_videoC2_pack_1 ), + .O(\vga/Madd_ram_addr_videoC2 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_cy<7>_rt .LOC = "CLB_R16C5.S0"; + X_MUX2 \vga/Madd_ram_addr_video_Madd_cy<7>_rt ( + .IA(\NLW_vga/Madd_ram_addr_video_Madd_cy<7>_rt_IA_UNCONNECTED ), + .IB(\vga/Madd_ram_addr_video_Madd_cy<7>_rt_173 ), + .SEL(\vga/ram_addr_video<7>/LOGIC_ONE_172 ), + .O(\vga/ram_addr_video<7>/CYMUXG ) + ); + defparam \vga/ram_addr_video<7>/CYINIT .LOC = "CLB_R16C5.S0"; + X_BUF \vga/ram_addr_video<7>/CYINIT ( + .I(\vga/ram_addr_video<5>/CYMUXG ), + .O(\vga/ram_addr_video<7>/CYINIT_174 ) + ); + defparam \vga/vgacore/vcnt_Eqn_1_SW0 .INIT = 16'hFA00; + defparam \vga/vgacore/vcnt_Eqn_1_SW0 .LOC = "CLB_R17C9.S0"; + X_LUT4 \vga/vgacore/vcnt_Eqn_1_SW0 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(VCC), + .ADR2(\vga/vgacore/vcnt [0]), + .ADR3(\vga/vgacore/vcnt [3]), + .O(N839) + ); + defparam \vga/Madd_ram_addr_videoR21 .INIT = 16'hA55A; + defparam \vga/Madd_ram_addr_videoR21 .LOC = "CLB_R17C9.S0"; + X_LUT4 \vga/Madd_ram_addr_videoR21 ( + .ADR0(\vga/vgacore/vcnt [5]), + .ADR1(VCC), + .ADR2(\vga/vgacore/vcnt [3]), + .ADR3(\vga/vgacore/hcnt [9]), + .O(\vga/Madd_ram_addr_videoR2 ) + ); + defparam \N839/XUSED .LOC = "CLB_R17C9.S0"; + X_BUF \N839/XUSED ( + .I(N839), + .O(N839_0) + ); + defparam \N839/YUSED .LOC = "CLB_R17C9.S0"; + X_BUF \N839/YUSED ( + .I(\vga/Madd_ram_addr_videoR2 ), + .O(\vga/Madd_ram_addr_videoR2_0 ) + ); + defparam \vga/ps2/ps2_clk_edge2 .INIT = 16'h1008; + defparam \vga/ps2/ps2_clk_edge2 .LOC = "CLB_R10C16.S0"; + X_LUT4 \vga/ps2/ps2_clk_edge2 ( + .ADR0(\vga/ps2/ps2_clk_r [1]), + .ADR1(\vga/ps2/ps2_clk_r [2]), + .ADR2(\vga/ps2/ps2_clk_r [3]), + .ADR3(\vga/ps2/ps2_clk_r [4]), + .O(\vga/ps2/ps2_clk_edge_pack_1 ) + ); + defparam \vga/ps2/timer_x<1>1 .INIT = 16'h00AA; + defparam \vga/ps2/timer_x<1>1 .LOC = "CLB_R10C16.S0"; + X_LUT4 \vga/ps2/timer_x<1>1 ( + .ADR0(\vga/ps2/_addsub0000<1>_0 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/ps2/ps2_clk_edge ), + .O(\vga/ps2/timer_x [1]) + ); + defparam \vga/ps2/timer_r<1>/XUSED .LOC = "CLB_R10C16.S0"; + X_BUF \vga/ps2/timer_r<1>/XUSED ( + .I(\vga/ps2/ps2_clk_edge_pack_1 ), + .O(\vga/ps2/ps2_clk_edge ) + ); + defparam \vga/ps2/timer_r_1 .LOC = "CLB_R10C16.S0"; + defparam \vga/ps2/timer_r_1 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_1 ( + .I(\vga/ps2/timer_x [1]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<1>/FFY/RST ), + .O(\vga/ps2/timer_r [1]) + ); + defparam \vga/ps2/timer_r<1>/FFY/RSTOR .LOC = "CLB_R10C16.S0"; + X_INV \vga/ps2/timer_r<1>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/timer_r<1>/FFY/RST ) + ); + defparam \vga/ps2/error_x13 .INIT = 16'hFF7E; + defparam \vga/ps2/error_x13 .LOC = "CLB_R8C19.S0"; + X_LUT4 \vga/ps2/error_x13 ( + .ADR0(\vga/ps2/bitcnt_r [3]), + .ADR1(\vga/ps2/bitcnt_r [0]), + .ADR2(\vga/ps2/bitcnt_r [1]), + .ADR3(\vga/ps2/bitcnt_r [2]), + .O(\vga/ps2/error_x_map855 ) + ); + defparam \vga/ps2/_cmp_eq00001 .INIT = 16'h0080; + defparam \vga/ps2/_cmp_eq00001 .LOC = "CLB_R8C19.S0"; + X_LUT4 \vga/ps2/_cmp_eq00001 ( + .ADR0(\vga/ps2/bitcnt_r [0]), + .ADR1(\vga/ps2/bitcnt_r [1]), + .ADR2(\vga/ps2/bitcnt_r [3]), + .ADR3(\vga/ps2/bitcnt_r [2]), + .O(\vga/ps2/_cmp_eq0000 ) + ); + defparam \vga/ps2/error_x_map855/XUSED .LOC = "CLB_R8C19.S0"; + X_BUF \vga/ps2/error_x_map855/XUSED ( + .I(\vga/ps2/error_x_map855 ), + .O(\vga/ps2/error_x_map855_0 ) + ); + defparam \vga/ps2/error_x_map855/YUSED .LOC = "CLB_R8C19.S0"; + X_BUF \vga/ps2/error_x_map855/YUSED ( + .I(\vga/ps2/_cmp_eq0000 ), + .O(\vga/ps2/_cmp_eq0000_0 ) + ); + defparam \vga/ps2/_cmp_eq00018 .INIT = 16'h0008; + defparam \vga/ps2/_cmp_eq00018 .LOC = "CLB_R8C15.S0"; + X_LUT4 \vga/ps2/_cmp_eq00018 ( + .ADR0(\vga/ps2/timer_r [6]), + .ADR1(\vga/ps2/timer_r [7]), + .ADR2(\vga/ps2/timer_r [4]), + .ADR3(\vga/ps2/timer_r [5]), + .O(\vga/ps2/_cmp_eq0001_map1032 ) + ); + defparam \vga/ps2/_cmp_eq0001_map1032/YUSED .LOC = "CLB_R8C15.S0"; + X_BUF \vga/ps2/_cmp_eq0001_map1032/YUSED ( + .I(\vga/ps2/_cmp_eq0001_map1032 ), + .O(\vga/ps2/_cmp_eq0001_map1032_0 ) + ); + defparam \vga/vgacore/_and00005 .INIT = 16'h8000; + defparam \vga/vgacore/_and00005 .LOC = "CLB_R17C8.S0"; + X_LUT4 \vga/vgacore/_and00005 ( + .ADR0(\vga/vgacore/hcnt [1]), + .ADR1(\vga/vgacore/hcnt [2]), + .ADR2(\vga/vgacore/hcnt [4]), + .ADR3(\vga/vgacore/hcnt [3]), + .O(\vga/vgacore/_and0000_map807_pack_1 ) + ); + defparam \vga/vgacore/_and000015 .INIT = 16'h4404; + defparam \vga/vgacore/_and000015 .LOC = "CLB_R17C8.S0"; + X_LUT4 \vga/vgacore/_and000015 ( + .ADR0(\vga/vgacore/hcnt [8]), + .ADR1(\vga/vgacore/hcnt [7]), + .ADR2(N3132_0), + .ADR3(\vga/vgacore/_and0000_map807 ), + .O(\vga/vgacore/_and0000_map811 ) + ); + defparam \vga/vgacore/_and0000_map807/XUSED .LOC = "CLB_R17C8.S0"; + X_BUF \vga/vgacore/_and0000_map807/XUSED ( + .I(\vga/vgacore/_and0000_map807_pack_1 ), + .O(\vga/vgacore/_and0000_map807 ) + ); + defparam \vga/vgacore/_and0000_map807/YUSED .LOC = "CLB_R17C8.S0"; + X_BUF \vga/vgacore/_and0000_map807/YUSED ( + .I(\vga/vgacore/_and0000_map811 ), + .O(\vga/vgacore/_and0000_map811_0 ) + ); + defparam \vga/vgacore/vcnt_1_1/CKINV .LOC = "CLB_R18C8.S1"; + X_INV \vga/vgacore/vcnt_1_1/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt_1_1/CKMUXNOT ) + ); + defparam \vga/vgacore/vcnt_1_1 .LOC = "CLB_R18C8.S1"; + defparam \vga/vgacore/vcnt_1_1 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_1_1 ( + .I(\vga/vgacore/Result<1>1_0 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt_1_1/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt_1_1/FFY/RST ), + .O(\vga/vgacore/vcnt_1_1_8 ) + ); + defparam \vga/vgacore/vcnt_1_1/FFY/RSTOR .LOC = "CLB_R18C8.S1"; + X_INV \vga/vgacore/vcnt_1_1/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt_1_1/FFY/RST ) + ); + defparam \vga/vgacore/vcnt_2_1/CKINV .LOC = "CLB_R18C8.S0"; + X_INV \vga/vgacore/vcnt_2_1/CKINV ( + .I(\vga/vgacore/hblank_21 ), + .O(\vga/vgacore/vcnt_2_1/CKMUXNOT ) + ); + defparam \vga/vgacore/vcnt_2_1 .LOC = "CLB_R18C8.S0"; + defparam \vga/vgacore/vcnt_2_1 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_2_1 ( + .I(\vga/vgacore/Result<2>1_0 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt_2_1/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt_2_1/FFY/RST ), + .O(\vga/vgacore/vcnt_2_1_9 ) + ); + defparam \vga/vgacore/vcnt_2_1/FFY/RSTOR .LOC = "CLB_R18C8.S0"; + X_INV \vga/vgacore/vcnt_2_1/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt_2_1/FFY/RST ) + ); + defparam \vga/scancode_convert/_not00091 .INIT = 16'h0080; + defparam \vga/scancode_convert/_not00091 .LOC = "CLB_R12C31.S1"; + X_LUT4 \vga/scancode_convert/_not00091 ( + .ADR0(\vga/ps2/sc_r [2]), + .ADR1(\vga/scancode_convert/_and0000_0 ), + .ADR2(\vga/scancode_convert/N10_0 ), + .ADR3(\vga/ps2/sc_r [1]), + .O(\vga/scancode_convert/_not0009 ) + ); + defparam \vga/scancode_convert/_not0009/YUSED .LOC = "CLB_R12C31.S1"; + X_BUF \vga/scancode_convert/_not0009/YUSED ( + .I(\vga/scancode_convert/_not0009 ), + .O(\vga/scancode_convert/_not0009_0 ) + ); + defparam \vga/rom_addr_char<2>3 .INIT = 16'hC808; + defparam \vga/rom_addr_char<2>3 .LOC = "CLB_R15C6.S1"; + X_LUT4 \vga/rom_addr_char<2>3 ( + .ADR0(\vga/N6_0 ), + .ADR1(\vga/rom_addr_char [2]), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N7_0 ), + .O(\vga/N0112_pack_1 ) + ); + defparam \vga/charload317 .INIT = 16'h4540; + defparam \vga/charload317 .LOC = "CLB_R15C6.S1"; + X_LUT4 \vga/charload317 ( + .ADR0(\vga/rom_addr_char [4]), + .ADR1(\vga/N11123_0 ), + .ADR2(\vga/rom_addr_char [3]), + .ADR3(\vga/N0112 ), + .O(\vga/charload3_map953 ) + ); + defparam \vga/N0112/XUSED .LOC = "CLB_R15C6.S1"; + X_BUF \vga/N0112/XUSED ( + .I(\vga/N0112_pack_1 ), + .O(\vga/N0112 ) + ); + defparam \vga/N0112/YUSED .LOC = "CLB_R15C6.S1"; + X_BUF \vga/N0112/YUSED ( + .I(\vga/charload3_map953 ), + .O(\vga/charload3_map953_0 ) + ); + defparam \vga/rom_addr_char<2>6 .INIT = 16'hC480; + defparam \vga/rom_addr_char<2>6 .LOC = "CLB_R10C3.S0"; + X_LUT4 \vga/rom_addr_char<2>6 ( + .ADR0(\vga/rom_addr_char_1_1_7 ), + .ADR1(\vga/rom_addr_char [2]), + .ADR2(\vga/N222_0 ), + .ADR3(\vga/N221_0 ), + .O(\vga/N011234567_pack_1 ) + ); + defparam \vga/rom_addr_char<4>71 .INIT = 16'h0B08; + defparam \vga/rom_addr_char<4>71 .LOC = "CLB_R10C3.S0"; + X_LUT4 \vga/rom_addr_char<4>71 ( + .ADR0(\vga/N1112_0 ), + .ADR1(\vga/rom_addr_char [3]), + .ADR2(\vga/rom_addr_char [4]), + .ADR3(\vga/N011234567 ), + .O(\vga/rom_addr_char<4>11234 ) + ); + defparam \vga/N011234567/XUSED .LOC = "CLB_R10C3.S0"; + X_BUF \vga/N011234567/XUSED ( + .I(\vga/N011234567_pack_1 ), + .O(\vga/N011234567 ) + ); + defparam \vga/N011234567/YUSED .LOC = "CLB_R10C3.S0"; + X_BUF \vga/N011234567/YUSED ( + .I(\vga/rom_addr_char<4>11234 ), + .O(\vga/rom_addr_char<4>11234_0 ) + ); + defparam \vga/charload713 .INIT = 16'hD080; + defparam \vga/charload713 .LOC = "CLB_R12C4.S0"; + X_LUT4 \vga/charload713 ( + .ADR0(\vga/rom_addr_char [4]), + .ADR1(\vga/rom_addr_char<3>_f611234_0 ), + .ADR2(\vga/rom_addr_char [5]), + .ADR3(\vga/rom_addr_char<3>_f612345_0 ), + .O(\vga/charload7_map993 ) + ); + defparam \vga/rom_addr_char<4>1 .INIT = 16'hCFC0; + defparam \vga/rom_addr_char<4>1 .LOC = "CLB_R12C4.S0"; + X_LUT4 \vga/rom_addr_char<4>1 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char<3>_f63_0 ), + .ADR2(\vga/rom_addr_char [4]), + .ADR3(\vga/rom_addr_char<3>_f62_0 ), + .O(\vga/rom_addr_char<4>11_175 ) + ); + defparam \vga/charload7_map993/XUSED .LOC = "CLB_R12C4.S0"; + X_BUF \vga/charload7_map993/XUSED ( + .I(\vga/charload7_map993 ), + .O(\vga/charload7_map993_0 ) + ); + defparam \vga/charload7_map993/YUSED .LOC = "CLB_R12C4.S0"; + X_BUF \vga/charload7_map993/YUSED ( + .I(\vga/rom_addr_char<4>11_175 ), + .O(\vga/rom_addr_char<4>11_0 ) + ); + defparam \vga/scancode_convert/strobe_out .LOC = "CLB_R13C25.S1"; + defparam \vga/scancode_convert/strobe_out .INIT = 1'b0; + X_FF \vga/scancode_convert/strobe_out ( + .I(\vga/scancode_convert/state_FFd2_28 ), + .CE(\vga/scancode_convert/_not0011_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/strobe_out/FFY/RST ), + .O(\vga/scancode_convert/strobe_out_15 ) + ); + defparam \vga/scancode_convert/strobe_out/FFY/RSTOR .LOC = "CLB_R13C25.S1"; + X_INV \vga/scancode_convert/strobe_out/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/scancode_convert/strobe_out/FFY/RST ) + ); + defparam \vga/char_rom/Mrom_data3 .INIT = 16'h1201; + defparam \vga/char_rom/Mrom_data3 .LOC = "CLB_R10C8.S0"; + X_LUT4 \vga/char_rom/Mrom_data3 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N4_pack_1 ) + ); + defparam \vga/rom_addr_char<2>11 .INIT = 16'h4400; + defparam \vga/rom_addr_char<2>11 .LOC = "CLB_R10C8.S0"; + X_LUT4 \vga/rom_addr_char<2>11 ( + .ADR0(\vga/rom_addr_char [2]), + .ADR1(\vga/rom_addr_char_1_1_7 ), + .ADR2(VCC), + .ADR3(\vga/N4 ), + .O(\vga/N1112 ) + ); + defparam \vga/N4/XUSED .LOC = "CLB_R10C8.S0"; + X_BUF \vga/N4/XUSED ( + .I(\vga/N4_pack_1 ), + .O(\vga/N4 ) + ); + defparam \vga/N4/YUSED .LOC = "CLB_R10C8.S0"; + X_BUF \vga/N4/YUSED ( + .I(\vga/N1112 ), + .O(\vga/N1112_0 ) + ); + defparam \vga/char_rom/Mrom_data7 .INIT = 16'h0843; + defparam \vga/char_rom/Mrom_data7 .LOC = "CLB_R15C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data7 ( + .ADR0(\vga/vgacore/vcnt_0_1_17 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_1_1_8 ), + .ADR3(\vga/vgacore/vcnt_2_1_9 ), + .O(\vga/N10 ) + ); + defparam \vga/char_rom/Mrom_data4 .INIT = 16'h0D14; + defparam \vga/char_rom/Mrom_data4 .LOC = "CLB_R15C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data4 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N6 ) + ); + defparam \vga/N10/XUSED .LOC = "CLB_R15C3.S1"; + X_BUF \vga/N10/XUSED ( + .I(\vga/N10 ), + .O(\vga/N10_0 ) + ); + defparam \vga/N10/YUSED .LOC = "CLB_R15C3.S1"; + X_BUF \vga/N10/YUSED ( + .I(\vga/N6 ), + .O(\vga/N6_0 ) + ); + defparam \vga/rom_addr_char<1>113_SW0 .INIT = 16'hCCC0; + defparam \vga/rom_addr_char<1>113_SW0 .LOC = "CLB_R17C6.S0"; + X_LUT4 \vga/rom_addr_char<1>113_SW0 ( + .ADR0(VCC), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(N3170) + ); + defparam \vga/char_rom/Mrom_data5 .INIT = 16'h0040; + defparam \vga/char_rom/Mrom_data5 .LOC = "CLB_R17C6.S0"; + X_LUT4 \vga/char_rom/Mrom_data5 ( + .ADR0(\vga/vgacore/vcnt_1_1_8 ), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(\vga/vgacore/vcnt_2_1_9 ), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(\vga/N7 ) + ); + defparam \N3170/XUSED .LOC = "CLB_R17C6.S0"; + X_BUF \N3170/XUSED ( + .I(N3170), + .O(N3170_0) + ); + defparam \N3170/YUSED .LOC = "CLB_R17C6.S0"; + X_BUF \N3170/YUSED ( + .I(\vga/N7 ), + .O(\vga/N7_0 ) + ); + defparam \vga/char_rom/Mrom_data6 .INIT = 16'h1050; + defparam \vga/char_rom/Mrom_data6 .LOC = "CLB_R20C6.S0"; + X_LUT4 \vga/char_rom/Mrom_data6 ( + .ADR0(\vga/rom_addr_char_0_1_18 ), + .ADR1(\vga/vgacore/vcnt_2_1_9 ), + .ADR2(\vga/vgacore/vcnt_0_1_17 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N8_pack_1 ) + ); + defparam \vga/rom_addr_char<2>12 .INIT = 16'h5000; + defparam \vga/rom_addr_char<2>12 .LOC = "CLB_R20C6.S0"; + X_LUT4 \vga/rom_addr_char<2>12 ( + .ADR0(\vga/rom_addr_char [2]), + .ADR1(VCC), + .ADR2(\vga/rom_addr_char_1_1_7 ), + .ADR3(\vga/N8 ), + .O(\vga/N11123 ) + ); + defparam \vga/N8/XUSED .LOC = "CLB_R20C6.S0"; + X_BUF \vga/N8/XUSED ( + .I(\vga/N8_pack_1 ), + .O(\vga/N8 ) + ); + defparam \vga/N8/YUSED .LOC = "CLB_R20C6.S0"; + X_BUF \vga/N8/YUSED ( + .I(\vga/N11123 ), + .O(\vga/N11123_0 ) + ); + defparam \vga/rom_addr_char<1>121_SW0 .INIT = 16'hDFEB; + defparam \vga/rom_addr_char<1>121_SW0 .LOC = "CLB_R21C3.S1"; + X_LUT4 \vga/rom_addr_char<1>121_SW0 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/rom_addr_char [1]), + .ADR2(\vga/rom_addr_char_0_1_18 ), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(N3160) + ); + defparam \vga/char_rom/Mrom_data9 .INIT = 16'h0022; + defparam \vga/char_rom/Mrom_data9 .LOC = "CLB_R21C3.S1"; + X_LUT4 \vga/char_rom/Mrom_data9 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(\vga/N12 ) + ); + defparam \N3160/XUSED .LOC = "CLB_R21C3.S1"; + X_BUF \N3160/XUSED ( + .I(N3160), + .O(N3160_0) + ); + defparam \N3160/YUSED .LOC = "CLB_R21C3.S1"; + X_BUF \N3160/YUSED ( + .I(\vga/N12 ), + .O(\vga/N12_0 ) + ); + defparam \vga/crt/state_Out911 .INIT = 16'h33FF; + defparam \vga/crt/state_Out911 .LOC = "CLB_R14C13.S0"; + X_LUT4 \vga/crt/state_Out911 ( + .ADR0(VCC), + .ADR1(\vga/crt/state_FFd3_11 ), + .ADR2(VCC), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(\vga/crt/N91_pack_1 ) + ); + defparam \vga/crt/_mux0002<6>1 .INIT = 16'h3CAA; + defparam \vga/crt/_mux0002<6>1 .LOC = "CLB_R14C13.S0"; + X_LUT4 \vga/crt/_mux0002<6>1 ( + .ADR0(\vga/crt_data [6]), + .ADR1(\vga/crt/cursor_h [5]), + .ADR2(\vga/crt/cursor_h [6]), + .ADR3(\vga/crt/N91 ), + .O(\vga/crt/_mux0002 [6]) + ); + defparam \vga/crt/ram_data<6>/XUSED .LOC = "CLB_R14C13.S0"; + X_BUF \vga/crt/ram_data<6>/XUSED ( + .I(\vga/crt/N91_pack_1 ), + .O(\vga/crt/N91 ) + ); + defparam \vga/crt/state_FFd3-In37 .INIT = 16'h2F0F; + defparam \vga/crt/state_FFd3-In37 .LOC = "CLB_R16C16.S0"; + X_LUT4 \vga/crt/state_FFd3-In37 ( + .ADR0(\vga/crt/write_delay [1]), + .ADR1(\vga/crt/write_delay [2]), + .ADR2(\vga/crt/state_FFd1_13 ), + .ADR3(\vga/crt/write_delay [0]), + .O(\vga/crt/state_FFd3-In_map800_pack_1 ) + ); + defparam \vga/crt/state_FFd3-In48 .INIT = 16'hF5F0; + defparam \vga/crt/state_FFd3-In48 .LOC = "CLB_R16C16.S0"; + X_LUT4 \vga/crt/state_FFd3-In48 ( + .ADR0(\vga/crt/state_FFd3_11 ), + .ADR1(VCC), + .ADR2(N3144_0), + .ADR3(\vga/crt/state_FFd3-In_map800 ), + .O(\vga/crt/state_FFd3-In ) + ); + defparam \vga/crt/state_FFd3/XUSED .LOC = "CLB_R16C16.S0"; + X_BUF \vga/crt/state_FFd3/XUSED ( + .I(\vga/crt/state_FFd3-In_map800_pack_1 ), + .O(\vga/crt/state_FFd3-In_map800 ) + ); + defparam \vga/crt/state_FFd3 .LOC = "CLB_R16C16.S0"; + defparam \vga/crt/state_FFd3 .INIT = 1'b0; + X_FF \vga/crt/state_FFd3 ( + .I(\vga/crt/state_FFd3-In ), + .CE(VCC), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/state_FFd3/FFY/RST ), + .O(\vga/crt/state_FFd3_11 ) + ); + defparam \vga/crt/state_FFd3/FFY/RSTOR .LOC = "CLB_R16C16.S0"; + X_INV \vga/crt/state_FFd3/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/state_FFd3/FFY/RST ) + ); + defparam \vga/insert_crt_data1 .INIT = 16'h5050; + defparam \vga/insert_crt_data1 .LOC = "CLB_R16C18.S0"; + X_LUT4 \vga/insert_crt_data1 ( + .ADR0(\vga/scancode_convert/key_up_14 ), + .ADR1(VCC), + .ADR2(\vga/scancode_convert/strobe_out_15 ), + .ADR3(VCC), + .O(\vga/insert_crt_data_pack_1 ) + ); + defparam \vga/crt/state_FFd1-In_SW0 .INIT = 16'hA00C; + defparam \vga/crt/state_FFd1-In_SW0 .LOC = "CLB_R16C18.S0"; + X_LUT4 \vga/crt/state_FFd1-In_SW0 ( + .ADR0(\vga/insert_crt_data ), + .ADR1(\vga/crt/state_FFd1_13 ), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/state_FFd2_12 ), + .O(N116) + ); + defparam \vga/insert_crt_data/XUSED .LOC = "CLB_R16C18.S0"; + X_BUF \vga/insert_crt_data/XUSED ( + .I(\vga/insert_crt_data_pack_1 ), + .O(\vga/insert_crt_data ) + ); + defparam \vga/insert_crt_data/YUSED .LOC = "CLB_R16C18.S0"; + X_BUF \vga/insert_crt_data/YUSED ( + .I(N116), + .O(N116_0) + ); + defparam \vga/crt/state_FFd1-In_SW1 .INIT = 16'hF380; + defparam \vga/crt/state_FFd1-In_SW1 .LOC = "CLB_R16C17.S1"; + X_LUT4 \vga/crt/state_FFd1-In_SW1 ( + .ADR0(\vga/insert_crt_data ), + .ADR1(\vga/crt/state_FFd2_12 ), + .ADR2(\vga/crt/state_FFd3_11 ), + .ADR3(\vga/crt/state_FFd1_13 ), + .O(N117_pack_1) + ); + defparam \vga/crt/state_FFd1-In .INIT = 16'hFE02; + defparam \vga/crt/state_FFd1-In .LOC = "CLB_R16C17.S1"; + X_LUT4 \vga/crt/state_FFd1-In ( + .ADR0(N116_0), + .ADR1(\vga/crt/_cmp_eq0001_0 ), + .ADR2(\vga/crt/newline_20 ), + .ADR3(N117), + .O(\vga/crt/state_FFd1-In_176 ) + ); + defparam \vga/crt/state_FFd1/XUSED .LOC = "CLB_R16C17.S1"; + X_BUF \vga/crt/state_FFd1/XUSED ( + .I(N117_pack_1), + .O(N117) + ); + defparam \vga/crt/state_FFd1 .LOC = "CLB_R16C17.S1"; + defparam \vga/crt/state_FFd1 .INIT = 1'b0; + X_FF \vga/crt/state_FFd1 ( + .I(\vga/crt/state_FFd1-In_176 ), + .CE(VCC), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/state_FFd1/FFY/RST ), + .O(\vga/crt/state_FFd1_13 ) + ); + defparam \vga/crt/state_FFd1/FFY/RSTOR .LOC = "CLB_R16C17.S1"; + X_INV \vga/crt/state_FFd1/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/state_FFd1/FFY/RST ) + ); + defparam \vga/crt/_cmp_eq000111 .INIT = 16'h0002; + defparam \vga/crt/_cmp_eq000111 .LOC = "CLB_R16C16.S1"; + X_LUT4 \vga/crt/_cmp_eq000111 ( + .ADR0(\vga/crt_data [3]), + .ADR1(\vga/crt_data [5]), + .ADR2(\vga/crt_data [6]), + .ADR3(\vga/crt_data [4]), + .O(\vga/crt/N16_pack_1 ) + ); + defparam \vga/crt/_and0000_SW1 .INIT = 16'hBFFF; + defparam \vga/crt/_and0000_SW1 .LOC = "CLB_R16C16.S1"; + X_LUT4 \vga/crt/_and0000_SW1 ( + .ADR0(\vga/crt_data [1]), + .ADR1(\vga/crt/state_FFd1_13 ), + .ADR2(\vga/crt_data [0]), + .ADR3(\vga/crt/N16 ), + .O(N306) + ); + defparam \vga/crt/N16/XUSED .LOC = "CLB_R16C16.S1"; + X_BUF \vga/crt/N16/XUSED ( + .I(\vga/crt/N16_pack_1 ), + .O(\vga/crt/N16 ) + ); + defparam \vga/crt/N16/YUSED .LOC = "CLB_R16C16.S1"; + X_BUF \vga/crt/N16/YUSED ( + .I(N306), + .O(N306_0) + ); + defparam \vga/rom_addr_char<1>/CKINV .LOC = "CLB_R16C1.S0"; + X_INV \vga/rom_addr_char<1>/CKINV ( + .I(\vga/pclk [2]), + .O(\vga/rom_addr_char<1>/CKMUXNOT ) + ); + defparam \vga/rom_addr_char_0 .LOC = "CLB_R16C1.S0"; + defparam \vga/rom_addr_char_0 .INIT = 1'b0; + X_FF \vga/rom_addr_char_0 ( + .I(\vga/ram_data_out [0]), + .CE(VCC), + .CLK(\vga/rom_addr_char<1>/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char [0]) + ); + defparam \vga/rom_addr_char<3>/CKINV .LOC = "CLB_R27C1.S0"; + X_INV \vga/rom_addr_char<3>/CKINV ( + .I(\vga/pclk [2]), + .O(\vga/rom_addr_char<3>/CKMUXNOT ) + ); + defparam \vga/rom_addr_char_2 .LOC = "CLB_R27C1.S0"; + defparam \vga/rom_addr_char_2 .INIT = 1'b0; + X_FF \vga/rom_addr_char_2 ( + .I(\vga/ram_data_out [2]), + .CE(VCC), + .CLK(\vga/rom_addr_char<3>/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char [2]) + ); + defparam \vga/rom_addr_char<5>/CKINV .LOC = "CLB_R12C1.S0"; + X_INV \vga/rom_addr_char<5>/CKINV ( + .I(\vga/pclk [2]), + .O(\vga/rom_addr_char<5>/CKMUXNOT ) + ); + defparam \vga/rom_addr_char_4 .LOC = "CLB_R12C1.S0"; + defparam \vga/rom_addr_char_4 .INIT = 1'b0; + X_FF \vga/rom_addr_char_4 ( + .I(\vga/ram_data_out [4]), + .CE(VCC), + .CLK(\vga/rom_addr_char<5>/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char [4]) + ); + defparam \vga/rom_addr_char<6>/CKINV .LOC = "CLB_R8C1.S0"; + X_INV \vga/rom_addr_char<6>/CKINV ( + .I(\vga/pclk [2]), + .O(\vga/rom_addr_char<6>/CKMUXNOT ) + ); + defparam \vga/rom_addr_char_6 .LOC = "CLB_R8C1.S0"; + defparam \vga/rom_addr_char_6 .INIT = 1'b0; + X_FF \vga/rom_addr_char_6 ( + .I(\vga/ram_data_out [6]), + .CE(VCC), + .CLK(\vga/rom_addr_char<6>/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char [6]) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1158 .INIT = 16'hF4F7; + defparam \vga/scancode_convert/scancode_rom/data<0>1158 .LOC = "CLB_R15C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>1158 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/sc [3]), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1461 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>119 .INIT = 16'hAEEA; + defparam \vga/scancode_convert/scancode_rom/data<0>119 .LOC = "CLB_R15C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>119 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1429 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1_map1461/XUSED .LOC = "CLB_R15C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1_map1461/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1461 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1461_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1_map1461/YUSED .LOC = "CLB_R15C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1_map1461/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1429 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1429_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>101 .INIT = 16'hBBDD; + defparam \vga/scancode_convert/scancode_rom/data<1>101 .LOC = "CLB_R15C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<1>101 ( + .ADR0(\vga/scancode_convert/sc [0]), + .ADR1(\vga/scancode_convert/sc [1]), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/N28 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>241 .INIT = 16'hAA55; + defparam \vga/scancode_convert/scancode_rom/data<0>241 .LOC = "CLB_R15C35.S0"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>241 ( + .ADR0(\vga/scancode_convert/sc [1]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/N18 ) + ); + defparam \vga/scancode_convert/scancode_rom/N28/XUSED .LOC = "CLB_R15C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N28/XUSED ( + .I(\vga/scancode_convert/scancode_rom/N28 ), + .O(\vga/scancode_convert/scancode_rom/N28_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/N28/YUSED .LOC = "CLB_R15C35.S0"; + X_BUF \vga/scancode_convert/scancode_rom/N28/YUSED ( + .I(\vga/scancode_convert/scancode_rom/N18 ), + .O(\vga/scancode_convert/scancode_rom/N18_0 ) + ); + defparam \vga/scancode_convert/sc_0 .LOC = "CLB_R14C35.S0"; + defparam \vga/scancode_convert/sc_0 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_0 ( + .I(\vga/ps2/sc_r [0]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc [0]) + ); + defparam \vga/scancode_convert/sc_2 .LOC = "CLB_R13C34.S1"; + defparam \vga/scancode_convert/sc_2 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_2 ( + .I(\vga/ps2/sc_r [2]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc [2]) + ); + defparam \vga/scancode_convert/sc_4 .LOC = "CLB_R10C35.S0"; + defparam \vga/scancode_convert/sc_4 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_4 ( + .I(\vga/ps2/sc_r [4]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc [4]) + ); + defparam \vga/scancode_convert/sc_6 .LOC = "CLB_R11C30.S0"; + defparam \vga/scancode_convert/sc_6 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_6 ( + .I(\vga/ps2/sc_r [6]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc [6]) + ); + defparam \vga/ps2/sc_r<1>/FFX/RSTOR .LOC = "CLB_R11C28.S1"; + X_BUF \vga/ps2/sc_r<1>/FFX/RSTOR ( + .I(\vga/ps2/sc_r<1>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<1>/FFX/RST ) + ); + defparam \vga/ps2/sc_r_1 .LOC = "CLB_R11C28.S1"; + defparam \vga/ps2/sc_r_1 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_1 ( + .I(\vga/ps2/sc_r [2]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<1>/FFX/RST ), + .O(\vga/ps2/sc_r [1]) + ); + defparam \vga/ps2/sc_r<1>/SRMUX .LOC = "CLB_R11C28.S1"; + X_INV \vga/ps2/sc_r<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/sc_r<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/sc_r_0 .LOC = "CLB_R11C28.S1"; + defparam \vga/ps2/sc_r_0 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_0 ( + .I(\vga/ps2/sc_r [1]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<1>/FFY/RST ), + .O(\vga/ps2/sc_r [0]) + ); + defparam \vga/ps2/sc_r<1>/FFY/RSTOR .LOC = "CLB_R11C28.S1"; + X_BUF \vga/ps2/sc_r<1>/FFY/RSTOR ( + .I(\vga/ps2/sc_r<1>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<1>/FFY/RST ) + ); + defparam \vga/ps2/sc_r<3>/FFX/RSTOR .LOC = "CLB_R11C29.S1"; + X_BUF \vga/ps2/sc_r<3>/FFX/RSTOR ( + .I(\vga/ps2/sc_r<3>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<3>/FFX/RST ) + ); + defparam \vga/ps2/sc_r_3 .LOC = "CLB_R11C29.S1"; + defparam \vga/ps2/sc_r_3 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_3 ( + .I(\vga/ps2/sc_r [4]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<3>/FFX/RST ), + .O(\vga/ps2/sc_r [3]) + ); + defparam \vga/ps2/sc_r<3>/SRMUX .LOC = "CLB_R11C29.S1"; + X_INV \vga/ps2/sc_r<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/sc_r<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/sc_r_2 .LOC = "CLB_R11C29.S1"; + defparam \vga/ps2/sc_r_2 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_2 ( + .I(\vga/ps2/sc_r [3]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<3>/FFY/RST ), + .O(\vga/ps2/sc_r [2]) + ); + defparam \vga/ps2/sc_r<3>/FFY/RSTOR .LOC = "CLB_R11C29.S1"; + X_BUF \vga/ps2/sc_r<3>/FFY/RSTOR ( + .I(\vga/ps2/sc_r<3>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<3>/FFY/RST ) + ); + defparam \vga/ps2/sc_r<5>/FFX/RSTOR .LOC = "CLB_R10C28.S1"; + X_BUF \vga/ps2/sc_r<5>/FFX/RSTOR ( + .I(\vga/ps2/sc_r<5>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<5>/FFX/RST ) + ); + defparam \vga/ps2/sc_r_5 .LOC = "CLB_R10C28.S1"; + defparam \vga/ps2/sc_r_5 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_5 ( + .I(\vga/ps2/sc_r [6]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<5>/FFX/RST ), + .O(\vga/ps2/sc_r [5]) + ); + defparam \vga/ps2/sc_r<5>/SRMUX .LOC = "CLB_R10C28.S1"; + X_INV \vga/ps2/sc_r<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/sc_r<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/sc_r_4 .LOC = "CLB_R10C28.S1"; + defparam \vga/ps2/sc_r_4 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_4 ( + .I(\vga/ps2/sc_r [5]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<5>/FFY/RST ), + .O(\vga/ps2/sc_r [4]) + ); + defparam \vga/ps2/sc_r<5>/FFY/RSTOR .LOC = "CLB_R10C28.S1"; + X_BUF \vga/ps2/sc_r<5>/FFY/RSTOR ( + .I(\vga/ps2/sc_r<5>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<5>/FFY/RST ) + ); + defparam \vga/ps2/sc_r<7>/FFX/RSTOR .LOC = "CLB_R10C28.S0"; + X_BUF \vga/ps2/sc_r<7>/FFX/RSTOR ( + .I(\vga/ps2/sc_r<7>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<7>/FFX/RST ) + ); + defparam \vga/ps2/sc_r_7 .LOC = "CLB_R10C28.S0"; + defparam \vga/ps2/sc_r_7 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_7 ( + .I(\vga/ps2/sc_r [8]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<7>/FFX/RST ), + .O(\vga/ps2/sc_r [7]) + ); + defparam \vga/ps2/sc_r<7>/SRMUX .LOC = "CLB_R10C28.S0"; + X_INV \vga/ps2/sc_r<7>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/sc_r<7>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/ps2/sc_r_6 .LOC = "CLB_R10C28.S0"; + defparam \vga/ps2/sc_r_6 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_6 ( + .I(\vga/ps2/sc_r [7]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<7>/FFY/RST ), + .O(\vga/ps2/sc_r [6]) + ); + defparam \vga/ps2/sc_r<7>/FFY/RSTOR .LOC = "CLB_R10C28.S0"; + X_BUF \vga/ps2/sc_r<7>/FFY/RSTOR ( + .I(\vga/ps2/sc_r<7>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/sc_r<7>/FFY/RST ) + ); + defparam \vga/ps2/sc_r_8 .LOC = "CLB_R9C7.S1"; + defparam \vga/ps2/sc_r_8 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_8 ( + .I(\vga/ps2/sc_r [9]), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/sc_r<8>/FFY/RST ), + .O(\vga/ps2/sc_r [8]) + ); + defparam \vga/ps2/sc_r<8>/FFY/RSTOR .LOC = "CLB_R9C7.S1"; + X_INV \vga/ps2/sc_r<8>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/sc_r<8>/FFY/RST ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>327 .INIT = 16'h0288; + defparam \vga/scancode_convert/scancode_rom/data<5>327 .LOC = "CLB_R12C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>327 ( + .ADR0(\vga/scancode_convert/sc [4]), + .ADR1(\vga/scancode_convert/sc_1_1_23 ), + .ADR2(\vga/scancode_convert/raise1_33 ), + .ADR3(\vga/scancode_convert/sc_0_1_10 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1245 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>341 .INIT = 16'hFF0C; + defparam \vga/scancode_convert/scancode_rom/data<5>341 .LOC = "CLB_R12C34.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<5>341 ( + .ADR0(VCC), + .ADR1(\vga/scancode_convert/sc_1_1_23 ), + .ADR2(\vga/scancode_convert/sc_0_1_10 ), + .ADR3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1249 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3_map1245/XUSED .LOC = "CLB_R12C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3_map1245/XUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1245 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1245_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3_map1245/YUSED .LOC = "CLB_R12C34.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<5>3_map1245/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<5>3_map1249 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1249_0 ) + ); + defparam \vga/vgacore/vcnt_Eqn_3_SW0 .INIT = 16'hEAEA; + defparam \vga/vgacore/vcnt_Eqn_3_SW0 .LOC = "CLB_R17C10.S0"; + X_LUT4 \vga/vgacore/vcnt_Eqn_3_SW0 ( + .ADR0(\vga/vgacore/vcnt [2]), + .ADR1(\vga/vgacore/vcnt [0]), + .ADR2(\vga/vgacore/vcnt [1]), + .ADR3(VCC), + .O(N786) + ); + defparam \N786/YUSED .LOC = "CLB_R17C10.S0"; + X_BUF \N786/YUSED ( + .I(N786), + .O(N786_0) + ); + defparam \vga/vgacore/vcnt_Eqn_bis_021_SW0 .INIT = 16'hFFFE; + defparam \vga/vgacore/vcnt_Eqn_bis_021_SW0 .LOC = "CLB_R15C9.S0"; + X_LUT4 \vga/vgacore/vcnt_Eqn_bis_021_SW0 ( + .ADR0(\vga/vgacore/vcnt [7]), + .ADR1(\vga/vgacore/vcnt [6]), + .ADR2(\vga/vgacore/vcnt [5]), + .ADR3(\vga/vgacore/vcnt [4]), + .O(N3108) + ); + defparam \vga/_and0000129 .INIT = 16'h8241; + defparam \vga/_and0000129 .LOC = "CLB_R15C9.S0"; + X_LUT4 \vga/_and0000129 ( + .ADR0(\vga/crt/cursor_v [1]), + .ADR1(\vga/crt/cursor_v [0]), + .ADR2(\vga/vgacore/vcnt [3]), + .ADR3(\vga/vgacore/vcnt [4]), + .O(\vga/_and0000_map918 ) + ); + defparam \N3108/XUSED .LOC = "CLB_R15C9.S0"; + X_BUF \N3108/XUSED ( + .I(N3108), + .O(N3108_0) + ); + defparam \N3108/YUSED .LOC = "CLB_R15C9.S0"; + X_BUF \N3108/YUSED ( + .I(\vga/_and0000_map918 ), + .O(\vga/_and0000_map918_0 ) + ); + defparam \vga/scancode_convert/_or00001 .INIT = 16'hFFAA; + defparam \vga/scancode_convert/_or00001 .LOC = "CLB_R13C30.S0"; + X_LUT4 \vga/scancode_convert/_or00001 ( + .ADR0(\vga/scancode_convert/state_FFd3_29 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/scancode_convert/state_FFd2_28 ), + .O(\vga/scancode_convert/_or0000 ) + ); + defparam \vga/scancode_convert/_or0000/YUSED .LOC = "CLB_R13C30.S0"; + X_BUF \vga/scancode_convert/_or0000/YUSED ( + .I(\vga/scancode_convert/_or0000 ), + .O(\vga/scancode_convert/_or0000_0 ) + ); + defparam \vga/charload6111 .INIT = 16'hD888; + defparam \vga/charload6111 .LOC = "CLB_R13C9.S1"; + X_LUT4 \vga/charload6111 ( + .ADR0(\vga/rom_addr_char [6]), + .ADR1(\vga/rom_addr_char<5>_f512_0 ), + .ADR2(\vga/charload6_map1018_0 ), + .ADR3(\vga/rom_addr_char [5]), + .O(\vga/charload6_map1022_pack_1 ) + ); + defparam \vga/charload6153 .INIT = 16'hEEE2; + defparam \vga/charload6153 .LOC = "CLB_R13C9.S1"; + X_LUT4 \vga/charload6153 ( + .ADR0(\vga/pixel_hold [3]), + .ADR1(\vga/charload_19 ), + .ADR2(\vga/cursor_match_0 ), + .ADR3(\vga/charload6_map1022 ), + .O(\vga/_mux0002 [3]) + ); + defparam \vga/pixel_hold<4>/XUSED .LOC = "CLB_R13C9.S1"; + X_BUF \vga/pixel_hold<4>/XUSED ( + .I(\vga/charload6_map1022_pack_1 ), + .O(\vga/charload6_map1022 ) + ); + defparam \vga/pixel_hold_4 .LOC = "CLB_R13C9.S1"; + defparam \vga/pixel_hold_4 .INIT = 1'b0; + X_FF \vga/pixel_hold_4 ( + .I(\vga/_mux0002 [3]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [4]) + ); + defparam \vga/_and0000156 .INIT = 16'h9009; + defparam \vga/_and0000156 .LOC = "CLB_R15C10.S0"; + X_LUT4 \vga/_and0000156 ( + .ADR0(\vga/crt/cursor_v [3]), + .ADR1(\vga/vgacore/vcnt [6]), + .ADR2(\vga/crt/cursor_v [2]), + .ADR3(\vga/vgacore/vcnt [5]), + .O(\vga/_and0000_map929 ) + ); + defparam \vga/_and0000_map929/YUSED .LOC = "CLB_R15C10.S0"; + X_BUF \vga/_and0000_map929/YUSED ( + .I(\vga/_and0000_map929 ), + .O(\vga/_and0000_map929_0 ) + ); + defparam \vga/pixelData<0>/LOGIC_ONE .LOC = "CLB_R12C8.S1"; + X_ONE \vga/pixelData<0>/LOGIC_ONE ( + .O(\vga/pixelData<0>/LOGIC_ONE_177 ) + ); + defparam \vga/pixelData<0>/SRMUX .LOC = "CLB_R12C8.S1"; + X_INV \vga/pixelData<0>/SRMUX ( + .I(\vga/pixel_hold [7]), + .O(\vga/pixelData<0>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/pixelData_0 .LOC = "CLB_R12C8.S1"; + defparam \vga/pixelData_0 .INIT = 1'b0; + X_SFF \vga/pixelData_0 ( + .I(\vga/pixelData<0>/LOGIC_ONE_177 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .SSET(GND), + .SRST(\vga/pixelData<0>/SRMUX_OUTPUTNOT ), + .O(\vga/pixelData [0]) + ); + defparam \vga/ps2/_cmp_eq000112 .INIT = 16'h000F; + defparam \vga/ps2/_cmp_eq000112 .LOC = "CLB_R6C17.S1"; + X_LUT4 \vga/ps2/_cmp_eq000112 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/timer_r [12]), + .ADR3(\vga/ps2/timer_r [13]), + .O(\vga/ps2/_cmp_eq0001_map1035 ) + ); + defparam \vga/ps2/_cmp_eq0001_map1035/YUSED .LOC = "CLB_R6C17.S1"; + X_BUF \vga/ps2/_cmp_eq0001_map1035/YUSED ( + .I(\vga/ps2/_cmp_eq0001_map1035 ), + .O(\vga/ps2/_cmp_eq0001_map1035_0 ) + ); + defparam \vga/_and0000183 .INIT = 16'h8241; + defparam \vga/_and0000183 .LOC = "CLB_R13C10.S0"; + X_LUT4 \vga/_and0000183 ( + .ADR0(\vga/crt/cursor_v [4]), + .ADR1(\vga/vgacore/vcnt [8]), + .ADR2(\vga/crt/cursor_v [5]), + .ADR3(\vga/vgacore/vcnt [7]), + .O(\vga/_and0000_map940 ) + ); + defparam \vga/_and0000_map940/YUSED .LOC = "CLB_R13C10.S0"; + X_BUF \vga/_and0000_map940/YUSED ( + .I(\vga/_and0000_map940 ), + .O(\vga/_and0000_map940_0 ) + ); + defparam \vga/_and0000184 .INIT = 16'hCC00; + defparam \vga/_and0000184 .LOC = "CLB_R14C10.S0"; + X_LUT4 \vga/_and0000184 ( + .ADR0(VCC), + .ADR1(\vga/_and0000_map940_0 ), + .ADR2(VCC), + .ADR3(\vga/_and0000_map929_0 ), + .O(\vga/_and0000_map941_pack_1 ) + ); + defparam \vga/_and0000215 .INIT = 16'h8200; + defparam \vga/_and0000215 .LOC = "CLB_R14C10.S0"; + X_LUT4 \vga/_and0000215 ( + .ADR0(\vga/_and0000_map918_0 ), + .ADR1(\vga/vgacore/hcnt [9]), + .ADR2(\vga/crt/cursor_h [6]), + .ADR3(\vga/_and0000_map941 ), + .O(\vga/_and0000_map943 ) + ); + defparam \vga/_and0000_map941/XUSED .LOC = "CLB_R14C10.S0"; + X_BUF \vga/_and0000_map941/XUSED ( + .I(\vga/_and0000_map941_pack_1 ), + .O(\vga/_and0000_map941 ) + ); + defparam \vga/_and0000_map941/YUSED .LOC = "CLB_R14C10.S0"; + X_BUF \vga/_and0000_map941/YUSED ( + .I(\vga/_and0000_map943 ), + .O(\vga/_and0000_map943_0 ) + ); + defparam \vga/ps2/_cmp_eq000130 .INIT = 16'h0200; + defparam \vga/ps2/_cmp_eq000130 .LOC = "CLB_R7C17.S1"; + X_LUT4 \vga/ps2/_cmp_eq000130 ( + .ADR0(\vga/ps2/timer_r [11]), + .ADR1(\vga/ps2/timer_r [10]), + .ADR2(\vga/ps2/timer_r [9]), + .ADR3(\vga/ps2/timer_r [8]), + .O(\vga/ps2/_cmp_eq0001_map1041 ) + ); + defparam \vga/ps2/_cmp_eq0001_map1041/YUSED .LOC = "CLB_R7C17.S1"; + X_BUF \vga/ps2/_cmp_eq0001_map1041/YUSED ( + .I(\vga/ps2/_cmp_eq0001_map1041 ), + .O(\vga/ps2/_cmp_eq0001_map1041_0 ) + ); + defparam \vga/rom_addr_char_0_1/CKINV .LOC = "CLB_R16C1.S1"; + X_INV \vga/rom_addr_char_0_1/CKINV ( + .I(\vga/pclk [2]), + .O(\vga/rom_addr_char_0_1/CKMUXNOT ) + ); + defparam \vga/rom_addr_char_0_1 .LOC = "CLB_R16C1.S1"; + defparam \vga/rom_addr_char_0_1 .INIT = 1'b0; + X_FF \vga/rom_addr_char_0_1 ( + .I(\vga/ram_data_out [0]), + .CE(VCC), + .CLK(\vga/rom_addr_char_0_1/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char_0_1_18 ) + ); + defparam \vga/rom_addr_char_1_1/CKINV .LOC = "CLB_R17C1.S1"; + X_INV \vga/rom_addr_char_1_1/CKINV ( + .I(\vga/pclk [2]), + .O(\vga/rom_addr_char_1_1/CKMUXNOT ) + ); + defparam \vga/rom_addr_char_1_1 .LOC = "CLB_R17C1.S1"; + defparam \vga/rom_addr_char_1_1 .INIT = 1'b0; + X_FF \vga/rom_addr_char_1_1 ( + .I(\vga/ram_data_out [1]), + .CE(VCC), + .CLK(\vga/rom_addr_char_1_1/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char_1_1_7 ) + ); + defparam \vga/ps2/_cmp_eq000156 .INIT = 16'h8000; + defparam \vga/ps2/_cmp_eq000156 .LOC = "CLB_R8C18.S0"; + X_LUT4 \vga/ps2/_cmp_eq000156 ( + .ADR0(\vga/ps2/_cmp_eq0001_map1047_0 ), + .ADR1(\vga/ps2/_cmp_eq0001_map1041_0 ), + .ADR2(\vga/ps2/_cmp_eq0001_map1032_0 ), + .ADR3(\vga/ps2/_cmp_eq0001_map1035_0 ), + .O(\vga/ps2/_cmp_eq0001_pack_1 ) + ); + defparam \vga/ps2/scancode_rdy1 .INIT = 16'hA000; + defparam \vga/ps2/scancode_rdy1 .LOC = "CLB_R8C18.S0"; + X_LUT4 \vga/ps2/scancode_rdy1 ( + .ADR0(\vga/ps2/ps2_clk_r [1]), + .ADR1(VCC), + .ADR2(\vga/ps2/_cmp_eq0000_0 ), + .ADR3(\vga/ps2/_cmp_eq0001 ), + .O(\vga/ps2/scancode_rdy ) + ); + defparam \vga/ps2/rdy_r/XUSED .LOC = "CLB_R8C18.S0"; + X_BUF \vga/ps2/rdy_r/XUSED ( + .I(\vga/ps2/_cmp_eq0001_pack_1 ), + .O(\vga/ps2/_cmp_eq0001 ) + ); + defparam \vga/ps2/rdy_r .LOC = "CLB_R8C18.S0"; + defparam \vga/ps2/rdy_r .INIT = 1'b0; + X_FF \vga/ps2/rdy_r ( + .I(\vga/ps2/scancode_rdy ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/rdy_r/FFY/RST ), + .O(\vga/ps2/rdy_r_1 ) + ); + defparam \vga/ps2/rdy_r/FFY/RSTOR .LOC = "CLB_R8C18.S0"; + X_INV \vga/ps2/rdy_r/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ps2/rdy_r/FFY/RST ) + ); + defparam \vga/crt/_cmp_eq00011 .INIT = 16'h0020; + defparam \vga/crt/_cmp_eq00011 .LOC = "CLB_R16C17.S0"; + X_LUT4 \vga/crt/_cmp_eq00011 ( + .ADR0(\vga/crt/N16 ), + .ADR1(\vga/crt_data [0]), + .ADR2(\vga/crt_data [1]), + .ADR3(\vga/crt_data [2]), + .O(\vga/crt/_cmp_eq0001 ) + ); + defparam \vga/crt/_cmp_eq0001/YUSED .LOC = "CLB_R16C17.S0"; + X_BUF \vga/crt/_cmp_eq0001/YUSED ( + .I(\vga/crt/_cmp_eq0001 ), + .O(\vga/crt/_cmp_eq0001_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>14 .INIT = 16'h8000; + defparam \vga/scancode_convert/scancode_rom/data<0>14 .LOC = "CLB_R15C33.S1"; + X_LUT4 \vga/scancode_convert/scancode_rom/data<0>14 ( + .ADR0(\vga/scancode_convert/sc [3]), + .ADR1(\vga/scancode_convert/sc [4]), + .ADR2(\vga/scancode_convert/sc [0]), + .ADR3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1423 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1_map1423/YUSED .LOC = "CLB_R15C33.S1"; + X_BUF \vga/scancode_convert/scancode_rom/data<0>1_map1423/YUSED ( + .I(\vga/scancode_convert/scancode_rom/data<0>1_map1423 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1423_0 ) + ); + defparam \vga/vgacore/_and000015_SW0 .INIT = 16'h0055; + defparam \vga/vgacore/_and000015_SW0 .LOC = "CLB_R15C8.S1"; + X_LUT4 \vga/vgacore/_and000015_SW0 ( + .ADR0(\vga/vgacore/hcnt [6]), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(\vga/vgacore/hcnt [5]), + .O(N3132) + ); + defparam \vga/vgacore/_and000033 .INIT = 16'h0010; + defparam \vga/vgacore/_and000033 .LOC = "CLB_R15C8.S1"; + X_LUT4 \vga/vgacore/_and000033 ( + .ADR0(\vga/vgacore/hcnt [5]), + .ADR1(\vga/vgacore/hcnt [7]), + .ADR2(\vga/vgacore/hcnt [8]), + .ADR3(\vga/vgacore/hcnt [6]), + .O(\vga/vgacore/_and0000_map817 ) + ); + defparam \N3132/XUSED .LOC = "CLB_R15C8.S1"; + X_BUF \N3132/XUSED ( + .I(N3132), + .O(N3132_0) + ); + defparam \N3132/YUSED .LOC = "CLB_R15C8.S1"; + X_BUF \N3132/YUSED ( + .I(\vga/vgacore/_and0000_map817 ), + .O(\vga/vgacore/_and0000_map817_0 ) + ); + defparam \vga/_and000026 .INIT = 16'h8421; + defparam \vga/_and000026 .LOC = "CLB_R17C8.S1"; + X_LUT4 \vga/_and000026 ( + .ADR0(\vga/vgacore/hcnt [3]), + .ADR1(\vga/vgacore/hcnt [4]), + .ADR2(\vga/crt/cursor_h [0]), + .ADR3(\vga/crt/cursor_h [1]), + .O(\vga/_and0000_map879 ) + ); + defparam \vga/vgacore/_and000046 .INIT = 16'h0001; + defparam \vga/vgacore/_and000046 .LOC = "CLB_R17C8.S1"; + X_LUT4 \vga/vgacore/_and000046 ( + .ADR0(\vga/vgacore/hcnt [1]), + .ADR1(\vga/vgacore/hcnt [4]), + .ADR2(\vga/vgacore/hcnt [2]), + .ADR3(\vga/vgacore/hcnt [3]), + .O(\vga/vgacore/_and0000_map824 ) + ); + defparam \vga/_and0000_map879/XUSED .LOC = "CLB_R17C8.S1"; + X_BUF \vga/_and0000_map879/XUSED ( + .I(\vga/_and0000_map879 ), + .O(\vga/_and0000_map879_0 ) + ); + defparam \vga/_and0000_map879/YUSED .LOC = "CLB_R17C8.S1"; + X_BUF \vga/_and0000_map879/YUSED ( + .I(\vga/vgacore/_and0000_map824 ), + .O(\vga/vgacore/_and0000_map824_0 ) + ); + defparam \vga/vgacore/_and000047 .INIT = 16'h8888; + defparam \vga/vgacore/_and000047 .LOC = "CLB_R16C8.S0"; + X_LUT4 \vga/vgacore/_and000047 ( + .ADR0(\vga/vgacore/_and0000_map824_0 ), + .ADR1(\vga/vgacore/_and0000_map817_0 ), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/vgacore/_and0000_map825_pack_1 ) + ); + defparam \vga/vgacore/_and000074 .INIT = 16'h4440; + defparam \vga/vgacore/_and000074 .LOC = "CLB_R16C8.S0"; + X_LUT4 \vga/vgacore/_and000074 ( + .ADR0(\vga/vgacore/hcnt [10]), + .ADR1(\vga/vgacore/hcnt [9]), + .ADR2(\vga/vgacore/_and0000_map811_0 ), + .ADR3(\vga/vgacore/_and0000_map825 ), + .O(\vga/vgacore/_and0000 ) + ); + defparam \vga/vgacore/hsync/XUSED .LOC = "CLB_R16C8.S0"; + X_BUF \vga/vgacore/hsync/XUSED ( + .I(\vga/vgacore/_and0000_map825_pack_1 ), + .O(\vga/vgacore/_and0000_map825 ) + ); + defparam \vga/vgacore/hsync .LOC = "CLB_R16C8.S0"; + defparam \vga/vgacore/hsync .INIT = 1'b0; + X_FF \vga/vgacore/hsync ( + .I(\vga/vgacore/_and0000 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hsync/FFY/RST ), + .O(\vga/vgacore/hsync_3 ) + ); + defparam \vga/vgacore/hsync/FFY/RSTOR .LOC = "CLB_R16C8.S0"; + X_INV \vga/vgacore/hsync/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hsync/FFY/RST ) + ); + defparam \vga/charload513 .INIT = 16'hE040; + defparam \vga/charload513 .LOC = "CLB_R20C7.S0"; + X_LUT4 \vga/charload513 ( + .ADR0(\vga/rom_addr_char [4]), + .ADR1(\vga/rom_addr_char<3>_f6123_0 ), + .ADR2(\vga/rom_addr_char [5]), + .ADR3(\vga/rom_addr_char<3>_f6112_0 ), + .O(\vga/charload5_map965 ) + ); + defparam \vga/charload413 .INIT = 16'hAC00; + defparam \vga/charload413 .LOC = "CLB_R20C7.S0"; + X_LUT4 \vga/charload413 ( + .ADR0(\vga/rom_addr_char<3>_f611_0 ), + .ADR1(\vga/rom_addr_char<3>_f612_0 ), + .ADR2(\vga/rom_addr_char [4]), + .ADR3(\vga/rom_addr_char [5]), + .O(\vga/charload4_map979 ) + ); + defparam \vga/charload5_map965/XUSED .LOC = "CLB_R20C7.S0"; + X_BUF \vga/charload5_map965/XUSED ( + .I(\vga/charload5_map965 ), + .O(\vga/charload5_map965_0 ) + ); + defparam \vga/charload5_map965/YUSED .LOC = "CLB_R20C7.S0"; + X_BUF \vga/charload5_map965/YUSED ( + .I(\vga/charload4_map979 ), + .O(\vga/charload4_map979_0 ) + ); + defparam \vga/rom_addr_char<1>152_SW0 .INIT = 16'h2277; + defparam \vga/rom_addr_char<1>152_SW0 .LOC = "CLB_R13C7.S1"; + X_LUT4 \vga/rom_addr_char<1>152_SW0 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/rom_addr_char_0_1_18 ), + .ADR2(VCC), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(N3172) + ); + defparam \vga/rom_addr_char<1>104_SW0 .INIT = 16'h88AA; + defparam \vga/rom_addr_char<1>104_SW0 .LOC = "CLB_R13C7.S1"; + X_LUT4 \vga/rom_addr_char<1>104_SW0 ( + .ADR0(\vga/rom_addr_char [1]), + .ADR1(\vga/vgacore/vcnt_0_1_17 ), + .ADR2(VCC), + .ADR3(\vga/rom_addr_char_0_1_18 ), + .O(N3148) + ); + defparam \N3172/XUSED .LOC = "CLB_R13C7.S1"; + X_BUF \N3172/XUSED ( + .I(N3172), + .O(N3172_0) + ); + defparam \N3172/YUSED .LOC = "CLB_R13C7.S1"; + X_BUF \N3172/YUSED ( + .I(N3148), + .O(N3148_0) + ); + defparam \vga/_and000053 .INIT = 16'h9009; + defparam \vga/_and000053 .LOC = "CLB_R15C7.S0"; + X_LUT4 \vga/_and000053 ( + .ADR0(\vga/vgacore/hcnt [5]), + .ADR1(\vga/crt/cursor_h [2]), + .ADR2(\vga/vgacore/hcnt [6]), + .ADR3(\vga/crt/cursor_h [3]), + .O(\vga/_and0000_map890 ) + ); + defparam \vga/_and0000_map890/YUSED .LOC = "CLB_R15C7.S0"; + X_BUF \vga/_and0000_map890/YUSED ( + .I(\vga/_and0000_map890 ), + .O(\vga/_and0000_map890_0 ) + ); + defparam \vga/charload617 .INIT = 16'h3202; + defparam \vga/charload617 .LOC = "CLB_R9C3.S1"; + X_LUT4 \vga/charload617 ( + .ADR0(\vga/N96_0 ), + .ADR1(\vga/rom_addr_char [2]), + .ADR2(\vga/rom_addr_char [1]), + .ADR3(\vga/N30_0 ), + .O(\vga/charload6_map1010_pack_1 ) + ); + defparam \vga/charload628 .INIT = 16'hCC80; + defparam \vga/charload628 .LOC = "CLB_R9C3.S1"; + X_LUT4 \vga/charload628 ( + .ADR0(\vga/rom_addr_char [2]), + .ADR1(\vga/rom_addr_char [3]), + .ADR2(\vga/N98_0 ), + .ADR3(\vga/charload6_map1010 ), + .O(\vga/charload6_map1012 ) + ); + defparam \vga/charload6_map1010/XUSED .LOC = "CLB_R9C3.S1"; + X_BUF \vga/charload6_map1010/XUSED ( + .I(\vga/charload6_map1010_pack_1 ), + .O(\vga/charload6_map1010 ) + ); + defparam \vga/charload6_map1010/YUSED .LOC = "CLB_R9C3.S1"; + X_BUF \vga/charload6_map1010/YUSED ( + .I(\vga/charload6_map1012 ), + .O(\vga/charload6_map1012_0 ) + ); + defparam \vga/charload637 .INIT = 16'h2222; + defparam \vga/charload637 .LOC = "CLB_R9C3.S0"; + X_LUT4 \vga/charload637 ( + .ADR0(\vga/rom_addr_char<2>_f51234_0 ), + .ADR1(\vga/rom_addr_char [3]), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/charload6_map1014_pack_1 ) + ); + defparam \vga/charload669 .INIT = 16'hF5E4; + defparam \vga/charload669 .LOC = "CLB_R9C3.S0"; + X_LUT4 \vga/charload669 ( + .ADR0(\vga/rom_addr_char [4]), + .ADR1(\vga/charload6_map1012_0 ), + .ADR2(\vga/rom_addr_char<3>_f61234_0 ), + .ADR3(\vga/charload6_map1014 ), + .O(\vga/charload6_map1018 ) + ); + defparam \vga/charload6_map1014/XUSED .LOC = "CLB_R9C3.S0"; + X_BUF \vga/charload6_map1014/XUSED ( + .I(\vga/charload6_map1014_pack_1 ), + .O(\vga/charload6_map1014 ) + ); + defparam \vga/charload6_map1014/YUSED .LOC = "CLB_R9C3.S0"; + X_BUF \vga/charload6_map1014/YUSED ( + .I(\vga/charload6_map1018 ), + .O(\vga/charload6_map1018_0 ) + ); + defparam \vga/crtclk1/BYMUX .LOC = "CLB_R24C21.S0"; + X_INV \vga/crtclk1/BYMUX ( + .I(\vga/crtclk_4 ), + .O(\vga/crtclk1/BYMUXNOT ) + ); + defparam \vga/crtclk .LOC = "CLB_R24C21.S0"; + defparam \vga/crtclk .INIT = 1'b0; + X_FF \vga/crtclk ( + .I(\vga/crtclk1/BYMUXNOT ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/crtclk1/FFY/RST ), + .O(\vga/crtclk1 ) + ); + defparam \vga/crtclk1/FFY/RSTOR .LOC = "CLB_R24C21.S0"; + X_INV \vga/crtclk1/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crtclk1/FFY/RST ) + ); + defparam \vga/scancode_convert/sc_0_1 .LOC = "CLB_R13C32.S1"; + defparam \vga/scancode_convert/sc_0_1 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_0_1 ( + .I(\vga/ps2/sc_r [0]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc_0_1_10 ) + ); + defparam \vga/crt_data<1>/SRMUX .LOC = "CLB_R16C25.S0"; + X_INV \vga/crt_data<1>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt_data<1>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt_data_0 .LOC = "CLB_R16C25.S0"; + defparam \vga/crt_data_0 .INIT = 1'b0; + X_FF \vga/crt_data_0 ( + .I(\vga/scancode_convert/ascii [0]), + .CE(VCC), + .CLK(\vga/scancode_convert/strobe_out_15 ), + .SET(GND), + .RST(\vga/crt_data<1>/FFY/RST ), + .O(\vga/crt_data [0]) + ); + defparam \vga/crt_data<1>/FFY/RSTOR .LOC = "CLB_R16C25.S0"; + X_BUF \vga/crt_data<1>/FFY/RSTOR ( + .I(\vga/crt_data<1>/SRMUX_OUTPUTNOT ), + .O(\vga/crt_data<1>/FFY/RST ) + ); + defparam \vga/scancode_convert/sc_1_1 .LOC = "CLB_R13C33.S0"; + defparam \vga/scancode_convert/sc_1_1 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_1_1 ( + .I(\vga/ps2/sc_r [1]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc_1_1_23 ) + ); + defparam \vga/crt_data<3>/SRMUX .LOC = "CLB_R16C21.S0"; + X_INV \vga/crt_data<3>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt_data<3>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt_data_2 .LOC = "CLB_R16C21.S0"; + defparam \vga/crt_data_2 .INIT = 1'b0; + X_FF \vga/crt_data_2 ( + .I(\vga/scancode_convert/ascii [2]), + .CE(VCC), + .CLK(\vga/scancode_convert/strobe_out_15 ), + .SET(GND), + .RST(\vga/crt_data<3>/FFY/RST ), + .O(\vga/crt_data [2]) + ); + defparam \vga/crt_data<3>/FFY/RSTOR .LOC = "CLB_R16C21.S0"; + X_BUF \vga/crt_data<3>/FFY/RSTOR ( + .I(\vga/crt_data<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt_data<3>/FFY/RST ) + ); + defparam \vga/crt_data<5>/SRMUX .LOC = "CLB_R14C25.S1"; + X_INV \vga/crt_data<5>/SRMUX ( + .I(reset_n_IBUF_0), + .O(\vga/crt_data<5>/SRMUX_OUTPUTNOT ) + ); + defparam \vga/crt_data_4 .LOC = "CLB_R14C25.S1"; + defparam \vga/crt_data_4 .INIT = 1'b0; + X_FF \vga/crt_data_4 ( + .I(\vga/scancode_convert/ascii [4]), + .CE(VCC), + .CLK(\vga/scancode_convert/strobe_out_15 ), + .SET(GND), + .RST(\vga/crt_data<5>/FFY/RST ), + .O(\vga/crt_data [4]) + ); + defparam \vga/crt_data<5>/FFY/RSTOR .LOC = "CLB_R14C25.S1"; + X_BUF \vga/crt_data<5>/FFY/RSTOR ( + .I(\vga/crt_data<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt_data<5>/FFY/RST ) + ); + defparam \vga/crt_data_6 .LOC = "CLB_R14C25.S0"; + defparam \vga/crt_data_6 .INIT = 1'b0; + X_FF \vga/crt_data_6 ( + .I(\vga/scancode_convert/ascii [6]), + .CE(VCC), + .CLK(\vga/scancode_convert/strobe_out_15 ), + .SET(GND), + .RST(\vga/crt_data<6>/FFY/RST ), + .O(\vga/crt_data [6]) + ); + defparam \vga/crt_data<6>/FFY/RSTOR .LOC = "CLB_R14C25.S0"; + X_INV \vga/crt_data<6>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt_data<6>/FFY/RST ) + ); + defparam \vga/vgacore/hcnt<0>/LOGIC_ONE .LOC = "CLB_R20C7.S1"; + X_ONE \vga/vgacore/hcnt<0>/LOGIC_ONE ( + .O(\vga/vgacore/hcnt<0>/LOGIC_ONE_178 ) + ); + defparam \vga/vgacore/hcnt<0>/LOGIC_ZERO .LOC = "CLB_R20C7.S1"; + X_ZERO \vga/vgacore/hcnt<0>/LOGIC_ZERO ( + .O(\vga/vgacore/hcnt<0>/LOGIC_ZERO_180 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<0> .LOC = "CLB_R20C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<0> ( + .IA(\vga/vgacore/hcnt_Eqn_0_mand1 ), + .IB(\vga/vgacore/hcnt<0>/LOGIC_ZERO_180 ), + .SEL(\vga/vgacore/Result [0]), + .O(\vga/vgacore/Mcount_hcnt_cy<0>_rt_179 ) + ); + defparam \vga/vgacore/hcnt_Eqn_0_mand .LOC = "CLB_R20C7.S1"; + X_AND2 \vga/vgacore/hcnt_Eqn_0_mand ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [0]), + .O(\vga/vgacore/hcnt_Eqn_0_mand1 ) + ); + defparam \vga/vgacore/Mcount_hcnt_lut<0> .INIT = 16'h4444; + defparam \vga/vgacore/Mcount_hcnt_lut<0> .LOC = "CLB_R20C7.S1"; + X_LUT4 \vga/vgacore/Mcount_hcnt_lut<0> ( + .ADR0(\vga/vgacore/hcnt [0]), + .ADR1(\vga/vgacore/hcnt_Eqn_bis_0 ), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/vgacore/Result [0]) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<4>_inv_INV_0 .INIT = 16'h5555; + defparam \vga/vgacore/Mcompar__cmp_lt0000_cy<4>_inv_INV_0 .LOC = "CLB_R20C7.S1"; + X_LUT4 \vga/vgacore/Mcompar__cmp_lt0000_cy<4>_inv_INV_0 ( + .ADR0(\vga/vgacore/Mcompar__cmp_lt0000_cy<4>_0 ), + .ADR1(VCC), + .ADR2(VCC), + .ADR3(VCC), + .O(\vga/vgacore/hcnt_Eqn_bis_0_pack_1 ) + ); + defparam \vga/vgacore/hcnt<0>/YUSED .LOC = "CLB_R20C7.S1"; + X_BUF \vga/vgacore/hcnt<0>/YUSED ( + .I(\vga/vgacore/hcnt_Eqn_bis_0_pack_1 ), + .O(\vga/vgacore/hcnt_Eqn_bis_0 ) + ); + defparam \vga/vgacore/Mcount_hcnt_cy<0>_rt .LOC = "CLB_R20C7.S1"; + X_MUX2 \vga/vgacore/Mcount_hcnt_cy<0>_rt ( + .IA(\NLW_vga/vgacore/Mcount_hcnt_cy<0>_rt_IA_UNCONNECTED ), + .IB(\vga/vgacore/Mcount_hcnt_cy<0>_rt_179 ), + .SEL(\vga/vgacore/hcnt<0>/LOGIC_ONE_178 ), + .O(\vga/vgacore/hcnt<0>/CYMUXG ) + ); + defparam \vga/vgacore/hcnt_0 .LOC = "CLB_R20C7.S1"; + defparam \vga/vgacore/hcnt_0 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_0 ( + .I(\vga/vgacore/Result [0]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<0>/FFX/RST ), + .O(\vga/vgacore/hcnt [0]) + ); + defparam \vga/vgacore/hcnt<0>/FFX/RSTOR .LOC = "CLB_R20C7.S1"; + X_INV \vga/vgacore/hcnt<0>/FFX/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hcnt<0>/FFX/RST ) + ); + defparam \vga/scancode_convert/_cmp_eq0000_SW0_SW0 .INIT = 16'h0FFF; + defparam \vga/scancode_convert/_cmp_eq0000_SW0_SW0 .LOC = "CLB_R11C29.S0"; + X_LUT4 \vga/scancode_convert/_cmp_eq0000_SW0_SW0 ( + .ADR0(VCC), + .ADR1(VCC), + .ADR2(\vga/ps2/sc_r [7]), + .ADR3(\vga/ps2/sc_r [5]), + .O(N3100) + ); + defparam \N3100/YUSED .LOC = "CLB_R11C29.S0"; + X_BUF \N3100/YUSED ( + .I(N3100), + .O(N3100_0) + ); + defparam \vga/vgacore/_and0001_SW0 .INIT = 16'hFCFF; + defparam \vga/vgacore/_and0001_SW0 .LOC = "CLB_R16C6.S1"; + X_LUT4 \vga/vgacore/_and0001_SW0 ( + .ADR0(VCC), + .ADR1(N3222_0), + .ADR2(\vga/vgacore/vcnt [9]), + .ADR3(\vga/vgacore/vcnt_1_1_8 ), + .O(N44_pack_1) + ); + defparam \vga/vgacore/_and0001 .INIT = 16'h0004; + defparam \vga/vgacore/_and0001 .LOC = "CLB_R16C6.S1"; + X_LUT4 \vga/vgacore/_and0001 ( + .ADR0(\vga/vgacore/vcnt_2_1_9 ), + .ADR1(\vga/vgacore/vcnt [3]), + .ADR2(\vga/vgacore/vcnt [4]), + .ADR3(N44), + .O(\vga/vgacore/_and0001_181 ) + ); + defparam \vga/vgacore/vsync/XUSED .LOC = "CLB_R16C6.S1"; + X_BUF \vga/vgacore/vsync/XUSED ( + .I(N44_pack_1), + .O(N44) + ); + defparam \vga/vgacore/vsync .LOC = "CLB_R16C6.S1"; + defparam \vga/vgacore/vsync .INIT = 1'b0; + X_FF \vga/vgacore/vsync ( + .I(\vga/vgacore/_and0001_181 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/vsync/FFY/RST ), + .O(\vga/vgacore/vsync_2 ) + ); + defparam \vga/vgacore/vsync/FFY/RSTOR .LOC = "CLB_R16C6.S1"; + X_INV \vga/vgacore/vsync/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vsync/FFY/RST ) + ); + defparam \vga/pclk__mux0000<2>_SW0 .INIT = 16'hFF15; + defparam \vga/pclk__mux0000<2>_SW0 .LOC = "CLB_R14C6.S0"; + X_LUT4 \vga/pclk__mux0000<2>_SW0 ( + .ADR0(\vga/crt/state_FFd1_13 ), + .ADR1(\vga/crt/state_FFd3_11 ), + .ADR2(\vga/crt/state_FFd2_12 ), + .ADR3(\vga/vgacore/hblank_21 ), + .O(N89_pack_1) + ); + defparam \vga/pclk__mux0000<2> .INIT = 16'hFF6C; + defparam \vga/pclk__mux0000<2> .LOC = "CLB_R14C6.S0"; + X_LUT4 \vga/pclk__mux0000<2> ( + .ADR0(\vga/pclk [1]), + .ADR1(\vga/pclk [2]), + .ADR2(\vga/pclk [0]), + .ADR3(N89), + .O(\vga/pclk__mux0000 [2]) + ); + defparam \vga/pclk<2>/XUSED .LOC = "CLB_R14C6.S0"; + X_BUF \vga/pclk<2>/XUSED ( + .I(N89_pack_1), + .O(N89) + ); + defparam \vga/pclk_2 .LOC = "CLB_R14C6.S0"; + defparam \vga/pclk_2 .INIT = 1'b1; + X_FF \vga/pclk_2 ( + .I(\vga/pclk__mux0000 [2]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/pclk<2>/FFY/SET ), + .RST(GND), + .O(\vga/pclk [2]) + ); + defparam \vga/pclk<2>/FFY/SETOR .LOC = "CLB_R14C6.S0"; + X_INV \vga/pclk<2>/FFY/SETOR ( + .I(reset_n_IBUF_0), + .O(\vga/pclk<2>/FFY/SET ) + ); + defparam \vga/scancode_convert/ascii_3 .LOC = "CLB_R18C35.S1"; + defparam \vga/scancode_convert/ascii_3 .INIT = 1'b0; + X_FF \vga/scancode_convert/ascii_3 ( + .I(\vga/scancode_convert/rom_data [3]), + .CE(\vga/scancode_convert/_or0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/ascii [3]) + ); + defparam \vga/scancode_convert/ascii_4 .LOC = "CLB_R12C36.S1"; + defparam \vga/scancode_convert/ascii_4 .INIT = 1'b0; + X_FF \vga/scancode_convert/ascii_4 ( + .I(\vga/scancode_convert/rom_data [4]), + .CE(\vga/scancode_convert/_or0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/ascii [4]) + ); + defparam \vga/pixel_hold_0 .LOC = "CLB_R13C8.S0"; + defparam \vga/pixel_hold_0 .INIT = 1'b0; + X_FF \vga/pixel_hold_0 ( + .I(\vga/_mux0002 [7]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [0]) + ); + defparam \vga/pixel_hold_1 .LOC = "CLB_R13C7.S0"; + defparam \vga/pixel_hold_1 .INIT = 1'b0; + X_FF \vga/pixel_hold_1 ( + .I(\vga/_mux0002 [6]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [1]) + ); + defparam \vga/pixel_hold_5 .LOC = "CLB_R13C9.S0"; + defparam \vga/pixel_hold_5 .INIT = 1'b0; + X_FF \vga/pixel_hold_5 ( + .I(\vga/_mux0002 [2]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [5]) + ); + defparam \vga/pixel_hold_3 .LOC = "CLB_R13C8.S1"; + defparam \vga/pixel_hold_3 .INIT = 1'b0; + X_FF \vga/pixel_hold_3 ( + .I(\vga/_mux0002 [4]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [3]) + ); + defparam \vga/pixel_hold_6 .LOC = "CLB_R12C6.S0"; + defparam \vga/pixel_hold_6 .INIT = 1'b0; + X_FF \vga/pixel_hold_6 ( + .I(\vga/_mux0002 [1]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/pixel_hold [6]) + ); + defparam \vga/vgacore/hblank .LOC = "CLB_R16C7.S0"; + defparam \vga/vgacore/hblank .INIT = 1'b0; + X_FF \vga/vgacore/hblank ( + .I(\vga/vgacore/_mux0002 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hblank/FFY/RST ), + .O(\vga/vgacore/hblank_21 ) + ); + defparam \vga/vgacore/hblank/FFY/RSTOR .LOC = "CLB_R16C7.S0"; + X_INV \vga/vgacore/hblank/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/hblank/FFY/RST ) + ); + defparam \vga/vgacore/hcnt_2 .LOC = "CLB_R19C7.S1"; + defparam \vga/vgacore/hcnt_2 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_2 ( + .I(\vga/vgacore/Result [2]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<1>/FFY/RST ), + .O(\vga/vgacore/hcnt [2]) + ); + defparam \vga/vgacore/hcnt<1>/FFY/RSTOR .LOC = "CLB_R19C7.S1"; + X_BUF \vga/vgacore/hcnt<1>/FFY/RSTOR ( + .I(\vga/vgacore/hcnt<1>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<1>/FFY/RST ) + ); + defparam \vga/vgacore/hcnt_4 .LOC = "CLB_R18C7.S1"; + defparam \vga/vgacore/hcnt_4 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_4 ( + .I(\vga/vgacore/Result [4]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<3>/FFY/RST ), + .O(\vga/vgacore/hcnt [4]) + ); + defparam \vga/vgacore/hcnt<3>/FFY/RSTOR .LOC = "CLB_R18C7.S1"; + X_BUF \vga/vgacore/hcnt<3>/FFY/RSTOR ( + .I(\vga/vgacore/hcnt<3>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<3>/FFY/RST ) + ); + defparam \vga/vgacore/hcnt_6 .LOC = "CLB_R17C7.S1"; + defparam \vga/vgacore/hcnt_6 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_6 ( + .I(\vga/vgacore/Result [6]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<5>/FFY/RST ), + .O(\vga/vgacore/hcnt [6]) + ); + defparam \vga/vgacore/hcnt<5>/FFY/RSTOR .LOC = "CLB_R17C7.S1"; + X_BUF \vga/vgacore/hcnt<5>/FFY/RSTOR ( + .I(\vga/vgacore/hcnt<5>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<5>/FFY/RST ) + ); + defparam \vga/vgacore/hcnt_8 .LOC = "CLB_R16C7.S1"; + defparam \vga/vgacore/hcnt_8 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_8 ( + .I(\vga/vgacore/Result [8]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<7>/FFY/RST ), + .O(\vga/vgacore/hcnt [8]) + ); + defparam \vga/vgacore/hcnt<7>/FFY/RSTOR .LOC = "CLB_R16C7.S1"; + X_BUF \vga/vgacore/hcnt<7>/FFY/RSTOR ( + .I(\vga/vgacore/hcnt<7>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<7>/FFY/RST ) + ); + defparam \vga/vgacore/hcnt_10 .LOC = "CLB_R15C7.S1"; + defparam \vga/vgacore/hcnt_10 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_10 ( + .I(\vga/vgacore/Result [10]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<9>/FFY/RST ), + .O(\vga/vgacore/hcnt [10]) + ); + defparam \vga/vgacore/hcnt<9>/FFY/RSTOR .LOC = "CLB_R15C7.S1"; + X_BUF \vga/vgacore/hcnt<9>/FFY/RSTOR ( + .I(\vga/vgacore/hcnt<9>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<9>/FFY/RST ) + ); + defparam \vga/vgacore/vcnt_0_1 .LOC = "CLB_R19C9.S1"; + defparam \vga/vgacore/vcnt_0_1 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_0_1 ( + .I(N3216), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<0>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<0>/FFY/RST ), + .O(\vga/vgacore/vcnt_0_1_17 ) + ); + defparam \vga/vgacore/vcnt<0>/FFY/RSTOR .LOC = "CLB_R19C9.S1"; + X_BUF \vga/vgacore/vcnt<0>/FFY/RSTOR ( + .I(\vga/vgacore/vcnt<0>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<0>/FFY/RST ) + ); + defparam \vga/vgacore/vcnt_2 .LOC = "CLB_R18C9.S1"; + defparam \vga/vgacore/vcnt_2 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_2 ( + .I(\vga/vgacore/Result<2>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<1>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<1>/FFY/RST ), + .O(\vga/vgacore/vcnt [2]) + ); + defparam \vga/vgacore/vcnt<1>/FFY/RSTOR .LOC = "CLB_R18C9.S1"; + X_BUF \vga/vgacore/vcnt<1>/FFY/RSTOR ( + .I(\vga/vgacore/vcnt<1>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<1>/FFY/RST ) + ); + defparam \vga/vgacore/vcnt_4 .LOC = "CLB_R17C9.S1"; + defparam \vga/vgacore/vcnt_4 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_4 ( + .I(\vga/vgacore/Result<4>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<3>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<3>/FFY/RST ), + .O(\vga/vgacore/vcnt [4]) + ); + defparam \vga/vgacore/vcnt<3>/FFY/RSTOR .LOC = "CLB_R17C9.S1"; + X_BUF \vga/vgacore/vcnt<3>/FFY/RSTOR ( + .I(\vga/vgacore/vcnt<3>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<3>/FFY/RST ) + ); + defparam \vga/vgacore/vcnt_6 .LOC = "CLB_R16C9.S1"; + defparam \vga/vgacore/vcnt_6 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_6 ( + .I(\vga/vgacore/Result<6>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<5>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<5>/FFY/RST ), + .O(\vga/vgacore/vcnt [6]) + ); + defparam \vga/vgacore/vcnt<5>/FFY/RSTOR .LOC = "CLB_R16C9.S1"; + X_BUF \vga/vgacore/vcnt<5>/FFY/RSTOR ( + .I(\vga/vgacore/vcnt<5>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<5>/FFY/RST ) + ); + defparam \vga/vgacore/vcnt_8 .LOC = "CLB_R15C9.S1"; + defparam \vga/vgacore/vcnt_8 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_8 ( + .I(\vga/vgacore/Result<8>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<7>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<7>/FFY/RST ), + .O(\vga/vgacore/vcnt [8]) + ); + defparam \vga/vgacore/vcnt<7>/FFY/RSTOR .LOC = "CLB_R15C9.S1"; + X_BUF \vga/vgacore/vcnt<7>/FFY/RSTOR ( + .I(\vga/vgacore/vcnt<7>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<7>/FFY/RST ) + ); + defparam \vga/crt/cursor_v_2 .LOC = "CLB_R15C13.S1"; + defparam \vga/crt/cursor_v_2 .INIT = 1'b0; + X_FF \vga/crt/cursor_v_2 ( + .I(\vga/crt/cursor_v_Eqn_2 ), + .CE(\vga/crt/_not0007_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_v<3>/FFY/RST ), + .O(\vga/crt/cursor_v [2]) + ); + defparam \vga/crt/cursor_v<3>/FFY/RSTOR .LOC = "CLB_R15C13.S1"; + X_BUF \vga/crt/cursor_v<3>/FFY/RSTOR ( + .I(\vga/crt/cursor_v<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_v<3>/FFY/RST ) + ); + defparam \vga/crt/cursor_v_4 .LOC = "CLB_R15C14.S0"; + defparam \vga/crt/cursor_v_4 .INIT = 1'b0; + X_FF \vga/crt/cursor_v_4 ( + .I(\vga/crt/cursor_v_Eqn_4 ), + .CE(\vga/crt/_not0007_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_v<5>/FFY/RST ), + .O(\vga/crt/cursor_v [4]) + ); + defparam \vga/crt/cursor_v<5>/FFY/RSTOR .LOC = "CLB_R15C14.S0"; + X_BUF \vga/crt/cursor_v<5>/FFY/RSTOR ( + .I(\vga/crt/cursor_v<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_v<5>/FFY/RST ) + ); + defparam \vga/crt/ram_data_0 .LOC = "CLB_R18C13.S0"; + defparam \vga/crt/ram_data_0 .INIT = 1'b0; + X_FF \vga/crt/ram_data_0 ( + .I(\vga/crt/_mux0002 [0]), + .CE(\vga/crt/_not0008_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/ram_data<1>/FFY/RST ), + .O(\vga/crt/ram_data [0]) + ); + defparam \vga/crt/ram_data<1>/FFY/RSTOR .LOC = "CLB_R18C13.S0"; + X_BUF \vga/crt/ram_data<1>/FFY/RSTOR ( + .I(\vga/crt/ram_data<1>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/ram_data<1>/FFY/RST ) + ); + defparam \vga/crt/ram_data_2 .LOC = "CLB_R18C9.S0"; + defparam \vga/crt/ram_data_2 .INIT = 1'b0; + X_FF \vga/crt/ram_data_2 ( + .I(\vga/crt/_mux0002 [2]), + .CE(\vga/crt/_not0008_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/ram_data<3>/FFY/RST ), + .O(\vga/crt/ram_data [2]) + ); + defparam \vga/crt/ram_data<3>/FFY/RSTOR .LOC = "CLB_R18C9.S0"; + X_BUF \vga/crt/ram_data<3>/FFY/RSTOR ( + .I(\vga/crt/ram_data<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/ram_data<3>/FFY/RST ) + ); + defparam \vga/crt/ram_data_4 .LOC = "CLB_R14C13.S1"; + defparam \vga/crt/ram_data_4 .INIT = 1'b0; + X_FF \vga/crt/ram_data_4 ( + .I(\vga/crt/_mux0002 [4]), + .CE(\vga/crt/_not0008_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/ram_data<5>/FFY/RST ), + .O(\vga/crt/ram_data [4]) + ); + defparam \vga/crt/ram_data<5>/FFY/RSTOR .LOC = "CLB_R14C13.S1"; + X_BUF \vga/crt/ram_data<5>/FFY/RSTOR ( + .I(\vga/crt/ram_data<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/ram_data<5>/FFY/RST ) + ); + defparam \vga/scancode_convert/state_FFd5 .LOC = "CLB_R12C28.S0"; + defparam \vga/scancode_convert/state_FFd5 .INIT = 1'b0; + X_FF \vga/scancode_convert/state_FFd5 ( + .I(\vga/scancode_convert/state_FFd5-In_166 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/state_FFd6/FFY/RST ), + .O(\vga/scancode_convert/state_FFd5_31 ) + ); + defparam \vga/scancode_convert/state_FFd6/FFY/RSTOR .LOC = "CLB_R12C28.S0"; + X_BUF \vga/scancode_convert/state_FFd6/FFY/RSTOR ( + .I(\vga/scancode_convert/state_FFd6/SRMUX_OUTPUTNOT ), + .O(\vga/scancode_convert/state_FFd6/FFY/RST ) + ); + defparam \vga/ps2/timer_r_10 .LOC = "CLB_R6C17.S0"; + defparam \vga/ps2/timer_r_10 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_10 ( + .I(\vga/ps2/timer_x [10]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<11>/FFY/RST ), + .O(\vga/ps2/timer_r [10]) + ); + defparam \vga/ps2/timer_r<11>/FFY/RSTOR .LOC = "CLB_R6C17.S0"; + X_BUF \vga/ps2/timer_r<11>/FFY/RSTOR ( + .I(\vga/ps2/timer_r<11>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<11>/FFY/RST ) + ); + defparam \vga/ps2/timer_r_12 .LOC = "CLB_R6C16.S0"; + defparam \vga/ps2/timer_r_12 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_12 ( + .I(\vga/ps2/timer_x [12]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<13>/FFY/RST ), + .O(\vga/ps2/timer_r [12]) + ); + defparam \vga/ps2/timer_r<13>/FFY/RSTOR .LOC = "CLB_R6C16.S0"; + X_BUF \vga/ps2/timer_r<13>/FFY/RSTOR ( + .I(\vga/ps2/timer_r<13>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<13>/FFY/RST ) + ); + defparam \vga/scancode_convert/hold_count_0 .LOC = "CLB_R14C26.S0"; + defparam \vga/scancode_convert/hold_count_0 .INIT = 1'b0; + X_FF \vga/scancode_convert/hold_count_0 ( + .I(\vga/scancode_convert/hold_count__mux0000 [0]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/hold_count<1>/FFY/RST ), + .O(\vga/scancode_convert/hold_count [0]) + ); + defparam \vga/scancode_convert/hold_count<1>/FFY/RSTOR .LOC = "CLB_R14C26.S0"; + X_BUF \vga/scancode_convert/hold_count<1>/FFY/RSTOR ( + .I(\vga/scancode_convert/hold_count<1>/SRMUX_OUTPUTNOT ), + .O(\vga/scancode_convert/hold_count<1>/FFY/RST ) + ); + defparam \vga/ps2/timer_r_2 .LOC = "CLB_R9C16.S0"; + defparam \vga/ps2/timer_r_2 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_2 ( + .I(\vga/ps2/timer_x [2]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<3>/FFY/RST ), + .O(\vga/ps2/timer_r [2]) + ); + defparam \vga/ps2/timer_r<3>/FFY/RSTOR .LOC = "CLB_R9C16.S0"; + X_BUF \vga/ps2/timer_r<3>/FFY/RSTOR ( + .I(\vga/ps2/timer_r<3>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<3>/FFY/RST ) + ); + defparam \vga/ps2/timer_r_4 .LOC = "CLB_R8C16.S0"; + defparam \vga/ps2/timer_r_4 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_4 ( + .I(\vga/ps2/timer_x [4]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<5>/FFY/RST ), + .O(\vga/ps2/timer_r [4]) + ); + defparam \vga/ps2/timer_r<5>/FFY/RSTOR .LOC = "CLB_R8C16.S0"; + X_BUF \vga/ps2/timer_r<5>/FFY/RSTOR ( + .I(\vga/ps2/timer_r<5>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<5>/FFY/RST ) + ); + defparam \vga/ps2/timer_r_6 .LOC = "CLB_R8C15.S1"; + defparam \vga/ps2/timer_r_6 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_6 ( + .I(\vga/ps2/timer_x [6]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<7>/FFY/RST ), + .O(\vga/ps2/timer_r [6]) + ); + defparam \vga/ps2/timer_r<7>/FFY/RSTOR .LOC = "CLB_R8C15.S1"; + X_BUF \vga/ps2/timer_r<7>/FFY/RSTOR ( + .I(\vga/ps2/timer_r<7>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<7>/FFY/RST ) + ); + defparam \vga/ps2/timer_r_8 .LOC = "CLB_R7C17.S0"; + defparam \vga/ps2/timer_r_8 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_8 ( + .I(\vga/ps2/timer_x [8]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<9>/FFY/RST ), + .O(\vga/ps2/timer_r [8]) + ); + defparam \vga/ps2/timer_r<9>/FFY/RSTOR .LOC = "CLB_R7C17.S0"; + X_BUF \vga/ps2/timer_r<9>/FFY/RSTOR ( + .I(\vga/ps2/timer_r<9>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<9>/FFY/RST ) + ); + defparam \vga/pclk_0 .LOC = "CLB_R14C6.S1"; + defparam \vga/pclk_0 .INIT = 1'b1; + X_FF \vga/pclk_0 ( + .I(\vga/pclk__mux0000 [0]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/pclk<1>/FFY/SET ), + .RST(GND), + .O(\vga/pclk [0]) + ); + defparam \vga/pclk<1>/FFY/SETOR .LOC = "CLB_R14C6.S1"; + X_BUF \vga/pclk<1>/FFY/SETOR ( + .I(\vga/pclk<1>/SRMUX_OUTPUTNOT ), + .O(\vga/pclk<1>/FFY/SET ) + ); + defparam \vga/crt/cursor_h_0 .LOC = "CLB_R18C13.S1"; + defparam \vga/crt/cursor_h_0 .INIT = 1'b0; + X_FF \vga/crt/cursor_h_0 ( + .I(\vga/crt/cursor_h_Eqn_0 ), + .CE(\vga/crt/_not0006_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_h<1>/FFY/RST ), + .O(\vga/crt/cursor_h [0]) + ); + defparam \vga/crt/cursor_h<1>/FFY/RSTOR .LOC = "CLB_R18C13.S1"; + X_BUF \vga/crt/cursor_h<1>/FFY/RSTOR ( + .I(\vga/crt/cursor_h<1>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_h<1>/FFY/RST ) + ); + defparam \vga/crt/cursor_h_2 .LOC = "CLB_R17C13.S0"; + defparam \vga/crt/cursor_h_2 .INIT = 1'b0; + X_FF \vga/crt/cursor_h_2 ( + .I(\vga/crt/cursor_h_Eqn_2 ), + .CE(\vga/crt/_not0006_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_h<3>/FFY/RST ), + .O(\vga/crt/cursor_h [2]) + ); + defparam \vga/crt/cursor_h<3>/FFY/RSTOR .LOC = "CLB_R17C13.S0"; + X_BUF \vga/crt/cursor_h<3>/FFY/RSTOR ( + .I(\vga/crt/cursor_h<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_h<3>/FFY/RST ) + ); + defparam \vga/crt/cursor_h_4 .LOC = "CLB_R17C14.S0"; + defparam \vga/crt/cursor_h_4 .INIT = 1'b0; + X_FF \vga/crt/cursor_h_4 ( + .I(\vga/crt/cursor_h_Eqn_4 ), + .CE(\vga/crt/_not0006_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_h<5>/FFY/RST ), + .O(\vga/crt/cursor_h [4]) + ); + defparam \vga/crt/cursor_h<5>/FFY/RSTOR .LOC = "CLB_R17C14.S0"; + X_BUF \vga/crt/cursor_h<5>/FFY/RSTOR ( + .I(\vga/crt/cursor_h<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_h<5>/FFY/RST ) + ); + defparam \vga/ram_wclk .LOC = "CLB_R15C6.S0"; + defparam \vga/ram_wclk .INIT = 1'b0; + X_FF \vga/ram_wclk ( + .I(\vga/_mux0000 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ram_wclk/FFY/RST ), + .O(\vga/ram_wclk_5 ) + ); + defparam \vga/ram_wclk/FFY/RSTOR .LOC = "CLB_R15C6.S0"; + X_INV \vga/ram_wclk/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/ram_wclk/FFY/RST ) + ); + defparam \vga/crt/ram_data_6 .LOC = "CLB_R14C13.S0"; + defparam \vga/crt/ram_data_6 .INIT = 1'b0; + X_FF \vga/crt/ram_data_6 ( + .I(\vga/crt/_mux0002 [6]), + .CE(\vga/crt/_not0008_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/ram_data<6>/FFY/RST ), + .O(\vga/crt/ram_data [6]) + ); + defparam \vga/crt/ram_data<6>/FFY/RSTOR .LOC = "CLB_R14C13.S0"; + X_INV \vga/crt/ram_data<6>/FFY/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/ram_data<6>/FFY/RST ) + ); + defparam \vga/ps2/ps2_clk_r_0 .LOC = "PAD309"; + defparam \vga/ps2/ps2_clk_r_0 .INIT = 1'b1; + X_FF \vga/ps2/ps2_clk_r_0 ( + .I(\ps2_clk/IDELAY ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\ps2_clk/IFF/SET ), + .RST(GND), + .O(\vga/ps2/ps2_clk_r [0]) + ); + defparam \ps2_clk/IFF/SETOR .LOC = "PAD309"; + X_INV \ps2_clk/IFF/SETOR ( + .I(reset_n_IBUF_0), + .O(\ps2_clk/IFF/SET ) + ); + defparam \vga/ps2/sc_r_9 .LOC = "PAD315"; + defparam \vga/ps2/sc_r_9 .INIT = 1'b0; + X_FF \vga/ps2/sc_r_9 ( + .I(\ps2_data/IDELAY ), + .CE(\vga/ps2/ps2_clk_fall_edge_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\ps2_data/IFF/RST ), + .O(\vga/ps2/sc_r [9]) + ); + defparam \ps2_data/IFF/RSTOR .LOC = "PAD315"; + X_INV \ps2_data/IFF/RSTOR ( + .I(reset_n_IBUF_0), + .O(\ps2_data/IFF/RST ) + ); + defparam \vga/crt/state_FFd2 .LOC = "CLB_R15C18.S0"; + defparam \vga/crt/state_FFd2 .INIT = 1'b0; + X_FF \vga/crt/state_FFd2 ( + .I(\vga/crt/state_FFd2-In ), + .CE(VCC), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/state_FFd2/FFX/RST ), + .O(\vga/crt/state_FFd2_12 ) + ); + defparam \vga/crt/state_FFd2/FFX/RSTOR .LOC = "CLB_R15C18.S0"; + X_INV \vga/crt/state_FFd2/FFX/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/crt/state_FFd2/FFX/RST ) + ); + defparam \vga/vgacore/hcnt_3 .LOC = "CLB_R18C7.S1"; + defparam \vga/vgacore/hcnt_3 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_3 ( + .I(\vga/vgacore/Result [3]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<3>/FFX/RST ), + .O(\vga/vgacore/hcnt [3]) + ); + defparam \vga/vgacore/hcnt<3>/FFX/RSTOR .LOC = "CLB_R18C7.S1"; + X_BUF \vga/vgacore/hcnt<3>/FFX/RSTOR ( + .I(\vga/vgacore/hcnt<3>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<3>/FFX/RST ) + ); + defparam \vga/vgacore/hcnt_5 .LOC = "CLB_R17C7.S1"; + defparam \vga/vgacore/hcnt_5 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_5 ( + .I(\vga/vgacore/Result [5]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<5>/FFX/RST ), + .O(\vga/vgacore/hcnt [5]) + ); + defparam \vga/vgacore/hcnt<5>/FFX/RSTOR .LOC = "CLB_R17C7.S1"; + X_BUF \vga/vgacore/hcnt<5>/FFX/RSTOR ( + .I(\vga/vgacore/hcnt<5>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<5>/FFX/RST ) + ); + defparam \vga/vgacore/hcnt_7 .LOC = "CLB_R16C7.S1"; + defparam \vga/vgacore/hcnt_7 .INIT = 1'b0; + X_FF \vga/vgacore/hcnt_7 ( + .I(\vga/vgacore/Result [7]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/vgacore/hcnt<7>/FFX/RST ), + .O(\vga/vgacore/hcnt [7]) + ); + defparam \vga/vgacore/hcnt<7>/FFX/RSTOR .LOC = "CLB_R16C7.S1"; + X_BUF \vga/vgacore/hcnt<7>/FFX/RSTOR ( + .I(\vga/vgacore/hcnt<7>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/hcnt<7>/FFX/RST ) + ); + defparam \vga/vgacore/vcnt_1 .LOC = "CLB_R18C9.S1"; + defparam \vga/vgacore/vcnt_1 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_1 ( + .I(\vga/vgacore/Result<1>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<1>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<1>/FFX/RST ), + .O(\vga/vgacore/vcnt [1]) + ); + defparam \vga/vgacore/vcnt<1>/FFX/RSTOR .LOC = "CLB_R18C9.S1"; + X_BUF \vga/vgacore/vcnt<1>/FFX/RSTOR ( + .I(\vga/vgacore/vcnt<1>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<1>/FFX/RST ) + ); + defparam \vga/vgacore/vcnt_3 .LOC = "CLB_R17C9.S1"; + defparam \vga/vgacore/vcnt_3 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_3 ( + .I(\vga/vgacore/Result<3>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<3>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<3>/FFX/RST ), + .O(\vga/vgacore/vcnt [3]) + ); + defparam \vga/vgacore/vcnt<3>/FFX/RSTOR .LOC = "CLB_R17C9.S1"; + X_BUF \vga/vgacore/vcnt<3>/FFX/RSTOR ( + .I(\vga/vgacore/vcnt<3>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<3>/FFX/RST ) + ); + defparam \vga/vgacore/vcnt_5 .LOC = "CLB_R16C9.S1"; + defparam \vga/vgacore/vcnt_5 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_5 ( + .I(\vga/vgacore/Result<5>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<5>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<5>/FFX/RST ), + .O(\vga/vgacore/vcnt [5]) + ); + defparam \vga/vgacore/vcnt<5>/FFX/RSTOR .LOC = "CLB_R16C9.S1"; + X_BUF \vga/vgacore/vcnt<5>/FFX/RSTOR ( + .I(\vga/vgacore/vcnt<5>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<5>/FFX/RST ) + ); + defparam \vga/vgacore/vcnt_7 .LOC = "CLB_R15C9.S1"; + defparam \vga/vgacore/vcnt_7 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_7 ( + .I(\vga/vgacore/Result<7>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<7>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<7>/FFX/RST ), + .O(\vga/vgacore/vcnt [7]) + ); + defparam \vga/vgacore/vcnt<7>/FFX/RSTOR .LOC = "CLB_R15C9.S1"; + X_BUF \vga/vgacore/vcnt<7>/FFX/RSTOR ( + .I(\vga/vgacore/vcnt<7>/SRMUX_OUTPUTNOT ), + .O(\vga/vgacore/vcnt<7>/FFX/RST ) + ); + defparam \vga/vgacore/vcnt_9 .LOC = "CLB_R14C9.S1"; + defparam \vga/vgacore/vcnt_9 .INIT = 1'b0; + X_FF \vga/vgacore/vcnt_9 ( + .I(\vga/vgacore/Result<9>1 ), + .CE(VCC), + .CLK(\vga/vgacore/vcnt<9>/CKMUXNOT ), + .SET(GND), + .RST(\vga/vgacore/vcnt<9>/FFX/RST ), + .O(\vga/vgacore/vcnt [9]) + ); + defparam \vga/vgacore/vcnt<9>/FFX/RSTOR .LOC = "CLB_R14C9.S1"; + X_INV \vga/vgacore/vcnt<9>/FFX/RSTOR ( + .I(reset_n_IBUF_0), + .O(\vga/vgacore/vcnt<9>/FFX/RST ) + ); + defparam \vga/scancode_convert/ascii_5 .LOC = "CLB_R11C35.S1"; + defparam \vga/scancode_convert/ascii_5 .INIT = 1'b0; + X_FF \vga/scancode_convert/ascii_5 ( + .I(\vga/scancode_convert/rom_data [5]), + .CE(\vga/scancode_convert/_or0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/ascii [5]) + ); + defparam \vga/crt/cursor_v_3 .LOC = "CLB_R15C13.S1"; + defparam \vga/crt/cursor_v_3 .INIT = 1'b0; + X_FF \vga/crt/cursor_v_3 ( + .I(\vga/crt/cursor_v_Eqn_3 ), + .CE(\vga/crt/_not0007_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_v<3>/FFX/RST ), + .O(\vga/crt/cursor_v [3]) + ); + defparam \vga/crt/cursor_v<3>/FFX/RSTOR .LOC = "CLB_R15C13.S1"; + X_BUF \vga/crt/cursor_v<3>/FFX/RSTOR ( + .I(\vga/crt/cursor_v<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_v<3>/FFX/RST ) + ); + defparam \vga/crt/cursor_v_5 .LOC = "CLB_R15C14.S0"; + defparam \vga/crt/cursor_v_5 .INIT = 1'b0; + X_FF \vga/crt/cursor_v_5 ( + .I(\vga/crt/cursor_v_Eqn_5 ), + .CE(\vga/crt/_not0007_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_v<5>/FFX/RST ), + .O(\vga/crt/cursor_v [5]) + ); + defparam \vga/crt/cursor_v<5>/FFX/RSTOR .LOC = "CLB_R15C14.S0"; + X_BUF \vga/crt/cursor_v<5>/FFX/RSTOR ( + .I(\vga/crt/cursor_v<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_v<5>/FFX/RST ) + ); + defparam \vga/crt/ram_data_1 .LOC = "CLB_R18C13.S0"; + defparam \vga/crt/ram_data_1 .INIT = 1'b0; + X_FF \vga/crt/ram_data_1 ( + .I(\vga/crt/_mux0002 [1]), + .CE(\vga/crt/_not0008_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/ram_data<1>/FFX/RST ), + .O(\vga/crt/ram_data [1]) + ); + defparam \vga/crt/ram_data<1>/FFX/RSTOR .LOC = "CLB_R18C13.S0"; + X_BUF \vga/crt/ram_data<1>/FFX/RSTOR ( + .I(\vga/crt/ram_data<1>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/ram_data<1>/FFX/RST ) + ); + defparam \vga/crt/ram_data_3 .LOC = "CLB_R18C9.S0"; + defparam \vga/crt/ram_data_3 .INIT = 1'b0; + X_FF \vga/crt/ram_data_3 ( + .I(\vga/crt/_mux0002 [3]), + .CE(\vga/crt/_not0008_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/ram_data<3>/FFX/RST ), + .O(\vga/crt/ram_data [3]) + ); + defparam \vga/crt/ram_data<3>/FFX/RSTOR .LOC = "CLB_R18C9.S0"; + X_BUF \vga/crt/ram_data<3>/FFX/RSTOR ( + .I(\vga/crt/ram_data<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/ram_data<3>/FFX/RST ) + ); + defparam \vga/crt/ram_data_5 .LOC = "CLB_R14C13.S1"; + defparam \vga/crt/ram_data_5 .INIT = 1'b0; + X_FF \vga/crt/ram_data_5 ( + .I(\vga/crt/_mux0002 [5]), + .CE(\vga/crt/_not0008_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/ram_data<5>/FFX/RST ), + .O(\vga/crt/ram_data [5]) + ); + defparam \vga/crt/ram_data<5>/FFX/RSTOR .LOC = "CLB_R14C13.S1"; + X_BUF \vga/crt/ram_data<5>/FFX/RSTOR ( + .I(\vga/crt/ram_data<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/ram_data<5>/FFX/RST ) + ); + defparam \vga/scancode_convert/state_FFd6 .LOC = "CLB_R12C28.S0"; + defparam \vga/scancode_convert/state_FFd6 .INIT = 1'b1; + X_FF \vga/scancode_convert/state_FFd6 ( + .I(\vga/scancode_convert/state_FFd6/LOGIC_ZERO_165 ), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/scancode_convert/state_FFd6/FFX/SET ), + .RST(GND), + .O(\vga/scancode_convert/state_FFd6_35 ) + ); + defparam \vga/scancode_convert/state_FFd6/FFX/SETOR .LOC = "CLB_R12C28.S0"; + X_BUF \vga/scancode_convert/state_FFd6/FFX/SETOR ( + .I(\vga/scancode_convert/state_FFd6/SRMUX_OUTPUTNOT ), + .O(\vga/scancode_convert/state_FFd6/FFX/SET ) + ); + defparam \vga/ps2/timer_r_11 .LOC = "CLB_R6C17.S0"; + defparam \vga/ps2/timer_r_11 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_11 ( + .I(\vga/ps2/timer_x [11]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<11>/FFX/RST ), + .O(\vga/ps2/timer_r [11]) + ); + defparam \vga/ps2/timer_r<11>/FFX/RSTOR .LOC = "CLB_R6C17.S0"; + X_BUF \vga/ps2/timer_r<11>/FFX/RSTOR ( + .I(\vga/ps2/timer_r<11>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<11>/FFX/RST ) + ); + defparam \vga/video_ram/ram_addr_w_1 .LOC = "CLB_R19C4.S0"; + defparam \vga/video_ram/ram_addr_w_1 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_1 ( + .I(\vga/ram_addr_mux [1]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [1]) + ); + defparam \vga/video_ram/ram_addr_w_3 .LOC = "CLB_R15C2.S0"; + defparam \vga/video_ram/ram_addr_w_3 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_3 ( + .I(\vga/ram_addr_mux [3]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [3]) + ); + defparam \vga/video_ram/ram_addr_w_7 .LOC = "CLB_R15C2.S1"; + defparam \vga/video_ram/ram_addr_w_7 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_7 ( + .I(\vga/ram_addr_mux [7]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [7]) + ); + defparam \vga/video_ram/ram_addr_w_9 .LOC = "CLB_R15C4.S1"; + defparam \vga/video_ram/ram_addr_w_9 .INIT = 1'b0; + X_FF \vga/video_ram/ram_addr_w_9 ( + .I(\vga/ram_addr_mux [9]), + .CE(VCC), + .CLK(\vga/ram_wclk_5 ), + .SET(GND), + .RST(GND), + .O(\vga/video_ram/ram_addr_w [9]) + ); + defparam \vga/scancode_convert/hold_count_1 .LOC = "CLB_R14C26.S0"; + defparam \vga/scancode_convert/hold_count_1 .INIT = 1'b0; + X_FF \vga/scancode_convert/hold_count_1 ( + .I(\vga/scancode_convert/hold_count__mux0000 [1]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/scancode_convert/hold_count<1>/FFX/RST ), + .O(\vga/scancode_convert/hold_count [1]) + ); + defparam \vga/scancode_convert/hold_count<1>/FFX/RSTOR .LOC = "CLB_R14C26.S0"; + X_BUF \vga/scancode_convert/hold_count<1>/FFX/RSTOR ( + .I(\vga/scancode_convert/hold_count<1>/SRMUX_OUTPUTNOT ), + .O(\vga/scancode_convert/hold_count<1>/FFX/RST ) + ); + defparam \vga/ps2/timer_r_3 .LOC = "CLB_R9C16.S0"; + defparam \vga/ps2/timer_r_3 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_3 ( + .I(\vga/ps2/timer_x [3]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<3>/FFX/RST ), + .O(\vga/ps2/timer_r [3]) + ); + defparam \vga/ps2/timer_r<3>/FFX/RSTOR .LOC = "CLB_R9C16.S0"; + X_BUF \vga/ps2/timer_r<3>/FFX/RSTOR ( + .I(\vga/ps2/timer_r<3>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<3>/FFX/RST ) + ); + defparam \vga/ps2/timer_r_5 .LOC = "CLB_R8C16.S0"; + defparam \vga/ps2/timer_r_5 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_5 ( + .I(\vga/ps2/timer_x [5]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<5>/FFX/RST ), + .O(\vga/ps2/timer_r [5]) + ); + defparam \vga/ps2/timer_r<5>/FFX/RSTOR .LOC = "CLB_R8C16.S0"; + X_BUF \vga/ps2/timer_r<5>/FFX/RSTOR ( + .I(\vga/ps2/timer_r<5>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<5>/FFX/RST ) + ); + defparam \vga/ps2/timer_r_9 .LOC = "CLB_R7C17.S0"; + defparam \vga/ps2/timer_r_9 .INIT = 1'b0; + X_FF \vga/ps2/timer_r_9 ( + .I(\vga/ps2/timer_x [9]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(\vga/ps2/timer_r<9>/FFX/RST ), + .O(\vga/ps2/timer_r [9]) + ); + defparam \vga/ps2/timer_r<9>/FFX/RSTOR .LOC = "CLB_R7C17.S0"; + X_BUF \vga/ps2/timer_r<9>/FFX/RSTOR ( + .I(\vga/ps2/timer_r<9>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/timer_r<9>/FFX/RST ) + ); + defparam \vga/pclk_1 .LOC = "CLB_R14C6.S1"; + defparam \vga/pclk_1 .INIT = 1'b1; + X_FF \vga/pclk_1 ( + .I(\vga/pclk__mux0000 [1]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/pclk<1>/FFX/SET ), + .RST(GND), + .O(\vga/pclk [1]) + ); + defparam \vga/pclk<1>/FFX/SETOR .LOC = "CLB_R14C6.S1"; + X_BUF \vga/pclk<1>/FFX/SETOR ( + .I(\vga/pclk<1>/SRMUX_OUTPUTNOT ), + .O(\vga/pclk<1>/FFX/SET ) + ); + defparam \vga/crt/cursor_h_1 .LOC = "CLB_R18C13.S1"; + defparam \vga/crt/cursor_h_1 .INIT = 1'b0; + X_FF \vga/crt/cursor_h_1 ( + .I(\vga/crt/cursor_h_Eqn_1 ), + .CE(\vga/crt/_not0006_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_h<1>/FFX/RST ), + .O(\vga/crt/cursor_h [1]) + ); + defparam \vga/crt/cursor_h<1>/FFX/RSTOR .LOC = "CLB_R18C13.S1"; + X_BUF \vga/crt/cursor_h<1>/FFX/RSTOR ( + .I(\vga/crt/cursor_h<1>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_h<1>/FFX/RST ) + ); + defparam \vga/crt/cursor_h_3 .LOC = "CLB_R17C13.S0"; + defparam \vga/crt/cursor_h_3 .INIT = 1'b0; + X_FF \vga/crt/cursor_h_3 ( + .I(\vga/crt/cursor_h_Eqn_3 ), + .CE(\vga/crt/_not0006_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_h<3>/FFX/RST ), + .O(\vga/crt/cursor_h [3]) + ); + defparam \vga/crt/cursor_h<3>/FFX/RSTOR .LOC = "CLB_R17C13.S0"; + X_BUF \vga/crt/cursor_h<3>/FFX/RSTOR ( + .I(\vga/crt/cursor_h<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_h<3>/FFX/RST ) + ); + defparam \vga/crt/cursor_h_5 .LOC = "CLB_R17C14.S0"; + defparam \vga/crt/cursor_h_5 .INIT = 1'b0; + X_FF \vga/crt/cursor_h_5 ( + .I(\vga/crt/cursor_h_Eqn_5 ), + .CE(\vga/crt/_not0006_0 ), + .CLK(\vga/crtclk_4 ), + .SET(GND), + .RST(\vga/crt/cursor_h<5>/FFX/RST ), + .O(\vga/crt/cursor_h [5]) + ); + defparam \vga/crt/cursor_h<5>/FFX/RSTOR .LOC = "CLB_R17C14.S0"; + X_BUF \vga/crt/cursor_h<5>/FFX/RSTOR ( + .I(\vga/crt/cursor_h<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt/cursor_h<5>/FFX/RST ) + ); + defparam \vga/scancode_convert/sc_1 .LOC = "CLB_R14C35.S0"; + defparam \vga/scancode_convert/sc_1 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_1 ( + .I(\vga/ps2/sc_r [1]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc [1]) + ); + defparam \vga/scancode_convert/sc_3 .LOC = "CLB_R13C34.S1"; + defparam \vga/scancode_convert/sc_3 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_3 ( + .I(\vga/ps2/sc_r [3]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc [3]) + ); + defparam \vga/scancode_convert/sc_5 .LOC = "CLB_R10C35.S0"; + defparam \vga/scancode_convert/sc_5 .INIT = 1'b0; + X_FF \vga/scancode_convert/sc_5 ( + .I(\vga/ps2/sc_r [5]), + .CE(\vga/scancode_convert/_and0000_0 ), + .CLK(gray_cnt_FFd1_0), + .SET(GND), + .RST(GND), + .O(\vga/scancode_convert/sc [5]) + ); + defparam \vga/rom_addr_char_1 .LOC = "CLB_R16C1.S0"; + defparam \vga/rom_addr_char_1 .INIT = 1'b0; + X_FF \vga/rom_addr_char_1 ( + .I(\vga/ram_data_out [1]), + .CE(VCC), + .CLK(\vga/rom_addr_char<1>/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char [1]) + ); + defparam \vga/rom_addr_char_3 .LOC = "CLB_R27C1.S0"; + defparam \vga/rom_addr_char_3 .INIT = 1'b0; + X_FF \vga/rom_addr_char_3 ( + .I(\vga/ram_data_out [3]), + .CE(VCC), + .CLK(\vga/rom_addr_char<3>/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char [3]) + ); + defparam \vga/rom_addr_char_5 .LOC = "CLB_R12C1.S0"; + defparam \vga/rom_addr_char_5 .INIT = 1'b0; + X_FF \vga/rom_addr_char_5 ( + .I(\vga/ram_data_out [5]), + .CE(VCC), + .CLK(\vga/rom_addr_char<5>/CKMUXNOT ), + .SET(GND), + .RST(GND), + .O(\vga/rom_addr_char [5]) + ); + defparam \vga/ps2/ps2_clk_r_2 .LOC = "CLB_R11C8.S1"; + defparam \vga/ps2/ps2_clk_r_2 .INIT = 1'b1; + X_FF \vga/ps2/ps2_clk_r_2 ( + .I(\vga/ps2/ps2_clk_r [1]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/ps2/ps2_clk_r<2>/FFX/SET ), + .RST(GND), + .O(\vga/ps2/ps2_clk_r [2]) + ); + defparam \vga/ps2/ps2_clk_r<2>/FFX/SETOR .LOC = "CLB_R11C8.S1"; + X_BUF \vga/ps2/ps2_clk_r<2>/FFX/SETOR ( + .I(\vga/ps2/ps2_clk_r<2>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/ps2_clk_r<2>/FFX/SET ) + ); + defparam \vga/ps2/ps2_clk_r_4 .LOC = "CLB_R10C13.S0"; + defparam \vga/ps2/ps2_clk_r_4 .INIT = 1'b1; + X_FF \vga/ps2/ps2_clk_r_4 ( + .I(\vga/ps2/ps2_clk_r [3]), + .CE(VCC), + .CLK(gray_cnt_FFd1_0), + .SET(\vga/ps2/ps2_clk_r<4>/FFX/SET ), + .RST(GND), + .O(\vga/ps2/ps2_clk_r [4]) + ); + defparam \vga/ps2/ps2_clk_r<4>/FFX/SETOR .LOC = "CLB_R10C13.S0"; + X_BUF \vga/ps2/ps2_clk_r<4>/FFX/SETOR ( + .I(\vga/ps2/ps2_clk_r<4>/SRMUX_OUTPUTNOT ), + .O(\vga/ps2/ps2_clk_r<4>/FFX/SET ) + ); + defparam gray_cnt_FFd1.LOC = "CLB_R2C21.S0"; + defparam gray_cnt_FFd1.INIT = 1'b0; + X_FF gray_cnt_FFd1 ( + .I(gray_cnt_FFd2_36), + .CE(VCC), + .CLK(clka_BUFGP), + .SET(GND), + .RST(\gray_cnt_FFd11/FFX/RST ), + .O(gray_cnt_FFd11) + ); + defparam \gray_cnt_FFd11/FFX/RSTOR .LOC = "CLB_R2C21.S0"; + X_BUF \gray_cnt_FFd11/FFX/RSTOR ( + .I(\gray_cnt_FFd11/SRMUX_OUTPUTNOT ), + .O(\gray_cnt_FFd11/FFX/RST ) + ); + defparam \vga/crt_data_1 .LOC = "CLB_R16C25.S0"; + defparam \vga/crt_data_1 .INIT = 1'b0; + X_FF \vga/crt_data_1 ( + .I(\vga/scancode_convert/ascii [1]), + .CE(VCC), + .CLK(\vga/scancode_convert/strobe_out_15 ), + .SET(GND), + .RST(\vga/crt_data<1>/FFX/RST ), + .O(\vga/crt_data [1]) + ); + defparam \vga/crt_data<1>/FFX/RSTOR .LOC = "CLB_R16C25.S0"; + X_BUF \vga/crt_data<1>/FFX/RSTOR ( + .I(\vga/crt_data<1>/SRMUX_OUTPUTNOT ), + .O(\vga/crt_data<1>/FFX/RST ) + ); + defparam \vga/crt_data_3 .LOC = "CLB_R16C21.S0"; + defparam \vga/crt_data_3 .INIT = 1'b0; + X_FF \vga/crt_data_3 ( + .I(\vga/scancode_convert/ascii [3]), + .CE(VCC), + .CLK(\vga/scancode_convert/strobe_out_15 ), + .SET(GND), + .RST(\vga/crt_data<3>/FFX/RST ), + .O(\vga/crt_data [3]) + ); + defparam \vga/crt_data<3>/FFX/RSTOR .LOC = "CLB_R16C21.S0"; + X_BUF \vga/crt_data<3>/FFX/RSTOR ( + .I(\vga/crt_data<3>/SRMUX_OUTPUTNOT ), + .O(\vga/crt_data<3>/FFX/RST ) + ); + defparam \vga/crt_data_5 .LOC = "CLB_R14C25.S1"; + defparam \vga/crt_data_5 .INIT = 1'b0; + X_FF \vga/crt_data_5 ( + .I(\vga/scancode_convert/ascii [5]), + .CE(VCC), + .CLK(\vga/scancode_convert/strobe_out_15 ), + .SET(GND), + .RST(\vga/crt_data<5>/FFX/RST ), + .O(\vga/crt_data [5]) + ); + defparam \vga/crt_data<5>/FFX/RSTOR .LOC = "CLB_R14C25.S1"; + X_BUF \vga/crt_data<5>/FFX/RSTOR ( + .I(\vga/crt_data<5>/SRMUX_OUTPUTNOT ), + .O(\vga/crt_data<5>/FFX/RST ) + ); + X_ONE GLOBAL_LOGIC1_VCC ( + .O(GLOBAL_LOGIC1) + ); + X_ZERO GLOBAL_LOGIC0_GND ( + .O(GLOBAL_LOGIC0) + ); + defparam \clka/PAD .LOC = "GCLKPAD1"; + X_IPAD \clka/PAD ( + .PAD(clka) + ); + defparam \vga/crtclk_BUFG/BUF .LOC = "GCLKBUF0"; + X_CKBUF \vga/crtclk_BUFG/BUF ( + .I(\vga/crtclk1 ), + .O(\vga/crtclk_4 ) + ); + defparam \clka_BUFGP/BUFG/BUF .LOC = "GCLKBUF1"; + X_CKBUF \clka_BUFGP/BUFG/BUF ( + .I(clka), + .O(clka_BUFGP) + ); + defparam \gray_cnt_FFd1_BUFG/BUF .LOC = "GCLKBUF3"; + X_CKBUF \gray_cnt_FFd1_BUFG/BUF ( + .I(gray_cnt_FFd11), + .O(gray_cnt_FFd1_0) + ); + X_ZERO NlwBlock_fpga_GND ( + .O(GND) + ); + X_ONE NlwBlock_fpga_VCC ( + .O(VCC) + ); +endmodule + + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire PRLD; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + diff --git a/xilinx/vga/netgen/synthesis/fpga_synthesis.nlf b/xilinx/vga/netgen/synthesis/fpga_synthesis.nlf new file mode 100644 index 0000000..f2e59af --- /dev/null +++ b/xilinx/vga/netgen/synthesis/fpga_synthesis.nlf @@ -0,0 +1,19 @@ +Release 8.2i - netgen I.31 +Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. + +Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis +-ofmt verilog -sim fpga.ngc fpga_synthesis.v + +Reading design 'fpga.ngc' ... +Flattening design ... +Processing design ... + Preping design's networks ... + Preping design's macros ... +Writing Verilog netlist file +'/mwave/work/nt/xess/xilinx/vga/netgen/synthesis/fpga_synthesis.v' ... +INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM + simulation primitives and has to be used with UNISIM simulation library for + correct compilation and simulation. +Number of warnings: 0 +Number of info messages: 1 +Total memory usage is 151704 kilobytes diff --git a/xilinx/vga/netgen/synthesis/fpga_synthesis.v b/xilinx/vga/netgen/synthesis/fpga_synthesis.v new file mode 100644 index 0000000..30cefc0 --- /dev/null +++ b/xilinx/vga/netgen/synthesis/fpga_synthesis.v @@ -0,0 +1,8736 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: I.31 +// \ \ Application: netgen +// / / Filename: fpga_synthesis.v +// /___/ /\ Timestamp: Fri Dec 29 10:06:07 2006 +// \ \ / \ +// \___\/\___\ +// +// Command : -intstyle ise -insert_glbl true -w -dir netgen/synthesis -ofmt verilog -sim fpga.ngc fpga_synthesis.v +// Device : xc2s200-5-fg256 +// Input file : fpga.ngc +// Output file : /mwave/work/nt/xess/xilinx/vga/netgen/synthesis/fpga_synthesis.v +// # of Modules : 1 +// Design Name : fpga +// Xilinx : /opt/Xilinx +// +// Purpose: +// This verilog netlist is a verification model and uses simulation +// primitives which may not represent the true implementation of the +// device, however the netlist is functionally correct and should not +// be modified. This file cannot be synthesized and should only be used +// with supported simulation tools. +// +// Reference: +// Development System Reference Guide, Chapter 23 +// Synthesis and Simulation Design Guide, Chapter 6 +// +//////////////////////////////////////////////////////////////////////////////// + +`timescale 1 ns/1 ps + +module fpga ( + reset_n, ps2_clk, ps2_data, clka, vga_hsync_n, fpga_din_d0, vga_red0, vga_red1, vga_red2, vga_green0, vga_green1, vga_green2, vga_blue0, vga_blue1, +vga_blue2, vga_vsync_n, fpga_d1, fpga_d2, fpga_d3, fpga_d4, fpga_d5, fpga_d6, fpga_d7 +); + input reset_n; + input ps2_clk; + input ps2_data; + input clka; + output vga_hsync_n; + output fpga_din_d0; + output vga_red0; + output vga_red1; + output vga_red2; + output vga_green0; + output vga_green1; + output vga_green2; + output vga_blue0; + output vga_blue1; + output vga_blue2; + output vga_vsync_n; + output fpga_d1; + output fpga_d2; + output fpga_d3; + output fpga_d4; + output fpga_d5; + output fpga_d6; + output fpga_d7; + wire reset_n_IBUF_0; + wire ps2_clk_IBUF_1; + wire ps2_data_IBUF_2; + wire vga_hsync_n_OBUF_3; + wire clka_BUFGP_4; + wire vga_vsync_n_OBUF_5; + wire \vga/vgacore/vsync_6 ; + wire \vga/vgacore/hsync_7 ; + wire \vga/ps2/rdy_r_8 ; + wire N2; + wire N3; + wire gray_cnt_FFd1_9; + wire gray_cnt_FFd2_10; + wire \gray_cnt_FFd2-In ; + wire gray_cnt_Rst_inv; + wire \vga/ram_wclk_11 ; + wire \vga/_cmp_eq0000 ; + wire \vga/_not0001 ; + wire \vga/insert_crt_data ; + wire \vga/_mux0000 ; + wire \vga/vgacore/hblank_12 ; + wire \vga/cursor_match ; + wire \vga/charload_13 ; + wire \vga/clearing ; + wire \vga/charclk ; + wire \vga/scancode_convert/strobe_out_14 ; + wire \vga/crtclk_15 ; + wire \vga/ram_we_n ; + wire \vga/scancode_convert/key_up_16 ; + wire \vga/pixel_hold<7>_inv ; + wire \vga/Madd_ram_addr_videoR2 ; + wire \vga/Madd_ram_addr_videoC2 ; + wire \vga/N2 ; + wire \vga/N4 ; + wire \vga/N6 ; + wire \vga/N7 ; + wire \vga/N8 ; + wire \vga/N10 ; + wire \vga/N11 ; + wire \vga/N12 ; + wire \vga/N13 ; + wire \vga/N14 ; + wire \vga/N15 ; + wire \vga/N16 ; + wire \vga/N17 ; + wire \vga/N20 ; + wire \vga/N21 ; + wire \vga/N22 ; + wire \vga/N23 ; + wire \vga/N24 ; + wire \vga/N25 ; + wire \vga/N26 ; + wire \vga/N27 ; + wire \vga/N28 ; + wire \vga/N29 ; + wire \vga/N30 ; + wire \vga/N31 ; + wire \vga/N32 ; + wire \vga/N33 ; + wire \vga/N34 ; + wire \vga/N35 ; + wire \vga/N37 ; + wire \vga/N38 ; + wire \vga/N39 ; + wire \vga/N40 ; + wire \vga/N41 ; + wire \vga/N43 ; + wire \vga/N44 ; + wire \vga/N45 ; + wire \vga/N47 ; + wire \vga/N48 ; + wire \vga/N49 ; + wire \vga/N50 ; + wire \vga/N53 ; + wire \vga/N54 ; + wire \vga/N55 ; + wire \vga/N56 ; + wire \vga/N57 ; + wire \vga/N58 ; + wire \vga/N59 ; + wire \vga/N60 ; + wire \vga/N61 ; + wire \vga/N62 ; + wire \vga/N63 ; + wire \vga/N64 ; + wire \vga/N65 ; + wire \vga/N66 ; + wire \vga/N67 ; + wire \vga/N68 ; + wire \vga/N69 ; + wire \vga/N70 ; + wire \vga/N71 ; + wire \vga/N72 ; + wire \vga/N73 ; + wire \vga/N74 ; + wire \vga/N75 ; + wire \vga/N78 ; + wire \vga/N79 ; + wire \vga/N80 ; + wire \vga/N81 ; + wire \vga/N82 ; + wire \vga/N83 ; + wire \vga/N85 ; + wire \vga/N86 ; + wire \vga/N87 ; + wire \vga/N88 ; + wire \vga/N89 ; + wire \vga/N90 ; + wire \vga/N94 ; + wire \vga/N95 ; + wire \vga/N96 ; + wire \vga/N98 ; + wire \vga/N99 ; + wire \vga/N101 ; + wire \vga/N102 ; + wire \vga/N104 ; + wire \vga/N105 ; + wire \vga/N106 ; + wire \vga/N110 ; + wire \vga/N111 ; + wire \vga/N113 ; + wire \vga/N114 ; + wire \vga/N115 ; + wire \vga/N116 ; + wire \vga/N117 ; + wire \vga/N118 ; + wire \vga/N120 ; + wire \vga/N121 ; + wire \vga/N125 ; + wire \vga/N126 ; + wire \vga/N127 ; + wire \vga/N128 ; + wire \vga/N129 ; + wire \vga/N130 ; + wire \vga/N131 ; + wire \vga/N132 ; + wire \vga/N133 ; + wire \vga/N134 ; + wire \vga/N137 ; + wire \vga/N138 ; + wire \vga/N139 ; + wire \vga/N142 ; + wire \vga/N143 ; + wire \vga/N144 ; + wire \vga/N145 ; + wire \vga/N146 ; + wire \vga/N147 ; + wire \vga/N149 ; + wire \vga/N150 ; + wire \vga/N151 ; + wire \vga/N152 ; + wire \vga/N155 ; + wire \vga/N157 ; + wire \vga/N159 ; + wire \vga/N167 ; + wire \vga/N170 ; + wire \vga/N171 ; + wire \vga/N172 ; + wire \vga/N175 ; + wire \vga/N176 ; + wire \vga/N178 ; + wire \vga/N179 ; + wire \vga/N183 ; + wire \vga/N184 ; + wire \vga/N186 ; + wire \vga/N190 ; + wire \vga/N191 ; + wire \vga/N192 ; + wire \vga/N193 ; + wire \vga/N194 ; + wire \vga/N201 ; + wire \vga/N205 ; + wire \vga/N208 ; + wire \vga/N213 ; + wire \vga/N214 ; + wire \vga/N215 ; + wire \vga/N216 ; + wire \vga/N218 ; + wire \vga/N219 ; + wire \vga/N221 ; + wire \vga/N222 ; + wire \vga/N224 ; + wire \vga/N226 ; + wire \vga/N01 ; + wire \vga/N1101 ; + wire \vga/rom_addr_char<2>_f5_17 ; + wire \vga/N2123 ; + wire \vga/N312 ; + wire \vga/rom_addr_char<2>_f51_18 ; + wire \vga/rom_addr_char<3>_f6_19 ; + wire \vga/N412 ; + wire \vga/N512 ; + wire \vga/rom_addr_char<2>_f52_20 ; + wire \vga/N612 ; + wire \vga/N712 ; + wire \vga/rom_addr_char<2>_f53_21 ; + wire \vga/rom_addr_char<3>_f61_22 ; + wire \vga/N912 ; + wire \vga/N1011 ; + wire \vga/rom_addr_char<2>_f54_23 ; + wire \vga/N1111 ; + wire \vga/N1211 ; + wire \vga/rom_addr_char<2>_f55 ; + wire \vga/rom_addr_char<3>_f62_24 ; + wire \vga/N1311 ; + wire \vga/N1411 ; + wire \vga/rom_addr_char<2>_f56 ; + wire \vga/N1511 ; + wire \vga/N1611 ; + wire \vga/rom_addr_char<2>_f57 ; + wire \vga/rom_addr_char<3>_f63_25 ; + wire \vga/rom_addr_char<4>11_26 ; + wire \vga/N1711 ; + wire \vga/N1811 ; + wire \vga/rom_addr_char<2>_f58 ; + wire \vga/rom_addr_char<2>11_27 ; + wire \vga/N1911 ; + wire \vga/N2011 ; + wire \vga/N2111 ; + wire \vga/rom_addr_char<2>_f59 ; + wire \vga/rom_addr_char<2>2 ; + wire \vga/N2211 ; + wire \vga/rom_addr_char<4>_f5_28 ; + wire \vga/N1112 ; + wire \vga/N0112 ; + wire \vga/N11123 ; + wire \vga/N01123 ; + wire \vga/N111234 ; + wire \vga/rom_addr_char<2>_f512 ; + wire \vga/N21234 ; + wire \vga/N3123 ; + wire \vga/rom_addr_char<2>_f511 ; + wire \vga/rom_addr_char<3>_f612 ; + wire \vga/N4123 ; + wire \vga/N5 ; + wire \vga/rom_addr_char<2>_f521 ; + wire \vga/N6123 ; + wire \vga/N7123 ; + wire \vga/rom_addr_char<2>_f531 ; + wire \vga/rom_addr_char<3>_f611 ; + wire \vga/N8123 ; + wire \vga/N9 ; + wire \vga/rom_addr_char<2>_f541 ; + wire \vga/N1012 ; + wire \vga/N11112 ; + wire \vga/rom_addr_char<2>_f551 ; + wire \vga/rom_addr_char<3>_f621 ; + wire \vga/N1212 ; + wire \vga/N1312 ; + wire \vga/rom_addr_char<2>_f561 ; + wire \vga/N1412 ; + wire \vga/N1512 ; + wire \vga/rom_addr_char<2>_f571 ; + wire \vga/rom_addr_char<3>_f631 ; + wire \vga/N1612 ; + wire \vga/N1712 ; + wire \vga/N1812 ; + wire \vga/rom_addr_char<2>_f581 ; + wire \vga/N1912 ; + wire \vga/N2012 ; + wire \vga/rom_addr_char<2>_f591 ; + wire \vga/rom_addr_char<3>_f64_29 ; + wire \vga/N2112 ; + wire \vga/N2212 ; + wire \vga/rom_addr_char<2>_f510 ; + wire \vga/N231 ; + wire \vga/N241 ; + wire \vga/rom_addr_char<2>_f5111 ; + wire \vga/rom_addr_char<3>_f65 ; + wire \vga/N251 ; + wire \vga/rom_addr_char<5>_f5_30 ; + wire \vga/N011234 ; + wire \vga/N1112345 ; + wire \vga/rom_addr_char<2>_f5123 ; + wire \vga/N212345 ; + wire \vga/N31234 ; + wire \vga/rom_addr_char<2>_f5112 ; + wire \vga/rom_addr_char<3>_f6123 ; + wire \vga/N41234 ; + wire \vga/N5123 ; + wire \vga/rom_addr_char<2>_f5212 ; + wire \vga/N61234 ; + wire \vga/N71234 ; + wire \vga/rom_addr_char<2>_f5312 ; + wire \vga/rom_addr_char<3>_f6112 ; + wire \vga/N81234 ; + wire \vga/N91 ; + wire \vga/rom_addr_char<2>_f5412 ; + wire \vga/N10123 ; + wire \vga/N111123 ; + wire \vga/rom_addr_char<2>_f5512 ; + wire \vga/rom_addr_char<3>_f6212 ; + wire \vga/N12123 ; + wire \vga/N13123 ; + wire \vga/rom_addr_char<2>_f5612 ; + wire \vga/N14123 ; + wire \vga/N15123 ; + wire \vga/rom_addr_char<2>_f5712 ; + wire \vga/rom_addr_char<3>_f6312 ; + wire \vga/N16123 ; + wire \vga/N17123 ; + wire \vga/N18123 ; + wire \vga/rom_addr_char<2>_f5812 ; + wire \vga/N19123 ; + wire \vga/N20123 ; + wire \vga/rom_addr_char<2>_f5912 ; + wire \vga/rom_addr_char<3>_f641 ; + wire \vga/N21123 ; + wire \vga/N22123 ; + wire \vga/rom_addr_char<2>_f5101 ; + wire \vga/N2412 ; + wire \vga/rom_addr_char<2>_f51112 ; + wire \vga/rom_addr_char<3>_f651 ; + wire \vga/N2512 ; + wire \vga/rom_addr_char<5>_f51_31 ; + wire \vga/N0112345 ; + wire \vga/N11123456 ; + wire \vga/rom_addr_char<2>_f51234 ; + wire \vga/N2123456 ; + wire \vga/N312345 ; + wire \vga/rom_addr_char<2>_f51123 ; + wire \vga/N412345 ; + wire \vga/N51234 ; + wire \vga/rom_addr_char<2>_f52123 ; + wire \vga/rom_addr_char<3>_f61234 ; + wire \vga/N612345 ; + wire \vga/N712345 ; + wire \vga/rom_addr_char<2>_f53123 ; + wire \vga/N9123 ; + wire \vga/rom_addr_char<2>_f54123 ; + wire \vga/rom_addr_char<3>_f61123 ; + wire \vga/N101234 ; + wire \vga/N1110 ; + wire \vga/rom_addr_char<2>_f55123 ; + wire \vga/N121234 ; + wire \vga/N131234 ; + wire \vga/rom_addr_char<2>_f56123 ; + wire \vga/rom_addr_char<3>_f62123 ; + wire \vga/N141234 ; + wire \vga/N151234 ; + wire \vga/N161234 ; + wire \vga/rom_addr_char<2>_f57123 ; + wire \vga/N181234 ; + wire \vga/rom_addr_char<2>_f58123 ; + wire \vga/rom_addr_char<3>_f63123 ; + wire \vga/N191234 ; + wire \vga/N201234 ; + wire \vga/rom_addr_char<2>_f59123 ; + wire \vga/N211234 ; + wire \vga/N221234 ; + wire \vga/rom_addr_char<2>_f51012 ; + wire \vga/rom_addr_char<3>_f6412 ; + wire \vga/N23123 ; + wire \vga/rom_addr_char<5>_f512 ; + wire \vga/rom_addr_char<1>_mmx_out ; + wire \vga/N01123456 ; + wire \vga/N111234567 ; + wire \vga/rom_addr_char<2>_f512345 ; + wire \vga/N21234567 ; + wire \vga/N3123456 ; + wire \vga/rom_addr_char<2>_f511234 ; + wire \vga/rom_addr_char<3>_f612345 ; + wire \vga/N4123456 ; + wire \vga/N512345 ; + wire \vga/rom_addr_char<2>_f521234 ; + wire \vga/N6123456 ; + wire \vga/N7123456 ; + wire \vga/rom_addr_char<2>_f531234 ; + wire \vga/rom_addr_char<3>_f611234 ; + wire \vga/N8123456 ; + wire \vga/N91234 ; + wire \vga/rom_addr_char<2>_f541234 ; + wire \vga/N1012345 ; + wire \vga/N1111234 ; + wire \vga/rom_addr_char<2>_f551234 ; + wire \vga/rom_addr_char<3>_f621234 ; + wire \vga/N1212345 ; + wire \vga/N1312345 ; + wire \vga/rom_addr_char<2>_f561234 ; + wire \vga/N1412345 ; + wire \vga/N1512345 ; + wire \vga/rom_addr_char<2>_f571234 ; + wire \vga/rom_addr_char<3>_f631234 ; + wire \vga/N1612345 ; + wire \vga/rom_addr_char<1>112_32 ; + wire \vga/N1712345 ; + wire \vga/rom_addr_char<1>2_33 ; + wire \vga/N1812345 ; + wire \vga/rom_addr_char<3>_f5_34 ; + wire \vga/N1912345 ; + wire \vga/N2012345 ; + wire \vga/rom_addr_char<2>_f581234 ; + wire \vga/N2212345 ; + wire \vga/rom_addr_char<2>_f591234 ; + wire \vga/rom_addr_char<3>_f64123 ; + wire \vga/N231234 ; + wire \vga/rom_addr_char<5>_f5123 ; + wire \vga/N011234567 ; + wire \vga/rom_addr_char<4>11234 ; + wire \vga/Madd_ram_addr_videoC_mand1 ; + wire \vga/Madd_ram_addr_videoC1_mand1 ; + wire \vga/N229 ; + wire \vga/N230 ; + wire \vga/Madd_ram_addr_videoC3_mand1 ; + wire \vga/N2313 ; + wire \vga/Madd_ram_addr_videoC4_mand1 ; + wire \vga/N232 ; + wire \vga/N233 ; + wire \vga/crt/_cmp_eq0001 ; + wire \vga/crt/_cmp_eq0004 ; + wire \vga/crt/_not0010 ; + wire \vga/crt/_not0006 ; + wire \vga/crt/_not0007 ; + wire \vga/crt/_not0008 ; + wire \vga/crt/eol_35 ; + wire \vga/crt/scroll_36 ; + wire \vga/crt/newline_37 ; + wire \vga/crt/_and0000_38 ; + wire \vga/crt/_and0001_39 ; + wire \vga/crt/Madd_ram_addrR2 ; + wire \vga/crt/Madd_ram_addrC2 ; + wire \vga/crt/cursor_v_Eqn_0 ; + wire \vga/crt/cursor_v_Eqn_1 ; + wire \vga/crt/cursor_v_Eqn_2 ; + wire \vga/crt/cursor_v_Eqn_3 ; + wire \vga/crt/cursor_v_Eqn_4 ; + wire \vga/crt/cursor_v_Eqn_5 ; + wire \vga/crt/Result<0>1 ; + wire \vga/crt/cursor_h_Eqn_0 ; + wire \vga/crt/Result<1>1 ; + wire \vga/crt/cursor_h_Eqn_1 ; + wire \vga/crt/Result<2>1 ; + wire \vga/crt/cursor_h_Eqn_2 ; + wire \vga/crt/Result<3>1 ; + wire \vga/crt/cursor_h_Eqn_3 ; + wire \vga/crt/Result<4>1 ; + wire \vga/crt/cursor_h_Eqn_4 ; + wire \vga/crt/Result<5>1 ; + wire \vga/crt/cursor_h_Eqn_5 ; + wire \vga/crt/cursor_h_Eqn_6 ; + wire \vga/crt/N3 ; + wire \vga/crt/Madd_ram_addrC_mand1 ; + wire \vga/crt/Madd_ram_addrC1_mand1 ; + wire \vga/crt/N8 ; + wire \vga/crt/N9 ; + wire \vga/crt/Madd_ram_addrC3_mand1 ; + wire \vga/crt/N10 ; + wire \vga/crt/Madd_ram_addrC4_mand1 ; + wire \vga/crt/N11 ; + wire \vga/crt/N12 ; + wire \vga/crt/state_FFd1_40 ; + wire \vga/crt/state_FFd2_41 ; + wire \vga/crt/state_FFd3_42 ; + wire \vga/crt/state_FFd1-In_43 ; + wire \vga/crt/state_FFd2-In ; + wire \vga/crt/state_FFd3-In ; + wire \vga/crt/N91 ; + wire \vga/crt/N16 ; + wire \vga/vgacore/_mux0002 ; + wire \vga/vgacore/_and0000 ; + wire \vga/vgacore/_and0001_44 ; + wire \vga/vgacore/hcnt_Eqn_1 ; + wire \vga/vgacore/hcnt_Eqn_2 ; + wire \vga/vgacore/hcnt_Eqn_3 ; + wire \vga/vgacore/hcnt_Eqn_4 ; + wire \vga/vgacore/hcnt_Eqn_5 ; + wire \vga/vgacore/hcnt_Eqn_6 ; + wire \vga/vgacore/hcnt_Eqn_7 ; + wire \vga/vgacore/hcnt_Eqn_8 ; + wire \vga/vgacore/hcnt_Eqn_9 ; + wire \vga/vgacore/hcnt_Eqn_10 ; + wire \vga/vgacore/hcnt_Eqn_bis_0 ; + wire \vga/vgacore/vcnt_Eqn_1_45 ; + wire \vga/vgacore/vcnt_Eqn_2 ; + wire \vga/vgacore/vcnt_Eqn_3_46 ; + wire \vga/vgacore/vcnt_Eqn_4 ; + wire \vga/vgacore/vcnt_Eqn_5 ; + wire \vga/vgacore/vcnt_Eqn_6 ; + wire \vga/vgacore/vcnt_Eqn_7 ; + wire \vga/vgacore/vcnt_Eqn_8 ; + wire \vga/vgacore/vcnt_Eqn_9 ; + wire \vga/vgacore/Result<0>1 ; + wire \vga/vgacore/Result<1>1 ; + wire \vga/vgacore/Result<2>1 ; + wire \vga/vgacore/Result<3>1 ; + wire \vga/vgacore/Result<4>1 ; + wire \vga/vgacore/Result<5>1 ; + wire \vga/vgacore/Result<6>1 ; + wire \vga/vgacore/Result<7>1 ; + wire \vga/vgacore/Result<8>1 ; + wire \vga/vgacore/Result<9>1 ; + wire \vga/vgacore/vcnt_Eqn_bis_0 ; + wire \vga/vgacore/N4 ; + wire \vga/vgacore/N5 ; + wire \vga/vgacore/N6 ; + wire \vga/vgacore/N7 ; + wire \vga/vgacore/hcnt_Eqn_0_mand1 ; + wire \vga/vgacore/vcnt_Eqn_0_mand1 ; + wire \vga/vgacore/N0 ; + wire \vga/vgacore/N51 ; + wire \vga/vgacore/N61 ; + wire \vga/ps2/error_r_47 ; + wire \vga/ps2/error_x ; + wire \vga/ps2/_cmp_eq0000 ; + wire \vga/ps2/_cmp_eq0001 ; + wire \vga/ps2/ps2_clk_fall_edge ; + wire \vga/ps2/scancode_rdy ; + wire \vga/ps2/ps2_clk_edge ; + wire \vga/ps2/N5 ; + wire \vga/scancode_convert/release_prefix_set ; + wire \vga/scancode_convert/capslock_48 ; + wire \vga/scancode_convert/shift_49 ; + wire \vga/scancode_convert/capslock_toggle ; + wire \vga/scancode_convert/state_FFd4_50 ; + wire \vga/scancode_convert/_cmp_eq0000_51 ; + wire \vga/scancode_convert/state_FFd2_52 ; + wire \vga/scancode_convert/_cmp_eq0005 ; + wire \vga/scancode_convert/state_FFd1_53 ; + wire \vga/scancode_convert/state_FFd5_54 ; + wire \vga/scancode_convert/_not0010 ; + wire \vga/scancode_convert/_not0011 ; + wire \vga/scancode_convert/_not0012 ; + wire \vga/scancode_convert/_not0007_55 ; + wire \vga/scancode_convert/_not0008 ; + wire \vga/scancode_convert/_not0009 ; + wire \vga/scancode_convert/state_FFd3_56 ; + wire \vga/scancode_convert/raise ; + wire \vga/scancode_convert/ctrl_57 ; + wire \vga/scancode_convert/_and0000 ; + wire \vga/scancode_convert/ctrl_set_58 ; + wire \vga/scancode_convert/shift_set ; + wire \vga/scancode_convert/_or0000 ; + wire \vga/scancode_convert/release_prefix_59 ; + wire \vga/scancode_convert/state_FFd6_60 ; + wire \vga/scancode_convert/state_FFd1-In ; + wire \vga/scancode_convert/state_FFd2-In_61 ; + wire \vga/scancode_convert/state_FFd3-In_62 ; + wire \vga/scancode_convert/state_FFd4-In ; + wire \vga/scancode_convert/state_FFd5-In_63 ; + wire \vga/scancode_convert/N31 ; + wire \vga/scancode_convert/N10 ; + wire \vga/scancode_convert/N11 ; + wire \vga/scancode_convert/scancode_rom/N7 ; + wire \vga/scancode_convert/scancode_rom/N9 ; + wire \vga/scancode_convert/scancode_rom/N12 ; + wire \vga/scancode_convert/scancode_rom/N18 ; + wire \vga/scancode_convert/scancode_rom/N25 ; + wire \vga/scancode_convert/scancode_rom/N28 ; + wire \vga/scancode_convert/scancode_rom/N43 ; + wire N44; + wire \vga/pixel<8>_map785 ; + wire N89; + wire N116; + wire N117; + wire N124; + wire N126; + wire N128; + wire \vga/crt/state_FFd3-In_map800 ; + wire \vga/vgacore/_and0000_map807 ; + wire \vga/vgacore/_and0000_map811 ; + wire \vga/vgacore/_and0000_map817 ; + wire \vga/vgacore/_and0000_map824 ; + wire \vga/vgacore/_and0000_map825 ; + wire N235; + wire N237; + wire \vga/scancode_convert/shift_set_map833 ; + wire \vga/scancode_convert/shift_set_map836 ; + wire \vga/scancode_convert/state_FFd4-In_map845 ; + wire N293; + wire N301; + wire N305; + wire N306; + wire \vga/ps2/error_x_map855 ; + wire \vga/charload2_map865 ; + wire \vga/_and0000_map879 ; + wire \vga/_and0000_map890 ; + wire \vga/_and0000_map902 ; + wire \vga/_and0000_map918 ; + wire \vga/_and0000_map929 ; + wire \vga/_and0000_map940 ; + wire \vga/_and0000_map941 ; + wire \vga/_and0000_map943 ; + wire N560; + wire N562; + wire \vga/charload3_map953 ; + wire \vga/charload5_map965 ; + wire \vga/charload4_map979 ; + wire \vga/charload7_map993 ; + wire \vga/charload6_map1010 ; + wire \vga/charload6_map1012 ; + wire \vga/charload6_map1014 ; + wire \vga/charload6_map1018 ; + wire \vga/charload6_map1022 ; + wire N786; + wire \vga/ps2/_cmp_eq0001_map1032 ; + wire \vga/ps2/_cmp_eq0001_map1035 ; + wire \vga/ps2/_cmp_eq0001_map1041 ; + wire \vga/ps2/_cmp_eq0001_map1047 ; + wire N839; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1056 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1098 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1110 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1121 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1124 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1129 ; + wire \vga/scancode_convert/scancode_rom/data<2>1_map1144 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1158 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1171 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1178 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1185 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1201 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1221 ; + wire \vga/scancode_convert/scancode_rom/data<3>1_map1229 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1245 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1249 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1260 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1276 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1291 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1295 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1314 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1337 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1340 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1363 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1376 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1381 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1394 ; + wire \vga/scancode_convert/scancode_rom/data<5>3_map1416 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1423 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1429 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1438 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1443 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1445 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1449 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1461 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1475 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1503 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1517 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1526 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1529 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1534 ; + wire \vga/scancode_convert/scancode_rom/data<0>1_map1535 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1548 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1556 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1560 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1565 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1609 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1633 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1666 ; + wire \vga/scancode_convert/scancode_rom/data<4>1_map1669 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1686 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1690 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1701 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1708 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1717 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1729 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1751 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1774 ; + wire \vga/scancode_convert/scancode_rom/data<1>2_map1780 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1803 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1808 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1820 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1831 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1838 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1850 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1860 ; + wire \vga/scancode_convert/scancode_rom/data<6>1_map1863 ; + wire \vga/crt/cursor_v_1_rt_64 ; + wire \vga/crt/cursor_v_2_rt_65 ; + wire \vga/crt/cursor_v_3_rt_66 ; + wire \vga/crt/cursor_v_4_rt_67 ; + wire \vga/crt/cursor_h_1_rt_68 ; + wire \vga/crt/cursor_h_2_rt_69 ; + wire \vga/crt/cursor_h_3_rt_70 ; + wire \vga/crt/cursor_h_4_rt_71 ; + wire \vga/crt/cursor_h_5_rt_72 ; + wire \vga/vgacore/hcnt_4_rt_73 ; + wire \vga/ps2/timer_r_1_rt_74 ; + wire \vga/ps2/timer_r_2_rt_75 ; + wire \vga/ps2/timer_r_3_rt_76 ; + wire \vga/ps2/timer_r_4_rt_77 ; + wire \vga/ps2/timer_r_5_rt_78 ; + wire \vga/ps2/timer_r_6_rt_79 ; + wire \vga/ps2/timer_r_7_rt_80 ; + wire \vga/ps2/timer_r_8_rt_81 ; + wire \vga/ps2/timer_r_9_rt_82 ; + wire \vga/ps2/timer_r_10_rt_83 ; + wire \vga/ps2/timer_r_11_rt_84 ; + wire \vga/ps2/timer_r_12_rt_85 ; + wire \vga/vgacore/vcnt_8_rt_86 ; + wire \vga/crt/cursor_v_5_rt_87 ; + wire \vga/crt/cursor_v_5_rt1_88 ; + wire \vga/crt/cursor_h_6_rt_89 ; + wire \vga/ps2/timer_r_13_rt_90 ; + wire N3078; + wire N3079; + wire N3080; + wire N3081; + wire N3084; + wire N3085; + wire N3087; + wire N3089; + wire N3100; + wire N3104; + wire N3106; + wire N3108; + wire N3110; + wire N3112; + wire N3116; + wire N3117; + wire N3118; + wire N3119; + wire N3120; + wire N3121; + wire N3124; + wire N3126; + wire N3130; + wire N3132; + wire N3136; + wire N3141; + wire N3142; + wire N3144; + wire N3146; + wire N3148; + wire N3150; + wire N3158; + wire N3160; + wire N3162; + wire N3164; + wire N3166; + wire N3170; + wire N3172; + wire N3174; + wire N3175; + wire N3177; + wire N3178; + wire N3180; + wire \vga/scancode_convert/sc_1_1_91 ; + wire \vga/scancode_convert/raise1_92 ; + wire \vga/scancode_convert/sc_0_1_93 ; + wire N3184; + wire N3185; + wire N3186; + wire N3187; + wire N3188; + wire N3189; + wire N3190; + wire N3191; + wire N3192; + wire N3193; + wire N3194; + wire N3195; + wire N3196; + wire N3197; + wire N3198; + wire N3199; + wire N3200; + wire N3201; + wire N3202; + wire N3203; + wire N3204; + wire N3205; + wire N3206; + wire N3207; + wire N3208; + wire N3209; + wire N3210; + wire N3211; + wire N3212; + wire N3213; + wire N3214; + wire N3215; + wire gray_cnt_FFd11; + wire \vga/crtclk1 ; + wire \vga/rom_addr_char_0_1_94 ; + wire \vga/rom_addr_char_1_1_95 ; + wire N3216; + wire \vga/vgacore/vcnt_0_1_96 ; + wire \vga/vgacore/vcnt_1_1_97 ; + wire \vga/vgacore/vcnt_2_1_98 ; + wire gray_cnt_Rst_inv1_INV_0_1_99; + wire N3219; + wire N3220; + wire N3221; + wire N3222; + wire N3224; + wire N3225; + wire N3226; + wire N3227; + wire N3228; + wire N3229; + wire N3230; + wire N3231; + wire N3233; + wire N3234; + wire N3235; + wire N3236; + wire N3237; + wire N3238; + wire N3239; + wire N3242; + wire N3243; + wire N3244; + wire N3245; + wire N3248; + wire N3249; + wire N3250; + wire N3254; + wire N3255; + wire N3256; + wire N3257; + wire N3259; + wire N3261; + wire N3262; + wire N3264; + wire N3265; + wire N3266; + wire N3267; + wire N3268; + wire N3269; + wire N3270; + wire N3271; + wire N3272; + wire N3273; + wire N3274; + wire N3275; + wire N3276; + wire \NLW_vga/inst_Mram_mem8_DIB<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem8_DOA<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem11_DIB<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem11_DOA<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem21_DIB<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem21_DOA<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem31_DIB<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem31_DOA<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem41_DIB<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem41_DOA<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem51_DIB<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem51_DOA<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem61_DIB<0>_UNCONNECTED ; + wire \NLW_vga/inst_Mram_mem61_DOA<0>_UNCONNECTED ; + wire [8 : 8] pixel; + wire [6 : 0] \vga/scancode_convert/ascii ; + wire [0 : 0] \vga/pixelData ; + wire [9 : 0] \vga/vgacore/vcnt ; + wire [10 : 0] \vga/vgacore/hcnt ; + wire [11 : 5] \vga/ram_addr_video ; + wire [11 : 5] \vga/ram_addr_write ; + wire [11 : 0] \vga/ram_addr_mux ; + wire [7 : 0] \vga/pixel_hold ; + wire [2 : 0] \vga/pclk ; + wire [6 : 0] \vga/rom_addr_char ; + wire [6 : 0] \vga/crt/ram_data ; + wire [6 : 0] \vga/ram_data_out ; + wire [9 : 0] \vga/ps2/sc_r ; + wire [6 : 0] \vga/crt_data ; + wire [6 : 0] \vga/crt/cursor_h ; + wire [5 : 0] \vga/crt/cursor_v ; + wire [7 : 0] \vga/_mux0002 ; + wire [11 : 0] \vga/video_ram/ram_addr_w ; + wire [2 : 0] \vga/pclk__mux0000 ; + wire [10 : 5] \vga/Madd_ram_addr_video_Madd_cy ; + wire [2 : 0] \vga/crt/write_delay ; + wire [6 : 0] \vga/crt/_mux0002 ; + wire [2 : 0] \vga/crt/write_delay__mux0000 ; + wire [6 : 0] \vga/crt/Result ; + wire [10 : 5] \vga/crt/Madd_ram_addr_Madd_cy ; + wire [4 : 0] \vga/crt/Mcount_cursor_v_cy ; + wire [5 : 0] \vga/crt/Mcount_cursor_h_cy ; + wire [10 : 0] \vga/vgacore/Result ; + wire [4 : 0] \vga/vgacore/Mcompar__cmp_lt0000_cy ; + wire [9 : 0] \vga/vgacore/Mcount_hcnt_cy ; + wire [8 : 0] \vga/vgacore/Mcount_vcnt_cy ; + wire [13 : 1] \vga/ps2/_addsub0000 ; + wire [13 : 0] \vga/ps2/timer_x ; + wire [3 : 0] \vga/ps2/bitcnt_r ; + wire [4 : 0] \vga/ps2/ps2_clk_r ; + wire [13 : 0] \vga/ps2/timer_r ; + wire [3 : 0] \vga/ps2/bitcnt_x ; + wire [12 : 0] \vga/ps2/Madd__addsub0000_cy ; + wire [5 : 0] \vga/scancode_convert/rom_data ; + wire [6 : 6] \vga/scancode_convert/_mux0008 ; + wire [6 : 0] \vga/scancode_convert/sc ; + wire [2 : 0] \vga/scancode_convert/hold_count ; + wire [2 : 0] \vga/scancode_convert/hold_count__mux0000 ; + GND XST_GND ( + .G(N2) + ); + VCC XST_VCC ( + .P(N3) + ); + FDC gray_cnt_FFd2 ( + .D(\gray_cnt_FFd2-In ), + .CLR(gray_cnt_Rst_inv), + .C(clka_BUFGP_4), + .Q(gray_cnt_FFd2_10) + ); + FDC gray_cnt_FFd1 ( + .D(gray_cnt_FFd2_10), + .CLR(gray_cnt_Rst_inv), + .C(clka_BUFGP_4), + .Q(gray_cnt_FFd11) + ); + FDC \vga/crtclk ( + .D(\vga/_not0001 ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/crtclk1 ) + ); + FDC \vga/ram_wclk ( + .D(\vga/_mux0000 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ram_wclk_11 ) + ); + FDC_1 \vga/charload ( + .D(\vga/_cmp_eq0000 ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/charload_13 ) + ); + FDC \vga/crt_data_0 ( + .D(\vga/scancode_convert/ascii [0]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/scancode_convert/strobe_out_14 ), + .Q(\vga/crt_data [0]) + ); + FDC \vga/crt_data_1 ( + .D(\vga/scancode_convert/ascii [1]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/scancode_convert/strobe_out_14 ), + .Q(\vga/crt_data [1]) + ); + FDC \vga/crt_data_2 ( + .D(\vga/scancode_convert/ascii [2]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/scancode_convert/strobe_out_14 ), + .Q(\vga/crt_data [2]) + ); + FDC \vga/crt_data_3 ( + .D(\vga/scancode_convert/ascii [3]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/scancode_convert/strobe_out_14 ), + .Q(\vga/crt_data [3]) + ); + FDC \vga/crt_data_4 ( + .D(\vga/scancode_convert/ascii [4]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/scancode_convert/strobe_out_14 ), + .Q(\vga/crt_data [4]) + ); + FDC \vga/crt_data_5 ( + .D(\vga/scancode_convert/ascii [5]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/scancode_convert/strobe_out_14 ), + .Q(\vga/crt_data [5]) + ); + FDC \vga/crt_data_6 ( + .D(\vga/scancode_convert/ascii [6]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/scancode_convert/strobe_out_14 ), + .Q(\vga/crt_data [6]) + ); + FD \vga/rom_addr_char_0 ( + .D(\vga/ram_data_out [0]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char [0]) + ); + FD \vga/rom_addr_char_1 ( + .D(\vga/ram_data_out [1]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char [1]) + ); + FD \vga/rom_addr_char_2 ( + .D(\vga/ram_data_out [2]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char [2]) + ); + FD \vga/rom_addr_char_3 ( + .D(\vga/ram_data_out [3]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char [3]) + ); + FD \vga/rom_addr_char_4 ( + .D(\vga/ram_data_out [4]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char [4]) + ); + FD \vga/rom_addr_char_5 ( + .D(\vga/ram_data_out [5]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char [5]) + ); + FD \vga/rom_addr_char_6 ( + .D(\vga/ram_data_out [6]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char [6]) + ); + FD \vga/pixel_hold_0 ( + .D(\vga/_mux0002 [7]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [0]) + ); + FD \vga/pixel_hold_1 ( + .D(\vga/_mux0002 [6]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [1]) + ); + FD \vga/pixel_hold_2 ( + .D(\vga/_mux0002 [5]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [2]) + ); + FD \vga/pixel_hold_3 ( + .D(\vga/_mux0002 [4]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [3]) + ); + FD \vga/pixel_hold_4 ( + .D(\vga/_mux0002 [3]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [4]) + ); + FD \vga/pixel_hold_5 ( + .D(\vga/_mux0002 [2]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [5]) + ); + FD \vga/pixel_hold_6 ( + .D(\vga/_mux0002 [1]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [6]) + ); + FD \vga/pixel_hold_7 ( + .D(\vga/_mux0002 [0]), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixel_hold [7]) + ); + FDR \vga/pixelData_0 ( + .D(N3), + .R(\vga/pixel_hold<7>_inv ), + .C(gray_cnt_FFd1_9), + .Q(\vga/pixelData [0]) + ); + FD \vga/video_ram/ram_addr_w_0 ( + .D(\vga/ram_addr_mux [0]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [0]) + ); + FD \vga/video_ram/ram_addr_w_1 ( + .D(\vga/ram_addr_mux [1]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [1]) + ); + FD \vga/video_ram/ram_addr_w_2 ( + .D(\vga/ram_addr_mux [2]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [2]) + ); + FD \vga/video_ram/ram_addr_w_3 ( + .D(\vga/ram_addr_mux [3]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [3]) + ); + FD \vga/video_ram/ram_addr_w_4 ( + .D(\vga/ram_addr_mux [4]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [4]) + ); + FD \vga/video_ram/ram_addr_w_5 ( + .D(\vga/ram_addr_mux [5]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [5]) + ); + FD \vga/video_ram/ram_addr_w_6 ( + .D(\vga/ram_addr_mux [6]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [6]) + ); + FD \vga/video_ram/ram_addr_w_7 ( + .D(\vga/ram_addr_mux [7]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [7]) + ); + FD \vga/video_ram/ram_addr_w_8 ( + .D(\vga/ram_addr_mux [8]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [8]) + ); + FD \vga/video_ram/ram_addr_w_9 ( + .D(\vga/ram_addr_mux [9]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [9]) + ); + FD \vga/video_ram/ram_addr_w_10 ( + .D(\vga/ram_addr_mux [10]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [10]) + ); + FD \vga/video_ram/ram_addr_w_11 ( + .D(\vga/ram_addr_mux [11]), + .C(\vga/ram_wclk_11 ), + .Q(\vga/video_ram/ram_addr_w [11]) + ); + FDP \vga/pclk_0 ( + .D(\vga/pclk__mux0000 [0]), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/pclk [0]) + ); + FDP \vga/pclk_1 ( + .D(\vga/pclk__mux0000 [1]), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/pclk [1]) + ); + FDP \vga/pclk_2 ( + .D(\vga/pclk__mux0000 [2]), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/pclk [2]) + ); + defparam \vga/char_rom/Mrom_data1 .INIT = 16'h2000; + LUT4 \vga/char_rom/Mrom_data1 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N2 ) + ); + defparam \vga/char_rom/Mrom_data3 .INIT = 16'h0049; + LUT4 \vga/char_rom/Mrom_data3 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N4 ) + ); + defparam \vga/char_rom/Mrom_data4 .INIT = 16'h5112; + LUT4 \vga/char_rom/Mrom_data4 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N6 ) + ); + defparam \vga/char_rom/Mrom_data5 .INIT = 16'h0020; + LUT4 \vga/char_rom/Mrom_data5 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N7 ) + ); + defparam \vga/char_rom/Mrom_data6 .INIT = 16'h0222; + LUT4 \vga/char_rom/Mrom_data6 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N8 ) + ); + defparam \vga/char_rom/Mrom_data7 .INIT = 16'h2403; + LUT4 \vga/char_rom/Mrom_data7 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N10 ) + ); + defparam \vga/char_rom/Mrom_data8 .INIT = 16'h522A; + LUT4 \vga/char_rom/Mrom_data8 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N11 ) + ); + defparam \vga/char_rom/Mrom_data9 .INIT = 8'h04; + LUT3 \vga/char_rom/Mrom_data9 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N12 ) + ); + defparam \vga/char_rom/Mrom_data10 .INIT = 16'h081C; + LUT4 \vga/char_rom/Mrom_data10 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N13 ) + ); + defparam \vga/char_rom/Mrom_data11 .INIT = 16'h2000; + LUT4 \vga/char_rom/Mrom_data11 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N14 ) + ); + defparam \vga/char_rom/Mrom_data12 .INIT = 16'h0020; + LUT4 \vga/char_rom/Mrom_data12 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N15 ) + ); + defparam \vga/char_rom/Mrom_data13 .INIT = 16'h0706; + LUT4 \vga/char_rom/Mrom_data13 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N16 ) + ); + defparam \vga/char_rom/Mrom_data14 .INIT = 16'h3646; + LUT4 \vga/char_rom/Mrom_data14 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N17 ) + ); + defparam \vga/char_rom/Mrom_data17 .INIT = 16'h1E36; + LUT4 \vga/char_rom/Mrom_data17 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N20 ) + ); + defparam \vga/char_rom/Mrom_data18 .INIT = 16'h2400; + LUT4 \vga/char_rom/Mrom_data18 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N21 ) + ); + defparam \vga/char_rom/Mrom_data19 .INIT = 16'h0608; + LUT4 \vga/char_rom/Mrom_data19 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N22 ) + ); + defparam \vga/char_rom/Mrom_data20 .INIT = 16'h7E36; + LUT4 \vga/char_rom/Mrom_data20 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N23 ) + ); + defparam \vga/char_rom/Mrom_data21 .INIT = 16'h5506; + LUT4 \vga/char_rom/Mrom_data21 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N24 ) + ); + defparam \vga/char_rom/Mrom_data22 .INIT = 16'h0796; + LUT4 \vga/char_rom/Mrom_data22 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N25 ) + ); + defparam \vga/char_rom/Mrom_data23 .INIT = 16'h4C89; + LUT4 \vga/char_rom/Mrom_data23 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N26 ) + ); + defparam \vga/char_rom/Mrom_data24 .INIT = 16'h1555; + LUT4 \vga/char_rom/Mrom_data24 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N27 ) + ); + defparam \vga/char_rom/Mrom_data25 .INIT = 16'h215F; + LUT4 \vga/char_rom/Mrom_data25 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N28 ) + ); + defparam \vga/char_rom/Mrom_data26 .INIT = 16'h2AEA; + LUT4 \vga/char_rom/Mrom_data26 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N29 ) + ); + defparam \vga/char_rom/Mrom_data27 .INIT = 16'h1FFB; + LUT4 \vga/char_rom/Mrom_data27 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N30 ) + ); + defparam \vga/char_rom/Mrom_data28 .INIT = 16'h31E2; + LUT4 \vga/char_rom/Mrom_data28 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N31 ) + ); + defparam \vga/char_rom/Mrom_data29 .INIT = 16'h5562; + LUT4 \vga/char_rom/Mrom_data29 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N32 ) + ); + defparam \vga/char_rom/Mrom_data30 .INIT = 16'h2A2B; + LUT4 \vga/char_rom/Mrom_data30 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N33 ) + ); + defparam \vga/char_rom/Mrom_data31 .INIT = 16'h4F5F; + LUT4 \vga/char_rom/Mrom_data31 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N34 ) + ); + defparam \vga/char_rom/Mrom_data32 .INIT = 16'h0673; + LUT4 \vga/char_rom/Mrom_data32 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N35 ) + ); + defparam \vga/char_rom/Mrom_data34 .INIT = 16'h8004; + LUT4 \vga/char_rom/Mrom_data34 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N37 ) + ); + defparam \vga/char_rom/Mrom_data35 .INIT = 16'h4888; + LUT4 \vga/char_rom/Mrom_data35 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N38 ) + ); + defparam \vga/char_rom/Mrom_data36 .INIT = 16'h6064; + LUT4 \vga/char_rom/Mrom_data36 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N39 ) + ); + defparam \vga/char_rom/Mrom_data37 .INIT = 16'h15D5; + LUT4 \vga/char_rom/Mrom_data37 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N40 ) + ); + defparam \vga/char_rom/Mrom_data38 .INIT = 16'h4C88; + LUT4 \vga/char_rom/Mrom_data38 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N41 ) + ); + defparam \vga/char_rom/Mrom_data40 .INIT = 16'hDAD8; + LUT4 \vga/char_rom/Mrom_data40 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N43 ) + ); + defparam \vga/char_rom/Mrom_data41 .INIT = 16'h2400; + LUT4 \vga/char_rom/Mrom_data41 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N44 ) + ); + defparam \vga/char_rom/Mrom_data42 .INIT = 16'h6266; + LUT4 \vga/char_rom/Mrom_data42 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N45 ) + ); + defparam \vga/char_rom/Mrom_data43 .INIT = 16'h0600; + LUT4 \vga/char_rom/Mrom_data43 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N47 ) + ); + defparam \vga/char_rom/Mrom_data44 .INIT = 16'h71E3; + LUT4 \vga/char_rom/Mrom_data44 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N48 ) + ); + defparam \vga/char_rom/Mrom_data45 .INIT = 16'h242A; + LUT4 \vga/char_rom/Mrom_data45 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N49 ) + ); + defparam \vga/char_rom/Mrom_data46 .INIT = 16'h0602; + LUT4 \vga/char_rom/Mrom_data46 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N50 ) + ); + defparam \vga/char_rom/Mrom_data49 .INIT = 16'h0020; + LUT4 \vga/char_rom/Mrom_data49 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_0_1_96 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N53 ) + ); + defparam \vga/char_rom/Mrom_data50 .INIT = 16'h4501; + LUT4 \vga/char_rom/Mrom_data50 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N54 ) + ); + defparam \vga/char_rom/Mrom_data51 .INIT = 8'h49; + LUT3 \vga/char_rom/Mrom_data51 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N55 ) + ); + defparam \vga/char_rom/Mrom_data52 .INIT = 16'h297F; + LUT4 \vga/char_rom/Mrom_data52 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N56 ) + ); + defparam \vga/char_rom/Mrom_data53 .INIT = 16'h0549; + LUT4 \vga/char_rom/Mrom_data53 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N57 ) + ); + defparam \vga/char_rom/Mrom_data54 .INIT = 16'h2949; + LUT4 \vga/char_rom/Mrom_data54 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N58 ) + ); + defparam \vga/char_rom/Mrom_data55 .INIT = 16'h2441; + LUT4 \vga/char_rom/Mrom_data55 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N59 ) + ); + defparam \vga/char_rom/Mrom_data56 .INIT = 16'h0914; + LUT4 \vga/char_rom/Mrom_data56 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N60 ) + ); + defparam \vga/char_rom/Mrom_data57 .INIT = 8'h15; + LUT3 \vga/char_rom/Mrom_data57 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N61 ) + ); + defparam \vga/char_rom/Mrom_data58 .INIT = 16'h4149; + LUT4 \vga/char_rom/Mrom_data58 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N62 ) + ); + defparam \vga/char_rom/Mrom_data59 .INIT = 16'h4941; + LUT4 \vga/char_rom/Mrom_data59 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N63 ) + ); + defparam \vga/char_rom/Mrom_data60 .INIT = 16'h4941; + LUT4 \vga/char_rom/Mrom_data60 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N64 ) + ); + defparam \vga/char_rom/Mrom_data61 .INIT = 16'h4108; + LUT4 \vga/char_rom/Mrom_data61 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N65 ) + ); + defparam \vga/char_rom/Mrom_data62 .INIT = 16'h2420; + LUT4 \vga/char_rom/Mrom_data62 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N66 ) + ); + defparam \vga/char_rom/Mrom_data63 .INIT = 16'h0240; + LUT4 \vga/char_rom/Mrom_data63 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N67 ) + ); + defparam \vga/char_rom/Mrom_data64 .INIT = 16'h2403; + LUT4 \vga/char_rom/Mrom_data64 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N68 ) + ); + defparam \vga/char_rom/Mrom_data65 .INIT = 16'h4919; + LUT4 \vga/char_rom/Mrom_data65 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N69 ) + ); + defparam \vga/char_rom/Mrom_data66 .INIT = 16'h4001; + LUT4 \vga/char_rom/Mrom_data66 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N70 ) + ); + defparam \vga/char_rom/Mrom_data67 .INIT = 16'h2400; + LUT4 \vga/char_rom/Mrom_data67 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_0_1_96 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N71 ) + ); + defparam \vga/char_rom/Mrom_data68 .INIT = 16'h0814; + LUT4 \vga/char_rom/Mrom_data68 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N72 ) + ); + defparam \vga/char_rom/Mrom_data69 .INIT = 16'h4143; + LUT4 \vga/char_rom/Mrom_data69 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N73 ) + ); + defparam \vga/char_rom/Mrom_data70 .INIT = 16'h2BAA; + LUT4 \vga/char_rom/Mrom_data70 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N74 ) + ); + defparam \vga/char_rom/Mrom_data71 .INIT = 16'h8004; + LUT4 \vga/char_rom/Mrom_data71 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_0_1_96 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N75 ) + ); + defparam \vga/char_rom/Mrom_data74 .INIT = 16'h5444; + LUT4 \vga/char_rom/Mrom_data74 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N78 ) + ); + defparam \vga/char_rom/Mrom_data75 .INIT = 16'hA409; + LUT4 \vga/char_rom/Mrom_data75 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N79 ) + ); + defparam \vga/char_rom/Mrom_data76 .INIT = 16'h086C; + LUT4 \vga/char_rom/Mrom_data76 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N80 ) + ); + defparam \vga/char_rom/Mrom_data77 .INIT = 16'h06AF; + LUT4 \vga/char_rom/Mrom_data77 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N81 ) + ); + defparam \vga/char_rom/Mrom_data78 .INIT = 16'h0600; + LUT4 \vga/char_rom/Mrom_data78 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N82 ) + ); + defparam \vga/char_rom/Mrom_data79 .INIT = 16'h1E22; + LUT4 \vga/char_rom/Mrom_data79 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N83 ) + ); + defparam \vga/char_rom/Mrom_data81 .INIT = 16'h64E2; + LUT4 \vga/char_rom/Mrom_data81 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N85 ) + ); + defparam \vga/char_rom/Mrom_data82 .INIT = 16'h6040; + LUT4 \vga/char_rom/Mrom_data82 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_0_1_96 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N86 ) + ); + defparam \vga/char_rom/Mrom_data83 .INIT = 16'h36CC; + LUT4 \vga/char_rom/Mrom_data83 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N87 ) + ); + defparam \vga/char_rom/Mrom_data84 .INIT = 16'h414C; + LUT4 \vga/char_rom/Mrom_data84 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N88 ) + ); + defparam \vga/char_rom/Mrom_data85 .INIT = 16'h7060; + LUT4 \vga/char_rom/Mrom_data85 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N89 ) + ); + defparam \vga/char_rom/Mrom_data86 .INIT = 16'h0001; + LUT4 \vga/char_rom/Mrom_data86 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N90 ) + ); + defparam \vga/char_rom/Mrom_data89 .INIT = 16'h1D5D; + LUT4 \vga/char_rom/Mrom_data89 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_0_1_96 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N94 ) + ); + defparam \vga/char_rom/Mrom_data90 .INIT = 16'h0427; + LUT4 \vga/char_rom/Mrom_data90 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N95 ) + ); + defparam \vga/char_rom/Mrom_data91 .INIT = 16'h34E1; + LUT4 \vga/char_rom/Mrom_data91 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N96 ) + ); + defparam \vga/char_rom/Mrom_data93 .INIT = 16'h0860; + LUT4 \vga/char_rom/Mrom_data93 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N98 ) + ); + defparam \vga/char_rom/Mrom_data94 .INIT = 16'h7F49; + LUT4 \vga/char_rom/Mrom_data94 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N99 ) + ); + defparam \vga/char_rom/Mrom_data96 .INIT = 16'h4912; + LUT4 \vga/char_rom/Mrom_data96 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N101 ) + ); + defparam \vga/char_rom/Mrom_data97 .INIT = 16'h4149; + LUT4 \vga/char_rom/Mrom_data97 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N102 ) + ); + defparam \vga/char_rom/Mrom_data99 .INIT = 16'h2422; + LUT4 \vga/char_rom/Mrom_data99 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N104 ) + ); + defparam \vga/char_rom/Mrom_data100 .INIT = 16'h5292; + LUT4 \vga/char_rom/Mrom_data100 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N105 ) + ); + defparam \vga/char_rom/Mrom_data101 .INIT = 16'h131B; + LUT4 \vga/char_rom/Mrom_data101 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N106 ) + ); + defparam \vga/char_rom/Mrom_data105 .INIT = 16'h2AEA; + LUT4 \vga/char_rom/Mrom_data105 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N110 ) + ); + defparam \vga/char_rom/Mrom_data106 .INIT = 16'h0608; + LUT4 \vga/char_rom/Mrom_data106 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N111 ) + ); + defparam \vga/char_rom/Mrom_data108 .INIT = 16'h4104; + LUT4 \vga/char_rom/Mrom_data108 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N113 ) + ); + defparam \vga/char_rom/Mrom_data109 .INIT = 16'h4251; + LUT4 \vga/char_rom/Mrom_data109 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N114 ) + ); + defparam \vga/char_rom/Mrom_data110 .INIT = 16'h15D5; + LUT4 \vga/char_rom/Mrom_data110 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N115 ) + ); + defparam \vga/char_rom/Mrom_data111 .INIT = 16'h6068; + LUT4 \vga/char_rom/Mrom_data111 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N116 ) + ); + defparam \vga/char_rom/Mrom_data112 .INIT = 16'h1888; + LUT4 \vga/char_rom/Mrom_data112 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N117 ) + ); + defparam \vga/char_rom/Mrom_data113 .INIT = 16'h4145; + LUT4 \vga/char_rom/Mrom_data113 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N118 ) + ); + defparam \vga/char_rom/Mrom_data115 .INIT = 16'h8001; + LUT4 \vga/char_rom/Mrom_data115 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N120 ) + ); + defparam \vga/char_rom/Mrom_data116 .INIT = 16'h4453; + LUT4 \vga/char_rom/Mrom_data116 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N121 ) + ); + defparam \vga/char_rom/Mrom_data120 .INIT = 16'h28AE; + LUT4 \vga/char_rom/Mrom_data120 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N125 ) + ); + defparam \vga/char_rom/Mrom_data121 .INIT = 16'h2884; + LUT4 \vga/char_rom/Mrom_data121 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N126 ) + ); + defparam \vga/char_rom/Mrom_data122 .INIT = 16'h17D5; + LUT4 \vga/char_rom/Mrom_data122 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N127 ) + ); + defparam \vga/char_rom/Mrom_data123 .INIT = 16'h4404; + LUT4 \vga/char_rom/Mrom_data123 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N128 ) + ); + defparam \vga/char_rom/Mrom_data124 .INIT = 16'h2404; + LUT4 \vga/char_rom/Mrom_data124 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N129 ) + ); + defparam \vga/char_rom/Mrom_data125 .INIT = 16'h4048; + LUT4 \vga/char_rom/Mrom_data125 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N130 ) + ); + defparam \vga/char_rom/Mrom_data126 .INIT = 16'h6010; + LUT4 \vga/char_rom/Mrom_data126 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N131 ) + ); + defparam \vga/char_rom/Mrom_data127 .INIT = 16'h4514; + LUT4 \vga/char_rom/Mrom_data127 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N132 ) + ); + defparam \vga/char_rom/Mrom_data128 .INIT = 16'h4177; + LUT4 \vga/char_rom/Mrom_data128 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N133 ) + ); + defparam \vga/char_rom/Mrom_data129 .INIT = 16'h0002; + LUT4 \vga/char_rom/Mrom_data129 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N134 ) + ); + defparam \vga/char_rom/Mrom_data131 .INIT = 16'h4DC9; + LUT4 \vga/char_rom/Mrom_data131 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N137 ) + ); + defparam \vga/char_rom/Mrom_data132 .INIT = 16'h0666; + LUT4 \vga/char_rom/Mrom_data132 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N138 ) + ); + defparam \vga/char_rom/Mrom_data133 .INIT = 16'h042F; + LUT4 \vga/char_rom/Mrom_data133 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N139 ) + ); + defparam \vga/char_rom/Mrom_data136 .INIT = 16'h2C08; + LUT4 \vga/char_rom/Mrom_data136 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N142 ) + ); + defparam \vga/char_rom/Mrom_data137 .INIT = 16'h1060; + LUT4 \vga/char_rom/Mrom_data137 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N143 ) + ); + defparam \vga/char_rom/Mrom_data138 .INIT = 16'h4251; + LUT4 \vga/char_rom/Mrom_data138 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N144 ) + ); + defparam \vga/char_rom/Mrom_data139 .INIT = 16'h4951; + LUT4 \vga/char_rom/Mrom_data139 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N145 ) + ); + defparam \vga/char_rom/Mrom_data140 .INIT = 16'h4914; + LUT4 \vga/char_rom/Mrom_data140 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N146 ) + ); + defparam \vga/char_rom/Mrom_data141 .INIT = 16'h741A; + LUT4 \vga/char_rom/Mrom_data141 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N147 ) + ); + defparam \vga/char_rom/Mrom_data143 .INIT = 16'hE6CC; + LUT4 \vga/char_rom/Mrom_data143 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N149 ) + ); + defparam \vga/char_rom/Mrom_data144 .INIT = 16'h2414; + LUT4 \vga/char_rom/Mrom_data144 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N150 ) + ); + defparam \vga/char_rom/Mrom_data145 .INIT = 16'h0141; + LUT4 \vga/char_rom/Mrom_data145 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N151 ) + ); + defparam \vga/char_rom/Mrom_data146 .INIT = 16'h1411; + LUT4 \vga/char_rom/Mrom_data146 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N152 ) + ); + defparam \vga/char_rom/Mrom_data149 .INIT = 16'h2403; + LUT4 \vga/char_rom/Mrom_data149 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N155 ) + ); + defparam \vga/char_rom/Mrom_data151 .INIT = 16'h2400; + LUT4 \vga/char_rom/Mrom_data151 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N157 ) + ); + defparam \vga/char_rom/Mrom_data153 .INIT = 16'h0814; + LUT4 \vga/char_rom/Mrom_data153 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N159 ) + ); + defparam \vga/char_rom/Mrom_data161 .INIT = 16'h4443; + LUT4 \vga/char_rom/Mrom_data161 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N167 ) + ); + defparam \vga/char_rom/Mrom_data164 .INIT = 16'h9B72; + LUT4 \vga/char_rom/Mrom_data164 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N170 ) + ); + defparam \vga/char_rom/Mrom_data165 .INIT = 16'h0002; + LUT4 \vga/char_rom/Mrom_data165 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N171 ) + ); + defparam \vga/char_rom/Mrom_data166 .INIT = 16'h2400; + LUT4 \vga/char_rom/Mrom_data166 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N172 ) + ); + defparam \vga/char_rom/Mrom_data169 .INIT = 16'h326A; + LUT4 \vga/char_rom/Mrom_data169 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N175 ) + ); + defparam \vga/char_rom/Mrom_data170 .INIT = 16'h0786; + LUT4 \vga/char_rom/Mrom_data170 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N176 ) + ); + defparam \vga/char_rom/Mrom_data172 .INIT = 16'h8084; + LUT4 \vga/char_rom/Mrom_data172 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N178 ) + ); + defparam \vga/char_rom/Mrom_data173 .INIT = 16'h35E4; + LUT4 \vga/char_rom/Mrom_data173 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N179 ) + ); + defparam \vga/char_rom/Mrom_data176 .INIT = 16'h2407; + LUT4 \vga/char_rom/Mrom_data176 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N183 ) + ); + defparam \vga/char_rom/Mrom_data177 .INIT = 16'h129A; + LUT4 \vga/char_rom/Mrom_data177 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N184 ) + ); + defparam \vga/char_rom/Mrom_data179 .INIT = 16'h082A; + LUT4 \vga/char_rom/Mrom_data179 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N186 ) + ); + defparam \vga/char_rom/Mrom_data183 .INIT = 16'h2262; + LUT4 \vga/char_rom/Mrom_data183 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N190 ) + ); + defparam \vga/char_rom/Mrom_data184 .INIT = 16'h54C6; + LUT4 \vga/char_rom/Mrom_data184 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N191 ) + ); + defparam \vga/char_rom/Mrom_data185 .INIT = 16'h0616; + LUT4 \vga/char_rom/Mrom_data185 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N192 ) + ); + defparam \vga/char_rom/Mrom_data186 .INIT = 16'h1526; + LUT4 \vga/char_rom/Mrom_data186 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N193 ) + ); + defparam \vga/char_rom/Mrom_data187 .INIT = 16'h0860; + LUT4 \vga/char_rom/Mrom_data187 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N194 ) + ); + defparam \vga/char_rom/Mrom_data194 .INIT = 16'h1B7B; + LUT4 \vga/char_rom/Mrom_data194 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N201 ) + ); + defparam \vga/char_rom/Mrom_data198 .INIT = 16'h0223; + LUT4 \vga/char_rom/Mrom_data198 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N205 ) + ); + defparam \vga/char_rom/Mrom_data201 .INIT = 16'h1FB3; + LUT4 \vga/char_rom/Mrom_data201 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/rom_addr_char [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N208 ) + ); + defparam \vga/char_rom/Mrom_data206 .INIT = 16'h47AA; + LUT4 \vga/char_rom/Mrom_data206 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [1]), + .O(\vga/N213 ) + ); + defparam \vga/char_rom/Mrom_data207 .INIT = 16'h64EE; + LUT4 \vga/char_rom/Mrom_data207 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [2]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N214 ) + ); + defparam \vga/char_rom/Mrom_data208 .INIT = 16'h0484; + LUT4 \vga/char_rom/Mrom_data208 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N215 ) + ); + defparam \vga/char_rom/Mrom_data209 .INIT = 16'h6064; + LUT4 \vga/char_rom/Mrom_data209 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/rom_addr_char [0]), + .I3(\vga/vgacore/vcnt [0]), + .O(\vga/N216 ) + ); + defparam \vga/char_rom/Mrom_data211 .INIT = 16'h96CC; + LUT4 \vga/char_rom/Mrom_data211 ( + .I0(\vga/rom_addr_char [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [2]), + .O(\vga/N218 ) + ); + defparam \vga/char_rom/Mrom_data212 .INIT = 16'h0864; + LUT4 \vga/char_rom/Mrom_data212 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N219 ) + ); + defparam \vga/char_rom/Mrom_data213 .INIT = 16'h4224; + LUT4 \vga/char_rom/Mrom_data213 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N221 ) + ); + defparam \vga/char_rom/Mrom_data214 .INIT = 16'h0002; + LUT4 \vga/char_rom/Mrom_data214 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [0]), + .I2(\vga/vgacore/vcnt [1]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N222 ) + ); + defparam \vga/char_rom/Mrom_data216 .INIT = 16'h8000; + LUT4 \vga/char_rom/Mrom_data216 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [2]), + .I3(\vga/rom_addr_char [0]), + .O(\vga/N224 ) + ); + RAMB4_S1_S1 \vga/inst_Mram_mem8 ( + .CLKA(\vga/ram_wclk_11 ), + .CLKB(\vga/charclk ), + .ENA(N3), + .ENB(N3), + .RSTA(N2), + .RSTB(N2), + .WEA(\vga/N226 ), + .WEB(N2), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux [11], \vga/ram_addr_mux [10], \vga/ram_addr_mux [9], \vga/ram_addr_mux [8], \vga/ram_addr_mux [7], \vga/ram_addr_mux [6] +, \vga/ram_addr_mux [5], \vga/ram_addr_mux [4], \vga/ram_addr_mux [3], \vga/ram_addr_mux [2], \vga/ram_addr_mux [1], \vga/ram_addr_mux [0]}), + .DIA({\vga/crt/ram_data [0]}), + .DIB({\NLW_vga/inst_Mram_mem8_DIB<0>_UNCONNECTED }), + .DOA({\NLW_vga/inst_Mram_mem8_DOA<0>_UNCONNECTED }), + .DOB({\vga/ram_data_out [0]}) + ); + RAMB4_S1_S1 \vga/inst_Mram_mem11 ( + .CLKA(\vga/ram_wclk_11 ), + .CLKB(\vga/charclk ), + .ENA(N3), + .ENB(N3), + .RSTA(N2), + .RSTB(N2), + .WEA(\vga/N226 ), + .WEB(N2), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux [11], \vga/ram_addr_mux [10], \vga/ram_addr_mux [9], \vga/ram_addr_mux [8], \vga/ram_addr_mux [7], \vga/ram_addr_mux [6] +, \vga/ram_addr_mux [5], \vga/ram_addr_mux [4], \vga/ram_addr_mux [3], \vga/ram_addr_mux [2], \vga/ram_addr_mux [1], \vga/ram_addr_mux [0]}), + .DIA({\vga/crt/ram_data [1]}), + .DIB({\NLW_vga/inst_Mram_mem11_DIB<0>_UNCONNECTED }), + .DOA({\NLW_vga/inst_Mram_mem11_DOA<0>_UNCONNECTED }), + .DOB({\vga/ram_data_out [1]}) + ); + RAMB4_S1_S1 \vga/inst_Mram_mem21 ( + .CLKA(\vga/ram_wclk_11 ), + .CLKB(\vga/charclk ), + .ENA(N3), + .ENB(N3), + .RSTA(N2), + .RSTB(N2), + .WEA(\vga/N226 ), + .WEB(N2), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux [11], \vga/ram_addr_mux [10], \vga/ram_addr_mux [9], \vga/ram_addr_mux [8], \vga/ram_addr_mux [7], \vga/ram_addr_mux [6] +, \vga/ram_addr_mux [5], \vga/ram_addr_mux [4], \vga/ram_addr_mux [3], \vga/ram_addr_mux [2], \vga/ram_addr_mux [1], \vga/ram_addr_mux [0]}), + .DIA({\vga/crt/ram_data [2]}), + .DIB({\NLW_vga/inst_Mram_mem21_DIB<0>_UNCONNECTED }), + .DOA({\NLW_vga/inst_Mram_mem21_DOA<0>_UNCONNECTED }), + .DOB({\vga/ram_data_out [2]}) + ); + RAMB4_S1_S1 \vga/inst_Mram_mem31 ( + .CLKA(\vga/ram_wclk_11 ), + .CLKB(\vga/charclk ), + .ENA(N3), + .ENB(N3), + .RSTA(N2), + .RSTB(N2), + .WEA(\vga/N226 ), + .WEB(N2), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux [11], \vga/ram_addr_mux [10], \vga/ram_addr_mux [9], \vga/ram_addr_mux [8], \vga/ram_addr_mux [7], \vga/ram_addr_mux [6] +, \vga/ram_addr_mux [5], \vga/ram_addr_mux [4], \vga/ram_addr_mux [3], \vga/ram_addr_mux [2], \vga/ram_addr_mux [1], \vga/ram_addr_mux [0]}), + .DIA({\vga/crt/ram_data [3]}), + .DIB({\NLW_vga/inst_Mram_mem31_DIB<0>_UNCONNECTED }), + .DOA({\NLW_vga/inst_Mram_mem31_DOA<0>_UNCONNECTED }), + .DOB({\vga/ram_data_out [3]}) + ); + RAMB4_S1_S1 \vga/inst_Mram_mem41 ( + .CLKA(\vga/ram_wclk_11 ), + .CLKB(\vga/charclk ), + .ENA(N3), + .ENB(N3), + .RSTA(N2), + .RSTB(N2), + .WEA(\vga/N226 ), + .WEB(N2), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux [11], \vga/ram_addr_mux [10], \vga/ram_addr_mux [9], \vga/ram_addr_mux [8], \vga/ram_addr_mux [7], \vga/ram_addr_mux [6] +, \vga/ram_addr_mux [5], \vga/ram_addr_mux [4], \vga/ram_addr_mux [3], \vga/ram_addr_mux [2], \vga/ram_addr_mux [1], \vga/ram_addr_mux [0]}), + .DIA({\vga/crt/ram_data [4]}), + .DIB({\NLW_vga/inst_Mram_mem41_DIB<0>_UNCONNECTED }), + .DOA({\NLW_vga/inst_Mram_mem41_DOA<0>_UNCONNECTED }), + .DOB({\vga/ram_data_out [4]}) + ); + RAMB4_S1_S1 \vga/inst_Mram_mem51 ( + .CLKA(\vga/ram_wclk_11 ), + .CLKB(\vga/charclk ), + .ENA(N3), + .ENB(N3), + .RSTA(N2), + .RSTB(N2), + .WEA(\vga/N226 ), + .WEB(N2), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux [11], \vga/ram_addr_mux [10], \vga/ram_addr_mux [9], \vga/ram_addr_mux [8], \vga/ram_addr_mux [7], \vga/ram_addr_mux [6] +, \vga/ram_addr_mux [5], \vga/ram_addr_mux [4], \vga/ram_addr_mux [3], \vga/ram_addr_mux [2], \vga/ram_addr_mux [1], \vga/ram_addr_mux [0]}), + .DIA({\vga/crt/ram_data [5]}), + .DIB({\NLW_vga/inst_Mram_mem51_DIB<0>_UNCONNECTED }), + .DOA({\NLW_vga/inst_Mram_mem51_DOA<0>_UNCONNECTED }), + .DOB({\vga/ram_data_out [5]}) + ); + RAMB4_S1_S1 \vga/inst_Mram_mem61 ( + .CLKA(\vga/ram_wclk_11 ), + .CLKB(\vga/charclk ), + .ENA(N3), + .ENB(N3), + .RSTA(N2), + .RSTB(N2), + .WEA(\vga/N226 ), + .WEB(N2), + .ADDRA({\vga/video_ram/ram_addr_w [11], \vga/video_ram/ram_addr_w [10], \vga/video_ram/ram_addr_w [9], \vga/video_ram/ram_addr_w [8], +\vga/video_ram/ram_addr_w [7], \vga/video_ram/ram_addr_w [6], \vga/video_ram/ram_addr_w [5], \vga/video_ram/ram_addr_w [4], +\vga/video_ram/ram_addr_w [3], \vga/video_ram/ram_addr_w [2], \vga/video_ram/ram_addr_w [1], \vga/video_ram/ram_addr_w [0]}), + .ADDRB({\vga/ram_addr_mux [11], \vga/ram_addr_mux [10], \vga/ram_addr_mux [9], \vga/ram_addr_mux [8], \vga/ram_addr_mux [7], \vga/ram_addr_mux [6] +, \vga/ram_addr_mux [5], \vga/ram_addr_mux [4], \vga/ram_addr_mux [3], \vga/ram_addr_mux [2], \vga/ram_addr_mux [1], \vga/ram_addr_mux [0]}), + .DIA({\vga/crt/ram_data [6]}), + .DIB({\NLW_vga/inst_Mram_mem61_DIB<0>_UNCONNECTED }), + .DOA({\NLW_vga/inst_Mram_mem61_DOA<0>_UNCONNECTED }), + .DOB({\vga/ram_data_out [6]}) + ); + defparam \vga/rom_addr_char<1> .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1> ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N14 ), + .I2(\vga/N15 ), + .O(\vga/N01 ) + ); + defparam \vga/rom_addr_char<1>1 .INIT = 4'h8; + LUT2 \vga/rom_addr_char<1>1 ( + .I0(\vga/N13 ), + .I1(\vga/rom_addr_char [1]), + .O(\vga/N1101 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5 ( + .I0(\vga/N1101 ), + .I1(\vga/N01 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5_17 ) + ); + defparam \vga/rom_addr_char<1>2 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>2 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N11 ), + .I2(\vga/N12 ), + .O(\vga/N2123 ) + ); + defparam \vga/rom_addr_char<1>3 .INIT = 4'h8; + LUT2 \vga/rom_addr_char<1>3 ( + .I0(\vga/N10 ), + .I1(\vga/rom_addr_char_1_1_95 ), + .O(\vga/N312 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_0 ( + .I0(\vga/N312 ), + .I1(\vga/N2123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51_18 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6 ( + .I0(\vga/rom_addr_char<2>_f51_18 ), + .I1(\vga/rom_addr_char<2>_f5_17 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6_19 ) + ); + defparam \vga/rom_addr_char<1>4 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>4 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N21 ), + .I2(\vga/N22 ), + .O(\vga/N412 ) + ); + defparam \vga/rom_addr_char<1>5 .INIT = 4'h4; + LUT2 \vga/rom_addr_char<1>5 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N20 ), + .O(\vga/N512 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_1 ( + .I0(\vga/N512 ), + .I1(\vga/N412 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f52_20 ) + ); + defparam \vga/rom_addr_char<1>7 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>7 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N16 ), + .I2(\vga/N17 ), + .O(\vga/N712 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_2 ( + .I0(\vga/N712 ), + .I1(\vga/N612 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f53_21 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_0 ( + .I0(\vga/rom_addr_char<2>_f53_21 ), + .I1(\vga/rom_addr_char<2>_f52_20 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f61_22 ) + ); + defparam \vga/rom_addr_char<1>8 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>8 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N29 ), + .I2(\vga/N30 ), + .O(\vga/N912 ) + ); + defparam \vga/rom_addr_char<1>9 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>9 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N27 ), + .I2(\vga/N28 ), + .O(\vga/N1011 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_3 ( + .I0(\vga/N1011 ), + .I1(\vga/N912 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f54_23 ) + ); + defparam \vga/rom_addr_char<1>10 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>10 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N25 ), + .I2(\vga/N26 ), + .O(\vga/N1111 ) + ); + defparam \vga/rom_addr_char<1>11 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>11 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N23 ), + .I2(\vga/N24 ), + .O(\vga/N1211 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_4 ( + .I0(\vga/N1211 ), + .I1(\vga/N1111 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f55 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_1 ( + .I0(\vga/rom_addr_char<2>_f55 ), + .I1(\vga/rom_addr_char<2>_f54_23 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f62_24 ) + ); + defparam \vga/rom_addr_char<1>12 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>12 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N7 ), + .I2(\vga/N37 ), + .O(\vga/N1311 ) + ); + defparam \vga/rom_addr_char<1>13 .INIT = 4'h4; + LUT2 \vga/rom_addr_char<1>13 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N35 ), + .O(\vga/N1411 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_5 ( + .I0(\vga/N1411 ), + .I1(\vga/N1311 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f56 ) + ); + defparam \vga/rom_addr_char<1>14 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>14 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N33 ), + .I2(\vga/N34 ), + .O(\vga/N1511 ) + ); + defparam \vga/rom_addr_char<1>15 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>15 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N31 ), + .I2(\vga/N32 ), + .O(\vga/N1611 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_6 ( + .I0(\vga/N1611 ), + .I1(N3078), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f57 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_2 ( + .I0(\vga/rom_addr_char<2>_f57 ), + .I1(\vga/rom_addr_char<2>_f56 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f63_25 ) + ); + defparam \vga/rom_addr_char<1>16 .INIT = 4'h8; + LUT2 \vga/rom_addr_char<1>16 ( + .I0(\vga/N45 ), + .I1(\vga/rom_addr_char [1]), + .O(\vga/N1711 ) + ); + defparam \vga/rom_addr_char<1>17 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>17 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N43 ), + .I2(\vga/N44 ), + .O(\vga/N1811 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_7 ( + .I0(\vga/N1811 ), + .I1(\vga/N1711 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f58 ) + ); + defparam \vga/rom_addr_char<3> .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<3> ( + .I0(\vga/rom_addr_char [3]), + .I1(\vga/rom_addr_char<2>_f58 ), + .I2(\vga/rom_addr_char<2>11_27 ), + .O(\vga/N1911 ) + ); + defparam \vga/rom_addr_char<1>18 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>18 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N40 ), + .I2(\vga/N41 ), + .O(\vga/N2011 ) + ); + defparam \vga/rom_addr_char<1>19 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>19 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N38 ), + .I2(\vga/N39 ), + .O(\vga/N2111 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_8 ( + .I0(\vga/N2111 ), + .I1(\vga/N2011 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f59 ) + ); + defparam \vga/rom_addr_char<3>1 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<3>1 ( + .I0(\vga/rom_addr_char [3]), + .I1(\vga/rom_addr_char<2>_f59 ), + .I2(\vga/rom_addr_char<2>2 ), + .O(\vga/N2211 ) + ); + MUXF5 \vga/rom_addr_char<4>_f5 ( + .I0(\vga/N2211 ), + .I1(\vga/N1911 ), + .S(\vga/rom_addr_char [4]), + .O(\vga/rom_addr_char<4>_f5_28 ) + ); + defparam \vga/rom_addr_char<2>11 .INIT = 8'h08; + LUT3 \vga/rom_addr_char<2>11 ( + .I0(\vga/N4 ), + .I1(\vga/rom_addr_char_1_1_95 ), + .I2(\vga/rom_addr_char [2]), + .O(\vga/N1112 ) + ); + defparam \vga/rom_addr_char<2>3 .INIT = 16'hE040; + LUT4 \vga/rom_addr_char<2>3 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N6 ), + .I2(\vga/rom_addr_char [2]), + .I3(\vga/N7 ), + .O(\vga/N0112 ) + ); + defparam \vga/rom_addr_char<2>12 .INIT = 8'h08; + LUT3 \vga/rom_addr_char<2>12 ( + .I0(\vga/N8 ), + .I1(\vga/rom_addr_char_1_1_95 ), + .I2(\vga/rom_addr_char [2]), + .O(\vga/N11123 ) + ); + defparam \vga/rom_addr_char<1>20 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>20 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N142 ), + .I2(\vga/N143 ), + .O(\vga/N01123 ) + ); + defparam \vga/rom_addr_char<1>110 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>110 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N25 ), + .I2(\vga/N13 ), + .O(\vga/N111234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f51 ( + .I0(\vga/N111234 ), + .I1(\vga/N01123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f512 ) + ); + defparam \vga/rom_addr_char<1>21 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>21 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N138 ), + .I2(\vga/N139 ), + .O(\vga/N21234 ) + ); + defparam \vga/rom_addr_char<1>31 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>31 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N47 ), + .I2(\vga/N137 ), + .O(\vga/N3123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_01 ( + .I0(\vga/N3123 ), + .I1(\vga/N21234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f511 ) + ); + MUXF6 \vga/rom_addr_char<3>_f61 ( + .I0(\vga/rom_addr_char<2>_f511 ), + .I1(\vga/rom_addr_char<2>_f512 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f612 ) + ); + defparam \vga/rom_addr_char<1>41 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>41 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N150 ), + .I2(\vga/N151 ), + .O(\vga/N4123 ) + ); + defparam \vga/rom_addr_char<1>51 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>51 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N55 ), + .I2(\vga/N149 ), + .O(\vga/N5 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_11 ( + .I0(\vga/N5 ), + .I1(\vga/N4123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f521 ) + ); + defparam \vga/rom_addr_char<1>61 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>61 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N146 ), + .I2(\vga/N147 ), + .O(\vga/N6123 ) + ); + defparam \vga/rom_addr_char<1>71 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>71 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N144 ), + .I2(\vga/N145 ), + .O(\vga/N7123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_21 ( + .I0(\vga/N7123 ), + .I1(\vga/N6123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f531 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_01 ( + .I0(\vga/rom_addr_char<2>_f531 ), + .I1(\vga/rom_addr_char<2>_f521 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f611 ) + ); + defparam \vga/rom_addr_char<1>81 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>81 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N53 ), + .I2(\vga/N128 ), + .O(\vga/N8123 ) + ); + defparam \vga/rom_addr_char<1>91 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>91 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N171 ), + .I2(\vga/N172 ), + .O(\vga/N9 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_31 ( + .I0(\vga/N9 ), + .I1(\vga/N8123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f541 ) + ); + defparam \vga/rom_addr_char<1>101 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>101 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N78 ), + .I2(\vga/N170 ), + .O(\vga/N1012 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_41 ( + .I0(\vga/N11112 ), + .I1(\vga/N1012 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f551 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_11 ( + .I0(\vga/rom_addr_char<2>_f551 ), + .I1(\vga/rom_addr_char<2>_f541 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f621 ) + ); + defparam \vga/rom_addr_char<1>131 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>131 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N178 ), + .I2(\vga/N179 ), + .O(\vga/N1312 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_51 ( + .I0(\vga/N1312 ), + .I1(\vga/N1212 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f561 ) + ); + defparam \vga/rom_addr_char<1>141 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>141 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N176 ), + .I2(\vga/N86 ), + .O(\vga/N1412 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_61 ( + .I0(\vga/N1512 ), + .I1(\vga/N1412 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f571 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_21 ( + .I0(\vga/rom_addr_char<2>_f571 ), + .I1(\vga/rom_addr_char<2>_f561 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f631 ) + ); + defparam \vga/rom_addr_char<4>3 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>3 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f621 ), + .I2(\vga/rom_addr_char<3>_f631 ), + .O(\vga/N1612 ) + ); + defparam \vga/rom_addr_char<1>161 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>161 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N67 ), + .I2(\vga/N159 ), + .O(\vga/N1712 ) + ); + defparam \vga/rom_addr_char<1>171 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>171 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N65 ), + .I2(\vga/N157 ), + .O(\vga/N1812 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_71 ( + .I0(\vga/N1812 ), + .I1(\vga/N1712 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f581 ) + ); + defparam \vga/rom_addr_char<1>181 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>181 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N63 ), + .I2(\vga/N155 ), + .O(\vga/N1912 ) + ); + defparam \vga/rom_addr_char<1>191 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>191 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N152 ), + .I2(\vga/N62 ), + .O(\vga/N2012 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_81 ( + .I0(\vga/N2012 ), + .I1(\vga/N1912 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f591 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_3 ( + .I0(\vga/rom_addr_char<2>_f591 ), + .I1(\vga/rom_addr_char<2>_f581 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f64_29 ) + ); + defparam \vga/rom_addr_char<1>201 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>201 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N113 ), + .I2(\vga/N75 ), + .O(\vga/N2112 ) + ); + defparam \vga/rom_addr_char<1>211 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>211 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N72 ), + .I2(\vga/N99 ), + .O(\vga/N2212 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_9 ( + .I0(\vga/N2212 ), + .I1(\vga/N2112 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f510 ) + ); + defparam \vga/rom_addr_char<1>22 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>22 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N70 ), + .I2(\vga/N71 ), + .O(\vga/N231 ) + ); + defparam \vga/rom_addr_char<1>23 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>23 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N155 ), + .I2(\vga/N64 ), + .O(\vga/N241 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_10 ( + .I0(\vga/N241 ), + .I1(N3079), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5111 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_4 ( + .I0(\vga/rom_addr_char<2>_f5111 ), + .I1(\vga/rom_addr_char<2>_f510 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f65 ) + ); + defparam \vga/rom_addr_char<4>11 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>11 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f64_29 ), + .I2(\vga/rom_addr_char<3>_f65 ), + .O(\vga/N251 ) + ); + MUXF5 \vga/rom_addr_char<5>_f5 ( + .I0(\vga/N251 ), + .I1(\vga/N1612 ), + .S(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f5_30 ) + ); + defparam \vga/rom_addr_char<1>24 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>24 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N14 ), + .I2(\vga/N53 ), + .O(\vga/N011234 ) + ); + defparam \vga/rom_addr_char<1>112 .INIT = 4'h8; + LUT2 \vga/rom_addr_char<1>112 ( + .I0(\vga/N40 ), + .I1(\vga/rom_addr_char [1]), + .O(\vga/N1112345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f52 ( + .I0(\vga/N1112345 ), + .I1(\vga/N011234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5123 ) + ); + defparam \vga/rom_addr_char<1>25 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>25 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N49 ), + .I2(\vga/N50 ), + .O(\vga/N212345 ) + ); + defparam \vga/rom_addr_char<1>32 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>32 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N47 ), + .I2(\vga/N48 ), + .O(\vga/N31234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_02 ( + .I0(\vga/N31234 ), + .I1(\vga/N212345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5112 ) + ); + MUXF6 \vga/rom_addr_char<3>_f62 ( + .I0(\vga/rom_addr_char<2>_f5112 ), + .I1(\vga/rom_addr_char<2>_f5123 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6123 ) + ); + defparam \vga/rom_addr_char<1>42 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>42 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N59 ), + .I2(\vga/N60 ), + .O(\vga/N41234 ) + ); + defparam \vga/rom_addr_char<1>52 .INIT = 4'h4; + LUT2 \vga/rom_addr_char<1>52 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N58 ), + .O(\vga/N5123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_12 ( + .I0(\vga/N5123 ), + .I1(\vga/N41234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5212 ) + ); + defparam \vga/rom_addr_char<1>62 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>62 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N56 ), + .I2(\vga/N57 ), + .O(\vga/N61234 ) + ); + defparam \vga/rom_addr_char<1>72 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>72 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N54 ), + .I2(\vga/N55 ), + .O(\vga/N71234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_22 ( + .I0(\vga/N71234 ), + .I1(\vga/N61234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5312 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_02 ( + .I0(\vga/rom_addr_char<2>_f5312 ), + .I1(\vga/rom_addr_char<2>_f5212 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6112 ) + ); + defparam \vga/rom_addr_char<1>82 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>82 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N82 ), + .I2(\vga/N83 ), + .O(\vga/N81234 ) + ); + defparam \vga/rom_addr_char<1>92 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>92 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N80 ), + .I2(\vga/N81 ), + .O(\vga/N91 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_32 ( + .I0(\vga/N91 ), + .I1(\vga/N81234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5412 ) + ); + defparam \vga/rom_addr_char<1>102 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>102 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N78 ), + .I2(\vga/N79 ), + .O(\vga/N10123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_42 ( + .I0(\vga/N111123 ), + .I1(N3080), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5512 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_12 ( + .I0(\vga/rom_addr_char<2>_f5512 ), + .I1(\vga/rom_addr_char<2>_f5412 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6212 ) + ); + defparam \vga/rom_addr_char<1>122 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>122 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N89 ), + .I2(\vga/N90 ), + .O(\vga/N12123 ) + ); + defparam \vga/rom_addr_char<1>132 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>132 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N87 ), + .I2(\vga/N88 ), + .O(\vga/N13123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_52 ( + .I0(\vga/N13123 ), + .I1(\vga/N12123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5612 ) + ); + defparam \vga/rom_addr_char<1>142 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>142 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N85 ), + .I2(\vga/N86 ), + .O(\vga/N14123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_62 ( + .I0(\vga/N15123 ), + .I1(\vga/N14123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5712 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_22 ( + .I0(\vga/rom_addr_char<2>_f5712 ), + .I1(\vga/rom_addr_char<2>_f5612 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6312 ) + ); + defparam \vga/rom_addr_char<4>4 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>4 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f6212 ), + .I2(\vga/rom_addr_char<3>_f6312 ), + .O(\vga/N16123 ) + ); + defparam \vga/rom_addr_char<1>162 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>162 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N67 ), + .I2(\vga/N65 ), + .O(\vga/N17123 ) + ); + defparam \vga/rom_addr_char<1>172 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>172 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N65 ), + .I2(\vga/N66 ), + .O(\vga/N18123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_72 ( + .I0(\vga/N18123 ), + .I1(\vga/N17123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5812 ) + ); + defparam \vga/rom_addr_char<1>182 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>182 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N63 ), + .I2(\vga/N64 ), + .O(\vga/N19123 ) + ); + defparam \vga/rom_addr_char<1>192 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>192 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N61 ), + .I2(\vga/N62 ), + .O(\vga/N20123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_82 ( + .I0(\vga/N20123 ), + .I1(N3081), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5912 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_31 ( + .I0(\vga/rom_addr_char<2>_f5912 ), + .I1(\vga/rom_addr_char<2>_f5812 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f641 ) + ); + defparam \vga/rom_addr_char<1>202 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>202 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N74 ), + .I2(\vga/N75 ), + .O(\vga/N21123 ) + ); + defparam \vga/rom_addr_char<1>212 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>212 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N72 ), + .I2(\vga/N73 ), + .O(\vga/N22123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_91 ( + .I0(\vga/N22123 ), + .I1(\vga/N21123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f5101 ) + ); + defparam \vga/rom_addr_char<1>231 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>231 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N68 ), + .I2(\vga/N69 ), + .O(\vga/N2412 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_101 ( + .I0(\vga/N2412 ), + .I1(\vga/N231 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51112 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_41 ( + .I0(\vga/rom_addr_char<2>_f51112 ), + .I1(\vga/rom_addr_char<2>_f5101 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f651 ) + ); + defparam \vga/rom_addr_char<4>12 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>12 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f641 ), + .I2(\vga/rom_addr_char<3>_f651 ), + .O(\vga/N2512 ) + ); + MUXF5 \vga/rom_addr_char<5>_f51 ( + .I0(\vga/N2512 ), + .I1(\vga/N16123 ), + .S(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f51_31 ) + ); + defparam \vga/rom_addr_char<1>26 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>26 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N94 ), + .I2(\vga/N95 ), + .O(\vga/N0112345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f53 ( + .I0(\vga/N11123456 ), + .I1(\vga/N0112345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51234 ) + ); + defparam \vga/rom_addr_char<1>33 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>33 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N104 ), + .I2(\vga/N105 ), + .O(\vga/N2123456 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_03 ( + .I0(\vga/N312345 ), + .I1(\vga/N2123456 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51123 ) + ); + defparam \vga/rom_addr_char<1>53 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>53 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N101 ), + .I2(\vga/N102 ), + .O(\vga/N412345 ) + ); + defparam \vga/rom_addr_char<1>63 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>63 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N99 ), + .I2(\vga/N55 ), + .O(\vga/N51234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_13 ( + .I0(\vga/N51234 ), + .I1(\vga/N412345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f52123 ) + ); + MUXF6 \vga/rom_addr_char<3>_f63 ( + .I0(\vga/rom_addr_char<2>_f52123 ), + .I1(\vga/rom_addr_char<2>_f51123 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f61234 ) + ); + defparam \vga/rom_addr_char<1>73 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>73 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N127 ), + .I2(\vga/N128 ), + .O(\vga/N612345 ) + ); + defparam \vga/rom_addr_char<1>83 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>83 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N125 ), + .I2(\vga/N126 ), + .O(\vga/N712345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_23 ( + .I0(\vga/N712345 ), + .I1(\vga/N612345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f53123 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_33 ( + .I0(\vga/N9123 ), + .I1(\vga/N10123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f54123 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_03 ( + .I0(\vga/rom_addr_char<2>_f54123 ), + .I1(\vga/rom_addr_char<2>_f53123 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f61123 ) + ); + defparam \vga/rom_addr_char<1>115 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>115 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N133 ), + .I2(\vga/N134 ), + .O(\vga/N101234 ) + ); + defparam \vga/rom_addr_char<1>123 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>123 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N131 ), + .I2(\vga/N132 ), + .O(\vga/N1110 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_43 ( + .I0(\vga/N1110 ), + .I1(\vga/N101234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f55123 ) + ); + defparam \vga/rom_addr_char<1>133 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>133 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N129 ), + .I2(\vga/N130 ), + .O(\vga/N121234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_53 ( + .I0(\vga/N131234 ), + .I1(\vga/N121234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f56123 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_13 ( + .I0(\vga/rom_addr_char<2>_f56123 ), + .I1(\vga/rom_addr_char<2>_f55123 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f62123 ) + ); + defparam \vga/rom_addr_char<4>5 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>5 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f61123 ), + .I2(\vga/rom_addr_char<3>_f62123 ), + .O(\vga/N141234 ) + ); + defparam \vga/rom_addr_char<1>153 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>153 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N82 ), + .I2(\vga/N113 ), + .O(\vga/N151234 ) + ); + defparam \vga/rom_addr_char<1>163 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>163 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N110 ), + .I2(\vga/N111 ), + .O(\vga/N161234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_63 ( + .I0(\vga/N161234 ), + .I1(\vga/N151234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f57123 ) + ); + defparam \vga/rom_addr_char<1>183 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>183 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N106 ), + .I2(\vga/N62 ), + .O(\vga/N181234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_73 ( + .I0(\vga/N181234 ), + .I1(\vga/N19123 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f58123 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_23 ( + .I0(\vga/rom_addr_char<2>_f58123 ), + .I1(\vga/rom_addr_char<2>_f57123 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f63123 ) + ); + defparam \vga/rom_addr_char<1>193 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>193 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N65 ), + .I2(\vga/N120 ), + .O(\vga/N191234 ) + ); + defparam \vga/rom_addr_char<1>203 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>203 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N117 ), + .I2(\vga/N118 ), + .O(\vga/N201234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_83 ( + .I0(\vga/N201234 ), + .I1(\vga/N191234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f59123 ) + ); + defparam \vga/rom_addr_char<1>213 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>213 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N115 ), + .I2(\vga/N116 ), + .O(\vga/N211234 ) + ); + defparam \vga/rom_addr_char<1>222 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>222 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N114 ), + .I2(\vga/N64 ), + .O(\vga/N221234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_92 ( + .I0(\vga/N221234 ), + .I1(\vga/N211234 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f51012 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_32 ( + .I0(\vga/rom_addr_char<2>_f51012 ), + .I1(\vga/rom_addr_char<2>_f59123 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f6412 ) + ); + defparam \vga/rom_addr_char<4>13 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>13 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f63123 ), + .I2(\vga/rom_addr_char<3>_f6412 ), + .O(\vga/N23123 ) + ); + MUXF5 \vga/rom_addr_char<5>_f52 ( + .I0(\vga/N23123 ), + .I1(\vga/N141234 ), + .S(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f512 ) + ); + defparam \vga/rom_addr_char<1>28 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>28 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N14 ), + .I2(\vga/N2 ), + .O(\vga/N01123456 ) + ); + defparam \vga/rom_addr_char<1>116 .INIT = 4'h8; + LUT2 \vga/rom_addr_char<1>116 ( + .I0(\vga/N186 ), + .I1(\vga/rom_addr_char [1]), + .O(\vga/N111234567 ) + ); + MUXF5 \vga/rom_addr_char<2>_f54 ( + .I0(\vga/N111234567 ), + .I1(\vga/N01123456 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f512345 ) + ); + defparam \vga/rom_addr_char<1>29 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>29 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N184 ), + .I2(\vga/N8 ), + .O(\vga/N21234567 ) + ); + defparam \vga/rom_addr_char<1>34 .INIT = 4'h8; + LUT2 \vga/rom_addr_char<1>34 ( + .I0(\vga/N183 ), + .I1(\vga/rom_addr_char_1_1_95 ), + .O(\vga/N3123456 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_04 ( + .I0(\vga/N3123456 ), + .I1(\vga/N21234567 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f511234 ) + ); + MUXF6 \vga/rom_addr_char<3>_f64 ( + .I0(\vga/rom_addr_char<2>_f511234 ), + .I1(\vga/rom_addr_char<2>_f512345 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f612345 ) + ); + defparam \vga/rom_addr_char<1>44 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>44 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N194 ), + .I2(\vga/N15 ), + .O(\vga/N4123456 ) + ); + defparam \vga/rom_addr_char<1>54 .INIT = 4'h4; + LUT2 \vga/rom_addr_char<1>54 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N193 ), + .O(\vga/N512345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_14 ( + .I0(\vga/N512345 ), + .I1(\vga/N4123456 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f521234 ) + ); + defparam \vga/rom_addr_char<1>64 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>64 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N191 ), + .I2(\vga/N192 ), + .O(\vga/N6123456 ) + ); + defparam \vga/rom_addr_char<1>74 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>74 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N16 ), + .I2(\vga/N190 ), + .O(\vga/N7123456 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_24 ( + .I0(\vga/N7123456 ), + .I1(\vga/N6123456 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f531234 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_04 ( + .I0(\vga/rom_addr_char<2>_f531234 ), + .I1(\vga/rom_addr_char<2>_f521234 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f611234 ) + ); + defparam \vga/rom_addr_char<1>84 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>84 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N41 ), + .I2(\vga/N213 ), + .O(\vga/N8123456 ) + ); + defparam \vga/rom_addr_char<1>94 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>94 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N27 ), + .I2(\vga/N29 ), + .O(\vga/N91234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_34 ( + .I0(\vga/N91234 ), + .I1(\vga/N8123456 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f541234 ) + ); + defparam \vga/rom_addr_char<1>117 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>117 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N2 ), + .I2(\vga/N208 ), + .O(\vga/N1111234 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_44 ( + .I0(\vga/N1111234 ), + .I1(\vga/N1012345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f551234 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_14 ( + .I0(\vga/rom_addr_char<2>_f551234 ), + .I1(\vga/rom_addr_char<2>_f541234 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f621234 ) + ); + defparam \vga/rom_addr_char<1>124 .INIT = 4'h8; + LUT2 \vga/rom_addr_char<1>124 ( + .I0(\vga/N134 ), + .I1(\vga/rom_addr_char [1]), + .O(\vga/N1212345 ) + ); + defparam \vga/rom_addr_char<1>134 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>134 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N218 ), + .I2(\vga/N219 ), + .O(\vga/N1312345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_54 ( + .I0(\vga/N1312345 ), + .I1(\vga/N1212345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f561234 ) + ); + defparam \vga/rom_addr_char<1>144 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>144 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N216 ), + .I2(\vga/N45 ), + .O(\vga/N1412345 ) + ); + defparam \vga/rom_addr_char<1>154 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>154 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N214 ), + .I2(\vga/N215 ), + .O(\vga/N1512345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_64 ( + .I0(\vga/N1512345 ), + .I1(\vga/N1412345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f571234 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_24 ( + .I0(\vga/rom_addr_char<2>_f571234 ), + .I1(\vga/rom_addr_char<2>_f561234 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f631234 ) + ); + defparam \vga/rom_addr_char<4>6 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>6 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f621234 ), + .I2(\vga/rom_addr_char<3>_f631234 ), + .O(\vga/N1612345 ) + ); + defparam \vga/rom_addr_char<2>5 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<2>5 ( + .I0(\vga/rom_addr_char [2]), + .I1(\vga/rom_addr_char<1>112_32 ), + .I2(\vga/rom_addr_char<1>_mmx_out ), + .O(\vga/N1712345 ) + ); + defparam \vga/rom_addr_char<2>13 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<2>13 ( + .I0(\vga/rom_addr_char [2]), + .I1(\vga/rom_addr_char<1>2_33 ), + .I2(\vga/rom_addr_char<1>_mmx_out ), + .O(\vga/N1812345 ) + ); + MUXF5 \vga/rom_addr_char<3>_f5 ( + .I0(\vga/N1812345 ), + .I1(\vga/N1712345 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f5_34 ) + ); + defparam \vga/rom_addr_char<1>184 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>184 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N134 ), + .I2(\vga/N37 ), + .O(\vga/N1912345 ) + ); + defparam \vga/rom_addr_char<1>194 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>194 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N35 ), + .I2(\vga/N205 ), + .O(\vga/N2012345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_74 ( + .I0(\vga/N2012345 ), + .I1(\vga/N1912345 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f581234 ) + ); + defparam \vga/rom_addr_char<1>214 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<1>214 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N30 ), + .I2(\vga/N201 ), + .O(\vga/N2212345 ) + ); + MUXF5 \vga/rom_addr_char<2>_f5_84 ( + .I0(\vga/N2212345 ), + .I1(\vga/N1511 ), + .S(\vga/rom_addr_char [2]), + .O(\vga/rom_addr_char<2>_f591234 ) + ); + MUXF6 \vga/rom_addr_char<3>_f6_33 ( + .I0(\vga/rom_addr_char<2>_f591234 ), + .I1(\vga/rom_addr_char<2>_f581234 ), + .S(\vga/rom_addr_char [3]), + .O(\vga/rom_addr_char<3>_f64123 ) + ); + defparam \vga/rom_addr_char<4>14 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>14 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f5_34 ), + .I2(\vga/rom_addr_char<3>_f64123 ), + .O(\vga/N231234 ) + ); + MUXF5 \vga/rom_addr_char<5>_f53 ( + .I0(\vga/N231234 ), + .I1(\vga/N1612345 ), + .S(\vga/rom_addr_char [5]), + .O(\vga/rom_addr_char<5>_f5123 ) + ); + defparam \vga/rom_addr_char<2>6 .INIT = 16'hE040; + LUT4 \vga/rom_addr_char<2>6 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N221 ), + .I2(\vga/rom_addr_char [2]), + .I3(\vga/N222 ), + .O(\vga/N011234567 ) + ); + MULT_AND \vga/Madd_ram_addr_videoC_mand ( + .I0(\vga/vgacore/vcnt [3]), + .I1(\vga/vgacore/hcnt [7]), + .LO(\vga/Madd_ram_addr_videoC_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<5> .INIT = 16'h8778; + LUT4 \vga/Madd_ram_addr_video_Madd_lut<5> ( + .I0(\vga/vgacore/vcnt [3]), + .I1(\vga/vgacore/hcnt [7]), + .I2(\vga/vgacore/hcnt [8]), + .I3(\vga/vgacore/vcnt [4]), + .O(\vga/ram_addr_video [5]) + ); + MUXCY \vga/Madd_ram_addr_video_Madd_cy<5> ( + .CI(N2), + .DI(\vga/Madd_ram_addr_videoC_mand1 ), + .S(\vga/ram_addr_video [5]), + .O(\vga/Madd_ram_addr_video_Madd_cy [5]) + ); + MULT_AND \vga/Madd_ram_addr_videoC1_mand ( + .I0(\vga/vgacore/vcnt [4]), + .I1(\vga/vgacore/hcnt [8]), + .LO(\vga/Madd_ram_addr_videoC1_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<6> .INIT = 8'h78; + LUT3 \vga/Madd_ram_addr_video_Madd_lut<6> ( + .I0(\vga/vgacore/vcnt [4]), + .I1(\vga/vgacore/hcnt [8]), + .I2(\vga/Madd_ram_addr_videoR2 ), + .O(\vga/N229 ) + ); + MUXCY \vga/Madd_ram_addr_video_Madd_cy<6> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [5]), + .DI(\vga/Madd_ram_addr_videoC1_mand1 ), + .S(\vga/N229 ), + .O(\vga/Madd_ram_addr_video_Madd_cy [6]) + ); + XORCY \vga/Madd_ram_addr_video_Madd_xor<6> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [5]), + .LI(\vga/N229 ), + .O(\vga/ram_addr_video [6]) + ); + MUXCY \vga/Madd_ram_addr_video_Madd_cy<7> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [6]), + .DI(\vga/Madd_ram_addr_videoC2 ), + .S(\vga/N230 ), + .O(\vga/Madd_ram_addr_video_Madd_cy [7]) + ); + XORCY \vga/Madd_ram_addr_video_Madd_xor<7> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [6]), + .LI(\vga/N230 ), + .O(\vga/ram_addr_video [7]) + ); + MULT_AND \vga/Madd_ram_addr_videoC3_mand ( + .I0(\vga/vgacore/vcnt [4]), + .I1(\vga/vgacore/vcnt [6]), + .LO(\vga/Madd_ram_addr_videoC3_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<8> .INIT = 16'h8778; + LUT4 \vga/Madd_ram_addr_video_Madd_lut<8> ( + .I0(\vga/vgacore/vcnt [4]), + .I1(\vga/vgacore/vcnt [6]), + .I2(\vga/vgacore/vcnt [7]), + .I3(\vga/vgacore/vcnt [5]), + .O(\vga/N2313 ) + ); + MUXCY \vga/Madd_ram_addr_video_Madd_cy<8> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [7]), + .DI(\vga/Madd_ram_addr_videoC3_mand1 ), + .S(\vga/N2313 ), + .O(\vga/Madd_ram_addr_video_Madd_cy [8]) + ); + XORCY \vga/Madd_ram_addr_video_Madd_xor<8> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [7]), + .LI(\vga/N2313 ), + .O(\vga/ram_addr_video [8]) + ); + MULT_AND \vga/Madd_ram_addr_videoC4_mand ( + .I0(\vga/vgacore/vcnt [5]), + .I1(\vga/vgacore/vcnt [7]), + .LO(\vga/Madd_ram_addr_videoC4_mand1 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<9> .INIT = 16'h8778; + LUT4 \vga/Madd_ram_addr_video_Madd_lut<9> ( + .I0(\vga/vgacore/vcnt [5]), + .I1(\vga/vgacore/vcnt [7]), + .I2(\vga/vgacore/vcnt [8]), + .I3(\vga/vgacore/vcnt [6]), + .O(\vga/N232 ) + ); + MUXCY \vga/Madd_ram_addr_video_Madd_cy<9> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [8]), + .DI(\vga/Madd_ram_addr_videoC4_mand1 ), + .S(\vga/N232 ), + .O(\vga/Madd_ram_addr_video_Madd_cy [9]) + ); + XORCY \vga/Madd_ram_addr_video_Madd_xor<9> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [8]), + .LI(\vga/N232 ), + .O(\vga/ram_addr_video [9]) + ); + MUXCY \vga/Madd_ram_addr_video_Madd_cy<10> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [9]), + .DI(\vga/vgacore/vcnt [7]), + .S(\vga/N233 ), + .O(\vga/Madd_ram_addr_video_Madd_cy [10]) + ); + XORCY \vga/Madd_ram_addr_video_Madd_xor<10> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [9]), + .LI(\vga/N233 ), + .O(\vga/ram_addr_video [10]) + ); + XORCY \vga/Madd_ram_addr_video_Madd_xor<11> ( + .CI(\vga/Madd_ram_addr_video_Madd_cy [10]), + .LI(\vga/vgacore/vcnt_8_rt_86 ), + .O(\vga/ram_addr_video [11]) + ); + FDCE \vga/crt/newline ( + .D(\vga/crt/N3 ), + .CE(\vga/crt/_not0010 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/newline_37 ) + ); + FDCE \vga/crt/ram_data_0 ( + .D(\vga/crt/_mux0002 [0]), + .CE(\vga/crt/_not0008 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/ram_data [0]) + ); + FDCE \vga/crt/ram_data_1 ( + .D(\vga/crt/_mux0002 [1]), + .CE(\vga/crt/_not0008 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/ram_data [1]) + ); + FDCE \vga/crt/ram_data_2 ( + .D(\vga/crt/_mux0002 [2]), + .CE(\vga/crt/_not0008 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/ram_data [2]) + ); + FDCE \vga/crt/ram_data_3 ( + .D(\vga/crt/_mux0002 [3]), + .CE(\vga/crt/_not0008 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/ram_data [3]) + ); + FDCE \vga/crt/ram_data_4 ( + .D(\vga/crt/_mux0002 [4]), + .CE(\vga/crt/_not0008 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/ram_data [4]) + ); + FDCE \vga/crt/ram_data_5 ( + .D(\vga/crt/_mux0002 [5]), + .CE(\vga/crt/_not0008 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/ram_data [5]) + ); + FDCE \vga/crt/ram_data_6 ( + .D(\vga/crt/_mux0002 [6]), + .CE(\vga/crt/_not0008 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/ram_data [6]) + ); + FDC \vga/crt/write_delay_0 ( + .D(\vga/crt/write_delay__mux0000 [0]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/write_delay [0]) + ); + FDC \vga/crt/write_delay_1 ( + .D(\vga/crt/write_delay__mux0000 [1]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/write_delay [1]) + ); + FDC \vga/crt/write_delay_2 ( + .D(\vga/crt/write_delay__mux0000 [2]), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/write_delay [2]) + ); + FDCE \vga/crt/cursor_h_0 ( + .D(\vga/crt/cursor_h_Eqn_0 ), + .CE(\vga/crt/_not0006 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_h [0]) + ); + FDCE \vga/crt/cursor_h_1 ( + .D(\vga/crt/cursor_h_Eqn_1 ), + .CE(\vga/crt/_not0006 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_h [1]) + ); + FDCE \vga/crt/cursor_h_2 ( + .D(\vga/crt/cursor_h_Eqn_2 ), + .CE(\vga/crt/_not0006 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_h [2]) + ); + FDCE \vga/crt/cursor_h_3 ( + .D(\vga/crt/cursor_h_Eqn_3 ), + .CE(\vga/crt/_not0006 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_h [3]) + ); + FDCE \vga/crt/cursor_h_4 ( + .D(\vga/crt/cursor_h_Eqn_4 ), + .CE(\vga/crt/_not0006 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_h [4]) + ); + FDCE \vga/crt/cursor_h_5 ( + .D(\vga/crt/cursor_h_Eqn_5 ), + .CE(\vga/crt/_not0006 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_h [5]) + ); + FDCE \vga/crt/cursor_h_6 ( + .D(\vga/crt/cursor_h_Eqn_6 ), + .CE(\vga/crt/_not0006 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_h [6]) + ); + FDCE \vga/crt/cursor_v_0 ( + .D(\vga/crt/cursor_v_Eqn_0 ), + .CE(\vga/crt/_not0007 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_v [0]) + ); + FDCE \vga/crt/cursor_v_1 ( + .D(\vga/crt/cursor_v_Eqn_1 ), + .CE(\vga/crt/_not0007 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_v [1]) + ); + FDCE \vga/crt/cursor_v_2 ( + .D(\vga/crt/cursor_v_Eqn_2 ), + .CE(\vga/crt/_not0007 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_v [2]) + ); + FDCE \vga/crt/cursor_v_3 ( + .D(\vga/crt/cursor_v_Eqn_3 ), + .CE(\vga/crt/_not0007 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_v [3]) + ); + FDCE \vga/crt/cursor_v_4 ( + .D(\vga/crt/cursor_v_Eqn_4 ), + .CE(\vga/crt/_not0007 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_v [4]) + ); + FDCE \vga/crt/cursor_v_5 ( + .D(\vga/crt/cursor_v_Eqn_5 ), + .CE(\vga/crt/_not0007 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/cursor_v [5]) + ); + MULT_AND \vga/crt/Madd_ram_addrC_mand ( + .I0(\vga/crt/cursor_h [4]), + .I1(\vga/crt/cursor_v [0]), + .LO(\vga/crt/Madd_ram_addrC_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<5> .INIT = 16'h8778; + LUT4 \vga/crt/Madd_ram_addr_Madd_lut<5> ( + .I0(\vga/crt/cursor_h [4]), + .I1(\vga/crt/cursor_v [0]), + .I2(\vga/crt/cursor_v [1]), + .I3(\vga/crt/cursor_h [5]), + .O(\vga/ram_addr_write [5]) + ); + MUXCY \vga/crt/Madd_ram_addr_Madd_cy<5> ( + .CI(N2), + .DI(\vga/crt/Madd_ram_addrC_mand1 ), + .S(\vga/ram_addr_write [5]), + .O(\vga/crt/Madd_ram_addr_Madd_cy [5]) + ); + MULT_AND \vga/crt/Madd_ram_addrC1_mand ( + .I0(\vga/crt/cursor_h [5]), + .I1(\vga/crt/cursor_v [1]), + .LO(\vga/crt/Madd_ram_addrC1_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<6> .INIT = 8'h78; + LUT3 \vga/crt/Madd_ram_addr_Madd_lut<6> ( + .I0(\vga/crt/cursor_h [5]), + .I1(\vga/crt/cursor_v [1]), + .I2(\vga/crt/Madd_ram_addrR2 ), + .O(\vga/crt/N8 ) + ); + MUXCY \vga/crt/Madd_ram_addr_Madd_cy<6> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [5]), + .DI(\vga/crt/Madd_ram_addrC1_mand1 ), + .S(\vga/crt/N8 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy [6]) + ); + XORCY \vga/crt/Madd_ram_addr_Madd_xor<6> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [5]), + .LI(\vga/crt/N8 ), + .O(\vga/ram_addr_write [6]) + ); + MUXCY \vga/crt/Madd_ram_addr_Madd_cy<7> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [6]), + .DI(\vga/crt/Madd_ram_addrC2 ), + .S(\vga/crt/N9 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy [7]) + ); + XORCY \vga/crt/Madd_ram_addr_Madd_xor<7> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [6]), + .LI(\vga/crt/N9 ), + .O(\vga/ram_addr_write [7]) + ); + MULT_AND \vga/crt/Madd_ram_addrC3_mand ( + .I0(\vga/crt/cursor_v [1]), + .I1(\vga/crt/cursor_v [3]), + .LO(\vga/crt/Madd_ram_addrC3_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<8> .INIT = 16'h8778; + LUT4 \vga/crt/Madd_ram_addr_Madd_lut<8> ( + .I0(\vga/crt/cursor_v [1]), + .I1(\vga/crt/cursor_v [3]), + .I2(\vga/crt/cursor_v [4]), + .I3(\vga/crt/cursor_v [2]), + .O(\vga/crt/N10 ) + ); + MUXCY \vga/crt/Madd_ram_addr_Madd_cy<8> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [7]), + .DI(\vga/crt/Madd_ram_addrC3_mand1 ), + .S(\vga/crt/N10 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy [8]) + ); + XORCY \vga/crt/Madd_ram_addr_Madd_xor<8> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [7]), + .LI(\vga/crt/N10 ), + .O(\vga/ram_addr_write [8]) + ); + MULT_AND \vga/crt/Madd_ram_addrC4_mand ( + .I0(\vga/crt/cursor_v [2]), + .I1(\vga/crt/cursor_v [4]), + .LO(\vga/crt/Madd_ram_addrC4_mand1 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<9> .INIT = 16'h8778; + LUT4 \vga/crt/Madd_ram_addr_Madd_lut<9> ( + .I0(\vga/crt/cursor_v [2]), + .I1(\vga/crt/cursor_v [4]), + .I2(\vga/crt/cursor_v [5]), + .I3(\vga/crt/cursor_v [3]), + .O(\vga/crt/N11 ) + ); + MUXCY \vga/crt/Madd_ram_addr_Madd_cy<9> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [8]), + .DI(\vga/crt/Madd_ram_addrC4_mand1 ), + .S(\vga/crt/N11 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy [9]) + ); + XORCY \vga/crt/Madd_ram_addr_Madd_xor<9> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [8]), + .LI(\vga/crt/N11 ), + .O(\vga/ram_addr_write [9]) + ); + MUXCY \vga/crt/Madd_ram_addr_Madd_cy<10> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [9]), + .DI(\vga/crt/cursor_v [4]), + .S(\vga/crt/N12 ), + .O(\vga/crt/Madd_ram_addr_Madd_cy [10]) + ); + XORCY \vga/crt/Madd_ram_addr_Madd_xor<10> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [9]), + .LI(\vga/crt/N12 ), + .O(\vga/ram_addr_write [10]) + ); + XORCY \vga/crt/Madd_ram_addr_Madd_xor<11> ( + .CI(\vga/crt/Madd_ram_addr_Madd_cy [10]), + .LI(\vga/crt/cursor_v_5_rt_87 ), + .O(\vga/ram_addr_write [11]) + ); + MUXCY \vga/crt/Mcount_cursor_v_cy<0> ( + .CI(N2), + .DI(N3), + .S(\vga/crt/Result [0]), + .O(\vga/crt/Mcount_cursor_v_cy [0]) + ); + MUXCY \vga/crt/Mcount_cursor_v_cy<1> ( + .CI(\vga/crt/Mcount_cursor_v_cy [0]), + .DI(N2), + .S(\vga/crt/cursor_v_1_rt_64 ), + .O(\vga/crt/Mcount_cursor_v_cy [1]) + ); + XORCY \vga/crt/Mcount_cursor_v_xor<1> ( + .CI(\vga/crt/Mcount_cursor_v_cy [0]), + .LI(\vga/crt/cursor_v_1_rt_64 ), + .O(\vga/crt/Result [1]) + ); + MUXCY \vga/crt/Mcount_cursor_v_cy<2> ( + .CI(\vga/crt/Mcount_cursor_v_cy [1]), + .DI(N2), + .S(\vga/crt/cursor_v_2_rt_65 ), + .O(\vga/crt/Mcount_cursor_v_cy [2]) + ); + XORCY \vga/crt/Mcount_cursor_v_xor<2> ( + .CI(\vga/crt/Mcount_cursor_v_cy [1]), + .LI(\vga/crt/cursor_v_2_rt_65 ), + .O(\vga/crt/Result [2]) + ); + MUXCY \vga/crt/Mcount_cursor_v_cy<3> ( + .CI(\vga/crt/Mcount_cursor_v_cy [2]), + .DI(N2), + .S(\vga/crt/cursor_v_3_rt_66 ), + .O(\vga/crt/Mcount_cursor_v_cy [3]) + ); + XORCY \vga/crt/Mcount_cursor_v_xor<3> ( + .CI(\vga/crt/Mcount_cursor_v_cy [2]), + .LI(\vga/crt/cursor_v_3_rt_66 ), + .O(\vga/crt/Result [3]) + ); + MUXCY \vga/crt/Mcount_cursor_v_cy<4> ( + .CI(\vga/crt/Mcount_cursor_v_cy [3]), + .DI(N2), + .S(\vga/crt/cursor_v_4_rt_67 ), + .O(\vga/crt/Mcount_cursor_v_cy [4]) + ); + XORCY \vga/crt/Mcount_cursor_v_xor<4> ( + .CI(\vga/crt/Mcount_cursor_v_cy [3]), + .LI(\vga/crt/cursor_v_4_rt_67 ), + .O(\vga/crt/Result [4]) + ); + XORCY \vga/crt/Mcount_cursor_v_xor<5> ( + .CI(\vga/crt/Mcount_cursor_v_cy [4]), + .LI(\vga/crt/cursor_v_5_rt1_88 ), + .O(\vga/crt/Result [5]) + ); + MUXCY \vga/crt/Mcount_cursor_h_cy<0> ( + .CI(N2), + .DI(N3), + .S(\vga/crt/Result<0>1 ), + .O(\vga/crt/Mcount_cursor_h_cy [0]) + ); + MUXCY \vga/crt/Mcount_cursor_h_cy<1> ( + .CI(\vga/crt/Mcount_cursor_h_cy [0]), + .DI(N2), + .S(\vga/crt/cursor_h_1_rt_68 ), + .O(\vga/crt/Mcount_cursor_h_cy [1]) + ); + XORCY \vga/crt/Mcount_cursor_h_xor<1> ( + .CI(\vga/crt/Mcount_cursor_h_cy [0]), + .LI(\vga/crt/cursor_h_1_rt_68 ), + .O(\vga/crt/Result<1>1 ) + ); + MUXCY \vga/crt/Mcount_cursor_h_cy<2> ( + .CI(\vga/crt/Mcount_cursor_h_cy [1]), + .DI(N2), + .S(\vga/crt/cursor_h_2_rt_69 ), + .O(\vga/crt/Mcount_cursor_h_cy [2]) + ); + XORCY \vga/crt/Mcount_cursor_h_xor<2> ( + .CI(\vga/crt/Mcount_cursor_h_cy [1]), + .LI(\vga/crt/cursor_h_2_rt_69 ), + .O(\vga/crt/Result<2>1 ) + ); + MUXCY \vga/crt/Mcount_cursor_h_cy<3> ( + .CI(\vga/crt/Mcount_cursor_h_cy [2]), + .DI(N2), + .S(\vga/crt/cursor_h_3_rt_70 ), + .O(\vga/crt/Mcount_cursor_h_cy [3]) + ); + XORCY \vga/crt/Mcount_cursor_h_xor<3> ( + .CI(\vga/crt/Mcount_cursor_h_cy [2]), + .LI(\vga/crt/cursor_h_3_rt_70 ), + .O(\vga/crt/Result<3>1 ) + ); + MUXCY \vga/crt/Mcount_cursor_h_cy<4> ( + .CI(\vga/crt/Mcount_cursor_h_cy [3]), + .DI(N2), + .S(\vga/crt/cursor_h_4_rt_71 ), + .O(\vga/crt/Mcount_cursor_h_cy [4]) + ); + XORCY \vga/crt/Mcount_cursor_h_xor<4> ( + .CI(\vga/crt/Mcount_cursor_h_cy [3]), + .LI(\vga/crt/cursor_h_4_rt_71 ), + .O(\vga/crt/Result<4>1 ) + ); + MUXCY \vga/crt/Mcount_cursor_h_cy<5> ( + .CI(\vga/crt/Mcount_cursor_h_cy [4]), + .DI(N2), + .S(\vga/crt/cursor_h_5_rt_72 ), + .O(\vga/crt/Mcount_cursor_h_cy [5]) + ); + XORCY \vga/crt/Mcount_cursor_h_xor<5> ( + .CI(\vga/crt/Mcount_cursor_h_cy [4]), + .LI(\vga/crt/cursor_h_5_rt_72 ), + .O(\vga/crt/Result<5>1 ) + ); + XORCY \vga/crt/Mcount_cursor_h_xor<6> ( + .CI(\vga/crt/Mcount_cursor_h_cy [5]), + .LI(\vga/crt/cursor_h_6_rt_89 ), + .O(\vga/crt/Result [6]) + ); + FDC \vga/crt/state_FFd3 ( + .D(\vga/crt/state_FFd3-In ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/state_FFd3_42 ) + ); + FDC \vga/crt/state_FFd1 ( + .D(\vga/crt/state_FFd1-In_43 ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/state_FFd1_40 ) + ); + FDC \vga/crt/state_FFd2 ( + .D(\vga/crt/state_FFd2-In ), + .CLR(gray_cnt_Rst_inv), + .C(\vga/crtclk_15 ), + .Q(\vga/crt/state_FFd2_41 ) + ); + FDC \vga/vgacore/hsync ( + .D(\vga/vgacore/_and0000 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hsync_7 ) + ); + FDC \vga/vgacore/vsync ( + .D(\vga/vgacore/_and0001_44 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/vsync_6 ) + ); + FDC \vga/vgacore/hblank ( + .D(\vga/vgacore/_mux0002 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hblank_12 ) + ); + FDC \vga/vgacore/hcnt_0 ( + .D(\vga/vgacore/Result [0]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [0]) + ); + FDC \vga/vgacore/hcnt_1 ( + .D(\vga/vgacore/Result [1]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [1]) + ); + FDC \vga/vgacore/hcnt_2 ( + .D(\vga/vgacore/Result [2]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [2]) + ); + FDC \vga/vgacore/hcnt_3 ( + .D(\vga/vgacore/Result [3]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [3]) + ); + FDC \vga/vgacore/hcnt_4 ( + .D(\vga/vgacore/Result [4]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [4]) + ); + FDC \vga/vgacore/hcnt_5 ( + .D(\vga/vgacore/Result [5]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [5]) + ); + FDC \vga/vgacore/hcnt_6 ( + .D(\vga/vgacore/Result [6]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [6]) + ); + FDC \vga/vgacore/hcnt_7 ( + .D(\vga/vgacore/Result [7]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [7]) + ); + FDC \vga/vgacore/hcnt_8 ( + .D(\vga/vgacore/Result [8]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [8]) + ); + FDC \vga/vgacore/hcnt_9 ( + .D(\vga/vgacore/Result [9]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [9]) + ); + FDC \vga/vgacore/hcnt_10 ( + .D(\vga/vgacore/Result [10]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/vgacore/hcnt [10]) + ); + FDC_1 \vga/vgacore/vcnt_0 ( + .D(\vga/vgacore/Result<0>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [0]) + ); + FDC_1 \vga/vgacore/vcnt_1 ( + .D(\vga/vgacore/Result<1>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [1]) + ); + FDC_1 \vga/vgacore/vcnt_2 ( + .D(\vga/vgacore/Result<2>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [2]) + ); + FDC_1 \vga/vgacore/vcnt_3 ( + .D(\vga/vgacore/Result<3>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [3]) + ); + FDC_1 \vga/vgacore/vcnt_4 ( + .D(\vga/vgacore/Result<4>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [4]) + ); + FDC_1 \vga/vgacore/vcnt_5 ( + .D(\vga/vgacore/Result<5>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [5]) + ); + FDC_1 \vga/vgacore/vcnt_6 ( + .D(\vga/vgacore/Result<6>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [6]) + ); + FDC_1 \vga/vgacore/vcnt_7 ( + .D(\vga/vgacore/Result<7>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [7]) + ); + FDC_1 \vga/vgacore/vcnt_8 ( + .D(\vga/vgacore/Result<8>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [8]) + ); + FDC_1 \vga/vgacore/vcnt_9 ( + .D(\vga/vgacore/Result<9>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt [9]) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<0> .INIT = 16'h8000; + LUT4 \vga/vgacore/Mcompar__cmp_lt0000_lut<0> ( + .I0(\vga/vgacore/hcnt [0]), + .I1(\vga/vgacore/hcnt [1]), + .I2(\vga/vgacore/hcnt [2]), + .I3(\vga/vgacore/hcnt [3]), + .O(\vga/vgacore/N4 ) + ); + MUXCY \vga/vgacore/Mcompar__cmp_lt0000_cy<0> ( + .CI(N3), + .DI(N2), + .S(\vga/vgacore/N4 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy [0]) + ); + MUXCY \vga/vgacore/Mcompar__cmp_lt0000_cy<1> ( + .CI(\vga/vgacore/Mcompar__cmp_lt0000_cy [0]), + .DI(N2), + .S(\vga/vgacore/hcnt_4_rt_73 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy [1]) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<2> .INIT = 8'h01; + LUT3 \vga/vgacore/Mcompar__cmp_lt0000_lut<2> ( + .I0(\vga/vgacore/hcnt [5]), + .I1(\vga/vgacore/hcnt [6]), + .I2(\vga/vgacore/hcnt [7]), + .O(\vga/vgacore/N5 ) + ); + MUXCY \vga/vgacore/Mcompar__cmp_lt0000_cy<2> ( + .CI(\vga/vgacore/Mcompar__cmp_lt0000_cy [1]), + .DI(N3), + .S(\vga/vgacore/N5 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy [2]) + ); + defparam \vga/vgacore/Mcompar__cmp_lt0000_lut<3> .INIT = 4'h8; + LUT2 \vga/vgacore/Mcompar__cmp_lt0000_lut<3> ( + .I0(\vga/vgacore/hcnt [8]), + .I1(\vga/vgacore/hcnt [9]), + .O(\vga/vgacore/N6 ) + ); + MUXCY \vga/vgacore/Mcompar__cmp_lt0000_cy<3> ( + .CI(\vga/vgacore/Mcompar__cmp_lt0000_cy [2]), + .DI(N2), + .S(\vga/vgacore/N6 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy [3]) + ); + MUXCY \vga/vgacore/Mcompar__cmp_lt0000_cy<4> ( + .CI(\vga/vgacore/Mcompar__cmp_lt0000_cy [3]), + .DI(N3), + .S(\vga/vgacore/N7 ), + .O(\vga/vgacore/Mcompar__cmp_lt0000_cy [4]) + ); + MULT_AND \vga/vgacore/hcnt_Eqn_0_mand ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [0]), + .LO(\vga/vgacore/hcnt_Eqn_0_mand1 ) + ); + defparam \vga/vgacore/Mcount_hcnt_lut<0> .INIT = 4'h4; + LUT2 \vga/vgacore/Mcount_hcnt_lut<0> ( + .I0(\vga/vgacore/hcnt [0]), + .I1(\vga/vgacore/hcnt_Eqn_bis_0 ), + .O(\vga/vgacore/Result [0]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<0> ( + .CI(N2), + .DI(\vga/vgacore/hcnt_Eqn_0_mand1 ), + .S(\vga/vgacore/Result [0]), + .O(\vga/vgacore/Mcount_hcnt_cy [0]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<1> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [0]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_1 ), + .O(\vga/vgacore/Mcount_hcnt_cy [1]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<1> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [0]), + .LI(\vga/vgacore/hcnt_Eqn_1 ), + .O(\vga/vgacore/Result [1]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<2> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [1]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_2 ), + .O(\vga/vgacore/Mcount_hcnt_cy [2]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<2> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [1]), + .LI(\vga/vgacore/hcnt_Eqn_2 ), + .O(\vga/vgacore/Result [2]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<3> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [2]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_3 ), + .O(\vga/vgacore/Mcount_hcnt_cy [3]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<3> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [2]), + .LI(\vga/vgacore/hcnt_Eqn_3 ), + .O(\vga/vgacore/Result [3]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<4> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [3]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_4 ), + .O(\vga/vgacore/Mcount_hcnt_cy [4]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<4> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [3]), + .LI(\vga/vgacore/hcnt_Eqn_4 ), + .O(\vga/vgacore/Result [4]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<5> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [4]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_5 ), + .O(\vga/vgacore/Mcount_hcnt_cy [5]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<5> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [4]), + .LI(\vga/vgacore/hcnt_Eqn_5 ), + .O(\vga/vgacore/Result [5]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<6> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [5]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_6 ), + .O(\vga/vgacore/Mcount_hcnt_cy [6]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<6> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [5]), + .LI(\vga/vgacore/hcnt_Eqn_6 ), + .O(\vga/vgacore/Result [6]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<7> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [6]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_7 ), + .O(\vga/vgacore/Mcount_hcnt_cy [7]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<7> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [6]), + .LI(\vga/vgacore/hcnt_Eqn_7 ), + .O(\vga/vgacore/Result [7]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<8> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [7]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_8 ), + .O(\vga/vgacore/Mcount_hcnt_cy [8]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<8> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [7]), + .LI(\vga/vgacore/hcnt_Eqn_8 ), + .O(\vga/vgacore/Result [8]) + ); + MUXCY \vga/vgacore/Mcount_hcnt_cy<9> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [8]), + .DI(N2), + .S(\vga/vgacore/hcnt_Eqn_9 ), + .O(\vga/vgacore/Mcount_hcnt_cy [9]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<9> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [8]), + .LI(\vga/vgacore/hcnt_Eqn_9 ), + .O(\vga/vgacore/Result [9]) + ); + XORCY \vga/vgacore/Mcount_hcnt_xor<10> ( + .CI(\vga/vgacore/Mcount_hcnt_cy [9]), + .LI(\vga/vgacore/hcnt_Eqn_10 ), + .O(\vga/vgacore/Result [10]) + ); + MULT_AND \vga/vgacore/vcnt_Eqn_0_mand ( + .I0(\vga/vgacore/vcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/vcnt [0]), + .LO(\vga/vgacore/vcnt_Eqn_0_mand1 ) + ); + defparam \vga/vgacore/Mcount_vcnt_lut<0> .INIT = 4'h4; + LUT2 \vga/vgacore/Mcount_vcnt_lut<0> ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt_Eqn_bis_0 ), + .O(\vga/vgacore/Result<0>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<0> ( + .CI(N2), + .DI(\vga/vgacore/vcnt_Eqn_0_mand1 ), + .S(\vga/vgacore/Result<0>1 ), + .O(\vga/vgacore/Mcount_vcnt_cy [0]) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<1> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [0]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_1_45 ), + .O(\vga/vgacore/Mcount_vcnt_cy [1]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<1> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [0]), + .LI(\vga/vgacore/vcnt_Eqn_1_45 ), + .O(\vga/vgacore/Result<1>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<2> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [1]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_2 ), + .O(\vga/vgacore/Mcount_vcnt_cy [2]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<2> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [1]), + .LI(\vga/vgacore/vcnt_Eqn_2 ), + .O(\vga/vgacore/Result<2>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<3> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [2]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_3_46 ), + .O(\vga/vgacore/Mcount_vcnt_cy [3]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<3> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [2]), + .LI(\vga/vgacore/vcnt_Eqn_3_46 ), + .O(\vga/vgacore/Result<3>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<4> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [3]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_4 ), + .O(\vga/vgacore/Mcount_vcnt_cy [4]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<4> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [3]), + .LI(\vga/vgacore/vcnt_Eqn_4 ), + .O(\vga/vgacore/Result<4>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<5> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [4]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_5 ), + .O(\vga/vgacore/Mcount_vcnt_cy [5]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<5> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [4]), + .LI(\vga/vgacore/vcnt_Eqn_5 ), + .O(\vga/vgacore/Result<5>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<6> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [5]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_6 ), + .O(\vga/vgacore/Mcount_vcnt_cy [6]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<6> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [5]), + .LI(\vga/vgacore/vcnt_Eqn_6 ), + .O(\vga/vgacore/Result<6>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<7> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [6]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_7 ), + .O(\vga/vgacore/Mcount_vcnt_cy [7]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<7> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [6]), + .LI(\vga/vgacore/vcnt_Eqn_7 ), + .O(\vga/vgacore/Result<7>1 ) + ); + MUXCY \vga/vgacore/Mcount_vcnt_cy<8> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [7]), + .DI(N2), + .S(\vga/vgacore/vcnt_Eqn_8 ), + .O(\vga/vgacore/Mcount_vcnt_cy [8]) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<8> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [7]), + .LI(\vga/vgacore/vcnt_Eqn_8 ), + .O(\vga/vgacore/Result<8>1 ) + ); + XORCY \vga/vgacore/Mcount_vcnt_xor<9> ( + .CI(\vga/vgacore/Mcount_vcnt_cy [8]), + .LI(\vga/vgacore/vcnt_Eqn_9 ), + .O(\vga/vgacore/Result<9>1 ) + ); + FDC \vga/ps2/rdy_r ( + .D(\vga/ps2/scancode_rdy ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/rdy_r_8 ) + ); + FDP \vga/ps2/ps2_clk_r_0 ( + .D(ps2_clk_IBUF_1), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/ps2_clk_r [0]) + ); + FDP \vga/ps2/ps2_clk_r_1 ( + .D(\vga/ps2/ps2_clk_r [0]), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/ps2_clk_r [1]) + ); + FDP \vga/ps2/ps2_clk_r_2 ( + .D(\vga/ps2/ps2_clk_r [1]), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/ps2_clk_r [2]) + ); + FDP \vga/ps2/ps2_clk_r_3 ( + .D(\vga/ps2/ps2_clk_r [2]), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/ps2_clk_r [3]) + ); + FDP \vga/ps2/ps2_clk_r_4 ( + .D(\vga/ps2/ps2_clk_r [3]), + .PRE(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/ps2_clk_r [4]) + ); + FDC \vga/ps2/timer_r_0 ( + .D(\vga/ps2/timer_x [0]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [0]) + ); + FDC \vga/ps2/timer_r_1 ( + .D(\vga/ps2/timer_x [1]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [1]) + ); + FDC \vga/ps2/timer_r_2 ( + .D(\vga/ps2/timer_x [2]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [2]) + ); + FDC \vga/ps2/timer_r_3 ( + .D(\vga/ps2/timer_x [3]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [3]) + ); + FDC \vga/ps2/timer_r_4 ( + .D(\vga/ps2/timer_x [4]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [4]) + ); + FDC \vga/ps2/timer_r_5 ( + .D(\vga/ps2/timer_x [5]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [5]) + ); + FDC \vga/ps2/timer_r_6 ( + .D(\vga/ps2/timer_x [6]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [6]) + ); + FDC \vga/ps2/timer_r_7 ( + .D(\vga/ps2/timer_x [7]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [7]) + ); + FDC \vga/ps2/timer_r_8 ( + .D(\vga/ps2/timer_x [8]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [8]) + ); + FDC \vga/ps2/timer_r_9 ( + .D(\vga/ps2/timer_x [9]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [9]) + ); + FDC \vga/ps2/timer_r_10 ( + .D(\vga/ps2/timer_x [10]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [10]) + ); + FDC \vga/ps2/timer_r_11 ( + .D(\vga/ps2/timer_x [11]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [11]) + ); + FDC \vga/ps2/timer_r_12 ( + .D(\vga/ps2/timer_x [12]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [12]) + ); + FDC \vga/ps2/timer_r_13 ( + .D(\vga/ps2/timer_x [13]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/timer_r [13]) + ); + FDC \vga/ps2/error_r ( + .D(\vga/ps2/error_x ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/error_r_47 ) + ); + FDC \vga/ps2/bitcnt_r_0 ( + .D(\vga/ps2/bitcnt_x [0]), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/bitcnt_r [0]) + ); + FDC \vga/ps2/bitcnt_r_1 ( + .D(\vga/ps2/bitcnt_x [1]), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/bitcnt_r [1]) + ); + FDC \vga/ps2/bitcnt_r_2 ( + .D(\vga/ps2/bitcnt_x [2]), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/bitcnt_r [2]) + ); + FDC \vga/ps2/bitcnt_r_3 ( + .D(\vga/ps2/bitcnt_x [3]), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/bitcnt_r [3]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<0> ( + .CI(N2), + .DI(N3), + .S(\vga/ps2/N5 ), + .O(\vga/ps2/Madd__addsub0000_cy [0]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<1> ( + .CI(\vga/ps2/Madd__addsub0000_cy [0]), + .DI(N2), + .S(\vga/ps2/timer_r_1_rt_74 ), + .O(\vga/ps2/Madd__addsub0000_cy [1]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<1> ( + .CI(\vga/ps2/Madd__addsub0000_cy [0]), + .LI(\vga/ps2/timer_r_1_rt_74 ), + .O(\vga/ps2/_addsub0000 [1]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<2> ( + .CI(\vga/ps2/Madd__addsub0000_cy [1]), + .DI(N2), + .S(\vga/ps2/timer_r_2_rt_75 ), + .O(\vga/ps2/Madd__addsub0000_cy [2]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<2> ( + .CI(\vga/ps2/Madd__addsub0000_cy [1]), + .LI(\vga/ps2/timer_r_2_rt_75 ), + .O(\vga/ps2/_addsub0000 [2]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<3> ( + .CI(\vga/ps2/Madd__addsub0000_cy [2]), + .DI(N2), + .S(\vga/ps2/timer_r_3_rt_76 ), + .O(\vga/ps2/Madd__addsub0000_cy [3]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<3> ( + .CI(\vga/ps2/Madd__addsub0000_cy [2]), + .LI(\vga/ps2/timer_r_3_rt_76 ), + .O(\vga/ps2/_addsub0000 [3]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<4> ( + .CI(\vga/ps2/Madd__addsub0000_cy [3]), + .DI(N2), + .S(\vga/ps2/timer_r_4_rt_77 ), + .O(\vga/ps2/Madd__addsub0000_cy [4]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<4> ( + .CI(\vga/ps2/Madd__addsub0000_cy [3]), + .LI(\vga/ps2/timer_r_4_rt_77 ), + .O(\vga/ps2/_addsub0000 [4]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<5> ( + .CI(\vga/ps2/Madd__addsub0000_cy [4]), + .DI(N2), + .S(\vga/ps2/timer_r_5_rt_78 ), + .O(\vga/ps2/Madd__addsub0000_cy [5]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<5> ( + .CI(\vga/ps2/Madd__addsub0000_cy [4]), + .LI(\vga/ps2/timer_r_5_rt_78 ), + .O(\vga/ps2/_addsub0000 [5]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<6> ( + .CI(\vga/ps2/Madd__addsub0000_cy [5]), + .DI(N2), + .S(\vga/ps2/timer_r_6_rt_79 ), + .O(\vga/ps2/Madd__addsub0000_cy [6]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<6> ( + .CI(\vga/ps2/Madd__addsub0000_cy [5]), + .LI(\vga/ps2/timer_r_6_rt_79 ), + .O(\vga/ps2/_addsub0000 [6]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<7> ( + .CI(\vga/ps2/Madd__addsub0000_cy [6]), + .DI(N2), + .S(\vga/ps2/timer_r_7_rt_80 ), + .O(\vga/ps2/Madd__addsub0000_cy [7]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<7> ( + .CI(\vga/ps2/Madd__addsub0000_cy [6]), + .LI(\vga/ps2/timer_r_7_rt_80 ), + .O(\vga/ps2/_addsub0000 [7]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<8> ( + .CI(\vga/ps2/Madd__addsub0000_cy [7]), + .DI(N2), + .S(\vga/ps2/timer_r_8_rt_81 ), + .O(\vga/ps2/Madd__addsub0000_cy [8]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<8> ( + .CI(\vga/ps2/Madd__addsub0000_cy [7]), + .LI(\vga/ps2/timer_r_8_rt_81 ), + .O(\vga/ps2/_addsub0000 [8]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<9> ( + .CI(\vga/ps2/Madd__addsub0000_cy [8]), + .DI(N2), + .S(\vga/ps2/timer_r_9_rt_82 ), + .O(\vga/ps2/Madd__addsub0000_cy [9]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<9> ( + .CI(\vga/ps2/Madd__addsub0000_cy [8]), + .LI(\vga/ps2/timer_r_9_rt_82 ), + .O(\vga/ps2/_addsub0000 [9]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<10> ( + .CI(\vga/ps2/Madd__addsub0000_cy [9]), + .DI(N2), + .S(\vga/ps2/timer_r_10_rt_83 ), + .O(\vga/ps2/Madd__addsub0000_cy [10]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<10> ( + .CI(\vga/ps2/Madd__addsub0000_cy [9]), + .LI(\vga/ps2/timer_r_10_rt_83 ), + .O(\vga/ps2/_addsub0000 [10]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<11> ( + .CI(\vga/ps2/Madd__addsub0000_cy [10]), + .DI(N2), + .S(\vga/ps2/timer_r_11_rt_84 ), + .O(\vga/ps2/Madd__addsub0000_cy [11]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<11> ( + .CI(\vga/ps2/Madd__addsub0000_cy [10]), + .LI(\vga/ps2/timer_r_11_rt_84 ), + .O(\vga/ps2/_addsub0000 [11]) + ); + MUXCY \vga/ps2/Madd__addsub0000_cy<12> ( + .CI(\vga/ps2/Madd__addsub0000_cy [11]), + .DI(N2), + .S(\vga/ps2/timer_r_12_rt_85 ), + .O(\vga/ps2/Madd__addsub0000_cy [12]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<12> ( + .CI(\vga/ps2/Madd__addsub0000_cy [11]), + .LI(\vga/ps2/timer_r_12_rt_85 ), + .O(\vga/ps2/_addsub0000 [12]) + ); + XORCY \vga/ps2/Madd__addsub0000_xor<13> ( + .CI(\vga/ps2/Madd__addsub0000_cy [12]), + .LI(\vga/ps2/timer_r_13_rt_90 ), + .O(\vga/ps2/_addsub0000 [13]) + ); + FDCE \vga/scancode_convert/shift ( + .D(\vga/scancode_convert/shift_set ), + .CE(\vga/scancode_convert/_not0007_55 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/shift_49 ) + ); + FDCE \vga/scancode_convert/capslock ( + .D(\vga/scancode_convert/_not0008 ), + .CE(\vga/scancode_convert/capslock_toggle ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/capslock_48 ) + ); + FDCE \vga/scancode_convert/ctrl ( + .D(\vga/scancode_convert/ctrl_set_58 ), + .CE(\vga/scancode_convert/_not0009 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ctrl_57 ) + ); + FDCE \vga/scancode_convert/release_prefix ( + .D(\vga/scancode_convert/release_prefix_set ), + .CE(\vga/scancode_convert/_not0010 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/release_prefix_59 ) + ); + FDE \vga/scancode_convert/sc_0 ( + .D(\vga/ps2/sc_r [0]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc [0]) + ); + FDE \vga/scancode_convert/sc_1 ( + .D(\vga/ps2/sc_r [1]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc [1]) + ); + FDE \vga/scancode_convert/sc_2 ( + .D(\vga/ps2/sc_r [2]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc [2]) + ); + FDE \vga/scancode_convert/sc_3 ( + .D(\vga/ps2/sc_r [3]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc [3]) + ); + FDE \vga/scancode_convert/sc_4 ( + .D(\vga/ps2/sc_r [4]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc [4]) + ); + FDE \vga/scancode_convert/sc_5 ( + .D(\vga/ps2/sc_r [5]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc [5]) + ); + FDE \vga/scancode_convert/sc_6 ( + .D(\vga/ps2/sc_r [6]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc [6]) + ); + FDE \vga/scancode_convert/ascii_0 ( + .D(\vga/scancode_convert/rom_data [0]), + .CE(\vga/scancode_convert/_or0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ascii [0]) + ); + FDE \vga/scancode_convert/ascii_1 ( + .D(\vga/scancode_convert/rom_data [1]), + .CE(\vga/scancode_convert/_or0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ascii [1]) + ); + FDE \vga/scancode_convert/ascii_2 ( + .D(\vga/scancode_convert/rom_data [2]), + .CE(\vga/scancode_convert/_or0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ascii [2]) + ); + FDE \vga/scancode_convert/ascii_3 ( + .D(\vga/scancode_convert/rom_data [3]), + .CE(\vga/scancode_convert/_or0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ascii [3]) + ); + FDE \vga/scancode_convert/ascii_4 ( + .D(\vga/scancode_convert/rom_data [4]), + .CE(\vga/scancode_convert/_or0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ascii [4]) + ); + FDE \vga/scancode_convert/ascii_5 ( + .D(\vga/scancode_convert/rom_data [5]), + .CE(\vga/scancode_convert/_or0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ascii [5]) + ); + FDE \vga/scancode_convert/ascii_6 ( + .D(\vga/scancode_convert/_mux0008 [6]), + .CE(\vga/scancode_convert/_or0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/ascii [6]) + ); + FDCE \vga/scancode_convert/strobe_out ( + .D(\vga/scancode_convert/state_FFd2_52 ), + .CE(\vga/scancode_convert/_not0011 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/strobe_out_14 ) + ); + FDCE \vga/scancode_convert/key_up ( + .D(\vga/scancode_convert/state_FFd3_56 ), + .CE(\vga/scancode_convert/_not0012 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/key_up_16 ) + ); + FDC \vga/scancode_convert/hold_count_0 ( + .D(\vga/scancode_convert/hold_count__mux0000 [0]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/hold_count [0]) + ); + FDC \vga/scancode_convert/hold_count_1 ( + .D(\vga/scancode_convert/hold_count__mux0000 [1]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/hold_count [1]) + ); + FDC \vga/scancode_convert/hold_count_2 ( + .D(\vga/scancode_convert/hold_count__mux0000 [2]), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/hold_count [2]) + ); + FDC \vga/scancode_convert/state_FFd3 ( + .D(\vga/scancode_convert/state_FFd3-In_62 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/state_FFd3_56 ) + ); + FDC \vga/scancode_convert/state_FFd1 ( + .D(\vga/scancode_convert/state_FFd1-In ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/state_FFd1_53 ) + ); + FDC \vga/scancode_convert/state_FFd2 ( + .D(\vga/scancode_convert/state_FFd2-In_61 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/state_FFd2_52 ) + ); + FDP \vga/scancode_convert/state_FFd6 ( + .D(N2), + .PRE(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/state_FFd6_60 ) + ); + FDC \vga/scancode_convert/state_FFd4 ( + .D(\vga/scancode_convert/state_FFd4-In ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/state_FFd4_50 ) + ); + FDC \vga/scancode_convert/state_FFd5 ( + .D(\vga/scancode_convert/state_FFd5-In_63 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/state_FFd5_54 ) + ); + defparam \vga/insert_crt_data1 .INIT = 4'h4; + LUT2 \vga/insert_crt_data1 ( + .I0(\vga/scancode_convert/key_up_16 ), + .I1(\vga/scancode_convert/strobe_out_14 ), + .O(\vga/insert_crt_data ) + ); + defparam \vga/rom_addr_char<2>4 .INIT = 8'h08; + LUT3 \vga/rom_addr_char<2>4 ( + .I0(\vga/rom_addr_char [2]), + .I1(\vga/N14 ), + .I2(\vga/rom_addr_char_1_1_95 ), + .O(\vga/rom_addr_char<2>11_27 ) + ); + defparam \vga/ram_addr_mux<11>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<11>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/ram_addr_write [11]), + .I2(\vga/ram_addr_video [11]), + .O(\vga/ram_addr_mux [11]) + ); + defparam \vga/ram_addr_mux<10>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<10>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/ram_addr_write [10]), + .I2(\vga/ram_addr_video [10]), + .O(\vga/ram_addr_mux [10]) + ); + defparam \vga/ram_addr_mux<9>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<9>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/ram_addr_write [9]), + .I2(\vga/ram_addr_video [9]), + .O(\vga/ram_addr_mux [9]) + ); + defparam \vga/ram_addr_mux<8>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<8>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/ram_addr_write [8]), + .I2(\vga/ram_addr_video [8]), + .O(\vga/ram_addr_mux [8]) + ); + defparam \vga/ram_addr_mux<7>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<7>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/ram_addr_write [7]), + .I2(\vga/ram_addr_video [7]), + .O(\vga/ram_addr_mux [7]) + ); + defparam \vga/ram_addr_mux<6>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<6>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/ram_addr_write [6]), + .I2(\vga/ram_addr_video [6]), + .O(\vga/ram_addr_mux [6]) + ); + defparam \vga/ram_addr_mux<5>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<5>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/ram_addr_write [5]), + .I2(\vga/ram_addr_video [5]), + .O(\vga/ram_addr_mux [5]) + ); + defparam \vga/ram_addr_mux<2>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<2>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/crt/cursor_h [2]), + .I2(\vga/vgacore/hcnt [5]), + .O(\vga/ram_addr_mux [2]) + ); + defparam \vga/ram_addr_mux<3>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<3>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/crt/cursor_h [3]), + .I2(\vga/vgacore/hcnt [6]), + .O(\vga/ram_addr_mux [3]) + ); + defparam \vga/ram_addr_mux<1>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<1>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/crt/cursor_h [1]), + .I2(\vga/vgacore/hcnt [4]), + .O(\vga/ram_addr_mux [1]) + ); + defparam \vga/ram_addr_mux<0>1 .INIT = 8'hE4; + LUT3 \vga/ram_addr_mux<0>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/crt/cursor_h [0]), + .I2(\vga/vgacore/hcnt [3]), + .O(\vga/ram_addr_mux [0]) + ); + defparam \vga/rom_addr_char<4>1 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<4>1 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f62_24 ), + .I2(\vga/rom_addr_char<3>_f63_25 ), + .O(\vga/rom_addr_char<4>11_26 ) + ); + defparam \vga/Madd_ram_addr_videoC21 .INIT = 8'hE8; + LUT3 \vga/Madd_ram_addr_videoC21 ( + .I0(\vga/vgacore/vcnt [3]), + .I1(\vga/vgacore/vcnt [5]), + .I2(\vga/vgacore/hcnt [9]), + .O(\vga/Madd_ram_addr_videoC2 ) + ); + defparam \vga/crt/Madd_ram_addrC21 .INIT = 8'hE8; + LUT3 \vga/crt/Madd_ram_addrC21 ( + .I0(\vga/crt/cursor_v [0]), + .I1(\vga/crt/cursor_v [2]), + .I2(\vga/crt/cursor_h [6]), + .O(\vga/crt/Madd_ram_addrC2 ) + ); + defparam \vga/crt/ram_we_n1 .INIT = 8'hF9; + LUT3 \vga/crt/ram_we_n1 ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt/state_FFd1_40 ), + .I2(\vga/crt/state_FFd2_41 ), + .O(\vga/ram_we_n ) + ); + defparam \vga/Madd_ram_addr_videoR21 .INIT = 8'h96; + LUT3 \vga/Madd_ram_addr_videoR21 ( + .I0(\vga/vgacore/hcnt [9]), + .I1(\vga/vgacore/vcnt [3]), + .I2(\vga/vgacore/vcnt [5]), + .O(\vga/Madd_ram_addr_videoR2 ) + ); + defparam \vga/crt/Madd_ram_addrR21 .INIT = 8'h96; + LUT3 \vga/crt/Madd_ram_addrR21 ( + .I0(\vga/crt/cursor_h [6]), + .I1(\vga/crt/cursor_v [0]), + .I2(\vga/crt/cursor_v [2]), + .O(\vga/crt/Madd_ram_addrR2 ) + ); + defparam \vga/crt/_cmp_eq000111 .INIT = 16'h0002; + LUT4 \vga/crt/_cmp_eq000111 ( + .I0(\vga/crt_data [3]), + .I1(\vga/crt_data [6]), + .I2(\vga/crt_data [5]), + .I3(\vga/crt_data [4]), + .O(\vga/crt/N16 ) + ); + defparam \vga/crt/_cmp_eq00011 .INIT = 16'h0020; + LUT4 \vga/crt/_cmp_eq00011 ( + .I0(\vga/crt_data [1]), + .I1(\vga/crt_data [0]), + .I2(\vga/crt/N16 ), + .I3(\vga/crt_data [2]), + .O(\vga/crt/_cmp_eq0001 ) + ); + defparam \vga/vgacore/_or000011 .INIT = 16'h8000; + LUT4 \vga/vgacore/_or000011 ( + .I0(\vga/vgacore/vcnt [7]), + .I1(\vga/vgacore/vcnt [8]), + .I2(\vga/vgacore/vcnt [6]), + .I3(\vga/vgacore/vcnt [5]), + .O(\vga/vgacore/N61 ) + ); + defparam \vga/rom_addr_char<4>71 .INIT = 16'h5410; + LUT4 \vga/rom_addr_char<4>71 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char [3]), + .I2(\vga/N011234567 ), + .I3(\vga/N1112 ), + .O(\vga/rom_addr_char<4>11234 ) + ); + defparam \vga/vgacore/_and0001_SW0 .INIT = 8'hF7; + LUT3 \vga/vgacore/_and0001_SW0 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/N61 ), + .I2(\vga/vgacore/vcnt [9]), + .O(N44) + ); + defparam \vga/vgacore/_and0001 .INIT = 16'h0002; + LUT4 \vga/vgacore/_and0001 ( + .I0(\vga/vgacore/vcnt [3]), + .I1(\vga/vgacore/vcnt [4]), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(N44), + .O(\vga/vgacore/_and0001_44 ) + ); + defparam \vga/pixel<8>27 .INIT = 8'h08; + LUT3 \vga/pixel<8>27 ( + .I0(\vga/pixel<8>_map785 ), + .I1(\vga/pixelData [0]), + .I2(\vga/vgacore/hblank_12 ), + .O(pixel[8]) + ); + defparam \vga/scancode_convert/hold_count__mux0000<0>1 .INIT = 4'h4; + LUT2 \vga/scancode_convert/hold_count__mux0000<0>1 ( + .I0(\vga/scancode_convert/hold_count [0]), + .I1(\vga/scancode_convert/state_FFd1_53 ), + .O(\vga/scancode_convert/hold_count__mux0000 [0]) + ); + defparam \vga/scancode_convert/hold_count__mux0000<1>1 .INIT = 8'h28; + LUT3 \vga/scancode_convert/hold_count__mux0000<1>1 ( + .I0(\vga/scancode_convert/state_FFd1_53 ), + .I1(\vga/scancode_convert/hold_count [0]), + .I2(\vga/scancode_convert/hold_count [1]), + .O(\vga/scancode_convert/hold_count__mux0000 [1]) + ); + defparam \vga/vgacore/_mux00021 .INIT = 16'hFCF8; + LUT4 \vga/vgacore/_mux00021 ( + .I0(\vga/vgacore/hcnt [7]), + .I1(\vga/vgacore/hcnt [9]), + .I2(\vga/vgacore/hcnt [10]), + .I3(\vga/vgacore/hcnt [8]), + .O(\vga/vgacore/_mux0002 ) + ); + defparam \vga/_mux00001 .INIT = 16'h04AE; + LUT4 \vga/_mux00001 ( + .I0(\vga/clearing ), + .I1(\vga/pclk [2]), + .I2(\vga/pclk [1]), + .I3(\vga/crtclk1 ), + .O(\vga/_mux0000 ) + ); + defparam \vga/pclk__mux0000<1>1 .INIT = 16'hFFF6; + LUT4 \vga/pclk__mux0000<1>1 ( + .I0(\vga/pclk [0]), + .I1(\vga/pclk [1]), + .I2(\vga/vgacore/hblank_12 ), + .I3(\vga/clearing ), + .O(\vga/pclk__mux0000 [1]) + ); + defparam \vga/scancode_convert/hold_count__mux0000<2>1 .INIT = 16'h4888; + LUT4 \vga/scancode_convert/hold_count__mux0000<2>1 ( + .I0(\vga/scancode_convert/hold_count [2]), + .I1(\vga/scancode_convert/state_FFd1_53 ), + .I2(\vga/scancode_convert/hold_count [0]), + .I3(\vga/scancode_convert/hold_count [1]), + .O(\vga/scancode_convert/hold_count__mux0000 [2]) + ); + defparam \vga/scancode_convert/_or00001 .INIT = 4'hE; + LUT2 \vga/scancode_convert/_or00001 ( + .I0(\vga/scancode_convert/state_FFd2_52 ), + .I1(\vga/scancode_convert/state_FFd3_56 ), + .O(\vga/scancode_convert/_or0000 ) + ); + defparam \vga/crt/_not00081 .INIT = 16'h4404; + LUT4 \vga/crt/_not00081 ( + .I0(\vga/crt/state_FFd1_40 ), + .I1(\vga/crt/state_FFd2_41 ), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/insert_crt_data ), + .O(\vga/crt/_not0008 ) + ); + defparam \vga/pclk__mux0000<2> .INIT = 16'hFF6A; + LUT4 \vga/pclk__mux0000<2> ( + .I0(\vga/pclk [2]), + .I1(\vga/pclk [1]), + .I2(\vga/pclk [0]), + .I3(N89), + .O(\vga/pclk__mux0000 [2]) + ); + defparam \vga/scancode_convert/state_FFd1-In1 .INIT = 8'hAE; + LUT3 \vga/scancode_convert/state_FFd1-In1 ( + .I0(\vga/scancode_convert/state_FFd4_50 ), + .I1(\vga/scancode_convert/state_FFd1_53 ), + .I2(\vga/scancode_convert/_cmp_eq0005 ), + .O(\vga/scancode_convert/state_FFd1-In ) + ); + defparam \vga/crt/write_delay__mux0000<1>1 .INIT = 8'h28; + LUT3 \vga/crt/write_delay__mux0000<1>1 ( + .I0(\vga/crt/_cmp_eq0004 ), + .I1(\vga/crt/write_delay [0]), + .I2(\vga/crt/write_delay [1]), + .O(\vga/crt/write_delay__mux0000 [1]) + ); + defparam \vga/crt/_mux0002<6>1 .INIT = 16'h7D28; + LUT4 \vga/crt/_mux0002<6>1 ( + .I0(\vga/crt/N91 ), + .I1(\vga/crt/cursor_h [5]), + .I2(\vga/crt/cursor_h [6]), + .I3(\vga/crt_data [6]), + .O(\vga/crt/_mux0002 [6]) + ); + defparam \vga/crt/write_delay__mux0000<2>1 .INIT = 16'h4888; + LUT4 \vga/crt/write_delay__mux0000<2>1 ( + .I0(\vga/crt/write_delay [2]), + .I1(\vga/crt/_cmp_eq0004 ), + .I2(\vga/crt/write_delay [0]), + .I3(\vga/crt/write_delay [1]), + .O(\vga/crt/write_delay__mux0000 [2]) + ); + defparam \vga/ps2/ps2_clk_edge2 .INIT = 16'h0240; + LUT4 \vga/ps2/ps2_clk_edge2 ( + .I0(\vga/ps2/ps2_clk_r [3]), + .I1(\vga/ps2/ps2_clk_r [1]), + .I2(\vga/ps2/ps2_clk_r [2]), + .I3(\vga/ps2/ps2_clk_r [4]), + .O(\vga/ps2/ps2_clk_edge ) + ); + defparam \vga/scancode_convert/_not00111 .INIT = 16'hFFEA; + LUT4 \vga/scancode_convert/_not00111 ( + .I0(\vga/scancode_convert/state_FFd3_56 ), + .I1(\vga/scancode_convert/state_FFd1_53 ), + .I2(\vga/scancode_convert/_cmp_eq0005 ), + .I3(\vga/scancode_convert/state_FFd2_52 ), + .O(\vga/scancode_convert/_not0011 ) + ); + defparam \vga/crt/state_Out911 .INIT = 4'h7; + LUT2 \vga/crt/state_Out911 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/state_FFd3_42 ), + .O(\vga/crt/N91 ) + ); + defparam \vga/ps2/_cmp_eq00001 .INIT = 16'h2000; + LUT4 \vga/ps2/_cmp_eq00001 ( + .I0(\vga/ps2/bitcnt_r [0]), + .I1(\vga/ps2/bitcnt_r [2]), + .I2(\vga/ps2/bitcnt_r [3]), + .I3(\vga/ps2/bitcnt_r [1]), + .O(\vga/ps2/_cmp_eq0000 ) + ); + defparam \vga/crt/state_FFd1-In_SW0 .INIT = 16'h9810; + LUT4 \vga/crt/state_FFd1-In_SW0 ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt/state_FFd2_41 ), + .I2(\vga/crt/state_FFd1_40 ), + .I3(\vga/insert_crt_data ), + .O(N116) + ); + defparam \vga/crt/state_FFd1-In_SW1 .INIT = 16'hBB80; + LUT4 \vga/crt/state_FFd1-In_SW1 ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt/state_FFd2_41 ), + .I2(\vga/insert_crt_data ), + .I3(\vga/crt/state_FFd1_40 ), + .O(N117) + ); + defparam \vga/crt/state_FFd1-In .INIT = 16'hFE02; + LUT4 \vga/crt/state_FFd1-In ( + .I0(N116), + .I1(\vga/crt/newline_37 ), + .I2(\vga/crt/_cmp_eq0001 ), + .I3(N117), + .O(\vga/crt/state_FFd1-In_43 ) + ); + defparam \vga/scancode_convert/_not00091 .INIT = 16'h2000; + LUT4 \vga/scancode_convert/_not00091 ( + .I0(\vga/scancode_convert/_and0000 ), + .I1(\vga/ps2/sc_r [1]), + .I2(\vga/scancode_convert/N10 ), + .I3(\vga/ps2/sc_r [2]), + .O(\vga/scancode_convert/_not0009 ) + ); + defparam \vga/crt/_not00071 .INIT = 16'h88A8; + LUT4 \vga/crt/_not00071 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/state_FFd1_40 ), + .I2(\vga/crt/eol_35 ), + .I3(\vga/crt/state_FFd3_42 ), + .O(\vga/crt/_not0007 ) + ); + defparam \vga/crt/_not00061 .INIT = 16'hAFA8; + LUT4 \vga/crt/_not00061 ( + .I0(\vga/crt/state_FFd1_40 ), + .I1(\vga/crt/eol_35 ), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/crt/state_FFd2_41 ), + .O(\vga/crt/_not0006 ) + ); + defparam \vga/vgacore/vcnt_Eqn_81 .INIT = 4'h4; + LUT2 \vga/vgacore/vcnt_Eqn_81 ( + .I0(\vga/vgacore/vcnt [9]), + .I1(\vga/vgacore/vcnt [8]), + .O(\vga/vgacore/vcnt_Eqn_8 ) + ); + defparam \vga/scancode_convert/state_FFd5-In_SW0 .INIT = 8'hEA; + LUT3 \vga/scancode_convert/state_FFd5-In_SW0 ( + .I0(\vga/scancode_convert/state_FFd6_60 ), + .I1(\vga/scancode_convert/_cmp_eq0005 ), + .I2(\vga/scancode_convert/state_FFd1_53 ), + .O(N124) + ); + defparam \vga/scancode_convert/state_FFd5-In .INIT = 16'hFF8C; + LUT4 \vga/scancode_convert/state_FFd5-In ( + .I0(\vga/scancode_convert/_cmp_eq0000_51 ), + .I1(\vga/scancode_convert/state_FFd5_54 ), + .I2(\vga/ps2/rdy_r_8 ), + .I3(N124), + .O(\vga/scancode_convert/state_FFd5-In_63 ) + ); + defparam \vga/scancode_convert/state_FFd2-In .INIT = 16'h0002; + LUT4 \vga/scancode_convert/state_FFd2-In ( + .I0(\vga/scancode_convert/_and0000 ), + .I1(\vga/scancode_convert/N11 ), + .I2(\vga/scancode_convert/_cmp_eq0000_51 ), + .I3(N126), + .O(\vga/scancode_convert/state_FFd2-In_61 ) + ); + defparam \vga/scancode_convert/state_FFd3-In .INIT = 16'h0020; + LUT4 \vga/scancode_convert/state_FFd3-In ( + .I0(N128), + .I1(\vga/scancode_convert/N11 ), + .I2(\vga/scancode_convert/_and0000 ), + .I3(\vga/scancode_convert/_cmp_eq0000_51 ), + .O(\vga/scancode_convert/state_FFd3-In_62 ) + ); + defparam \vga/crt/state_FFd3-In37 .INIT = 16'h55D5; + LUT4 \vga/crt/state_FFd3-In37 ( + .I0(\vga/crt/state_FFd1_40 ), + .I1(\vga/crt/write_delay [0]), + .I2(\vga/crt/write_delay [1]), + .I3(\vga/crt/write_delay [2]), + .O(\vga/crt/state_FFd3-In_map800 ) + ); + defparam \vga/vgacore/_and00005 .INIT = 16'h8000; + LUT4 \vga/vgacore/_and00005 ( + .I0(\vga/vgacore/hcnt [2]), + .I1(\vga/vgacore/hcnt [1]), + .I2(\vga/vgacore/hcnt [4]), + .I3(\vga/vgacore/hcnt [3]), + .O(\vga/vgacore/_and0000_map807 ) + ); + defparam \vga/vgacore/_and000033 .INIT = 16'h0002; + LUT4 \vga/vgacore/_and000033 ( + .I0(\vga/vgacore/hcnt [8]), + .I1(\vga/vgacore/hcnt [7]), + .I2(\vga/vgacore/hcnt [6]), + .I3(\vga/vgacore/hcnt [5]), + .O(\vga/vgacore/_and0000_map817 ) + ); + defparam \vga/vgacore/_and000046 .INIT = 16'h0001; + LUT4 \vga/vgacore/_and000046 ( + .I0(\vga/vgacore/hcnt [4]), + .I1(\vga/vgacore/hcnt [3]), + .I2(\vga/vgacore/hcnt [2]), + .I3(\vga/vgacore/hcnt [1]), + .O(\vga/vgacore/_and0000_map824 ) + ); + defparam \vga/vgacore/_and000047 .INIT = 4'h8; + LUT2 \vga/vgacore/_and000047 ( + .I0(\vga/vgacore/_and0000_map817 ), + .I1(\vga/vgacore/_and0000_map824 ), + .O(\vga/vgacore/_and0000_map825 ) + ); + defparam \vga/vgacore/vcnt_Eqn_71 .INIT = 4'h4; + LUT2 \vga/vgacore/vcnt_Eqn_71 ( + .I0(\vga/vgacore/vcnt [9]), + .I1(\vga/vgacore/vcnt [7]), + .O(\vga/vgacore/vcnt_Eqn_7 ) + ); + defparam \vga/vgacore/vcnt_Eqn_92 .INIT = 8'h80; + LUT3 \vga/vgacore/vcnt_Eqn_92 ( + .I0(\vga/vgacore/N51 ), + .I1(\vga/vgacore/vcnt [9]), + .I2(\vga/vgacore/N0 ), + .O(\vga/vgacore/vcnt_Eqn_9 ) + ); + defparam \vga/vgacore/vcnt_Eqn_61 .INIT = 4'h4; + LUT2 \vga/vgacore/vcnt_Eqn_61 ( + .I0(\vga/vgacore/vcnt [9]), + .I1(\vga/vgacore/vcnt [6]), + .O(\vga/vgacore/vcnt_Eqn_6 ) + ); + defparam \vga/vgacore/vcnt_Eqn_51 .INIT = 4'h4; + LUT2 \vga/vgacore/vcnt_Eqn_51 ( + .I0(\vga/vgacore/vcnt [9]), + .I1(\vga/vgacore/vcnt [5]), + .O(\vga/vgacore/vcnt_Eqn_5 ) + ); + defparam \vga/scancode_convert/state_FFd2-In111 .INIT = 4'h8; + LUT2 \vga/scancode_convert/state_FFd2-In111 ( + .I0(\vga/ps2/rdy_r_8 ), + .I1(\vga/scancode_convert/state_FFd5_54 ), + .O(\vga/scancode_convert/_and0000 ) + ); + defparam \vga/crt/state_Out41 .INIT = 8'h04; + LUT3 \vga/crt/state_Out41 ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt/state_FFd1_40 ), + .I2(\vga/crt/state_FFd2_41 ), + .O(\vga/crt/_cmp_eq0004 ) + ); + defparam \vga/scancode_convert/_cmp_eq00051 .INIT = 8'h04; + LUT3 \vga/scancode_convert/_cmp_eq00051 ( + .I0(\vga/scancode_convert/hold_count [0]), + .I1(\vga/scancode_convert/hold_count [2]), + .I2(\vga/scancode_convert/hold_count [1]), + .O(\vga/scancode_convert/_cmp_eq0005 ) + ); + defparam \vga/scancode_convert/capslock_toggle1 .INIT = 16'h2000; + LUT4 \vga/scancode_convert/capslock_toggle1 ( + .I0(\vga/scancode_convert/_and0000 ), + .I1(\vga/ps2/sc_r [0]), + .I2(\vga/scancode_convert/release_prefix_59 ), + .I3(\vga/scancode_convert/N11 ), + .O(\vga/scancode_convert/capslock_toggle ) + ); + defparam \vga/vgacore/vcnt_Eqn_41 .INIT = 4'h4; + LUT2 \vga/vgacore/vcnt_Eqn_41 ( + .I0(\vga/vgacore/vcnt [9]), + .I1(\vga/vgacore/vcnt [4]), + .O(\vga/vgacore/vcnt_Eqn_4 ) + ); + defparam \vga/crt/_and0001_SW0 .INIT = 4'hD; + LUT2 \vga/crt/_and0001_SW0 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/state_FFd1_40 ), + .O(N235) + ); + defparam \vga/scancode_convert/_cmp_eq00041 .INIT = 16'h0001; + LUT4 \vga/scancode_convert/_cmp_eq00041 ( + .I0(\vga/ps2/sc_r [7]), + .I1(\vga/ps2/sc_r [6]), + .I2(\vga/ps2/sc_r [5]), + .I3(N237), + .O(\vga/scancode_convert/N10 ) + ); + defparam \vga/scancode_convert/shift_set17 .INIT = 16'hC888; + LUT4 \vga/scancode_convert/shift_set17 ( + .I0(\vga/scancode_convert/shift_set_map833 ), + .I1(\vga/scancode_convert/shift_set_map836 ), + .I2(\vga/scancode_convert/N11 ), + .I3(\vga/ps2/sc_r [0]), + .O(\vga/scancode_convert/shift_set ) + ); + defparam \vga/ps2/ps2_clk_edge11 .INIT = 16'h0020; + LUT4 \vga/ps2/ps2_clk_edge11 ( + .I0(\vga/ps2/ps2_clk_r [4]), + .I1(\vga/ps2/ps2_clk_r [1]), + .I2(\vga/ps2/ps2_clk_r [3]), + .I3(\vga/ps2/ps2_clk_r [2]), + .O(\vga/ps2/ps2_clk_fall_edge ) + ); + defparam \vga/scancode_convert/_cmp_eq000221 .INIT = 16'h0020; + LUT4 \vga/scancode_convert/_cmp_eq000221 ( + .I0(N3268), + .I1(\vga/ps2/sc_r [5]), + .I2(\vga/ps2/sc_r [3]), + .I3(\vga/ps2/sc_r [7]), + .O(\vga/scancode_convert/N11 ) + ); + defparam \vga/scancode_convert/_not0007 .INIT = 16'hC888; + LUT4 \vga/scancode_convert/_not0007 ( + .I0(N3267), + .I1(\vga/scancode_convert/_and0000 ), + .I2(\vga/ps2/sc_r [0]), + .I3(\vga/scancode_convert/N11 ), + .O(\vga/scancode_convert/_not0007_55 ) + ); + defparam \vga/crt/eol .INIT = 16'h0020; + LUT4 \vga/crt/eol ( + .I0(\vga/crt/cursor_h [6]), + .I1(\vga/crt/cursor_h [5]), + .I2(\vga/crt/cursor_h [0]), + .I3(N293), + .O(\vga/crt/eol_35 ) + ); + defparam \vga/crt/cursor_v_Eqn_11 .INIT = 4'h4; + LUT2 \vga/crt/cursor_v_Eqn_11 ( + .I0(N3266), + .I1(\vga/crt/Result [1]), + .O(\vga/crt/cursor_v_Eqn_1 ) + ); + defparam \vga/ps2/timer_x<1>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<1>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [1]), + .O(\vga/ps2/timer_x [1]) + ); + defparam \vga/crt/cursor_h_Eqn_11 .INIT = 4'h4; + LUT2 \vga/crt/cursor_h_Eqn_11 ( + .I0(\vga/crt/_and0000_38 ), + .I1(\vga/crt/Result<1>1 ), + .O(\vga/crt/cursor_h_Eqn_1 ) + ); + defparam \vga/crt/scroll .INIT = 16'h2000; + LUT4 \vga/crt/scroll ( + .I0(\vga/crt/cursor_v [5]), + .I1(N301), + .I2(\vga/crt/cursor_v [4]), + .I3(\vga/crt/cursor_v [0]), + .O(\vga/crt/scroll_36 ) + ); + defparam \vga/crt/_and0000_SW1 .INIT = 16'hFF7F; + LUT4 \vga/crt/_and0000_SW1 ( + .I0(\vga/crt/state_FFd1_40 ), + .I1(\vga/crt_data [0]), + .I2(\vga/crt/N16 ), + .I3(\vga/crt_data [1]), + .O(N306) + ); + defparam \vga/crt/_and0000 .INIT = 16'h085D; + LUT4 \vga/crt/_and0000 ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt_data [2]), + .I2(N306), + .I3(N305), + .O(\vga/crt/_and0000_38 ) + ); + defparam \vga/crt/cursor_v_Eqn_21 .INIT = 4'h4; + LUT2 \vga/crt/cursor_v_Eqn_21 ( + .I0(\vga/crt/_and0001_39 ), + .I1(\vga/crt/Result [2]), + .O(\vga/crt/cursor_v_Eqn_2 ) + ); + defparam \vga/crt/cursor_h_Eqn_21 .INIT = 4'h4; + LUT2 \vga/crt/cursor_h_Eqn_21 ( + .I0(\vga/crt/_and0000_38 ), + .I1(\vga/crt/Result<2>1 ), + .O(\vga/crt/cursor_h_Eqn_2 ) + ); + defparam \vga/ps2/timer_x<2>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<2>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [2]), + .O(\vga/ps2/timer_x [2]) + ); + defparam \vga/crt/cursor_v_Eqn_31 .INIT = 4'h4; + LUT2 \vga/crt/cursor_v_Eqn_31 ( + .I0(\vga/crt/_and0001_39 ), + .I1(\vga/crt/Result [3]), + .O(\vga/crt/cursor_v_Eqn_3 ) + ); + defparam \vga/crt/cursor_h_Eqn_31 .INIT = 4'h4; + LUT2 \vga/crt/cursor_h_Eqn_31 ( + .I0(\vga/crt/_and0000_38 ), + .I1(\vga/crt/Result<3>1 ), + .O(\vga/crt/cursor_h_Eqn_3 ) + ); + defparam \vga/ps2/timer_x<3>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<3>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [3]), + .O(\vga/ps2/timer_x [3]) + ); + defparam \vga/crt/cursor_v_Eqn_41 .INIT = 4'h4; + LUT2 \vga/crt/cursor_v_Eqn_41 ( + .I0(\vga/crt/_and0001_39 ), + .I1(\vga/crt/Result [4]), + .O(\vga/crt/cursor_v_Eqn_4 ) + ); + defparam \vga/crt/cursor_h_Eqn_41 .INIT = 4'h4; + LUT2 \vga/crt/cursor_h_Eqn_41 ( + .I0(\vga/crt/_and0000_38 ), + .I1(\vga/crt/Result<4>1 ), + .O(\vga/crt/cursor_h_Eqn_4 ) + ); + defparam \vga/ps2/timer_x<4>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<4>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [4]), + .O(\vga/ps2/timer_x [4]) + ); + defparam \vga/crt/cursor_v_Eqn_51 .INIT = 4'h4; + LUT2 \vga/crt/cursor_v_Eqn_51 ( + .I0(\vga/crt/_and0001_39 ), + .I1(\vga/crt/Result [5]), + .O(\vga/crt/cursor_v_Eqn_5 ) + ); + defparam \vga/crt/cursor_h_Eqn_51 .INIT = 4'h4; + LUT2 \vga/crt/cursor_h_Eqn_51 ( + .I0(\vga/crt/_and0000_38 ), + .I1(\vga/crt/Result<5>1 ), + .O(\vga/crt/cursor_h_Eqn_5 ) + ); + defparam \vga/ps2/timer_x<5>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<5>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [5]), + .O(\vga/ps2/timer_x [5]) + ); + defparam \vga/crt/cursor_h_Eqn_61 .INIT = 4'h4; + LUT2 \vga/crt/cursor_h_Eqn_61 ( + .I0(\vga/crt/_and0000_38 ), + .I1(\vga/crt/Result [6]), + .O(\vga/crt/cursor_h_Eqn_6 ) + ); + defparam \vga/ps2/timer_x<6>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<6>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [6]), + .O(\vga/ps2/timer_x [6]) + ); + defparam \vga/ps2/timer_x<7>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<7>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [7]), + .O(\vga/ps2/timer_x [7]) + ); + defparam \vga/_and000026 .INIT = 16'h9009; + LUT4 \vga/_and000026 ( + .I0(\vga/crt/cursor_h [0]), + .I1(\vga/vgacore/hcnt [3]), + .I2(\vga/crt/cursor_h [1]), + .I3(\vga/vgacore/hcnt [4]), + .O(\vga/_and0000_map879 ) + ); + defparam \vga/_and000053 .INIT = 16'h9009; + LUT4 \vga/_and000053 ( + .I0(\vga/crt/cursor_h [2]), + .I1(\vga/vgacore/hcnt [5]), + .I2(\vga/crt/cursor_h [3]), + .I3(\vga/vgacore/hcnt [6]), + .O(\vga/_and0000_map890 ) + ); + defparam \vga/_and0000129 .INIT = 16'h9009; + LUT4 \vga/_and0000129 ( + .I0(\vga/crt/cursor_v [0]), + .I1(\vga/vgacore/vcnt [3]), + .I2(\vga/crt/cursor_v [1]), + .I3(\vga/vgacore/vcnt [4]), + .O(\vga/_and0000_map918 ) + ); + defparam \vga/_and0000156 .INIT = 16'h9009; + LUT4 \vga/_and0000156 ( + .I0(\vga/crt/cursor_v [2]), + .I1(\vga/vgacore/vcnt [5]), + .I2(\vga/crt/cursor_v [3]), + .I3(\vga/vgacore/vcnt [6]), + .O(\vga/_and0000_map929 ) + ); + defparam \vga/_and0000183 .INIT = 16'h9009; + LUT4 \vga/_and0000183 ( + .I0(\vga/crt/cursor_v [4]), + .I1(\vga/vgacore/vcnt [7]), + .I2(\vga/crt/cursor_v [5]), + .I3(\vga/vgacore/vcnt [8]), + .O(\vga/_and0000_map940 ) + ); + defparam \vga/_and0000184 .INIT = 4'h8; + LUT2 \vga/_and0000184 ( + .I0(\vga/_and0000_map929 ), + .I1(\vga/_and0000_map940 ), + .O(\vga/_and0000_map941 ) + ); + defparam \vga/_and0000215 .INIT = 16'h9000; + LUT4 \vga/_and0000215 ( + .I0(\vga/crt/cursor_h [6]), + .I1(\vga/vgacore/hcnt [9]), + .I2(\vga/_and0000_map918 ), + .I3(\vga/_and0000_map941 ), + .O(\vga/_and0000_map943 ) + ); + defparam \vga/_and0000238 .INIT = 16'h8000; + LUT4 \vga/_and0000238 ( + .I0(\vga/_and0000_map879 ), + .I1(\vga/_and0000_map890 ), + .I2(\vga/_and0000_map902 ), + .I3(\vga/_and0000_map943 ), + .O(\vga/cursor_match ) + ); + defparam \vga/ps2/timer_x<8>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<8>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [8]), + .O(\vga/ps2/timer_x [8]) + ); + defparam \vga/ps2/timer_x<9>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<9>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [9]), + .O(\vga/ps2/timer_x [9]) + ); + defparam \vga/ps2/timer_x<10>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<10>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [10]), + .O(\vga/ps2/timer_x [10]) + ); + defparam \vga/ps2/timer_x<11>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<11>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [11]), + .O(\vga/ps2/timer_x [11]) + ); + defparam \vga/ps2/timer_x<12>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<12>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [12]), + .O(\vga/ps2/timer_x [12]) + ); + defparam \vga/ps2/timer_x<13>1 .INIT = 4'h4; + LUT2 \vga/ps2/timer_x<13>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/_addsub0000 [13]), + .O(\vga/ps2/timer_x [13]) + ); + defparam \vga/vgacore/vcnt_Eqn_21 .INIT = 16'h22A2; + LUT4 \vga/vgacore/vcnt_Eqn_21 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [9]), + .I2(\vga/vgacore/N51 ), + .I3(\vga/vgacore/vcnt [3]), + .O(\vga/vgacore/vcnt_Eqn_2 ) + ); + defparam \vga/vgacore/hcnt_Eqn_101 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_101 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [10]), + .O(\vga/vgacore/hcnt_Eqn_10 ) + ); + defparam \vga/_cmp_eq00001 .INIT = 8'h80; + LUT3 \vga/_cmp_eq00001 ( + .I0(\vga/pclk [2]), + .I1(\vga/pclk [0]), + .I2(\vga/pclk [1]), + .O(\vga/_cmp_eq0000 ) + ); + defparam \vga/charload1 .INIT = 16'hFAD8; + LUT4 \vga/charload1 ( + .I0(\vga/charload_13 ), + .I1(\vga/cursor_match ), + .I2(\vga/pixel_hold [1]), + .I3(N560), + .O(\vga/_mux0002 [5]) + ); + defparam \vga/charload8 .INIT = 16'hFAD8; + LUT4 \vga/charload8 ( + .I0(\vga/charload_13 ), + .I1(\vga/cursor_match ), + .I2(\vga/pixel_hold [6]), + .I3(N562), + .O(\vga/_mux0002 [0]) + ); + defparam \vga/charload317 .INIT = 16'h5410; + LUT4 \vga/charload317 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char [3]), + .I2(\vga/N0112 ), + .I3(\vga/N11123 ), + .O(\vga/charload3_map953 ) + ); + defparam \vga/charload513 .INIT = 16'hE040; + LUT4 \vga/charload513 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f6123 ), + .I2(\vga/rom_addr_char [5]), + .I3(\vga/rom_addr_char<3>_f6112 ), + .O(\vga/charload5_map965 ) + ); + defparam \vga/charload413 .INIT = 16'hE040; + LUT4 \vga/charload413 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f612 ), + .I2(\vga/rom_addr_char [5]), + .I3(\vga/rom_addr_char<3>_f611 ), + .O(\vga/charload4_map979 ) + ); + defparam \vga/charload713 .INIT = 16'hE040; + LUT4 \vga/charload713 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f612345 ), + .I2(\vga/rom_addr_char [5]), + .I3(\vga/rom_addr_char<3>_f611234 ), + .O(\vga/charload7_map993 ) + ); + defparam \vga/charload617 .INIT = 16'h5410; + LUT4 \vga/charload617 ( + .I0(\vga/rom_addr_char [2]), + .I1(\vga/rom_addr_char [1]), + .I2(\vga/N96 ), + .I3(\vga/N30 ), + .O(\vga/charload6_map1010 ) + ); + defparam \vga/charload628 .INIT = 16'hC888; + LUT4 \vga/charload628 ( + .I0(\vga/charload6_map1010 ), + .I1(\vga/rom_addr_char [3]), + .I2(\vga/rom_addr_char [2]), + .I3(\vga/N98 ), + .O(\vga/charload6_map1012 ) + ); + defparam \vga/charload637 .INIT = 4'h4; + LUT2 \vga/charload637 ( + .I0(\vga/rom_addr_char [3]), + .I1(\vga/rom_addr_char<2>_f51234 ), + .O(\vga/charload6_map1014 ) + ); + defparam \vga/charload669 .INIT = 16'hFE54; + LUT4 \vga/charload669 ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/charload6_map1012 ), + .I2(\vga/charload6_map1014 ), + .I3(\vga/rom_addr_char<3>_f61234 ), + .O(\vga/charload6_map1018 ) + ); + defparam \vga/charload6111 .INIT = 16'hEA40; + LUT4 \vga/charload6111 ( + .I0(\vga/rom_addr_char [6]), + .I1(\vga/rom_addr_char [5]), + .I2(\vga/charload6_map1018 ), + .I3(\vga/rom_addr_char<5>_f512 ), + .O(\vga/charload6_map1022 ) + ); + defparam \vga/charload6153 .INIT = 16'hFAD8; + LUT4 \vga/charload6153 ( + .I0(\vga/charload_13 ), + .I1(\vga/cursor_match ), + .I2(\vga/pixel_hold [3]), + .I3(\vga/charload6_map1022 ), + .O(\vga/_mux0002 [3]) + ); + defparam \vga/vgacore/vcnt_Eqn_3_SW0 .INIT = 8'hEA; + LUT3 \vga/vgacore/vcnt_Eqn_3_SW0 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .O(N786) + ); + defparam \vga/vgacore/vcnt_Eqn_3 .INIT = 16'h22A2; + LUT4 \vga/vgacore/vcnt_Eqn_3 ( + .I0(\vga/vgacore/vcnt [3]), + .I1(\vga/vgacore/vcnt [9]), + .I2(\vga/vgacore/N51 ), + .I3(N786), + .O(\vga/vgacore/vcnt_Eqn_3_46 ) + ); + defparam \vga/ps2/_cmp_eq00018 .INIT = 16'h0020; + LUT4 \vga/ps2/_cmp_eq00018 ( + .I0(\vga/ps2/timer_r [7]), + .I1(\vga/ps2/timer_r [4]), + .I2(\vga/ps2/timer_r [6]), + .I3(\vga/ps2/timer_r [5]), + .O(\vga/ps2/_cmp_eq0001_map1032 ) + ); + defparam \vga/ps2/_cmp_eq000112 .INIT = 4'h1; + LUT2 \vga/ps2/_cmp_eq000112 ( + .I0(\vga/ps2/timer_r [12]), + .I1(\vga/ps2/timer_r [13]), + .O(\vga/ps2/_cmp_eq0001_map1035 ) + ); + defparam \vga/ps2/_cmp_eq000130 .INIT = 16'h0020; + LUT4 \vga/ps2/_cmp_eq000130 ( + .I0(\vga/ps2/timer_r [8]), + .I1(\vga/ps2/timer_r [9]), + .I2(\vga/ps2/timer_r [11]), + .I3(\vga/ps2/timer_r [10]), + .O(\vga/ps2/_cmp_eq0001_map1041 ) + ); + defparam \vga/ps2/_cmp_eq000142 .INIT = 16'h0002; + LUT4 \vga/ps2/_cmp_eq000142 ( + .I0(\vga/ps2/timer_r [2]), + .I1(\vga/ps2/timer_r [3]), + .I2(\vga/ps2/timer_r [0]), + .I3(\vga/ps2/timer_r [1]), + .O(\vga/ps2/_cmp_eq0001_map1047 ) + ); + defparam \vga/ps2/_cmp_eq000156 .INIT = 16'h8000; + LUT4 \vga/ps2/_cmp_eq000156 ( + .I0(\vga/ps2/_cmp_eq0001_map1032 ), + .I1(\vga/ps2/_cmp_eq0001_map1035 ), + .I2(\vga/ps2/_cmp_eq0001_map1041 ), + .I3(\vga/ps2/_cmp_eq0001_map1047 ), + .O(\vga/ps2/_cmp_eq0001 ) + ); + defparam \vga/vgacore/vcnt_Eqn_1_SW0 .INIT = 8'hC8; + LUT3 \vga/vgacore/vcnt_Eqn_1_SW0 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [3]), + .I2(\vga/vgacore/vcnt [0]), + .O(N839) + ); + defparam \vga/vgacore/vcnt_Eqn_1 .INIT = 16'h22A2; + LUT4 \vga/vgacore/vcnt_Eqn_1 ( + .I0(\vga/vgacore/vcnt [1]), + .I1(\vga/vgacore/vcnt [9]), + .I2(\vga/vgacore/N51 ), + .I3(N839), + .O(\vga/vgacore/vcnt_Eqn_1_45 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>101 .INIT = 8'hBD; + LUT3 \vga/scancode_convert/scancode_rom/data<1>101 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/N28 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1308 .INIT = 16'h24FF; + LUT4 \vga/scancode_convert/scancode_rom/data<2>1308 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1121 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1329 .INIT = 16'hCF8F; + LUT4 \vga/scancode_convert/scancode_rom/data<2>1329 ( + .I0(\vga/scancode_convert/scancode_rom/data<2>1_map1110 ), + .I1(\vga/scancode_convert/scancode_rom/data<2>1_map1121 ), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1124 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1458 .INIT = 16'hE444; + LUT4 \vga/scancode_convert/scancode_rom/data<2>1458 ( + .I0(\vga/scancode_convert/sc [6]), + .I1(\vga/scancode_convert/scancode_rom/data<2>1_map1098 ), + .I2(\vga/scancode_convert/scancode_rom/data<2>1_map1124 ), + .I3(\vga/scancode_convert/scancode_rom/data<2>1_map1144 ), + .O(\vga/scancode_convert/rom_data [2]) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>241 .INIT = 4'h9; + LUT2 \vga/scancode_convert/scancode_rom/data<0>241 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/N18 ) + ); + defparam \vga/vgacore/hcnt_Eqn_91 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_91 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [9]), + .O(\vga/vgacore/hcnt_Eqn_9 ) + ); + defparam \vga/vgacore/hcnt_Eqn_81 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_81 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [8]), + .O(\vga/vgacore/hcnt_Eqn_8 ) + ); + defparam \vga/vgacore/hcnt_Eqn_71 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_71 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [7]), + .O(\vga/vgacore/hcnt_Eqn_7 ) + ); + defparam \vga/vgacore/hcnt_Eqn_61 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_61 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [6]), + .O(\vga/vgacore/hcnt_Eqn_6 ) + ); + defparam \vga/vgacore/hcnt_Eqn_51 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_51 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [5]), + .O(\vga/vgacore/hcnt_Eqn_5 ) + ); + defparam \vga/vgacore/hcnt_Eqn_41 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_41 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [4]), + .O(\vga/vgacore/hcnt_Eqn_4 ) + ); + defparam \vga/vgacore/hcnt_Eqn_31 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_31 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [3]), + .O(\vga/vgacore/hcnt_Eqn_3 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>81 .INIT = 8'hF7; + LUT3 \vga/scancode_convert/scancode_rom/data<3>81 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/raise ), + .I2(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/N43 ) + ); + defparam \vga/vgacore/hcnt_Eqn_21 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_21 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [2]), + .O(\vga/vgacore/hcnt_Eqn_2 ) + ); + defparam \vga/vgacore/hcnt_Eqn_11 .INIT = 4'h8; + LUT2 \vga/vgacore/hcnt_Eqn_11 ( + .I0(\vga/vgacore/hcnt_Eqn_bis_0 ), + .I1(\vga/vgacore/hcnt [1]), + .O(\vga/vgacore/hcnt_Eqn_1 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>327 .INIT = 16'h4048; + LUT4 \vga/scancode_convert/scancode_rom/data<5>327 ( + .I0(\vga/scancode_convert/sc_0_1_93 ), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc_1_1_91 ), + .I3(\vga/scancode_convert/raise1_92 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1245 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>341 .INIT = 8'hAE; + LUT3 \vga/scancode_convert/scancode_rom/data<5>341 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc_1_1_91 ), + .I2(\vga/scancode_convert/sc_0_1_93 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1249 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>374 .INIT = 16'h1FBF; + LUT4 \vga/scancode_convert/scancode_rom/data<5>374 ( + .I0(\vga/scancode_convert/sc_1_1_91 ), + .I1(N3276), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc_0_1_93 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1260 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3193 .INIT = 16'hF3F2; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3193 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/raise ), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1276 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3282 .INIT = 16'hFF8C; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3282 ( + .I0(\vga/scancode_convert/scancode_rom/data<5>3_map1291 ), + .I1(\vga/scancode_convert/scancode_rom/data<5>3_map1276 ), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [2]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1295 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3483 .INIT = 16'hCF8F; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3483 ( + .I0(\vga/scancode_convert/scancode_rom/data<5>3_map1314 ), + .I1(\vga/scancode_convert/scancode_rom/data<5>3_map1337 ), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1340 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3614 .INIT = 16'h3365; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3614 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/raise ), + .I3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1363 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3746 .INIT = 16'h9454; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3746 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1394 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>14 .INIT = 16'h8000; + LUT4 \vga/scancode_convert/scancode_rom/data<0>14 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1423 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>119 .INIT = 16'hFF60; + LUT4 \vga/scancode_convert/scancode_rom/data<0>119 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1429 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>144 .INIT = 16'h2232; + LUT4 \vga/scancode_convert/scancode_rom/data<0>144 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1438 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1158 .INIT = 16'hFF27; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1158 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1461 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1206 .INIT = 16'h0626; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1206 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1475 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1492 .INIT = 16'hCF8F; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1492 ( + .I0(\vga/scancode_convert/scancode_rom/data<0>1_map1517 ), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1526 ), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/sc [3]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1529 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>281 .INIT = 16'h0602; + LUT4 \vga/scancode_convert/scancode_rom/data<1>281 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1701 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2109 .INIT = 16'h8808; + LUT4 \vga/scancode_convert/scancode_rom/data<1>2109 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1708 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2147 .INIT = 16'hF3F2; + LUT4 \vga/scancode_convert/scancode_rom/data<1>2147 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1717 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2184 .INIT = 16'h2C0C; + LUT4 \vga/scancode_convert/scancode_rom/data<1>2184 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [1]), + .I3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1729 ) + ); + defparam \vga/scancode_convert/raise1 .INIT = 8'hFE; + LUT3 \vga/scancode_convert/raise1 ( + .I0(\vga/scancode_convert/ctrl_57 ), + .I1(\vga/scancode_convert/shift_49 ), + .I2(\vga/scancode_convert/capslock_48 ), + .O(\vga/scancode_convert/raise ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1141 .INIT = 16'h20B9; + LUT4 \vga/scancode_convert/scancode_rom/data<6>1141 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [0]), + .I2(N3272), + .I3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1820 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1305 .INIT = 16'h09FF; + LUT4 \vga/scancode_convert/scancode_rom/data<6>1305 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [1]), + .I3(\vga/scancode_convert/sc [2]), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1850 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1360 .INIT = 8'hD5; + LUT3 \vga/scancode_convert/scancode_rom/data<6>1360 ( + .I0(\vga/scancode_convert/sc [6]), + .I1(\vga/scancode_convert/scancode_rom/data<6>1_map1860 ), + .I2(\vga/scancode_convert/scancode_rom/data<6>1_map1850 ), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1863 ) + ); + BUFGP clka_BUFGP ( + .I(clka), + .O(clka_BUFGP_4) + ); + IBUF reset_n_IBUF ( + .I(reset_n), + .O(reset_n_IBUF_0) + ); + IBUF ps2_clk_IBUF ( + .I(ps2_clk), + .O(ps2_clk_IBUF_1) + ); + IBUF ps2_data_IBUF ( + .I(ps2_data), + .O(ps2_data_IBUF_2) + ); + OBUF vga_hsync_n_OBUF ( + .I(vga_hsync_n_OBUF_3), + .O(vga_hsync_n) + ); + OBUF fpga_din_d0_OBUF ( + .I(\vga/scancode_convert/ascii [6]), + .O(fpga_din_d0) + ); + OBUF vga_red0_OBUF ( + .I(pixel[8]), + .O(vga_red0) + ); + OBUF vga_red1_OBUF ( + .I(pixel[8]), + .O(vga_red1) + ); + OBUF vga_red2_OBUF ( + .I(pixel[8]), + .O(vga_red2) + ); + OBUF vga_green0_OBUF ( + .I(pixel[8]), + .O(vga_green0) + ); + OBUF vga_green1_OBUF ( + .I(pixel[8]), + .O(vga_green1) + ); + OBUF vga_green2_OBUF ( + .I(pixel[8]), + .O(vga_green2) + ); + OBUF vga_blue0_OBUF ( + .I(pixel[8]), + .O(vga_blue0) + ); + OBUF vga_blue1_OBUF ( + .I(pixel[8]), + .O(vga_blue1) + ); + OBUF vga_blue2_OBUF ( + .I(pixel[8]), + .O(vga_blue2) + ); + OBUF vga_vsync_n_OBUF ( + .I(vga_vsync_n_OBUF_5), + .O(vga_vsync_n) + ); + OBUF fpga_d1_OBUF ( + .I(\vga/ps2/rdy_r_8 ), + .O(fpga_d1) + ); + OBUF fpga_d2_OBUF ( + .I(\vga/scancode_convert/ascii [5]), + .O(fpga_d2) + ); + OBUF fpga_d3_OBUF ( + .I(\vga/scancode_convert/ascii [4]), + .O(fpga_d3) + ); + OBUF fpga_d4_OBUF ( + .I(\vga/scancode_convert/ascii [3]), + .O(fpga_d4) + ); + OBUF fpga_d5_OBUF ( + .I(\vga/scancode_convert/ascii [2]), + .O(fpga_d5) + ); + OBUF fpga_d6_OBUF ( + .I(\vga/scancode_convert/ascii [1]), + .O(fpga_d6) + ); + OBUF fpga_d7_OBUF ( + .I(\vga/scancode_convert/ascii [0]), + .O(fpga_d7) + ); + FDCE \vga/ps2/sc_r_0 ( + .D(\vga/ps2/sc_r [1]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [0]) + ); + FDCE \vga/ps2/sc_r_1 ( + .D(\vga/ps2/sc_r [2]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [1]) + ); + FDCE \vga/ps2/sc_r_2 ( + .D(\vga/ps2/sc_r [3]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [2]) + ); + FDCE \vga/ps2/sc_r_3 ( + .D(\vga/ps2/sc_r [4]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [3]) + ); + FDCE \vga/ps2/sc_r_4 ( + .D(\vga/ps2/sc_r [5]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [4]) + ); + FDCE \vga/ps2/sc_r_5 ( + .D(\vga/ps2/sc_r [6]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [5]) + ); + FDCE \vga/ps2/sc_r_6 ( + .D(\vga/ps2/sc_r [7]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [6]) + ); + FDCE \vga/ps2/sc_r_7 ( + .D(\vga/ps2/sc_r [8]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [7]) + ); + FDCE \vga/ps2/sc_r_8 ( + .D(\vga/ps2/sc_r [9]), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [8]) + ); + FDCE \vga/ps2/sc_r_9 ( + .D(ps2_data_IBUF_2), + .CE(\vga/ps2/ps2_clk_fall_edge ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(gray_cnt_FFd1_9), + .Q(\vga/ps2/sc_r [9]) + ); + defparam \vga/crt/cursor_v_1_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_v_1_rt ( + .I0(\vga/crt/cursor_v [1]), + .O(\vga/crt/cursor_v_1_rt_64 ) + ); + defparam \vga/crt/cursor_v_2_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_v_2_rt ( + .I0(\vga/crt/cursor_v [2]), + .O(\vga/crt/cursor_v_2_rt_65 ) + ); + defparam \vga/crt/cursor_v_3_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_v_3_rt ( + .I0(\vga/crt/cursor_v [3]), + .O(\vga/crt/cursor_v_3_rt_66 ) + ); + defparam \vga/crt/cursor_v_4_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_v_4_rt ( + .I0(\vga/crt/cursor_v [4]), + .O(\vga/crt/cursor_v_4_rt_67 ) + ); + defparam \vga/crt/cursor_h_1_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_h_1_rt ( + .I0(\vga/crt/cursor_h [1]), + .O(\vga/crt/cursor_h_1_rt_68 ) + ); + defparam \vga/crt/cursor_h_2_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_h_2_rt ( + .I0(\vga/crt/cursor_h [2]), + .O(\vga/crt/cursor_h_2_rt_69 ) + ); + defparam \vga/crt/cursor_h_3_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_h_3_rt ( + .I0(\vga/crt/cursor_h [3]), + .O(\vga/crt/cursor_h_3_rt_70 ) + ); + defparam \vga/crt/cursor_h_4_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_h_4_rt ( + .I0(\vga/crt/cursor_h [4]), + .O(\vga/crt/cursor_h_4_rt_71 ) + ); + defparam \vga/crt/cursor_h_5_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_h_5_rt ( + .I0(\vga/crt/cursor_h [5]), + .O(\vga/crt/cursor_h_5_rt_72 ) + ); + defparam \vga/vgacore/hcnt_4_rt .INIT = 4'h2; + LUT1 \vga/vgacore/hcnt_4_rt ( + .I0(\vga/vgacore/hcnt [4]), + .O(\vga/vgacore/hcnt_4_rt_73 ) + ); + defparam \vga/ps2/timer_r_1_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_1_rt ( + .I0(\vga/ps2/timer_r [1]), + .O(\vga/ps2/timer_r_1_rt_74 ) + ); + defparam \vga/ps2/timer_r_2_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_2_rt ( + .I0(\vga/ps2/timer_r [2]), + .O(\vga/ps2/timer_r_2_rt_75 ) + ); + defparam \vga/ps2/timer_r_3_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_3_rt ( + .I0(\vga/ps2/timer_r [3]), + .O(\vga/ps2/timer_r_3_rt_76 ) + ); + defparam \vga/ps2/timer_r_4_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_4_rt ( + .I0(\vga/ps2/timer_r [4]), + .O(\vga/ps2/timer_r_4_rt_77 ) + ); + defparam \vga/ps2/timer_r_5_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_5_rt ( + .I0(\vga/ps2/timer_r [5]), + .O(\vga/ps2/timer_r_5_rt_78 ) + ); + defparam \vga/ps2/timer_r_6_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_6_rt ( + .I0(\vga/ps2/timer_r [6]), + .O(\vga/ps2/timer_r_6_rt_79 ) + ); + defparam \vga/ps2/timer_r_7_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_7_rt ( + .I0(\vga/ps2/timer_r [7]), + .O(\vga/ps2/timer_r_7_rt_80 ) + ); + defparam \vga/ps2/timer_r_8_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_8_rt ( + .I0(\vga/ps2/timer_r [8]), + .O(\vga/ps2/timer_r_8_rt_81 ) + ); + defparam \vga/ps2/timer_r_9_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_9_rt ( + .I0(\vga/ps2/timer_r [9]), + .O(\vga/ps2/timer_r_9_rt_82 ) + ); + defparam \vga/ps2/timer_r_10_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_10_rt ( + .I0(\vga/ps2/timer_r [10]), + .O(\vga/ps2/timer_r_10_rt_83 ) + ); + defparam \vga/ps2/timer_r_11_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_11_rt ( + .I0(\vga/ps2/timer_r [11]), + .O(\vga/ps2/timer_r_11_rt_84 ) + ); + defparam \vga/ps2/timer_r_12_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_12_rt ( + .I0(\vga/ps2/timer_r [12]), + .O(\vga/ps2/timer_r_12_rt_85 ) + ); + defparam \vga/vgacore/vcnt_8_rt .INIT = 4'h2; + LUT1 \vga/vgacore/vcnt_8_rt ( + .I0(\vga/vgacore/vcnt [8]), + .O(\vga/vgacore/vcnt_8_rt_86 ) + ); + defparam \vga/crt/cursor_v_5_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_v_5_rt ( + .I0(\vga/crt/cursor_v [5]), + .O(\vga/crt/cursor_v_5_rt_87 ) + ); + defparam \vga/crt/cursor_v_5_rt1 .INIT = 4'h2; + LUT1 \vga/crt/cursor_v_5_rt1 ( + .I0(\vga/crt/cursor_v [5]), + .O(\vga/crt/cursor_v_5_rt1_88 ) + ); + defparam \vga/crt/cursor_h_6_rt .INIT = 4'h2; + LUT1 \vga/crt/cursor_h_6_rt ( + .I0(\vga/crt/cursor_h [6]), + .O(\vga/crt/cursor_h_6_rt_89 ) + ); + defparam \vga/ps2/timer_r_13_rt .INIT = 4'h2; + LUT1 \vga/ps2/timer_r_13_rt ( + .I0(\vga/ps2/timer_r [13]), + .O(\vga/ps2/timer_r_13_rt_90 ) + ); + defparam \vga/rom_addr_char<2>_f5_65 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<2>_f5_65 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N33 ), + .I2(\vga/N34 ), + .O(N3078) + ); + defparam \vga/rom_addr_char<2>_f5_102 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<2>_f5_102 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N70 ), + .I2(\vga/N71 ), + .O(N3079) + ); + defparam \vga/rom_addr_char<2>_f5_421 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<2>_f5_421 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N78 ), + .I2(\vga/N79 ), + .O(N3080) + ); + defparam \vga/rom_addr_char<2>_f5_821 .INIT = 8'hE4; + LUT3 \vga/rom_addr_char<2>_f5_821 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/N63 ), + .I2(\vga/N64 ), + .O(N3081) + ); + defparam \vga/scancode_convert/_mux0008<6>1 .INIT = 16'h36CC; + LUT4 \vga/scancode_convert/_mux0008<6>1 ( + .I0(\vga/scancode_convert/scancode_rom/data<6>1_map1838 ), + .I1(\vga/scancode_convert/ctrl_57 ), + .I2(\vga/scancode_convert/sc [6]), + .I3(\vga/scancode_convert/scancode_rom/data<6>1_map1863 ), + .O(\vga/scancode_convert/_mux0008 [6]) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW1 .INIT = 16'hCF4F; + LUT4 \vga/scancode_convert/scancode_rom/data<6>1201_SW1 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/scancode_rom/data<6>1_map1808 ), + .I2(\vga/scancode_convert/sc [5]), + .I3(N3271), + .O(N3085) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1536 .INIT = 16'h555D; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1536 ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/sc [2]), + .I2(\vga/scancode_convert/sc [3]), + .I3(N3274), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1534 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1125 .INIT = 16'h4EFF; + LUT4 \vga/scancode_convert/scancode_rom/data<3>1125 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/scancode_rom/data<3>1_map1178 ), + .I2(\vga/scancode_convert/scancode_rom/N7 ), + .I3(\vga/scancode_convert/sc [2]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1185 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3696 .INIT = 16'hF7D5; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3696 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/scancode_rom/data<5>3_map1376 ), + .I3(\vga/scancode_convert/scancode_rom/data<5>3_map1363 ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1381 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1104 .INIT = 16'hFCF8; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1104 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1443 ), + .I2(\vga/scancode_convert/sc [5]), + .I3(\vga/scancode_convert/scancode_rom/data<0>1_map1423 ), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1445 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3895 .INIT = 16'hB111; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3895 ( + .I0(\vga/scancode_convert/sc [6]), + .I1(N3089), + .I2(\vga/scancode_convert/scancode_rom/data<5>3_map1416 ), + .I3(\vga/scancode_convert/scancode_rom/data<5>3_map1381 ), + .O(\vga/scancode_convert/rom_data [5]) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1108 .INIT = 16'hFFAE; + LUT4 \vga/scancode_convert/scancode_rom/data<6>1108 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [2]), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1808 ) + ); + defparam \vga/scancode_convert/_cmp_eq0000_SW0_SW0 .INIT = 4'h7; + LUT2 \vga/scancode_convert/_cmp_eq0000_SW0_SW0 ( + .I0(\vga/ps2/sc_r [7]), + .I1(\vga/ps2/sc_r [5]), + .O(N3100) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>182 .INIT = 16'hB111; + LUT4 \vga/scancode_convert/scancode_rom/data<4>182 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/scancode_rom/N25 ), + .I2(\vga/scancode_convert/scancode_rom/data<4>1_map1556 ), + .I3(\vga/scancode_convert/scancode_rom/data<4>1_map1548 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1560 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>242 .INIT = 16'hFF8B; + LUT4 \vga/scancode_convert/scancode_rom/data<1>242 ( + .I0(\vga/scancode_convert/scancode_rom/data<1>2_map1686 ), + .I1(\vga/scancode_convert/sc [2]), + .I2(\vga/scancode_convert/scancode_rom/N25 ), + .I3(\vga/scancode_convert/sc [5]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1690 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1569 .INIT = 16'h88D8; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1569 ( + .I0(\vga/scancode_convert/sc [6]), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1535 ), + .I2(\vga/scancode_convert/scancode_rom/data<0>1_map1445 ), + .I3(N3104), + .O(\vga/scancode_convert/rom_data [0]) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2497 .INIT = 16'h88D8; + LUT4 \vga/scancode_convert/scancode_rom/data<1>2497 ( + .I0(\vga/scancode_convert/sc [6]), + .I1(\vga/scancode_convert/scancode_rom/data<1>2_map1780 ), + .I2(\vga/scancode_convert/scancode_rom/data<1>2_map1690 ), + .I3(N3106), + .O(\vga/scancode_convert/rom_data [1]) + ); + defparam \vga/vgacore/vcnt_Eqn_bis_021_SW0 .INIT = 16'hFFFE; + LUT4 \vga/vgacore/vcnt_Eqn_bis_021_SW0 ( + .I0(\vga/vgacore/vcnt [7]), + .I1(\vga/vgacore/vcnt [6]), + .I2(\vga/vgacore/vcnt [5]), + .I3(\vga/vgacore/vcnt [4]), + .O(N3108) + ); + defparam \vga/vgacore/vcnt_Eqn_bis_021 .INIT = 16'h555D; + LUT4 \vga/vgacore/vcnt_Eqn_bis_021 ( + .I0(\vga/vgacore/vcnt [9]), + .I1(N3270), + .I2(\vga/vgacore/vcnt [8]), + .I3(N3108), + .O(\vga/vgacore/vcnt_Eqn_bis_0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1620 .INIT = 16'hEF45; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1620 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/scancode_rom/data<4>1_map1633 ), + .I2(N3110), + .I3(\vga/scancode_convert/scancode_rom/data<4>1_map1666 ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1669 ) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<3>1382 ( + .I0(N3116), + .I1(N3117), + .S(\vga/scancode_convert/sc [6]), + .O(\vga/scancode_convert/rom_data [3]) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1382_F .INIT = 16'hE444; + LUT4 \vga/scancode_convert/scancode_rom/data<3>1382_F ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<3>1_map1158 ), + .I2(\vga/scancode_convert/scancode_rom/data<3>1_map1171 ), + .I3(\vga/scancode_convert/scancode_rom/data<3>1_map1185 ), + .O(N3116) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1382_G .INIT = 16'hC888; + LUT4 \vga/scancode_convert/scancode_rom/data<3>1382_G ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<3>1_map1229 ), + .I2(\vga/scancode_convert/scancode_rom/data<3>1_map1201 ), + .I3(\vga/scancode_convert/scancode_rom/data<3>1_map1221 ), + .O(N3117) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<4>1437 ( + .I0(N3118), + .I1(N3119), + .S(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1633 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1437_F .INIT = 16'h8000; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1437_F ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [1]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3118) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1437_G .INIT = 16'h8220; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1437_G ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [1]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3119) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<4>1673 ( + .I0(N3120), + .I1(N3121), + .S(\vga/scancode_convert/sc [6]), + .O(\vga/scancode_convert/rom_data [4]) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1673_F .INIT = 16'hE444; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1673_F ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<4>1_map1560 ), + .I2(\vga/scancode_convert/scancode_rom/data<4>1_map1565 ), + .I3(\vga/scancode_convert/scancode_rom/data<4>1_map1609 ), + .O(N3120) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1673_G .INIT = 8'hC8; + LUT3 \vga/scancode_convert/scancode_rom/data<4>1673_G ( + .I0(\vga/scancode_convert/scancode_rom/data<4>1_map1669 ), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1534 ), + .I2(\vga/scancode_convert/sc [5]), + .O(N3121) + ); + defparam \vga/ps2/error_x13 .INIT = 16'hFF7E; + LUT4 \vga/ps2/error_x13 ( + .I0(\vga/ps2/bitcnt_r [0]), + .I1(\vga/ps2/bitcnt_r [3]), + .I2(\vga/ps2/bitcnt_r [1]), + .I3(\vga/ps2/bitcnt_r [2]), + .O(\vga/ps2/error_x_map855 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>186_SW0 .INIT = 16'h02C8; + LUT4 \vga/scancode_convert/scancode_rom/data<6>186_SW0 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [1]), + .O(N3124) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>186 .INIT = 16'hFF8B; + LUT4 \vga/scancode_convert/scancode_rom/data<6>186 ( + .I0(N3124), + .I1(\vga/scancode_convert/sc [2]), + .I2(N3269), + .I3(\vga/scancode_convert/sc [5]), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1803 ) + ); + defparam \vga/scancode_convert/_not00121 .INIT = 8'hEA; + LUT3 \vga/scancode_convert/_not00121 ( + .I0(\vga/scancode_convert/state_FFd3_56 ), + .I1(\vga/scancode_convert/_cmp_eq0005 ), + .I2(\vga/scancode_convert/state_FFd1_53 ), + .O(\vga/scancode_convert/_not0012 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1333_SW0 .INIT = 8'h4E; + LUT3 \vga/scancode_convert/scancode_rom/data<6>1333_SW0 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [0]), + .O(N3130) + ); + defparam \vga/vgacore/_and000015_SW0 .INIT = 4'h1; + LUT2 \vga/vgacore/_and000015_SW0 ( + .I0(\vga/vgacore/hcnt [6]), + .I1(\vga/vgacore/hcnt [5]), + .O(N3132) + ); + defparam \vga/vgacore/_and000015 .INIT = 16'h4404; + LUT4 \vga/vgacore/_and000015 ( + .I0(\vga/vgacore/hcnt [8]), + .I1(\vga/vgacore/hcnt [7]), + .I2(N3132), + .I3(\vga/vgacore/_and0000_map807 ), + .O(\vga/vgacore/_and0000_map811 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW1 .INIT = 16'hDDB1; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3852_SW1 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/raise ), + .I3(\vga/scancode_convert/sc [4]), + .O(N3136) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852 .INIT = 16'h1113; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3852 ( + .I0(N3087), + .I1(\vga/scancode_convert/sc [5]), + .I2(\vga/scancode_convert/sc [3]), + .I3(N3136), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1416 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1180_SW0 .INIT = 16'hE437; + LUT4 \vga/scancode_convert/scancode_rom/data<2>1180_SW0 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [2]), + .O(N3141) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1180_SW1 .INIT = 16'hDE87; + LUT4 \vga/scancode_convert/scancode_rom/data<2>1180_SW1 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3142) + ); + defparam \vga/crt/state_FFd3-In48 .INIT = 8'hAE; + LUT3 \vga/crt/state_FFd3-In48 ( + .I0(N3144), + .I1(\vga/crt/state_FFd3-In_map800 ), + .I2(\vga/crt/state_FFd3_42 ), + .O(\vga/crt/state_FFd3-In ) + ); + defparam \vga/vgacore/_and000074 .INIT = 16'h4440; + LUT4 \vga/vgacore/_and000074 ( + .I0(\vga/vgacore/hcnt [10]), + .I1(\vga/vgacore/hcnt [9]), + .I2(\vga/vgacore/_and0000_map811 ), + .I3(\vga/vgacore/_and0000_map825 ), + .O(\vga/vgacore/_and0000 ) + ); + defparam \vga/rom_addr_char<1>6_SW0 .INIT = 16'hC22F; + LUT4 \vga/rom_addr_char<1>6_SW0 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/rom_addr_char_1_1_95 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(N3146) + ); + defparam \vga/rom_addr_char<1>6 .INIT = 4'h1; + LUT2 \vga/rom_addr_char<1>6 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(N3146), + .O(\vga/N612 ) + ); + defparam \vga/rom_addr_char<1>43 .INIT = 16'h2CC9; + LUT4 \vga/rom_addr_char<1>43 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/N312345 ) + ); + defparam \vga/rom_addr_char<1>104_SW0 .INIT = 8'hC4; + LUT3 \vga/rom_addr_char<1>104_SW0 ( + .I0(\vga/rom_addr_char_0_1_94 ), + .I1(\vga/rom_addr_char [1]), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .O(N3148) + ); + defparam \vga/rom_addr_char<1>104 .INIT = 16'h4602; + LUT4 \vga/rom_addr_char<1>104 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(N3148), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N1012345 ) + ); + defparam \vga/charload8_SW0 .INIT = 16'h4602; + LUT4 \vga/charload8_SW0 ( + .I0(\vga/rom_addr_char [6]), + .I1(\vga/rom_addr_char [5]), + .I2(N3150), + .I3(\vga/rom_addr_char<4>11234 ), + .O(N562) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<7> .INIT = 8'h96; + LUT3 \vga/Madd_ram_addr_video_Madd_lut<7> ( + .I0(\vga/Madd_ram_addr_videoC2 ), + .I1(\vga/vgacore/vcnt [4]), + .I2(\vga/vgacore/vcnt [6]), + .O(\vga/N230 ) + ); + defparam \vga/Madd_ram_addr_video_Madd_lut<10> .INIT = 8'h6C; + LUT3 \vga/Madd_ram_addr_video_Madd_lut<10> ( + .I0(\vga/vgacore/vcnt [6]), + .I1(\vga/vgacore/vcnt [7]), + .I2(\vga/vgacore/vcnt [8]), + .O(\vga/N233 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<7> .INIT = 8'h96; + LUT3 \vga/crt/Madd_ram_addr_Madd_lut<7> ( + .I0(\vga/crt/Madd_ram_addrC2 ), + .I1(\vga/crt/cursor_v [1]), + .I2(\vga/crt/cursor_v [3]), + .O(\vga/crt/N9 ) + ); + defparam \vga/crt/Madd_ram_addr_Madd_lut<10> .INIT = 8'h6C; + LUT3 \vga/crt/Madd_ram_addr_Madd_lut<10> ( + .I0(\vga/crt/cursor_v [3]), + .I1(\vga/crt/cursor_v [4]), + .I2(\vga/crt/cursor_v [5]), + .O(\vga/crt/N12 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1123 .INIT = 16'hAAAE; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1123 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [1]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1449 ) + ); + defparam \vga/ps2/scancode_rdy1 .INIT = 8'h80; + LUT3 \vga/ps2/scancode_rdy1 ( + .I0(\vga/ps2/_cmp_eq0000 ), + .I1(\vga/ps2/_cmp_eq0001 ), + .I2(\vga/ps2/ps2_clk_r [1]), + .O(\vga/ps2/scancode_rdy ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1118 .INIT = 16'hAAAE; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1118 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1565 ) + ); + defparam \vga/scancode_convert/shift_set14 .INIT = 8'h08; + LUT3 \vga/scancode_convert/shift_set14 ( + .I0(\vga/scancode_convert/state_FFd5_54 ), + .I1(\vga/ps2/rdy_r_8 ), + .I2(\vga/scancode_convert/release_prefix_59 ), + .O(\vga/scancode_convert/shift_set_map836 ) + ); + defparam \vga/crt/write_delay__mux0000<0>1 .INIT = 16'h0002; + LUT4 \vga/crt/write_delay__mux0000<0>1 ( + .I0(\vga/crt/state_FFd1_40 ), + .I1(\vga/crt/write_delay [0]), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/crt/state_FFd2_41 ), + .O(\vga/crt/write_delay__mux0000 [0]) + ); + defparam \vga/crt/_mux0002<0>1 .INIT = 16'hEC4C; + LUT4 \vga/crt/_mux0002<0>1 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/cursor_h [0]), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/crt_data [0]), + .O(\vga/crt/_mux0002 [0]) + ); + defparam \vga/crt/_mux0002<1>1 .INIT = 16'hEC4C; + LUT4 \vga/crt/_mux0002<1>1 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/cursor_h [1]), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/crt_data [1]), + .O(\vga/crt/_mux0002 [1]) + ); + defparam \vga/crt/_mux0002<2>1 .INIT = 16'hEC4C; + LUT4 \vga/crt/_mux0002<2>1 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/cursor_h [2]), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/crt_data [2]), + .O(\vga/crt/_mux0002 [2]) + ); + defparam \vga/crt/_mux0002<4>1 .INIT = 16'hEC4C; + LUT4 \vga/crt/_mux0002<4>1 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/cursor_h [4]), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/crt_data [4]), + .O(\vga/crt/_mux0002 [4]) + ); + defparam \vga/crt/_mux0002<3>1 .INIT = 16'hEC4C; + LUT4 \vga/crt/_mux0002<3>1 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/cursor_h [3]), + .I2(\vga/crt/state_FFd3_42 ), + .I3(\vga/crt_data [3]), + .O(\vga/crt/_mux0002 [3]) + ); + defparam \vga/crt/_mux0002<5>1 .INIT = 16'hB313; + LUT4 \vga/crt/_mux0002<5>1 ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt/cursor_h [5]), + .I2(\vga/crt/state_FFd2_41 ), + .I3(\vga/crt_data [5]), + .O(\vga/crt/_mux0002 [5]) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1469 .INIT = 16'h5557; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1469 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [0]), + .I3(N3273), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1526 ) + ); + defparam \vga/scancode_convert/ctrl_set_SW1 .INIT = 8'hF7; + LUT3 \vga/scancode_convert/ctrl_set_SW1 ( + .I0(\vga/scancode_convert/state_FFd5_54 ), + .I1(\vga/ps2/rdy_r_8 ), + .I2(\vga/scancode_convert/release_prefix_59 ), + .O(N3158) + ); + defparam \vga/scancode_convert/ctrl_set .INIT = 16'h0020; + LUT4 \vga/scancode_convert/ctrl_set ( + .I0(\vga/ps2/sc_r [2]), + .I1(\vga/ps2/sc_r [1]), + .I2(\vga/scancode_convert/N10 ), + .I3(N3158), + .O(\vga/scancode_convert/ctrl_set_58 ) + ); + defparam \vga/crt/cursor_h_Eqn_01 .INIT = 4'h1; + LUT2 \vga/crt/cursor_h_Eqn_01 ( + .I0(\vga/crt/_and0000_38 ), + .I1(\vga/crt/cursor_h [0]), + .O(\vga/crt/cursor_h_Eqn_0 ) + ); + defparam \vga/crt/cursor_v_Eqn_01 .INIT = 4'h1; + LUT2 \vga/crt/cursor_v_Eqn_01 ( + .I0(\vga/crt/_and0001_39 ), + .I1(\vga/crt/cursor_v [0]), + .O(\vga/crt/cursor_v_Eqn_0 ) + ); + defparam \vga/scancode_convert/state_FFd4-In34 .INIT = 16'hFFEA; + LUT4 \vga/scancode_convert/state_FFd4-In34 ( + .I0(\vga/scancode_convert/state_FFd2_52 ), + .I1(\vga/scancode_convert/_and0000 ), + .I2(\vga/scancode_convert/state_FFd4-In_map845 ), + .I3(\vga/scancode_convert/state_FFd3_56 ), + .O(\vga/scancode_convert/state_FFd4-In ) + ); + defparam \vga/scancode_convert/_not00101 .INIT = 16'hEAAA; + LUT4 \vga/scancode_convert/_not00101 ( + .I0(\vga/scancode_convert/state_FFd4_50 ), + .I1(N3275), + .I2(\vga/ps2/rdy_r_8 ), + .I3(\vga/scancode_convert/state_FFd5_54 ), + .O(\vga/scancode_convert/_not0010 ) + ); + defparam \vga/scancode_convert/release_prefix_set1 .INIT = 8'h80; + LUT3 \vga/scancode_convert/release_prefix_set1 ( + .I0(\vga/scancode_convert/_cmp_eq0000_51 ), + .I1(\vga/ps2/rdy_r_8 ), + .I2(\vga/scancode_convert/state_FFd5_54 ), + .O(\vga/scancode_convert/release_prefix_set ) + ); + defparam \vga/ps2/timer_x<0>1 .INIT = 4'h1; + LUT2 \vga/ps2/timer_x<0>1 ( + .I0(\vga/ps2/ps2_clk_edge ), + .I1(\vga/ps2/timer_r [0]), + .O(\vga/ps2/timer_x [0]) + ); + defparam \vga/pclk__mux0000<0>1 .INIT = 16'hDDFD; + LUT4 \vga/pclk__mux0000<0>1 ( + .I0(\vga/pclk [0]), + .I1(\vga/vgacore/hblank_12 ), + .I2(\vga/crt/N91 ), + .I3(\vga/crt/state_FFd1_40 ), + .O(\vga/pclk__mux0000 [0]) + ); + defparam \vga/rom_addr_char<1>121_SW0 .INIT = 16'hBFF9; + LUT4 \vga/rom_addr_char<1>121_SW0 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(N3160) + ); + defparam \vga/rom_addr_char<1>121 .INIT = 4'h1; + LUT2 \vga/rom_addr_char<1>121 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(N3160), + .O(\vga/N1212 ) + ); + defparam \vga/rom_addr_char<2>15_SW0 .INIT = 16'hA877; + LUT4 \vga/rom_addr_char<2>15_SW0 ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/vgacore/vcnt_0_1_96 ), + .I2(\vga/rom_addr_char_1_1_95 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(N3162) + ); + defparam \vga/rom_addr_char<2>15 .INIT = 8'h08; + LUT3 \vga/rom_addr_char<2>15 ( + .I0(\vga/rom_addr_char [2]), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(N3162), + .O(\vga/rom_addr_char<2>2 ) + ); + defparam \vga/rom_addr_char<2>2_SW0 .INIT = 16'hFDBD; + LUT4 \vga/rom_addr_char<2>2_SW0 ( + .I0(\vga/rom_addr_char_1_1_95 ), + .I1(\vga/vgacore/vcnt_0_1_96 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(N3164) + ); + defparam \vga/rom_addr_char<1>114_SW0 .INIT = 16'hE878; + LUT4 \vga/rom_addr_char<1>114_SW0 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/rom_addr_char [1]), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(N3166) + ); + defparam \vga/rom_addr_char<1>114 .INIT = 4'h4; + LUT2 \vga/rom_addr_char<1>114 ( + .I0(N3166), + .I1(\vga/rom_addr_char_0_1_94 ), + .O(\vga/N11123456 ) + ); + defparam \vga/rom_addr_char<1>113_SW0 .INIT = 8'hC8; + LUT3 \vga/rom_addr_char<1>113_SW0 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .O(N3170) + ); + defparam \vga/rom_addr_char<1>113 .INIT = 16'h5410; + LUT4 \vga/rom_addr_char<1>113 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/rom_addr_char [1]), + .I2(N3170), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/N111123 ) + ); + defparam \vga/rom_addr_char<1>152_SW0 .INIT = 8'h1B; + LUT3 \vga/rom_addr_char<1>152_SW0 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/rom_addr_char_0_1_94 ), + .O(N3172) + ); + defparam \vga/rom_addr_char<1>152 .INIT = 16'h040E; + LUT4 \vga/rom_addr_char<1>152 ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(N3172), + .O(\vga/N15123 ) + ); + defparam \vga/write_ctrl .INIT = 8'h14; + LUT3 \vga/write_ctrl ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/state_FFd1_40 ), + .I2(\vga/crt/state_FFd3_42 ), + .O(\vga/N226 ) + ); + defparam \vga/rom_addr_char<1>111 .INIT = 16'h5D08; + LUT4 \vga/rom_addr_char<1>111 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/N167 ), + .O(\vga/N11112 ) + ); + defparam \vga/rom_addr_char<1>151 .INIT = 16'h88D8; + LUT4 \vga/rom_addr_char<1>151 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N175 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N1512 ) + ); + defparam \vga/rom_addr_char<1>103 .INIT = 16'h5D08; + LUT4 \vga/rom_addr_char<1>103 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/vgacore/vcnt_1_1_97 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/N121 ), + .O(\vga/N9123 ) + ); + defparam \vga/rom_addr_char<1>143 .INIT = 16'h88D8; + LUT4 \vga/rom_addr_char<1>143 ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/N78 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(\vga/N131234 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW0 .INIT = 8'h89; + LUT3 \vga/scancode_convert/scancode_rom/data<4>1308_SW0 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [3]), + .O(N3174) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308 .INIT = 16'h1FBF; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1308 ( + .I0(\vga/scancode_convert/raise ), + .I1(N3174), + .I2(\vga/scancode_convert/sc [2]), + .I3(N3175), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1609 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW2 .INIT = 16'h90D0; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1370_SW2 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [1]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3178) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370 .INIT = 16'hFFD8; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1370 ( + .I0(\vga/scancode_convert/scancode_rom/N12 ), + .I1(N3178), + .I2(N3177), + .I3(\vga/scancode_convert/sc [2]), + .O(\vga/scancode_convert/scancode_rom/data<0>1_map1503 ) + ); + defparam \vga/ps2/error_x24 .INIT = 16'hFF8C; + LUT4 \vga/ps2/error_x24 ( + .I0(\vga/ps2/error_x_map855 ), + .I1(\vga/ps2/_cmp_eq0001 ), + .I2(\vga/ps2/ps2_clk_r [1]), + .I3(\vga/ps2/error_r_47 ), + .O(\vga/ps2/error_x ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>126 .INIT = 16'h0602; + LUT4 \vga/scancode_convert/scancode_rom/data<3>126 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [2]), + .I2(N3180), + .I3(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1158 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1354 .INIT = 16'h88A8; + LUT4 \vga/scancode_convert/scancode_rom/data<2>1354 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1129 ) + ); + defparam \vga/crt/_not00101 .INIT = 16'h9888; + LUT4 \vga/crt/_not00101 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/state_FFd3_42 ), + .I2(\vga/crt/eol_35 ), + .I3(\vga/crt/state_FFd1_40 ), + .O(\vga/crt/_not0010 ) + ); + defparam \vga/crt/Mrom_set_newline1 .INIT = 16'h0020; + LUT4 \vga/crt/Mrom_set_newline1 ( + .I0(\vga/crt/eol_35 ), + .I1(\vga/crt/state_FFd3_42 ), + .I2(\vga/crt/state_FFd1_40 ), + .I3(\vga/crt/state_FFd2_41 ), + .O(\vga/crt/N3 ) + ); + defparam \vga/pclk__mux0000<2>_SW0 .INIT = 16'hFF13; + LUT4 \vga/pclk__mux0000<2>_SW0 ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt/state_FFd1_40 ), + .I2(\vga/crt/state_FFd2_41 ), + .I3(\vga/vgacore/hblank_12 ), + .O(N89) + ); + defparam \vga/crt/state_Out92 .INIT = 8'h15; + LUT3 \vga/crt/state_Out92 ( + .I0(\vga/crt/state_FFd1_40 ), + .I1(\vga/crt/state_FFd2_41 ), + .I2(\vga/crt/state_FFd3_42 ), + .O(\vga/clearing ) + ); + FDE \vga/scancode_convert/sc_1_1 ( + .D(\vga/ps2/sc_r [1]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc_1_1_91 ) + ); + FDE \vga/scancode_convert/sc_0_1 ( + .D(\vga/ps2/sc_r [0]), + .CE(\vga/scancode_convert/_and0000 ), + .C(gray_cnt_FFd1_9), + .Q(\vga/scancode_convert/sc_0_1_93 ) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<1>2260_SW0 ( + .I0(N3184), + .I1(N3185), + .S(\vga/scancode_convert/sc [2]), + .O(N3106) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2260_SW0_F .INIT = 8'h04; + LUT3 \vga/scancode_convert/scancode_rom/data<1>2260_SW0_F ( + .I0(\vga/scancode_convert/scancode_rom/data<1>2_map1701 ), + .I1(\vga/scancode_convert/sc [5]), + .I2(\vga/scancode_convert/scancode_rom/data<1>2_map1708 ), + .O(N3184) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2260_SW0_G .INIT = 16'h22A2; + LUT4 \vga/scancode_convert/scancode_rom/data<1>2260_SW0_G ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<1>2_map1717 ), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/scancode_rom/data<1>2_map1729 ), + .O(N3185) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<1>2416 ( + .I0(N3186), + .I1(N3187), + .S(\vga/scancode_convert/sc [0]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1774 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2416_F .INIT = 16'h15FF; + LUT4 \vga/scancode_convert/scancode_rom/data<1>2416_F ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [2]), + .O(N3186) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2416_G .INIT = 16'h55D5; + LUT4 \vga/scancode_convert/scancode_rom/data<1>2416_G ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/scancode_rom/N9 ), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [3]), + .O(N3187) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<0>1291_SW0 ( + .I0(N3188), + .I1(N3189), + .S(\vga/scancode_convert/sc [2]), + .O(N3104) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1291_SW0_F .INIT = 16'hA222; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1291_SW0_F ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1449 ), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/scancode_rom/N7 ), + .O(N3188) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1291_SW0_G .INIT = 16'h22A2; + LUT4 \vga/scancode_convert/scancode_rom/data<0>1291_SW0_G ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1461 ), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/scancode_rom/data<0>1_map1475 ), + .O(N3189) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<3>1299 ( + .I0(N3190), + .I1(N3191), + .S(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1221 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1299_F .INIT = 16'h2FFF; + LUT4 \vga/scancode_convert/scancode_rom/data<3>1299_F ( + .I0(\vga/scancode_convert/scancode_rom/N9 ), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [2]), + .O(N3190) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1299_G .INIT = 16'h4F5F; + LUT4 \vga/scancode_convert/scancode_rom/data<3>1299_G ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/sc [3]), + .O(N3191) + ); + MUXF5 \vga/charload1_SW0 ( + .I0(N3192), + .I1(N3193), + .S(\vga/rom_addr_char [6]), + .O(N560) + ); + defparam \vga/charload1_SW0_F .INIT = 16'hE040; + LUT4 \vga/charload1_SW0_F ( + .I0(\vga/rom_addr_char [4]), + .I1(\vga/rom_addr_char<3>_f6_19 ), + .I2(\vga/rom_addr_char [5]), + .I3(\vga/rom_addr_char<3>_f61_22 ), + .O(N3192) + ); + defparam \vga/charload1_SW0_G .INIT = 8'hE4; + LUT3 \vga/charload1_SW0_G ( + .I0(\vga/rom_addr_char [5]), + .I1(\vga/rom_addr_char<4>11_26 ), + .I2(\vga/rom_addr_char<4>_f5_28 ), + .O(N3193) + ); + MUXF5 \vga/rom_addr_char<1>1641 ( + .I0(N3194), + .I1(N3195), + .S(\vga/vgacore/vcnt_1_1_97 ), + .O(\vga/rom_addr_char<1>112_32 ) + ); + defparam \vga/rom_addr_char<1>1641_F .INIT = 8'hB9; + LUT3 \vga/rom_addr_char<1>1641_F ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_2_1_98 ), + .O(N3194) + ); + defparam \vga/rom_addr_char<1>1641_G .INIT = 16'h0999; + LUT4 \vga/rom_addr_char<1>1641_G ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_2_1_98 ), + .O(N3195) + ); + MUXF5 \vga/rom_addr_char<1>1741 ( + .I0(N3196), + .I1(N3197), + .S(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/rom_addr_char<1>2_33 ) + ); + defparam \vga/rom_addr_char<1>1741_F .INIT = 16'hFFAE; + LUT4 \vga/rom_addr_char<1>1741_F ( + .I0(\vga/vgacore/vcnt_1_1_97 ), + .I1(\vga/rom_addr_char [1]), + .I2(\vga/rom_addr_char_0_1_94 ), + .I3(\vga/vgacore/vcnt_0_1_96 ), + .O(N3196) + ); + defparam \vga/rom_addr_char<1>1741_G .INIT = 16'h06FF; + LUT4 \vga/rom_addr_char<1>1741_G ( + .I0(\vga/rom_addr_char [1]), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/vgacore/vcnt_0_1_96 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(N3197) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<6>1201_SW0 ( + .I0(N3198), + .I1(N3199), + .S(\vga/scancode_convert/sc [3]), + .O(N3084) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW0_F .INIT = 16'h3F2F; + LUT4 \vga/scancode_convert/scancode_rom/data<6>1201_SW0_F ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [2]), + .I2(\vga/scancode_convert/sc [5]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3198) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1201_SW0_G .INIT = 16'hF7D5; + LUT4 \vga/scancode_convert/scancode_rom/data<6>1201_SW0_G ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/sc [2]), + .I2(\vga/scancode_convert/scancode_rom/data<6>1_map1831 ), + .I3(\vga/scancode_convert/sc [1]), + .O(N3199) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<2>1207 ( + .I0(N3200), + .I1(N3201), + .S(\vga/scancode_convert/sc [5]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1098 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1207_F .INIT = 8'hC4; + LUT3 \vga/scancode_convert/scancode_rom/data<2>1207_F ( + .I0(\vga/scancode_convert/scancode_rom/N28 ), + .I1(\vga/scancode_convert/scancode_rom/data<2>1_map1056 ), + .I2(\vga/scancode_convert/sc [4]), + .O(N3200) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1207_G .INIT = 8'h1B; + LUT3 \vga/scancode_convert/scancode_rom/data<2>1207_G ( + .I0(\vga/scancode_convert/sc [4]), + .I1(N3141), + .I2(N3142), + .O(N3201) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<4>1588 ( + .I0(N3202), + .I1(N3203), + .S(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1666 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1588_F .INIT = 16'h0F16; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1588_F ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [1]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3202) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1588_G .INIT = 16'h00C6; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1588_G ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [1]), + .O(N3203) + ); + MUXF5 \vga/ps2/bitcnt_x<3> ( + .I0(N3204), + .I1(N3205), + .S(\vga/ps2/ps2_clk_fall_edge ), + .O(\vga/ps2/bitcnt_x [3]) + ); + defparam \vga/ps2/bitcnt_x<3>_F .INIT = 16'h0222; + LUT4 \vga/ps2/bitcnt_x<3>_F ( + .I0(\vga/ps2/bitcnt_r [3]), + .I1(\vga/ps2/error_r_47 ), + .I2(\vga/ps2/ps2_clk_r [1]), + .I3(\vga/ps2/_cmp_eq0001 ), + .O(N3204) + ); + defparam \vga/ps2/bitcnt_x<3>_G .INIT = 16'h6AAA; + LUT4 \vga/ps2/bitcnt_x<3>_G ( + .I0(\vga/ps2/bitcnt_r [3]), + .I1(\vga/ps2/bitcnt_r [2]), + .I2(\vga/ps2/bitcnt_r [1]), + .I3(\vga/ps2/bitcnt_r [0]), + .O(N3205) + ); + MUXF5 \vga/ps2/bitcnt_x<2>1 ( + .I0(N3206), + .I1(N3207), + .S(\vga/ps2/ps2_clk_fall_edge ), + .O(\vga/ps2/bitcnt_x [2]) + ); + defparam \vga/ps2/bitcnt_x<2>1_F .INIT = 16'h0222; + LUT4 \vga/ps2/bitcnt_x<2>1_F ( + .I0(\vga/ps2/bitcnt_r [2]), + .I1(\vga/ps2/error_r_47 ), + .I2(\vga/ps2/ps2_clk_r [1]), + .I3(\vga/ps2/_cmp_eq0001 ), + .O(N3206) + ); + defparam \vga/ps2/bitcnt_x<2>1_G .INIT = 8'h6C; + LUT3 \vga/ps2/bitcnt_x<2>1_G ( + .I0(\vga/ps2/bitcnt_r [1]), + .I1(\vga/ps2/bitcnt_r [2]), + .I2(\vga/ps2/bitcnt_r [0]), + .O(N3207) + ); + MUXF5 \vga/crt/state_FFd3-In48_SW0 ( + .I0(N3208), + .I1(N3209), + .S(\vga/crt/state_FFd2_41 ), + .O(N3144) + ); + defparam \vga/crt/state_FFd3-In48_SW0_F .INIT = 16'h0020; + LUT4 \vga/crt/state_FFd3-In48_SW0_F ( + .I0(\vga/crt/state_FFd3_42 ), + .I1(\vga/crt/newline_37 ), + .I2(\vga/crt/state_FFd1_40 ), + .I3(\vga/crt/_cmp_eq0001 ), + .O(N3208) + ); + defparam \vga/crt/state_FFd3-In48_SW0_G .INIT = 8'hFD; + LUT3 \vga/crt/state_FFd3-In48_SW0_G ( + .I0(\vga/scancode_convert/strobe_out_14 ), + .I1(\vga/scancode_convert/key_up_16 ), + .I2(\vga/crt/state_FFd1_40 ), + .O(N3209) + ); + MUXF5 \vga/charload217 ( + .I0(N3210), + .I1(N3211), + .S(\vga/rom_addr_char [3]), + .O(\vga/charload2_map865 ) + ); + defparam \vga/charload217_F .INIT = 16'h0020; + LUT4 \vga/charload217_F ( + .I0(\vga/vgacore/vcnt_2_1_98 ), + .I1(\vga/rom_addr_char [4]), + .I2(\vga/rom_addr_char [2]), + .I3(N3164), + .O(N3210) + ); + defparam \vga/charload217_G .INIT = 16'h0020; + LUT4 \vga/charload217_G ( + .I0(\vga/N4 ), + .I1(\vga/rom_addr_char [4]), + .I2(\vga/rom_addr_char [1]), + .I3(\vga/rom_addr_char [2]), + .O(N3211) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<5>3159_SW0 ( + .I0(N3212), + .I1(N3213), + .S(\vga/scancode_convert/sc [2]), + .O(N3112) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3159_SW0_F .INIT = 8'hF7; + LUT3 \vga/scancode_convert/scancode_rom/data<5>3159_SW0_F ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/scancode_rom/N12 ), + .O(N3212) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3159_SW0_G .INIT = 16'h47CF; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3159_SW0_G ( + .I0(\vga/scancode_convert/scancode_rom/data<5>3_map1249 ), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/scancode_rom/data<5>3_map1245 ), + .I3(\vga/scancode_convert/scancode_rom/data<5>3_map1260 ), + .O(N3213) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<5>3450 ( + .I0(N3214), + .I1(N3215), + .S(\vga/scancode_convert/raise ), + .O(\vga/scancode_convert/scancode_rom/data<5>3_map1337 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3450_F .INIT = 8'h7F; + LUT3 \vga/scancode_convert/scancode_rom/data<5>3450_F ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc_0_1_93 ), + .O(N3214) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3450_G .INIT = 16'h62FF; + LUT4 \vga/scancode_convert/scancode_rom/data<5>3450_G ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc_0_1_93 ), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [3]), + .O(N3215) + ); + BUFG gray_cnt_FFd1_BUFG ( + .I(gray_cnt_FFd11), + .O(gray_cnt_FFd1_9) + ); + BUFG \vga/crtclk_BUFG ( + .I(\vga/crtclk1 ), + .O(\vga/crtclk_15 ) + ); + INV \vga/crt/Mcount_cursor_v_lut<0>_INV_0 ( + .I(\vga/crt/cursor_v [0]), + .O(\vga/crt/Result [0]) + ); + INV \vga/crt/Mcount_cursor_h_lut<0>_INV_0 ( + .I(\vga/crt/cursor_h [0]), + .O(\vga/crt/Result<0>1 ) + ); + INV \vga/vgacore/Mcompar__cmp_lt0000_lut<4>_INV_0 ( + .I(\vga/vgacore/hcnt [10]), + .O(\vga/vgacore/N7 ) + ); + INV \vga/vgacore/Mcompar__cmp_lt0000_cy<4>_inv_INV_0 ( + .I(\vga/vgacore/Mcompar__cmp_lt0000_cy [4]), + .O(\vga/vgacore/hcnt_Eqn_bis_0 ) + ); + INV \vga/ps2/Madd__addsub0000_lut<0>_INV_0 ( + .I(\vga/ps2/timer_r [0]), + .O(\vga/ps2/N5 ) + ); + INV vga_hsync_n1_INV_0 ( + .I(\vga/vgacore/hsync_7 ), + .O(vga_hsync_n_OBUF_3) + ); + INV vga_vsync_n1_INV_0 ( + .I(\vga/vgacore/vsync_6 ), + .O(vga_vsync_n_OBUF_5) + ); + INV gray_cnt_Rst_inv1_INV_0 ( + .I(reset_n_IBUF_0), + .O(gray_cnt_Rst_inv) + ); + INV \vga/charclk1_INV_0 ( + .I(\vga/pclk [2]), + .O(\vga/charclk ) + ); + INV \vga/_not00011_INV_0 ( + .I(\vga/crtclk_15 ), + .O(\vga/_not0001 ) + ); + INV \gray_cnt_FFd2-In1_INV_0 ( + .I(gray_cnt_FFd1_9), + .O(\gray_cnt_FFd2-In ) + ); + INV \vga/scancode_convert/_not00081_INV_0 ( + .I(\vga/scancode_convert/capslock_48 ), + .O(\vga/scancode_convert/_not0008 ) + ); + INV \vga/pixel_hold<7>_inv1_INV_0 ( + .I(\vga/pixel_hold [7]), + .O(\vga/pixel_hold<7>_inv ) + ); + FD \vga/rom_addr_char_0_1 ( + .D(\vga/ram_data_out [0]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char_0_1_94 ) + ); + FD \vga/rom_addr_char_1_1 ( + .D(\vga/ram_data_out [1]), + .C(\vga/charclk ), + .Q(\vga/rom_addr_char_1_1_95 ) + ); + FDC_1 \vga/vgacore/vcnt_0_1 ( + .D(N3216), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt_0_1_96 ) + ); + defparam \vga/vgacore/Mcount_vcnt_lut<0>_1 .INIT = 4'h4; + LUT2 \vga/vgacore/Mcount_vcnt_lut<0>_1 ( + .I0(\vga/vgacore/vcnt [0]), + .I1(\vga/vgacore/vcnt_Eqn_bis_0 ), + .O(N3216) + ); + FDC_1 \vga/vgacore/vcnt_1_1 ( + .D(\vga/vgacore/Result<1>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt_1_1_97 ) + ); + FDC_1 \vga/vgacore/vcnt_2_1 ( + .D(\vga/vgacore/Result<2>1 ), + .CLR(gray_cnt_Rst_inv1_INV_0_1_99), + .C(\vga/vgacore/hblank_12 ), + .Q(\vga/vgacore/vcnt_2_1_98 ) + ); + INV gray_cnt_Rst_inv1_INV_0_1 ( + .I(reset_n_IBUF_0), + .O(gray_cnt_Rst_inv1_INV_0_1_99) + ); + defparam \vga/ram_addr_mux<4>1 .INIT = 16'h14BE; + LUT4 \vga/ram_addr_mux<4>1 ( + .I0(\vga/ram_we_n ), + .I1(\vga/crt/cursor_h [4]), + .I2(\vga/crt/cursor_v [0]), + .I3(\vga/vgacore/hcnt [7]), + .O(N3219) + ); + defparam \vga/ram_addr_mux<4>2 .INIT = 16'hBE14; + LUT4 \vga/ram_addr_mux<4>2 ( + .I0(\vga/ram_we_n ), + .I1(\vga/crt/cursor_v [0]), + .I2(\vga/crt/cursor_h [4]), + .I3(\vga/vgacore/hcnt [7]), + .O(N3220) + ); + MUXF5 \vga/ram_addr_mux<4>_f5 ( + .I0(N3220), + .I1(N3219), + .S(\vga/vgacore/vcnt [3]), + .O(\vga/ram_addr_mux [4]) + ); + defparam \vga/pixel<8>191 .INIT = 8'hD5; + LUT3 \vga/pixel<8>191 ( + .I0(\vga/vgacore/N51 ), + .I1(\vga/vgacore/vcnt_2_1_98 ), + .I2(\vga/vgacore/vcnt [3]), + .O(N3221) + ); + MUXF5 \vga/pixel<8>19_f5 ( + .I0(N3222), + .I1(N3221), + .S(\vga/vgacore/vcnt [9]), + .O(\vga/pixel<8>_map785 ) + ); + defparam \vga/ps2/bitcnt_x<0>11 .INIT = 16'h4446; + LUT4 \vga/ps2/bitcnt_x<0>11 ( + .I0(\vga/ps2/bitcnt_r [0]), + .I1(\vga/ps2/ps2_clk_fall_edge ), + .I2(\vga/ps2/ps2_clk_r [1]), + .I3(\vga/ps2/error_r_47 ), + .O(N3224) + ); + defparam \vga/ps2/bitcnt_x<0>12 .INIT = 8'h46; + LUT3 \vga/ps2/bitcnt_x<0>12 ( + .I0(\vga/ps2/bitcnt_r [0]), + .I1(\vga/ps2/ps2_clk_fall_edge ), + .I2(\vga/ps2/error_r_47 ), + .O(N3225) + ); + MUXF5 \vga/ps2/bitcnt_x<0>1_f5 ( + .I0(N3225), + .I1(N3224), + .S(\vga/ps2/_cmp_eq0001 ), + .O(\vga/ps2/bitcnt_x [0]) + ); + defparam \vga/crt/state_FFd2-In1 .INIT = 8'hF7; + LUT3 \vga/crt/state_FFd2-In1 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/insert_crt_data ), + .I2(\vga/crt/state_FFd1_40 ), + .O(N3226) + ); + defparam \vga/crt/state_FFd2-In2 .INIT = 16'hC888; + LUT4 \vga/crt/state_FFd2-In2 ( + .I0(\vga/crt/state_FFd1_40 ), + .I1(\vga/crt/state_FFd2_41 ), + .I2(\vga/crt/scroll_36 ), + .I3(\vga/crt/eol_35 ), + .O(N3227) + ); + MUXF5 \vga/crt/state_FFd2-In_f5 ( + .I0(N3227), + .I1(N3226), + .S(\vga/crt/state_FFd3_42 ), + .O(\vga/crt/state_FFd2-In ) + ); + defparam \vga/charload2371 .INIT = 4'h8; + LUT2 \vga/charload2371 ( + .I0(\vga/charload_13 ), + .I1(\vga/cursor_match ), + .O(N3228) + ); + defparam \vga/charload2372 .INIT = 16'hC888; + LUT4 \vga/charload2372 ( + .I0(\vga/cursor_match ), + .I1(\vga/charload_13 ), + .I2(\vga/charload2_map865 ), + .I3(\vga/rom_addr_char [5]), + .O(N3229) + ); + MUXF5 \vga/charload237_f5 ( + .I0(N3229), + .I1(N3228), + .S(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [7]) + ); + defparam \vga/ps2/bitcnt_x<1>11 .INIT = 4'h6; + LUT2 \vga/ps2/bitcnt_x<1>11 ( + .I0(\vga/ps2/bitcnt_r [1]), + .I1(\vga/ps2/bitcnt_r [0]), + .O(N3230) + ); + defparam \vga/ps2/bitcnt_x<1>12 .INIT = 16'h0222; + LUT4 \vga/ps2/bitcnt_x<1>12 ( + .I0(\vga/ps2/bitcnt_r [1]), + .I1(\vga/ps2/error_r_47 ), + .I2(\vga/ps2/ps2_clk_r [1]), + .I3(\vga/ps2/_cmp_eq0001 ), + .O(N3231) + ); + MUXF5 \vga/ps2/bitcnt_x<1>1_f5 ( + .I0(N3231), + .I1(N3230), + .S(\vga/ps2/ps2_clk_fall_edge ), + .O(\vga/ps2/bitcnt_x [1]) + ); + defparam \vga/charload3541 .INIT = 16'hAAEA; + LUT4 \vga/charload3541 ( + .I0(\vga/cursor_match ), + .I1(\vga/charload3_map953 ), + .I2(\vga/rom_addr_char [5]), + .I3(\vga/rom_addr_char [6]), + .O(N3233) + ); + MUXF5 \vga/charload354_f5 ( + .I0(\vga/pixel_hold [0]), + .I1(N3233), + .S(\vga/charload_13 ), + .O(\vga/_mux0002 [6]) + ); + defparam \vga/charload5581 .INIT = 16'hFAD8; + LUT4 \vga/charload5581 ( + .I0(\vga/charload_13 ), + .I1(\vga/rom_addr_char<5>_f51_31 ), + .I2(\vga/pixel_hold [2]), + .I3(\vga/cursor_match ), + .O(N3234) + ); + defparam \vga/charload5582 .INIT = 16'hFAD8; + LUT4 \vga/charload5582 ( + .I0(\vga/charload_13 ), + .I1(\vga/charload5_map965 ), + .I2(\vga/pixel_hold [2]), + .I3(\vga/cursor_match ), + .O(N3235) + ); + MUXF5 \vga/charload558_f5 ( + .I0(N3235), + .I1(N3234), + .S(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [4]) + ); + defparam \vga/charload4581 .INIT = 16'hFAD8; + LUT4 \vga/charload4581 ( + .I0(\vga/charload_13 ), + .I1(\vga/rom_addr_char<5>_f5_30 ), + .I2(\vga/pixel_hold [4]), + .I3(\vga/cursor_match ), + .O(N3236) + ); + defparam \vga/charload4582 .INIT = 16'hFAD8; + LUT4 \vga/charload4582 ( + .I0(\vga/charload_13 ), + .I1(\vga/charload4_map979 ), + .I2(\vga/pixel_hold [4]), + .I3(\vga/cursor_match ), + .O(N3237) + ); + MUXF5 \vga/charload458_f5 ( + .I0(N3237), + .I1(N3236), + .S(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [2]) + ); + defparam \vga/charload7581 .INIT = 16'hFAD8; + LUT4 \vga/charload7581 ( + .I0(\vga/charload_13 ), + .I1(\vga/rom_addr_char<5>_f5123 ), + .I2(\vga/pixel_hold [5]), + .I3(\vga/cursor_match ), + .O(N3238) + ); + defparam \vga/charload7582 .INIT = 16'hFAD8; + LUT4 \vga/charload7582 ( + .I0(\vga/charload_13 ), + .I1(\vga/charload7_map993 ), + .I2(\vga/pixel_hold [5]), + .I3(\vga/cursor_match ), + .O(N3239) + ); + MUXF5 \vga/charload758_f5 ( + .I0(N3239), + .I1(N3238), + .S(\vga/rom_addr_char [6]), + .O(\vga/_mux0002 [1]) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1111 .INIT = 16'h2000; + LUT4 \vga/scancode_convert/scancode_rom/data<2>1111 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [2]), + .O(N3242) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1112 .INIT = 4'h8; + LUT2 \vga/scancode_convert/scancode_rom/data<2>1112 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [2]), + .O(N3243) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<2>111_f5 ( + .I0(N3243), + .I1(N3242), + .S(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<2>1_map1056 ) + ); + defparam \vga/vgacore/vblank21 .INIT = 16'h0001; + LUT4 \vga/vgacore/vblank21 ( + .I0(\vga/vgacore/vcnt [7]), + .I1(\vga/vgacore/vcnt [4]), + .I2(\vga/vgacore/vcnt [6]), + .I3(\vga/vgacore/vcnt [5]), + .O(N3244) + ); + MUXF5 \vga/vgacore/vblank2_f5 ( + .I0(N3244), + .I1(N2), + .S(\vga/vgacore/vcnt [8]), + .O(\vga/vgacore/N51 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>13521 .INIT = 16'h0020; + LUT4 \vga/scancode_convert/scancode_rom/data<3>13521 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/sc [3]), + .O(N3245) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<3>1352_f5 ( + .I0(N3), + .I1(N3245), + .S(\vga/scancode_convert/sc [5]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1229 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1221 .INIT = 16'hFF27; + LUT4 \vga/scancode_convert/scancode_rom/data<4>1221 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/scancode_rom/N12 ), + .I3(\vga/scancode_convert/sc [3]), + .O(N3248) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<4>122_f5 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(N3248), + .S(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<4>1_map1548 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>23191 .INIT = 16'hAAAE; + LUT4 \vga/scancode_convert/scancode_rom/data<1>23191 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3249) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>23192 .INIT = 16'hFF62; + LUT4 \vga/scancode_convert/scancode_rom/data<1>23192 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [2]), + .O(N3250) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<1>2319_f5 ( + .I0(N3250), + .I1(N3249), + .S(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<1>2_map1751 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1410_SW01 .INIT = 8'hFE; + LUT3 \vga/scancode_convert/scancode_rom/data<2>1410_SW01 ( + .I0(\vga/scancode_convert/scancode_rom/N12 ), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [0]), + .O(N3254) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1410_SW02 .INIT = 8'hFD; + LUT3 \vga/scancode_convert/scancode_rom/data<2>1410_SW02 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [3]), + .O(N3255) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<2>1410_SW0_f5 ( + .I0(N3255), + .I1(N3254), + .S(\vga/scancode_convert/sc [4]), + .O(N3126) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1721 .INIT = 16'hFFD8; + LUT4 \vga/scancode_convert/scancode_rom/data<3>1721 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [2]), + .O(N3256) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>1722 .INIT = 16'hAAAE; + LUT4 \vga/scancode_convert/scancode_rom/data<3>1722 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/sc [0]), + .O(N3257) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<3>172_f5 ( + .I0(N3257), + .I1(N3256), + .S(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1171 ) + ); + defparam \vga/charload8_SW0_SW01 .INIT = 16'h7FFF; + LUT4 \vga/charload8_SW0_SW01 ( + .I0(\vga/rom_addr_char [2]), + .I1(\vga/rom_addr_char [3]), + .I2(\vga/rom_addr_char_1_1_95 ), + .I3(\vga/N224 ), + .O(N3259) + ); + MUXF5 \vga/charload8_SW0_SW0_f5 ( + .I0(N3), + .I1(N3259), + .S(\vga/rom_addr_char [4]), + .O(N3150) + ); + defparam \vga/rom_addr_char<1>_mmx_out11 .INIT = 16'h15FF; + LUT4 \vga/rom_addr_char<1>_mmx_out11 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/rom_addr_char_0_1_94 ), + .I2(\vga/rom_addr_char_1_1_95 ), + .I3(\vga/vgacore/vcnt_1_1_97 ), + .O(N3261) + ); + defparam \vga/rom_addr_char<1>_mmx_out12 .INIT = 16'hFBFF; + LUT4 \vga/rom_addr_char<1>_mmx_out12 ( + .I0(\vga/vgacore/vcnt_0_1_96 ), + .I1(\vga/rom_addr_char_1_1_95 ), + .I2(\vga/vgacore/vcnt_1_1_97 ), + .I3(\vga/rom_addr_char_0_1_94 ), + .O(N3262) + ); + MUXF5 \vga/rom_addr_char<1>_mmx_out1_f5 ( + .I0(N3262), + .I1(N3261), + .S(\vga/vgacore/vcnt_2_1_98 ), + .O(\vga/rom_addr_char<1>_mmx_out ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>12171 .INIT = 8'hEA; + LUT3 \vga/scancode_convert/scancode_rom/data<3>12171 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [3]), + .O(N3264) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>12172 .INIT = 8'hFE; + LUT3 \vga/scancode_convert/scancode_rom/data<3>12172 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .O(N3265) + ); + MUXF5 \vga/scancode_convert/scancode_rom/data<3>1217_f5 ( + .I0(N3265), + .I1(N3264), + .S(\vga/scancode_convert/sc [4]), + .O(\vga/scancode_convert/scancode_rom/data<3>1_map1201 ) + ); + defparam \vga/scancode_convert/state_FFd2-In_SW0 .INIT = 16'hFF60; + LUT4_L \vga/scancode_convert/state_FFd2-In_SW0 ( + .I0(\vga/ps2/sc_r [2]), + .I1(\vga/ps2/sc_r [1]), + .I2(\vga/scancode_convert/N10 ), + .I3(\vga/scancode_convert/release_prefix_59 ), + .LO(N126) + ); + defparam \vga/scancode_convert/state_FFd3-In_SW0 .INIT = 16'h90F0; + LUT4_L \vga/scancode_convert/state_FFd3-In_SW0 ( + .I0(\vga/ps2/sc_r [1]), + .I1(\vga/ps2/sc_r [2]), + .I2(\vga/scancode_convert/release_prefix_59 ), + .I3(\vga/scancode_convert/N10 ), + .LO(N128) + ); + defparam \vga/crt/_and0001 .INIT = 16'h0020; + LUT4_D \vga/crt/_and0001 ( + .I0(\vga/crt/eol_35 ), + .I1(\vga/crt/state_FFd3_42 ), + .I2(\vga/crt/scroll_36 ), + .I3(N235), + .LO(N3266), + .O(\vga/crt/_and0001_39 ) + ); + defparam \vga/scancode_convert/_cmp_eq00041_SW0 .INIT = 8'hFD; + LUT3_L \vga/scancode_convert/_cmp_eq00041_SW0 ( + .I0(\vga/ps2/sc_r [4]), + .I1(\vga/ps2/sc_r [3]), + .I2(\vga/ps2/sc_r [0]), + .LO(N237) + ); + defparam \vga/scancode_convert/shift_set6 .INIT = 8'h08; + LUT3_D \vga/scancode_convert/shift_set6 ( + .I0(\vga/scancode_convert/N10 ), + .I1(\vga/ps2/sc_r [1]), + .I2(\vga/ps2/sc_r [2]), + .LO(N3267), + .O(\vga/scancode_convert/shift_set_map833 ) + ); + defparam \vga/scancode_convert/state_FFd4-In24 .INIT = 16'hFF60; + LUT4_L \vga/scancode_convert/state_FFd4-In24 ( + .I0(\vga/ps2/sc_r [1]), + .I1(\vga/ps2/sc_r [2]), + .I2(\vga/scancode_convert/N10 ), + .I3(\vga/scancode_convert/N11 ), + .LO(\vga/scancode_convert/state_FFd4-In_map845 ) + ); + defparam \vga/scancode_convert/_cmp_eq000211 .INIT = 16'h0020; + LUT4_D \vga/scancode_convert/_cmp_eq000211 ( + .I0(\vga/ps2/sc_r [4]), + .I1(\vga/ps2/sc_r [2]), + .I2(\vga/ps2/sc_r [6]), + .I3(\vga/ps2/sc_r [1]), + .LO(N3268), + .O(\vga/scancode_convert/N31 ) + ); + defparam \vga/crt/eol_SW0 .INIT = 16'hFF7F; + LUT4_L \vga/crt/eol_SW0 ( + .I0(\vga/crt/cursor_h [3]), + .I1(\vga/crt/cursor_h [2]), + .I2(\vga/crt/cursor_h [1]), + .I3(\vga/crt/cursor_h [4]), + .LO(N293) + ); + defparam \vga/crt/scroll_SW0 .INIT = 8'hF7; + LUT3_L \vga/crt/scroll_SW0 ( + .I0(\vga/crt/cursor_v [1]), + .I1(\vga/crt/cursor_v [3]), + .I2(\vga/crt/cursor_v [2]), + .LO(N301) + ); + defparam \vga/crt/_and0000_SW0 .INIT = 8'h17; + LUT3_L \vga/crt/_and0000_SW0 ( + .I0(\vga/crt/state_FFd2_41 ), + .I1(\vga/crt/state_FFd1_40 ), + .I2(\vga/crt/eol_35 ), + .LO(N305) + ); + defparam \vga/_and000093 .INIT = 16'h9009; + LUT4_L \vga/_and000093 ( + .I0(\vga/crt/cursor_h [4]), + .I1(\vga/vgacore/hcnt [7]), + .I2(\vga/crt/cursor_h [5]), + .I3(\vga/vgacore/hcnt [8]), + .LO(\vga/_and0000_map902 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>111 .INIT = 8'h7F; + LUT3_D \vga/scancode_convert/scancode_rom/data<1>111 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [1]), + .LO(N3269), + .O(\vga/scancode_convert/scancode_rom/N25 ) + ); + defparam \vga/vgacore/vcnt_Eqn_911 .INIT = 16'h15FF; + LUT4_D \vga/vgacore/vcnt_Eqn_911 ( + .I0(\vga/vgacore/vcnt [2]), + .I1(\vga/vgacore/vcnt [1]), + .I2(\vga/vgacore/vcnt [0]), + .I3(\vga/vgacore/vcnt [3]), + .LO(N3270), + .O(\vga/vgacore/N0 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1264 .INIT = 16'h0141; + LUT4_L \vga/scancode_convert/scancode_rom/data<2>1264 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/raise ), + .LO(\vga/scancode_convert/scancode_rom/data<2>1_map1110 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>199 .INIT = 16'h6040; + LUT4_L \vga/scancode_convert/scancode_rom/data<3>199 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/raise ), + .LO(\vga/scancode_convert/scancode_rom/data<3>1_map1178 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3247 .INIT = 16'h04AE; + LUT4_L \vga/scancode_convert/scancode_rom/data<5>3247 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/raise ), + .LO(\vga/scancode_convert/scancode_rom/data<5>3_map1291 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3359 .INIT = 16'h153B; + LUT4_L \vga/scancode_convert/scancode_rom/data<5>3359 ( + .I0(\vga/scancode_convert/sc [0]), + .I1(\vga/scancode_convert/raise ), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [1]), + .LO(\vga/scancode_convert/scancode_rom/data<5>3_map1314 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3664 .INIT = 16'h1915; + LUT4_L \vga/scancode_convert/scancode_rom/data<5>3664 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [0]), + .I2(\vga/scancode_convert/sc [1]), + .I3(\vga/scancode_convert/raise ), + .LO(\vga/scancode_convert/scancode_rom/data<5>3_map1376 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>176 .INIT = 16'hCF4F; + LUT4_L \vga/scancode_convert/scancode_rom/data<0>176 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1429 ), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/scancode_rom/data<0>1_map1438 ), + .LO(\vga/scancode_convert/scancode_rom/data<0>1_map1443 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1437 .INIT = 16'h5457; + LUT4_L \vga/scancode_convert/scancode_rom/data<0>1437 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/raise ), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [0]), + .LO(\vga/scancode_convert/scancode_rom/data<0>1_map1517 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1539 .INIT = 16'hC888; + LUT4_L \vga/scancode_convert/scancode_rom/data<0>1539 ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1534 ), + .I2(\vga/scancode_convert/scancode_rom/data<0>1_map1503 ), + .I3(\vga/scancode_convert/scancode_rom/data<0>1_map1529 ), + .LO(\vga/scancode_convert/scancode_rom/data<0>1_map1535 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>145 .INIT = 16'h1FBF; + LUT4_L \vga/scancode_convert/scancode_rom/data<4>145 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/scancode_rom/N43 ), + .I2(\vga/scancode_convert/sc [3]), + .I3(\vga/scancode_convert/scancode_rom/N18 ), + .LO(\vga/scancode_convert/scancode_rom/data<4>1_map1556 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>218 .INIT = 16'h082A; + LUT4_L \vga/scancode_convert/scancode_rom/data<1>218 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/scancode_rom/N18 ), + .I3(\vga/scancode_convert/scancode_rom/N28 ), + .LO(\vga/scancode_convert/scancode_rom/data<1>2_map1686 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<1>2465 .INIT = 16'hC888; + LUT4_L \vga/scancode_convert/scancode_rom/data<1>2465 ( + .I0(\vga/scancode_convert/sc [5]), + .I1(\vga/scancode_convert/scancode_rom/data<0>1_map1534 ), + .I2(\vga/scancode_convert/scancode_rom/data<1>2_map1751 ), + .I3(\vga/scancode_convert/scancode_rom/data<1>2_map1774 ), + .LO(\vga/scancode_convert/scancode_rom/data<1>2_map1780 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1181 .INIT = 16'h15FF; + LUT4_D \vga/scancode_convert/scancode_rom/data<6>1181 ( + .I0(\vga/scancode_convert/sc [1]), + .I1(\vga/scancode_convert/sc [4]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [3]), + .LO(N3271), + .O(\vga/scancode_convert/scancode_rom/data<6>1_map1831 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>152 .INIT = 16'hFFEF; + LUT4_D \vga/scancode_convert/scancode_rom/data<0>152 ( + .I0(\vga/scancode_convert/shift_49 ), + .I1(\vga/scancode_convert/ctrl_57 ), + .I2(\vga/scancode_convert/sc_1_1_91 ), + .I3(\vga/scancode_convert/capslock_48 ), + .LO(N3272), + .O(\vga/scancode_convert/scancode_rom/N12 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1247 .INIT = 16'hE040; + LUT4_L \vga/scancode_convert/scancode_rom/data<6>1247 ( + .I0(\vga/scancode_convert/scancode_rom/data<6>1_map1820 ), + .I1(N3084), + .I2(\vga/scancode_convert/scancode_rom/data<6>1_map1803 ), + .I3(N3085), + .LO(\vga/scancode_convert/scancode_rom/data<6>1_map1838 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3852_SW0 .INIT = 8'h15; + LUT3_L \vga/scancode_convert/scancode_rom/data<5>3852_SW0 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/scancode_rom/data<5>3_map1394 ), + .LO(N3087) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1110 .INIT = 16'h3332; + LUT4_D \vga/scancode_convert/scancode_rom/data<0>1110 ( + .I0(\vga/scancode_convert/ctrl_57 ), + .I1(\vga/scancode_convert/sc_1_1_91 ), + .I2(\vga/scancode_convert/shift_49 ), + .I3(\vga/scancode_convert/capslock_48 ), + .LO(N3273), + .O(\vga/scancode_convert/scancode_rom/N9 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>31 .INIT = 8'hF7; + LUT3_D \vga/scancode_convert/scancode_rom/data<0>31 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .LO(N3274), + .O(\vga/scancode_convert/scancode_rom/N7 ) + ); + defparam \vga/scancode_convert/_cmp_eq0000 .INIT = 16'h0002; + LUT4_D \vga/scancode_convert/_cmp_eq0000 ( + .I0(\vga/scancode_convert/N31 ), + .I1(\vga/ps2/sc_r [3]), + .I2(\vga/ps2/sc_r [0]), + .I3(N3100), + .LO(N3275), + .O(\vga/scancode_convert/_cmp_eq0000_51 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<5>3895_SW0 .INIT = 16'h74FC; + LUT4_L \vga/scancode_convert/scancode_rom/data<5>3895_SW0 ( + .I0(\vga/scancode_convert/scancode_rom/data<5>3_map1340 ), + .I1(\vga/scancode_convert/sc [5]), + .I2(N3112), + .I3(\vga/scancode_convert/scancode_rom/data<5>3_map1295 ), + .LO(N3089) + ); + defparam \vga/scancode_convert/scancode_rom/data<2>1410 .INIT = 16'h5551; + LUT4_L \vga/scancode_convert/scancode_rom/data<2>1410 ( + .I0(\vga/scancode_convert/sc [5]), + .I1(N3126), + .I2(\vga/scancode_convert/sc [2]), + .I3(\vga/scancode_convert/scancode_rom/data<2>1_map1129 ), + .LO(\vga/scancode_convert/scancode_rom/data<2>1_map1144 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<6>1333 .INIT = 16'h2232; + LUT4_L \vga/scancode_convert/scancode_rom/data<6>1333 ( + .I0(\vga/scancode_convert/sc [2]), + .I1(\vga/scancode_convert/sc [5]), + .I2(\vga/scancode_convert/sc [1]), + .I3(N3130), + .LO(\vga/scancode_convert/scancode_rom/data<6>1_map1860 ) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1392_SW0 .INIT = 16'hFBFF; + LUT4_L \vga/scancode_convert/scancode_rom/data<4>1392_SW0 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/scancode_rom/N9 ), + .I2(\vga/scancode_convert/sc [4]), + .I3(\vga/scancode_convert/sc [0]), + .LO(N3110) + ); + defparam \vga/scancode_convert/scancode_rom/data<4>1308_SW1 .INIT = 16'hFD93; + LUT4_L \vga/scancode_convert/scancode_rom/data<4>1308_SW1 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [1]), + .LO(N3175) + ); + defparam \vga/scancode_convert/scancode_rom/data<0>1370_SW1 .INIT = 16'h9F02; + LUT4_L \vga/scancode_convert/scancode_rom/data<0>1370_SW1 ( + .I0(\vga/scancode_convert/sc [4]), + .I1(\vga/scancode_convert/sc [3]), + .I2(\vga/scancode_convert/sc [0]), + .I3(\vga/scancode_convert/sc [1]), + .LO(N3177) + ); + defparam \vga/scancode_convert/scancode_rom/data<3>126_SW1 .INIT = 8'hF7; + LUT3_L \vga/scancode_convert/scancode_rom/data<3>126_SW1 ( + .I0(\vga/scancode_convert/sc [3]), + .I1(\vga/scancode_convert/sc [1]), + .I2(\vga/scancode_convert/sc [0]), + .LO(N3180) + ); + defparam \vga/scancode_convert/raise1_1 .INIT = 8'hFE; + LUT3_D \vga/scancode_convert/raise1_1 ( + .I0(\vga/scancode_convert/ctrl_57 ), + .I1(\vga/scancode_convert/shift_49 ), + .I2(\vga/scancode_convert/capslock_48 ), + .LO(N3276), + .O(\vga/scancode_convert/raise1_92 ) + ); + INV \vga/pixel<8>192_INV_0 ( + .I(\vga/vgacore/N61 ), + .O(N3222) + ); +endmodule + + +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + + wire GSR; + wire GTS; + wire PRLD; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (weak1, weak0) GSR = GSR_int; + assign (weak1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule + diff --git a/xilinx/vga/netgen/synthesis/go.sh b/xilinx/vga/netgen/synthesis/go.sh new file mode 100755 index 0000000..3387c90 --- /dev/null +++ b/xilinx/vga/netgen/synthesis/go.sh @@ -0,0 +1,9 @@ +#!/bin/sh + +B=/wide/opt/Xilinx/verilog/src/unisims +C=/wide/opt/Xilinx/verilog/src/uni9000 + +#cver +iverilog $B/LUT*.v $B/VCC.v $B/GND.v $B/INV.* $B/IBUF.v $B/OBUF.v $B/MUXCY.v $B/FDCE.v $B/FDE.v $B/MUXF5.v $B/FDP.v $B/FDR.v $B/FDC.v $B/FD.v $B/RAMB4_S1_S1.v $B/MULT_AND.v $B/XORCY.v $B/FDC_1.v $B/BUFGP.v $B/BUFG.v $B/MUXF6.v fpga_synthesis.v + + diff --git a/xilinx/vga/netgen/synthesis/verilog.log b/xilinx/vga/netgen/synthesis/verilog.log new file mode 100644 index 0000000..a4f4676 --- /dev/null +++ b/xilinx/vga/netgen/synthesis/verilog.log @@ -0,0 +1,64 @@ +GPLCVER_2.10a of 10/12/04 (Linux-elf). +Copyright (c) 1991-2004 Pragmatic C Software Corp. + All Rights reserved. Licensed under the GNU General Public License (GPL). + See the 'COPYING' file for details. NO WARRANTY provided. +Today is Fri Dec 29 17:15:31 2006. +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT1_D.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT1_L.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT1.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT2_D.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT2_L.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT2.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT3_D.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT3_L.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT3.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT4_D.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT4_L.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT4.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT5_D.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT5_L.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT5.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT6_D.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT6_L.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/LUT6.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/VCC.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/GND.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/INV.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/IBUF.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/OBUF.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/MUXCY.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/FDCE.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/FDE.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/MUXF5.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/FDP.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/FDR.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/FDC.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/FD.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v" +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(557) ERROR** [1044] instance/gate "SETUP_ALL" type "localparam" connection list expected - = read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(664) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(665) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(666) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(667) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(668) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(669) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(670) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(671) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(672) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(673) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(674) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(675) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(676) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(677) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(678) ERROR** [1116] expression terminal expected - : read +**/opt/Xilinx/verilog/src/unisims/RAMB4_S1_S1.v(679) ERROR** [1116] expression terminal expected - : read +Compiling source file "/opt/Xilinx/verilog/src/unisims/MULT_AND.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/XORCY.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/FDC_1.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/BUFGP.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/BUFG.v" +Compiling source file "/opt/Xilinx/verilog/src/unisims/MUXF6.v" +Compiling source file "fpga_synthesis.v" + Unable to begin simulation. + There were 17 error(s), 0 warning(s), and 0 inform(s). +End of GPLCVER_2.10a at Fri Dec 29 17:15:31 2006 (elapsed 0.1 seconds). diff --git a/xilinx/vga/vga.ise b/xilinx/vga/vga.ise new file mode 100644 index 0000000..5a79050 Binary files /dev/null and b/xilinx/vga/vga.ise differ diff --git a/xilinx/vga/vga.ise_ISE_Backup b/xilinx/vga/vga.ise_ISE_Backup new file mode 100644 index 0000000..5a79050 Binary files /dev/null and b/xilinx/vga/vga.ise_ISE_Backup differ diff --git a/xilinx/vga/vga.ntrc_log b/xilinx/vga/vga.ntrc_log new file mode 100644 index 0000000..ce9c514 --- /dev/null +++ b/xilinx/vga/vga.ntrc_log @@ -0,0 +1,83 @@ +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- +-------------------- diff --git a/xilinx/vga/xst/work/hdllib.ref b/xilinx/vga/xst/work/hdllib.ref new file mode 100644 index 0000000..16c1b22 --- /dev/null +++ b/xilinx/vga/xst/work/hdllib.ref @@ -0,0 +1,9 @@ +MO video_ram NULL ../../v/video_ram.v vlg6E/video__ram.bin 1167708079 +MO scancode_rom NULL ../../v/scancode_rom.v vlg39/scancode__rom.bin 1167708079 +MO scancode_convert NULL ../../v/scancode.v vlg3C/scancode__convert.bin 1167708079 +MO crt NULL ../../v/crt.v vlg59/crt.bin 1167708079 +MO vga NULL ../../v/vga.v vlg6A/vga.bin 1167708079 +MO char_rom NULL ../../v/char_rom.v vlg13/char__rom.bin 1167708079 +MO fpga NULL ../../v/fpga.v vlg22/fpga.bin 1167708079 +MO ps2 NULL ../../v/ps2.v vlg61/ps2.bin 1167708079 +MO vgacore NULL ../../v/vgacore.v vlg17/vgacore.bin 1167708079 diff --git a/xilinx/vga/xst/work/vlg13/char__rom.bin b/xilinx/vga/xst/work/vlg13/char__rom.bin new file mode 100644 index 0000000..5268e54 Binary files /dev/null and b/xilinx/vga/xst/work/vlg13/char__rom.bin differ diff --git a/xilinx/vga/xst/work/vlg17/vgacore.bin b/xilinx/vga/xst/work/vlg17/vgacore.bin new file mode 100644 index 0000000..b8ab0b0 Binary files /dev/null and b/xilinx/vga/xst/work/vlg17/vgacore.bin differ diff --git a/xilinx/vga/xst/work/vlg22/fpga.bin b/xilinx/vga/xst/work/vlg22/fpga.bin new file mode 100644 index 0000000..b0d5d00 Binary files /dev/null and b/xilinx/vga/xst/work/vlg22/fpga.bin differ diff --git a/xilinx/vga/xst/work/vlg39/scancode__rom.bin b/xilinx/vga/xst/work/vlg39/scancode__rom.bin new file mode 100644 index 0000000..2b063f1 Binary files /dev/null and b/xilinx/vga/xst/work/vlg39/scancode__rom.bin differ diff --git a/xilinx/vga/xst/work/vlg3C/scancode__convert.bin b/xilinx/vga/xst/work/vlg3C/scancode__convert.bin new file mode 100644 index 0000000..229e07c Binary files /dev/null and b/xilinx/vga/xst/work/vlg3C/scancode__convert.bin differ diff --git a/xilinx/vga/xst/work/vlg59/crt.bin b/xilinx/vga/xst/work/vlg59/crt.bin new file mode 100644 index 0000000..993d99f Binary files /dev/null and b/xilinx/vga/xst/work/vlg59/crt.bin differ diff --git a/xilinx/vga/xst/work/vlg61/ps2.bin b/xilinx/vga/xst/work/vlg61/ps2.bin new file mode 100644 index 0000000..cfb3f8e Binary files /dev/null and b/xilinx/vga/xst/work/vlg61/ps2.bin differ diff --git a/xilinx/vga/xst/work/vlg6A/vga.bin b/xilinx/vga/xst/work/vlg6A/vga.bin new file mode 100644 index 0000000..f14dc79 Binary files /dev/null and b/xilinx/vga/xst/work/vlg6A/vga.bin differ diff --git a/xilinx/vga/xst/work/vlg6E/video__ram.bin b/xilinx/vga/xst/work/vlg6E/video__ram.bin new file mode 100644 index 0000000..10e94bd Binary files /dev/null and b/xilinx/vga/xst/work/vlg6E/video__ram.bin differ