Xilinx Design Summary

PDP8 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	493	15,360	3%
Number used as Flip Flops	481
Number used as Latches	12
Number of 4 input LUTs	1,605	15,360	10%
Logic Distribution
Number of occupied Slices	1,120	7,680	14%
Number of Slices containing only related logic	1,120	1,120	100%
Number of Slices containing unrelated logic	0	1,120	0%
Total Number 4 input LUTs	1,964	15,360	12%
Number used as logic	1,605
Number used as a route-thru	167
Number used for 32x1 RAMs	192
Number of bonded IOBs	116	173	67%
IOB Flip Flops	14
Number of GCLKs	3	8	37%
Total equivalent gate count for design	40,343
Additional JTAG gate count for IOBs	5,568

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met