Xilinx Design Summary

PS2 Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	37	4,704	1%
Number of 4 input LUTs	39	4,704	1%
Logic Distribution
Number of occupied Slices	39	2,352	1%
Number of Slices containing only related logic	39	39	100%
Number of Slices containing unrelated logic	0	39	0%
Total Number 4 input LUTs	52	4,704	1%
Number used as logic	39
Number used as a route-thru	13
Number of bonded IOBs	11	176	6%
IOB Flip Flops	2
Number of GCLKs	2	4	50%
Number of GCLKIOBs	1	4	25%
Total equivalent gate count for design	630
Additional JTAG gate count for IOBs	576

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met