89 lines
3.1 KiB
Plaintext
89 lines
3.1 KiB
Plaintext
DEC-8I-H8NA-D KT8/I Time-Sharing Option Functional Description
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DEC-8I-HOCA-D KE8/I Extended Arithmetic Element
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interrupt occurs here
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510 00516 7141 CLL CIA
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511 00517 1155 TAD LASTV
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512 00520 7630 SZL CLA
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513 00521 4526 ERROR /STORAGE FILLED BY PUSHDOWN LIST
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6000 PWS The contents of the AC register are loaded into the SW
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register. This instruction performs no operation if the IM
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flag is 1.
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6001 ION The IE flag is set to 1, enabling interrupts, after a one
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instruction delay.
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6002 IOF The IE flag is set to 0, disabling interrupts.
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6003 PSI Skip if the IE flag is 1. This instruction performs no
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operation if the IM flag is 1.
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6004 PAI The contents of the IB register are loaded into the IF
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register, and the II flag is set to 0, just as if a JMP or
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JMS was executed when the IM flag is 1. This instruction
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performs no operation if the IM flag is 1.
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6005 PAS The contents of the DF register are loaded into bits
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[03..05] of the SF register, and the contents of the IF
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register are loaded into bits [00..02] of the SF register,
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just as they would be loaded on an interrupt. This
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instruction performs no operation of the IM flag is 1.
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6006 PDX The DM flag is set to 1 for the execution of the next
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instruction. This instruction executes normally if IM is 1,
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but since DM is 1 anytime IM is 1, it effectively performs
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no operation.
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6007 PEX The IM flag is set to 1, switching the CPU into normal mode,
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after a one instruction delay. This instruction executes
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notmally if IM is 1, but effectively performs no operation.
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62x1 CDF Bits [06..08] of the instruction are loaded into the DF
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register.
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62x2 CIF Bits [06..08] of the instruction are loaded into the IB
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register, and the II flag is set to 1. The contents of the
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IB register will be loaded into the IF register, and the II
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flag will be set to 0, when the next JMP or JMS instruction
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is executed. The reload happens after any instruction and/or
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indirect address words are read, but before the JMS writes
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its return address; the return address is written to the new
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instruction field. The II flag blocks interrupts between the
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CIF and the JMP/JMS (page 53 of the 1970 small computer
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handbook describes the effect of the II flag, even though
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the flag itself is not described clearly).
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6214 RDF The contents of the DF register are logically ORed into
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bits [06..08] of the AC register.
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6224 RIF The contents of the IF register are logically ORed into
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bits [06..08] of the AC register.
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6234 RIB The contents of the SF register are logically ORed into
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bits [06..11] of the AC register; if the AC register is
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initially 0, then bits [09..11] of the AC register get the
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value which was in the DF register at the time of the last
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interrupt, and bits [06..08] of the AC register get the
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value which was in the IF register at the time of the last
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interrupt.
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6244 RMF Bits [03..05] of the SF register are loaded into the DF
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register, bits [00..02] of the SF register are loaded into
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the IB register, and the II flag is set to 1. The next JMP
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or JMS instruction completes the restore.
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-----
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rf08
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photocell
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DCIM - turn off photocell
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DIML - turn on photocell
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DMAR, DMAW - schedule work; delta to new location in time
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transfer in bursts
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