1132 lines
24 KiB
Verilog
1132 lines
24 KiB
Verilog
// RF08 Emulation using IDE disk
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// brad@heeltoe.com
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//`define debug_rf
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/*
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RF08 Sizes:
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2048 words/track 11 bits
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128 tracks 7 bits
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4 disks 2 bits
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-------
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20 bits
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1 111
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dma 98765432109876543210
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ddtttttttwwwwwwwwwww
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ema 876543210
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mapping RF08 to IDE disk drive
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2048 x 12 bits -> 2048 x 16 bits = 8 blocks of 512 bytes
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each track is 8 blocks
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each disk is (128 * 8) = 1024 blocks
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ide_block = (track * 8) + (word / 256)
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ide_block_index = word % 256
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ema bits 7 & 8 select which rs08 disk
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ema bits 6 - 0 select disk head (track #)
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dma contains lower disk word address (offset into block)
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writes to dma trigger i/o; adc is asserted after match w/disk
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-------------
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PDP-8 memory:
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7750 word count
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7751 current address
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PDP-8 IOT's:
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660x
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661x
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662x
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664x
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6601 DCMA Generates System Clear Pulse (SCLP) at IOP time 1.
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Clears disk memory eaddress(DMA), Parity Eror Flag (PEF),
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Data Request Late Flag (DRL), and sets logic to
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initial state for read or write. Does not clear
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interrupt enable or extended address register.
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6603 DMAR Generate SCLP at IOP time 1. At IOP time 2, loads DMA
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with AC and clears AC. Read continues for number words
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in WC register (7750)
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6605 DMAW Generate SCLP at IOP time 1. At IOP time 4, loads DMA
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with AC and clears AC. When the disk word address is located
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writing begins, disk address is incremented for each
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word written
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6611 DCIM clears disk interrupt enable and the extended address
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registers at IOP time 1.
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6612 DSAC At IOP time 2, skip if Address Confirmed (ADC) set indicating
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the DMA address and disk word address compare. AC is then
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cleared.
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6615 DIML At IOP time 1, clear interrupt enable and memory address
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extension registers. At IOP time 4, load interrupt enable
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and memory address extension register with AC, clear AC.
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6616 DIMA Clear ??? at IOP time 2. At IOP time 4 load AC with status
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register.
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6621 DFSE skip on error skip if DRL, PER WLS or NXD set
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6622 ??? skip if data completion DCF set
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6623 DISK skip on error or data completion; enabled at IOP 2
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6626 DMAC clear ac at IOP time 2 load AC from DMA at IOP time 4.
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6641 DCXA Clears EMA
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6643 DXAL Clears and loads EMA from AC. At IOP time 1, clear EMA, at
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IOP time 2, load EMA with AC. Clear AC
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6645 DXAC Clears AC and loads EMA into AC
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6646 DMMT Maintenance
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Real RF08 uses 3 cycle data break
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ac 8:0, ac 10:0 => 20 bit {EMA,DMA}
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20 bit {EMA,DMA} = { disk-select, track-select 6:0, word-select 11:0 }
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status
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EIE = WLS | DRL | NXD | PER
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*/
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/*
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3 cycle data break
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1. An address is read from the device to indicate the location of the
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word count register. This location specifies the number of words in
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the block yet to be transferred. The address is always the same for a
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given device.
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2. The content of the specficified word count register is read from
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memory and incremented by one. To transfer a block of n words, the
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word count is set to -n during the programmed initialization of the
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device. When this register is incremented to 0, a pulse is sent to
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the device to terminate the transfer.
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3. The location after the word count register contains the current
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address register for the device transfer. The content of this
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register is set to 1 less than the location to be affected by the next
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transfer. To transfer a block beginning at location A, the register is
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originally set to A-1.
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4. The content of the current address register is incremented by 1
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and then used to specify the location affected by the transfer.
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After the transfer of information has been accomplished through the
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data break factility, input data (or new output data) is processed,
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usually through the program interrupt facility. An interrupt is
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requested when the data transfer is completed and the service routine
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will process the information.
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----------- ----------- ----------- -----------
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*/
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/*
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HIGH LEVEL DISK STATE MACHINE:
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idle
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start-xfer
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read wc
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read addr
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if read
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goto check-xfer-read
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else
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goto begin-xfer-write
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check-xfer-read
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if memory buffer contains disk page
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read word from memory buffer at offset
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goto next-xfer-read
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else
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if memory buffer dirty
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goto write-old-page
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else
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goto read-new-page
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next-xfer-read
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write memory at addr
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goto next-xfer-incr
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next-xfer-incr
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incr addr
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incr wc
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if wc == 0
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goto done-xfer
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if read
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goto check-xfer-read
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else
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goto begin-xfer-write
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begin-xfer-write
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read from memory at addr
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goto check-xfer-write
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check-xfer-write
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if memory buffer contains disk page
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write word to memory buffer at offset
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set memory buffer dirty
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goto next-xfer-incr
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else
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if memory buffer dirty
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goto write-old-page
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else
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goto read-new-page
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done-xfer
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write addr to memory
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write wc to memory
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set done/interrupt
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goto idle
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read-new-page
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read memory buffer from ide
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remember memory buffer disk address
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clear memory buffer dirty
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if read
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goto check-xfer-read
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else
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goto check-xfer-write
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write-old-page
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write memory buffer to ide
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clear memory buffer dirty
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goto read-new-page
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----------- ----------- ----------- -----------
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DISK / DMA STATE MACHINE:
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external signals:
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ma_out
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ram_write_req
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ram_read_req
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ram_done
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mb_in
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mb_out
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internal signals:
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reg [19:0] disk_addr;
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wire [8:0] track;
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wire [11:0] ide_block;
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wire [7:0] ide_block_index;
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track = {ema[7:0], dma[11]};
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ide_block = {1'b0, track, 3'b0} + {8'b0, dma[11:8]}
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ide_block_index = dma[7:0];
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db_done <= 0;
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dma_done = 0;
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ram_read_req = 0;
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ram_write_req = 0;
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// idle
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DB_idle:
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// read word count
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DB_start_xfer1:
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disk_addr <= {ema, dma};
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ma_out = wc-address
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ram_read_req = 1
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dma_wc <= mb_in + 1;
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if ram_done db_next_state = DB_start_xfer2;
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// read addr
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DB_start_xfer2:
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ma_out = wc-address | 1
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ram_read_req = 1
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dma_addr <= mb_in + 1
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db_next_state = DB_start_xfer3;
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DB_start_xfer3:
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dma_done = dma_wc == 0
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if read
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db_next_state = DB_check_xfer_read;
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else
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db_next_state = DB_begin_xfer_write;
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// check buffer address
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DB_check_xfer_read:
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buffer_addr = disk_addr_offset
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if disk-addr-page == memory-buffer-addr-page
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buffer_rd = 1
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db_next_state = DB_next_xfer_read;
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else
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if buffer_dirty == 0
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db_next_state = DB_read_new_page;
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else
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db_next_state = DB_write_old_page;
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// write to ram
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DB_next_xfer_read:
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disk_addr <= disk_addr + 1
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ma_out = dma_addr
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mb_out = buffer_out
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ram_write_req = 1
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if ma_out = 7750
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dma_wc = buffer_out + 1
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if ma_out = 7751
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dma_addr = buffer_out + 1
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if ram_done
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else
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dma_done = dma_wc == 0
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if dma_done
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db_next_state = DB_done_xfer
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else
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db_next_state = DB_next_xfer_incr;
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DB_next_xfer_incr:
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dma_addr <= dma_addr + 1
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dma_wc <= dma_wc + 1
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if read
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db_next_state = DB_check_xfer_read;
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else
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db_next_state = DB_begin_xfer_write;
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// read from ram
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DB_begin_xfer_write:
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ma_out = dma_addr
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buffer_hold <= ram_in
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ram_read_req = 1
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if ram_done db_next_state = DB_check_xfer_write;
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// check buffer address
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DB_check_xfer_write:
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buffer_addr = disk_addr_offset
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if disk-addr-page == memory-buffer-addr-page
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buffer_wr = 1
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buffer_dirty <= 1
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disk_addr <= disk_addr + 1
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dma_done = dma_wc == 0
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if dma_done
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db_next_state = DB_done_xfer
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else
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db_next_state = DB_next_xfer_incr;
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else
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if buffer_dirty == 0
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db_next_state = DB_read_new_page
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else
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db_next_state = DB_write_old_page
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// done
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DB_done_xfer:
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ema <= disk_addr[18:11];
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dma <= disk_addr[10:0];
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ma_out = wc-address;
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mb_out = dma_addr
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ram_write_req = 1;
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if ram_done db_next_state = DB_start_xfer1;
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DB_done_xfer1:
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ma_out = wc-address | 1;
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mb_out = dma_wc
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ram_write_req = 1;
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if ram_done db_next_state = DB_done_xfer2;
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DB_done_xfer2:
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// wait for F2
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if state == F2
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db_next_state = DB_done_xfer3
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else
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db_next_state = DB_done_xfer2
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DB_done_xfer3:
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db_done <= 1
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//interrupt
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db_next_state = DB_idle
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DB_read_new_page:
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read block from ide
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set memory-buffer-addr-page
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buffer_dirty <= 0
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if read
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db_next_state = DB_check_xfer_read
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else
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db_next_state = DB_check_xfer_write
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DB_write_old_page:
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write block to ide
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buffer_dirty <= 0
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db_next_state = DB_read_new_page
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----------- ----------- ----------- -----------
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*/
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module pdp8_rf(clk, reset, iot, state, mb,
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io_data_in, io_data_out, io_select, io_selected,
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io_data_avail, io_interrupt, io_skip, io_clear_ac,
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ram_read_req, ram_write_req, ram_done,
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ram_ma, ram_in, ram_out,
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ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus);
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input clk, reset, iot;
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input [11:0] io_data_in;
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input [11:0] mb;
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input [3:0] state;
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input [5:0] io_select;
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input ram_done;
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input [11:0] ram_in;
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output reg [11:0] io_data_out;
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output reg io_selected;
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output reg io_data_avail;
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output io_interrupt;
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output reg io_skip;
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output reg io_clear_ac;
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output ram_read_req;
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output ram_write_req;
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output [11:0] ram_out;
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output [14:0] ram_ma;
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output ide_dior;
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output ide_diow;
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output [1:0] ide_cs;
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output [2:0] ide_da;
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inout [15:0] ide_data_bus;
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// -------------------------------------------------------
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parameter [3:0]
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F0 = 4'b0000,
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F1 = 4'b0001,
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F2 = 4'b0010,
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F3 = 4'b0011;
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parameter PCA_bit = 12'o4000; // photocell status
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parameter DRE_bit = 12'o2000; // data req enable
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parameter WLS_bit = 12'o1000; // write lock status
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parameter EIE_bit = 12'o0400; // error int enable
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parameter PIE_bit = 12'o0200; // photocell int enb
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parameter CIE_bit = 12'o0100; // done int enable
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parameter MEX_bit = 12'o0070; // memory extension
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parameter DRL_bit = 12'o0004; // data late error
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parameter NXD_bit = 12'o0002; // non-existent disk
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parameter PER_bit = 12'o0001; // parity error
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parameter WC_ADDR = 15'o07750;
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parameter CA_ADDR = 15'o07751;
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wire ADC;
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wire DRE;
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wire DRL;
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wire PER;
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wire PCA;
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reg [11:0] DMA;
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reg [7:0] EMA;
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reg DCF;
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reg PEF;
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reg CIE, EIE, NXD, PIE, WLS;
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reg [2:0] MEX;
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assign DRL = 1'b0;
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assign PER = 1'b0;
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reg [7:0] photocell_counter;
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parameter [3:0]
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DB_idle = 4'd0,
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DB_start_xfer1 = 4'd1,
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DB_start_xfer2 = 4'd2,
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DB_start_xfer3 = 4'd3,
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DB_check_xfer_read = 4'd4,
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DB_next_xfer_read = 4'd5,
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DB_next_xfer_incr = 4'd6,
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DB_begin_xfer_write = 4'd7,
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DB_check_xfer_write = 4'd8,
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DB_done_xfer = 4'd9,
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DB_done_xfer1 = 4'd10,
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DB_done_xfer2 = 4'd11,
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DB_done_xfer3 = 4'd12,
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DB_read_new_page = 4'd13,
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DB_write_old_page = 4'd14;
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reg [3:0] db_next_state;
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reg [3:0] db_state;
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wire active;
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reg is_read;
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reg is_write;
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reg dma_start;
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reg db_done;
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wire dma_done;
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reg clear_db_done;
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reg set_db_done;
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reg [14:0] dma_addr;
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reg [11:0] dma_wc;
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reg [19:0] disk_addr;
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reg load_disk_addr;
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reg incr_disk_addr;
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wire [7:0] buffer_addr;
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reg [19:8] buffer_disk_addr;
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reg buffer_dirty;
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reg [11:0] buffer_hold;
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reg load_buffer_hold;
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reg set_buffer_addr;
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reg set_buffer_dirty;
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wire buffer_matches_DMA;
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wire buffer_rd;
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wire buffer_wr;
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wire ide_read_req;
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wire ide_write_req;
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wire ide_done;
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wire ide_error;
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//
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assign io_interrupt = (CIE & DCF) ||
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(PIE & PCA) ||
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(EIE & (WLS | DRL | NXD | PER));
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assign active = is_read | is_write;
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assign buffer_matches_DMA = buffer_disk_addr[19:8] == disk_addr[19:8];
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assign buffer_addr = disk_addr[7:0];
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//
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// sector buffer
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//
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wire ide_active;
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wire [7:0] buff_addr;
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wire [11:0] buff_in;
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wire [11:0] buff_out;
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wire buff_rd;
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wire buff_wr;
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wire [7:0] ide_buffer_addr;
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wire [23:0] ide_block_number;
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wire [11:0] ide_buffer_in;
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wire [11:0] ide_buffer_out;
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wire ide_buffer_rd;
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wire ide_buffer_wr;
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// ide sector buffer
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ram_256x12 buffer(.clk(clk),
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.reset(reset),
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.a(buff_addr),
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.din(buff_in),
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.dout(buff_out),
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.ce(buff_rd | buff_wr),
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.we(buff_wr));
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assign ide_buffer_in = buff_out;
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assign ide_active = ide_read_req | ide_write_req;
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assign buff_addr = ide_active ? ide_buffer_addr : buffer_addr;
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assign buff_in = ide_active ? ide_buffer_out : buffer_hold;
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assign buff_rd = ide_active ? ide_buffer_rd : 1'b1/*buffer_rd?*/;
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assign buff_wr = ide_active ? ide_buffer_wr : buffer_wr;
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// ide disk
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ide_disk disk(.clk(clk),
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.reset(reset),
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.ide_lba(ide_block_number),
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.ide_read_req(ide_read_req),
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.ide_write_req(ide_write_req),
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.ide_error(ide_error),
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.ide_done(ide_done),
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.buffer_addr(ide_buffer_addr),
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.buffer_rd(ide_buffer_rd),
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.buffer_wr(ide_buffer_wr),
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.buffer_in(ide_buffer_in),
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.buffer_out(ide_buffer_out),
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.ide_data_bus(ide_data_bus),
|
|
.ide_dior(ide_dior),
|
|
.ide_diow(ide_diow),
|
|
.ide_cs(ide_cs),
|
|
.ide_da(ide_da));
|
|
|
|
assign ide_block_number = { 12'b0, disk_addr[19:8] };
|
|
|
|
//
|
|
// RF controller
|
|
//
|
|
|
|
// combinatorial logic
|
|
always @(state or iot or io_select or mb or io_data_in or
|
|
ADC or DRL or PER or WLS or NXD or DCF or
|
|
PCA or DRE or EIE or PIE or CIE or MEX or DMA or EMA or
|
|
disk_addr)
|
|
begin
|
|
// sampled during f1
|
|
io_skip = 0;
|
|
io_clear_ac = 0;
|
|
io_data_out = io_data_in;
|
|
io_data_avail = 1'b1;
|
|
dma_start = 1'b0;
|
|
io_selected = 1'b0;
|
|
|
|
if (state == F1 && iot)
|
|
case (io_select)
|
|
6'o60:
|
|
begin
|
|
io_selected = 1'b1;
|
|
case (mb[2:0] )
|
|
3'o3: // DMAR
|
|
begin
|
|
io_data_out = 0;
|
|
dma_start = 1'b1;
|
|
io_clear_ac = 1;
|
|
//`ifdef debug
|
|
// $display("rf: go! disk_addr %o", disk_addr);
|
|
//`endif
|
|
end
|
|
3'o5: // DMAW
|
|
begin
|
|
io_data_out = 0;
|
|
dma_start = 1'b1;
|
|
io_clear_ac = 1;
|
|
end
|
|
endcase
|
|
end // case: 6'o60
|
|
|
|
6'o61:
|
|
begin
|
|
io_selected = 1'b1;
|
|
case (mb[2:0])
|
|
3'o2: // DSAC
|
|
if (ADC)
|
|
begin
|
|
io_skip = 1;
|
|
io_data_out = 0;
|
|
end
|
|
3'o6: // DIMA
|
|
io_data_out = { PCA, DRE,WLS,
|
|
EIE, PIE,CIE,
|
|
MEX,
|
|
DRL,NXD,PER };
|
|
3'o5: // DIML
|
|
begin
|
|
io_data_out = 0;
|
|
io_clear_ac = 1;
|
|
end
|
|
endcase // case(mb[2:0])
|
|
end
|
|
|
|
6'o62:
|
|
begin
|
|
io_selected = 1'b1;
|
|
case (mb[2:0])
|
|
3'o1: // DFSE
|
|
if (DRL | PER | WLS | NXD)
|
|
io_skip = 1;
|
|
3'o2: // ???
|
|
if (DCF)
|
|
io_skip = 1;
|
|
3'o3: // DISK
|
|
if (DRL | PER | WLS | NXD | DCF)
|
|
io_skip = 1;
|
|
3'o6: // DMAC
|
|
begin
|
|
io_data_out = DMA;
|
|
io_clear_ac = 1;
|
|
end
|
|
endcase
|
|
end
|
|
|
|
6'o64:
|
|
begin
|
|
io_selected = 1'b1;
|
|
case (mb[2:0])
|
|
3'o3: // DXAL
|
|
begin
|
|
io_data_out = 0;
|
|
io_clear_ac = 1;
|
|
end
|
|
3'o5: // DXAC
|
|
io_data_out = EMA;
|
|
endcase // case(mb[2:0])
|
|
end
|
|
|
|
endcase // case(io_select)
|
|
end
|
|
|
|
|
|
//
|
|
// registers
|
|
//
|
|
always @(posedge clk)
|
|
if (reset)
|
|
begin
|
|
is_read <= 1'b0;
|
|
is_write <= 1'b0;
|
|
|
|
EMA <= 1'b0;
|
|
DMA <= 1'b0;
|
|
MEX <= 3'b0;
|
|
PEF <= 1'b0;
|
|
CIE <= 1'b0;
|
|
DCF <= 1'b1;
|
|
NXD <= 1'b0;
|
|
end
|
|
else
|
|
case (state)
|
|
F0:
|
|
begin
|
|
if (iot)
|
|
case (io_select)
|
|
6'o60: // DCMA
|
|
if (mb[2:0] == 3'b001)
|
|
begin
|
|
`ifdef debug
|
|
$display("rf: DCMA");
|
|
`endif
|
|
DMA <= 0;
|
|
PEF <= 1'b0;
|
|
NXD <= 1'b0;
|
|
DCF <= 1'b0;
|
|
end
|
|
6'o61:
|
|
case (mb[2:0])
|
|
3'o1: // DCIM
|
|
begin
|
|
EIE <= 1'b0;
|
|
PIE <= 1'b0;
|
|
CIE <= 1'b0;
|
|
MEX <= 3'b0;
|
|
`ifdef debug
|
|
$display("rf: DCIM");
|
|
`endif
|
|
end
|
|
3'o2: // DSAC
|
|
begin
|
|
end
|
|
3'o5: // DIML
|
|
begin
|
|
end
|
|
endcase // case(mb[2:0])
|
|
endcase
|
|
end
|
|
|
|
F1:
|
|
if (iot)
|
|
begin
|
|
`ifdef debug_rf
|
|
if (io_select == 6'o60 || io_select == 6'o64)
|
|
$display("iot2 %t, state %b, mb %o, io_select %o",
|
|
$time, state, mb, io_select);
|
|
`endif
|
|
case (io_select)
|
|
6'o60:
|
|
case (mb[2:0])
|
|
3'o3: // DMAR
|
|
begin
|
|
// clear ac
|
|
DMA <= io_data_in;
|
|
is_read <= 1'b1;
|
|
DCF <= 1'b0;
|
|
`ifdef debug
|
|
$display("rf: DMAR ac %o", io_data_in);
|
|
`endif
|
|
end
|
|
|
|
3'o5: // DMAW
|
|
begin
|
|
// clear ac
|
|
DMA <= io_data_in;
|
|
// is_write <= 1'b1;
|
|
//debug
|
|
is_read <= 1'b1;
|
|
DCF <= 1'b0;
|
|
end
|
|
endcase // case(mb[2:0])
|
|
|
|
6'o61:
|
|
case (mb[2:0])
|
|
3'o5: // DIML
|
|
begin
|
|
EIE <= io_data_in[8];
|
|
PIE <= io_data_in[7];
|
|
CIE <= io_data_in[6];
|
|
MEX <= io_data_in[5:3];
|
|
`ifdef debug
|
|
$display("rf: DIML %o", io_data_in);
|
|
`endif
|
|
end
|
|
endcase // case(mb[2:0])
|
|
|
|
6'o64:
|
|
case (mb[2:0])
|
|
1: // DCXA
|
|
EMA <= 0;
|
|
3: // DXAL
|
|
begin
|
|
// clear ac
|
|
EMA <= io_data_in;
|
|
end
|
|
endcase
|
|
|
|
endcase
|
|
|
|
end // if (iot)
|
|
|
|
F2:
|
|
begin
|
|
end
|
|
|
|
// F3 is a convenient time to do this
|
|
// note that state machine waits when done till next F2
|
|
// to sync up DB_done_xfer3 and F3
|
|
F3:
|
|
if (db_state == DB_done_xfer3)
|
|
begin
|
|
EMA <= disk_addr[19:12];
|
|
DMA <= disk_addr[11:0];
|
|
is_read <= 1'b0;
|
|
is_write <= 1'b0;
|
|
`ifdef debug
|
|
$display("rf: set DCF (CIE %b)", CIE);
|
|
`endif
|
|
DCF <= 1'b1;
|
|
end
|
|
|
|
endcase // case(state)
|
|
|
|
// comb logic to create 'next state'
|
|
always @(*)
|
|
begin
|
|
db_next_state = db_state;
|
|
load_disk_addr = 0;
|
|
incr_disk_addr = 0;
|
|
set_buffer_addr = 0;
|
|
set_buffer_dirty = 0;
|
|
load_buffer_hold = 0;
|
|
set_db_done = 0;
|
|
clear_db_done = 0;
|
|
|
|
case (db_state)
|
|
DB_idle:
|
|
if (dma_start)
|
|
db_next_state = DB_start_xfer1;
|
|
|
|
DB_start_xfer1:
|
|
if (ram_done)
|
|
begin
|
|
clear_db_done = 1;
|
|
load_disk_addr = 1;
|
|
db_next_state = DB_start_xfer2;
|
|
end
|
|
|
|
DB_start_xfer2:
|
|
if (ram_done)
|
|
begin
|
|
set_db_done = 1;
|
|
db_next_state = DB_start_xfer3;
|
|
end
|
|
|
|
DB_start_xfer3:
|
|
db_next_state = is_read ? DB_check_xfer_read : DB_begin_xfer_write;
|
|
|
|
DB_check_xfer_read:
|
|
begin
|
|
if (buffer_matches_DMA)
|
|
db_next_state = DB_next_xfer_read;
|
|
else
|
|
db_next_state = buffer_dirty ?
|
|
DB_write_old_page :
|
|
DB_read_new_page;
|
|
end
|
|
|
|
DB_next_xfer_read:
|
|
if (ram_done)
|
|
begin
|
|
incr_disk_addr = 1;
|
|
db_next_state = dma_done ? DB_done_xfer : DB_next_xfer_incr;
|
|
end
|
|
|
|
DB_next_xfer_incr:
|
|
db_next_state = is_read ? DB_check_xfer_read:DB_begin_xfer_write;
|
|
|
|
DB_begin_xfer_write:
|
|
if (ram_done)
|
|
begin
|
|
load_buffer_hold = 1;
|
|
db_next_state = DB_check_xfer_write;
|
|
end
|
|
|
|
DB_check_xfer_write:
|
|
if (buffer_matches_DMA)
|
|
begin
|
|
set_buffer_dirty = 1;
|
|
incr_disk_addr = 1;
|
|
db_next_state = dma_done ? DB_done_xfer : DB_next_xfer_incr;
|
|
end
|
|
else
|
|
db_next_state = buffer_dirty ?
|
|
DB_write_old_page :
|
|
DB_read_new_page;
|
|
|
|
DB_done_xfer:
|
|
if (ram_done)
|
|
db_next_state = DB_done_xfer1;
|
|
|
|
DB_done_xfer1:
|
|
if (ram_done)
|
|
db_next_state = DB_done_xfer2;
|
|
|
|
DB_done_xfer2:
|
|
if (state == F2)
|
|
db_next_state = DB_done_xfer3;
|
|
|
|
DB_done_xfer3:
|
|
db_next_state = DB_idle;
|
|
|
|
DB_read_new_page:
|
|
if (ide_done)
|
|
begin
|
|
set_buffer_addr = 1;
|
|
db_next_state = is_read ?
|
|
DB_check_xfer_read :
|
|
DB_check_xfer_write;
|
|
end
|
|
|
|
DB_write_old_page:
|
|
if (ide_done)
|
|
begin
|
|
set_buffer_addr = 1;
|
|
db_next_state = DB_read_new_page;
|
|
end
|
|
|
|
endcase
|
|
end
|
|
|
|
// db_state
|
|
always @(posedge clk)
|
|
if (reset)
|
|
db_state <= DB_idle;
|
|
else
|
|
db_state <= db_next_state;
|
|
|
|
assign dma_done = dma_wc == 12'o0000;
|
|
|
|
// general state - wc & ca
|
|
always @(posedge clk)
|
|
if (reset)
|
|
begin
|
|
dma_wc <= 12'b0;
|
|
dma_addr <= 14'b0;
|
|
end
|
|
else
|
|
begin
|
|
case (db_state)
|
|
|
|
DB_start_xfer1:
|
|
begin
|
|
dma_wc <= ram_in + 12'o0001;
|
|
`ifdef debug
|
|
if (ram_done) $display("rf: read wc %o", ram_in);
|
|
`endif
|
|
end
|
|
|
|
DB_start_xfer2:
|
|
begin
|
|
dma_addr <= { MEX, ram_in + 12'o0001 };
|
|
`ifdef debug
|
|
|
|
if (ram_done) $display("rf: read ca %o", ram_in);
|
|
`endif
|
|
end
|
|
|
|
DB_start_xfer3:
|
|
begin
|
|
// this state might be not be needed
|
|
`ifdef debug
|
|
$display("rf: start! disk_addr %o (%o %o)",
|
|
disk_addr, EMA, DMA);
|
|
`endif
|
|
end
|
|
|
|
DB_next_xfer_incr:
|
|
begin
|
|
dma_addr[11:0] <= dma_addr[11:0] + 12'o0001;
|
|
dma_wc <= dma_wc + 12'b1;
|
|
`ifdef debug_rf
|
|
$display("dma_wc %o dma_addr %o MEX %o",dma_wc,dma_addr,MEX);
|
|
`endif
|
|
end
|
|
|
|
DB_next_xfer_read:
|
|
begin
|
|
/* snoop for our wc & ca */
|
|
if (dma_addr == 12'o7750 && ram_done)
|
|
begin
|
|
dma_wc <= buff_out;
|
|
`ifdef debug
|
|
$display("rf: snoop update wc %o", buff_out);
|
|
`endif
|
|
end
|
|
|
|
if (dma_addr == 12'o7751 && ram_done)
|
|
begin
|
|
dma_addr[11:0] <= buff_out;
|
|
`ifdef debug
|
|
$display("rf: snoop update ca %o", buff_out);
|
|
`endif
|
|
end
|
|
|
|
`ifdef debug_rf
|
|
if (ram_done)
|
|
$display("rf: buffer read[%o] = %o", buff_addr, buff_out);
|
|
`endif
|
|
end
|
|
|
|
`ifdef debug
|
|
DB_done_xfer:
|
|
if (ram_done) $display("rf: write wc %o", dma_wc);
|
|
|
|
DB_done_xfer1:
|
|
if (ram_done) $display("rf: write ca %o", dma_addr);
|
|
|
|
DB_done_xfer2:
|
|
$display("rf: done");
|
|
`endif
|
|
|
|
endcase
|
|
end
|
|
|
|
//
|
|
always @(posedge clk)
|
|
if (reset)
|
|
buffer_hold <= 12'b0;
|
|
else
|
|
if (load_buffer_hold)
|
|
buffer_hold <= ram_in;
|
|
|
|
// done state
|
|
always @(posedge clk)
|
|
if (reset)
|
|
db_done <= 1'b1;
|
|
else
|
|
if (clear_db_done)
|
|
db_done <= 1'b0;
|
|
else
|
|
if (set_db_done)
|
|
db_done <= 1'b1;
|
|
|
|
// buffer address
|
|
always @(posedge clk)
|
|
if (reset)
|
|
begin
|
|
buffer_disk_addr[19:8] <= 12'b111111111111;
|
|
buffer_dirty <= 1'b0;
|
|
end
|
|
else
|
|
if (set_buffer_dirty)
|
|
buffer_dirty <= 1'b1;
|
|
else
|
|
if (set_buffer_addr)
|
|
begin
|
|
buffer_dirty <= 1'b0;
|
|
buffer_disk_addr[19:8] <= disk_addr[19:8];
|
|
end
|
|
|
|
// disk address
|
|
always @(posedge clk)
|
|
if (reset)
|
|
disk_addr <= 0;
|
|
else
|
|
if (load_disk_addr)
|
|
disk_addr <= {EMA, DMA};
|
|
else
|
|
if (incr_disk_addr)
|
|
disk_addr <= disk_addr + 20'b1;
|
|
|
|
|
|
//
|
|
// external ram control (for dma to/from pdp-8 memory)
|
|
//
|
|
assign ram_ma =
|
|
db_state == DB_start_xfer1 ? WC_ADDR :
|
|
db_state == DB_start_xfer2 ? CA_ADDR :
|
|
db_state == DB_next_xfer_read ? dma_addr :
|
|
db_state == DB_begin_xfer_write ? dma_addr :
|
|
db_state == DB_done_xfer ? WC_ADDR :
|
|
db_state == DB_done_xfer1 ? CA_ADDR :
|
|
15'b0;
|
|
|
|
assign ram_read_req =
|
|
(db_state == DB_start_xfer1) |
|
|
(db_state == DB_start_xfer2) |
|
|
(db_state == DB_begin_xfer_write);
|
|
|
|
assign ram_write_req =
|
|
(db_state == DB_next_xfer_read) |
|
|
(db_state == DB_done_xfer) |
|
|
(db_state == DB_done_xfer1);
|
|
|
|
assign ram_out =
|
|
db_state == DB_next_xfer_read ? buff_out :
|
|
db_state == DB_begin_xfer_write ? buffer_hold :
|
|
db_state == DB_done_xfer ? dma_wc :
|
|
db_state == DB_done_xfer1 ? dma_addr :
|
|
12'b0;
|
|
|
|
assign buffer_rd = db_state == DB_check_xfer_read && buffer_matches_DMA;
|
|
assign buffer_wr = db_state == DB_check_xfer_write && buffer_matches_DMA;
|
|
|
|
assign ide_read_req = db_state == DB_read_new_page;
|
|
assign ide_write_req = db_state == DB_write_old_page;
|
|
|
|
//
|
|
// RF08 state
|
|
//
|
|
assign ADC = buffer_matches_DMA;
|
|
|
|
// fake the photocell sensor
|
|
always @(posedge clk)
|
|
if (reset)
|
|
photocell_counter <= 0;
|
|
else
|
|
begin
|
|
photocell_counter <= photocell_counter + 1;
|
|
end
|
|
|
|
assign PCA = photocell_counter < 16;
|
|
assign DRE = ~db_done;
|
|
|
|
/* we don't support write lock */
|
|
always @(posedge clk)
|
|
if (reset)
|
|
begin
|
|
WLS <= 1'b0;
|
|
end
|
|
|
|
endmodule
|
|
|