75 lines
1.3 KiB
Verilog
75 lines
1.3 KiB
Verilog
/* 32kx12 static ram */
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module ram_32kx12(A, DI, DO, CE_N, WE_N);
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input[14:0] A;
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input[11:0] DI;
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input CE_N, WE_N;
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output[11:0] DO;
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reg[11:0] ram [0:32767];
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integer i;
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// synthesis translate_off
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reg [11:0] v;
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integer file;
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reg [1023:0] str;
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reg [1023:0] testfilename;
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integer n;
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initial
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begin
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for (i = 0; i < 32768; i=i+1)
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ram[i] = 12'b0;
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n = 0;
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`ifdef __ICARUS__
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n = $value$plusargs("test=%s", testfilename);
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`endif
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`ifdef __CVER__
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n = $scan$plusargs("test=", testfilename);
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`endif
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if (n == 0)
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begin
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testfilename = "../verif/default.mem";
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n = 1;
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end
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if (n > 0)
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begin
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$display("ram: code filename: %s", testfilename);
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file = $fopen(testfilename, "r");
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while ($fscanf(file, "%o %o\n", i, v) > 0)
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begin
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//$display("ram[%o] <- %o", i, v);
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ram[i] = v;
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end
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$fclose(file);
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end
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end
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always @(WE_N or CE_N or A or DI)
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begin
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if (WE_N == 0 && CE_N == 0)
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begin
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//$display("ram: write [%o] <- %o", A, DI);
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ram[ A ] = DI;
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end
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end
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//always @(A)
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// begin
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// $display("ram: ce %b, we %b [%o] -> %o", CE_N, WE_N, A, ram[A]);
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// end
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// assign DO = ram[ A ];
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assign DO = (^A === 1'bX || A === 1'bz) ? ram[0] : ram[A];
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endmodule
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