258 lines
4.8 KiB
Verilog
258 lines
4.8 KiB
Verilog
//
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// fake model of uart used for sim
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//
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//`define debug_fake_tx 1
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`define debug_fake_rx 1
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module fake_uart(clk, reset, state,
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tx_clk, tx_req, tx_ack, tx_data, tx_empty,
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rx_clk, rx_req, rx_ack, rx_empty, rx_data);
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input clk;
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input reset;
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input [3:0] state;
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input tx_clk;
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input tx_req;
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input [7:0] tx_data;
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input rx_clk;
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input rx_req;
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output tx_ack;
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output tx_empty;
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output rx_ack;
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output rx_empty;
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output reg [7:0] rx_data;
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//
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reg [1:0] t_state;
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wire [1:0] t_state_next;
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reg [1:0] r_state;
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wire [1:0] r_state_next;
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integer t_delay;
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reg t_done;
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//
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assign t_state_next =
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(t_state == 0 && tx_req) ? 1 :
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t_state == 1 ? 2 :
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(t_state == 2 && t_done) ? 0 :
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t_state;
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assign tx_ack = t_state == 1;
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assign tx_empty = t_delay == 0;
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initial
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begin
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t_delay = 0;
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refire_state = 0;
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end
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always @(posedge clk)
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begin
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if (t_state == 1)
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begin
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t_delay = 20;
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end
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if (t_delay > 0)
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begin
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t_delay = t_delay - 1;
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if (t_delay == 0)
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begin
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t_done = 1;
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//$display("xxx t_done; cycles %d", cycles);
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end
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`ifdef debug_fake_tx
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$display("t_state %d t_delay %d", t_state, t_delay);
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`endif
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end
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if (t_state == 0)
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t_done = 0;
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end
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integer cycles;
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initial
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cycles = 0;
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always @(posedge clk)
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begin
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if (state == 4'b0001)
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begin
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cycles = cycles + 1;
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//$display("cycles %d", cycles);
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// if (r_index == r_count && cycles >= 30000)
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// begin
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// $display("xxx want input; cycles %d", cycles);
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// end
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if (r_index == r_count && cycles == 200000)
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begin
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rdata[0] = "L";
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rdata[1] = "O";
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rdata[2] = "G";
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rdata[3] = "I";
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rdata[4] = "N";
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rdata[5] = " ";
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rdata[6] = "2";
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rdata[7] = " ";
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rdata[8] = "L";
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rdata[9] = "X";
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rdata[10] = "H";
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rdata[11] = "E";
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rdata[12] = "\215";
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rdata[13] = "\215";
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r_index = 0;
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r_count = 14;
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r_refires = 1;
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$display("xxx boom 1; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 300000)
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begin
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rdata[0] = "\215";
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r_index = 0;
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r_count = 1;
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r_refires = 2;
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$display("xxx boom 2; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 400000)
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begin
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rdata[0] = "\215";
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r_index = 0;
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r_count = 1;
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r_refires = 3;
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$display("xxx boom 3; cycles %d", cycles);
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end
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//`define msg_rcat 1
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`define msg_rfocal 1
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if (r_index == r_count && cycles == 500000)
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begin
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`ifdef msg_rcat
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rdata[0] = "R";
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rdata[1] = " ";
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rdata[2] = "C";
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rdata[3] = "A";
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rdata[4] = "T";
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rdata[5] = "\215";
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r_index = 0;
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r_count = 6;
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`endif
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`ifdef msg_rfocal
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rdata[0] = "R";
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rdata[1] = " ";
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rdata[2] = "F";
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rdata[3] = "O";
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rdata[4] = "C";
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rdata[5] = "A";
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rdata[6] = "L";
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rdata[7] = "\215";
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r_index = 0;
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r_count = 8;
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`endif
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r_refires = 4;
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$display("xxx boom 4; cycles %d", cycles);
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end
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if (r_index == r_count && cycles == 600000)
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begin
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rdata[0] = "\215";
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r_index = 0;
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r_count = 1;
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r_refires = 5;
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$display("xxx boom 5; cycles %d", cycles);
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end
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end
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end
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//
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assign r_state_next =
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r_state == 0 && rx_req ? 1 :
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r_state == 1 ? 2 :
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r_state == 2 ? 0 :
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r_state;
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assign rx_ack = r_state == 1;
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integer r_index, r_count, r_refires;
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integer do_refire, refire_state;
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assign rx_empty = r_index == r_count;
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initial
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begin
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r_index= 0;
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`ifdef no_fake_input
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r_count = 0;
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`else
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r_count = 22;
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`endif
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r_refires = 0;
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end
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reg [7:0] rdata[50:0];
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integer ii;
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/* "START\r01:01:85\r10:10\r" */
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initial
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begin
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ii = 0;
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rdata[ii] = 0; ii=ii+1;
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rdata[ii] = "S"; ii=ii+1;
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rdata[ii] = "T"; ii=ii+1;
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rdata[ii] = "A"; ii=ii+1;
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rdata[ii] = "R"; ii=ii+1;
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rdata[ii] = "T"; ii=ii+1;
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rdata[ii] = "\215"; ii=ii+1;
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rdata[ii] = "0"; ii=ii+1;
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rdata[ii] = "1"; ii=ii+1;
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rdata[ii] = ":"; ii=ii+1;
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rdata[ii] = "0"; ii=ii+1;
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rdata[ii] = "1"; ii=ii+1;
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rdata[ii] = ":"; ii=ii+1;
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rdata[ii] = "8"; ii=ii+1;
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rdata[ii] = "5"; ii=ii+1;
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rdata[ii] = "\215"; ii=ii+1;
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rdata[ii] = "1"; ii=ii+1;
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rdata[ii] = "0"; ii=ii+1;
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rdata[ii] = ":"; ii=ii+1;
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rdata[ii] = "1"; ii=ii+1;
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rdata[ii] = "0"; ii=ii+1;
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rdata[ii] = "\215"; ii=ii+1;
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rx_data = 0;
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end
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always @(*)
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begin
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if (r_state == 2)
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begin
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`ifdef debug_fake_rx
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$display("xxx dispense %0d %o %t",
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r_index, rdata[r_index], $time);
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`endif
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rx_data = rdata[r_index];
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r_index = r_index + 1;
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end
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end
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//
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always @(posedge clk)
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if (reset)
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t_state <= 0;
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else
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t_state <= t_state_next;
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always @(posedge clk)
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if (reset)
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r_state <= 0;
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else
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r_state <= r_state_next;
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endmodule
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