125 lines
2.2 KiB
Verilog
125 lines
2.2 KiB
Verilog
// run_io.v
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// testing top end for pdp8_io.v
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//
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`define debug
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`define sim_time
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`include "../rtl/pdp8_tt.v"
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`include "../rtl/pdp8_rf.v"
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`include "../rtl/pdp8_kw.v"
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`include "../rtl/pdp8_io.v"
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`include "../verif/fake_uart.v"
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`include "../rtl/brg.v"
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`include "../rtl/ide_disk.v"
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`include "../rtl/ide.v"
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`include "../rtl/ram_256x12.v"
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`timescale 1ns / 1ns
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module test;
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reg clk, reset;
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wire [11:0] io_data_in;
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wire [11:0] io_data_out;
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wire io_data_avail;
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wire io_interrupt;
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wire io_skip;
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wire io_clear_ac;
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wire [5:0] io_select;
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wire iot;
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wire [3:0] state;
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wire [11:0] mb;
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wire ext_ram_read_req;
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wire ext_ram_write_req;
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wire [14:0] ext_ram_ma;
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wire [11:0] ext_ram_in;
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wire ext_ram_done;
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wire [11:0] ext_ram_out;
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wire [15:0] ide_data_bus;
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wire ide_dior, ide_diow;
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wire [1:0] ide_cs;
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wire [2:0] ide_da;
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reg rs232_in;
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wire rs232_out;
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pdp8_io io(.clk(clk),
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.brgclk(clk),
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.reset(reset),
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.iot(iot),
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.state(state),
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.mb(mb),
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.io_data_in(io_data_out),
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.io_data_out(io_data_in),
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.io_select(io_select),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.io_clear_ac(io_clear_ac),
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.io_ram_read_req(ext_ram_read_req),
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.io_ram_write_req(ext_ram_write_req),
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.io_ram_done(ext_ram_done),
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.io_ram_ma(ext_ram_ma),
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.io_ram_in(ext_ram_in),
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.io_ram_out(ext_ram_out),
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.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da),
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.ide_data_bus(ide_data_bus),
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.rs232_in(rs232_in),
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.rs232_out(rs232_out));
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initial
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begin
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$timeformat(-9, 0, "ns", 7);
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$dumpfile("pdp8_io.vcd");
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$dumpvars(0, test.io);
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end
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initial
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begin
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clk = 0;
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reset = 0;
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rs232_in = 0;
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#1 begin
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reset = 1;
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end
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#50 begin
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reset = 0;
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end
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#3000 $finish;
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end
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always
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begin
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#10 clk = 0;
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#10 clk = 1;
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end
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//----
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integer cycle;
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initial
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cycle = 0;
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always @(posedge io.clk)
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begin
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cycle = cycle + 1;
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end
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endmodule
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