1025 lines
20 KiB
Verilog
1025 lines
20 KiB
Verilog
// PDP-8/I in verilog
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// copyright Brad Parker <brad@heeltoe.com> 2005-2010
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//
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// Based on descriptions in "Computer Engineering" and various PDP-8/I manuals
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// fully implements extended memory (IF & DF) and user mode (KT8/I)
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//
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// Mar 2010
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// co-simulation with simh & behavioral model to boot TSS/8
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// passes 8/I instruction and extended memory diags
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// split out peripherals, added external dma
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// Apr 2009
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// major revamp for synthesis, removed latches, added muxes, new top
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// Jan 2007
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// cleaned up state machines for synthesis
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// finished extended memory (IF & DF), user mode (KT8/I)
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// added rf08 registers
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// Dec 2006
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// cleaned up a little; now runs focal to prompt
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// moved i/o out to pdp8_io.v
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// added IF, DF, user mode
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// Nov 2005 Brad Parker brad@heeltoe.com
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// initial work; runs focal a bit
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//
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//
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// Instruction format:
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//
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// 0 1 2 3 4 5 6 7 8 9 10 11
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// |--op--|
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// 0 and
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// 1 tad
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// 2 isz
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// 3 dca
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// 4 jms
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// 5 jmp
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// 6 iot
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// 7 opr
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// group 1
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// 0
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// |cla|clf| | |
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// | | |cma cml| |
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// |bsw 001 |
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// |ral 010 |
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// |rtl 011 |
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// |rar 100 |
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// |rtr 101 |
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// | |iac
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//
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// group 2
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// 1 0
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// |sma|sza|snl|skp| |
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// |cla|
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// |osr|hlt
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//
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// group 3
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// 11 10 9 8 7 6 5 4 3 2 1 0
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// eae
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// 1 1
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// |cla|
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// |mqa|sca|mql|
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// |isn |
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//
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//
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//
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// cpu states
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//
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// F0 read ram[IF,pc]
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// F1 incr pc
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// F2 ?
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// F3 dispatch
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//
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// then
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//
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// E0 read ram[ea]
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// E1 decode
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// E2 write ram
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// E3 load
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//
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// or
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//
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// D0 read ram[ea]
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// D1 wait
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// D2 write ram
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// D3 load
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//
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// H0 halted
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//
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// ------
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// Rules for address calculation
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// 0 and
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// 1 tad
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// 2 isz
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// 3 dca
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//
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// // 11
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// 109876543210
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// cccIZooooooo
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//
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// bit 8 - indirect
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// bit 7 - page 0
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// bits 6:0 offset
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//
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// if 8:7 == 2'b00
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// ea = IF, pc[11:7], offset[6:0] ;; current page
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// if 8:7 == 2'b01
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// ea = IF, 5'b0, offset[6:0] ;; page 0
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// if 8:7 == 2'b10
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// ea = (DF, MA( IF, pc[11:7], offset[6:0] )) ;; *(current page)
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// if 8:7 == 2'b11
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// ea = (DF, MA( IF, 5'b0, offset[6:0] )) ;; *(page 0)
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// 4 jms
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// 5 jmp
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//
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// ------
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//
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// ea <= if Z
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// if I
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// {DF, 5'b0, mb[6:0]};
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// else
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// {IF, 5'b0, mb[6:0]};
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// else
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// if I
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// {DF, pc[11:7], mb[6:0]};
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// else
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// {IF, pc[11:7], mb[6:0]};
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//
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// ------
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//
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// Actions take during each state:
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//
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// F0 fetch
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// ma = {IF,pc}
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// check for interrupt
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//
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// F1 incr pc
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// ma = 0
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// ea <= { IF, ir_z_flag ? pc[11:7] : 5'b0, mb[6:0] };
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//
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// if opr
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// group 1 processing
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// group 2 processing
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//
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// if iot
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//
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// incr pc or skip (incr pc by 2)
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//
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// F2 ??
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// ma = pc
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//
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// F3 dispatch
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// ma = ea
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// if opr
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// group1 processing
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// if !opr && !iot
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// possible defer
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//
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// D0
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// ma = ea
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// mb <= ram[ma]
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// D1
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// ma = 0
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// D2 (write index reg)
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// ma = index reg ? ea : {DF,mb}
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// ram_wr = 1
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// D3
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// ea <= mb
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// ma = 0
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//
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// E0
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// ma = ea
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// mb <= ram[ma]
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// E1
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// ma = 0
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// E2 (write isz value, dca value, jms return)
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// ma = ea
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// ram_wr = 1
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// E3
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// ma = ea + 1 (only bottom 12 bits)
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//
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//
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// extended memory
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//
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// 62n1 cdf change data field; df <= mb[5:3]
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// 62n2 cif change instruction field; if <= mb[5:3], after next jmp or jms
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// 6214 rdf read df into ac[5:3]
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// 6224 rif read if into ac[5:3]
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// 6234 rib read sf into ac[5:0], which is {if,df}
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// 6244 rmf restore memory field, sf => ib, df
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// (remember that on interrupt, sf <= {if,df})
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//
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module pdp8(clk, reset, initial_pc, pc_out, ac_out,
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ram_addr, ram_data_out, ram_data_in, ram_rd, ram_wr,
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io_select, io_data_out, io_data_in,
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io_data_avail, io_interrupt, io_skip, io_clear_ac,
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switches, iot, state, mb,
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ext_ram_read_req, ext_ram_write_req, ext_ram_done,
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ext_ram_ma, ext_ram_in, ext_ram_out);
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input clk, reset;
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input [14:0] initial_pc;
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input [11:0] ram_data_in;
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output ram_rd;
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output ram_wr;
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output [11:0] ram_data_out;
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output [14:0] ram_addr;
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output [11:0] pc_out;
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output [11:0] ac_out;
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output [5:0] io_select;
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input [11:0] io_data_in;
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output [11:0] io_data_out;
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input io_data_avail;
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input io_interrupt;
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input io_skip;
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input io_clear_ac;
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output iot;
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output [3:0] state;
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output [11:0] mb;
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input [11:0] switches;
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input ext_ram_read_req;
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input ext_ram_write_req;
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input [14:0] ext_ram_ma;
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input [11:0] ext_ram_in;
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output ext_ram_done;
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output [11:0] ext_ram_out;
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// memory buffer, holds data, instructions
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reg [11:0] mb;
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// generate address of work in memory being accessed
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wire [14:0] ma;
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// accumulator & link
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reg [11:0] ac;
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reg l;
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// MQ
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reg [11:0] mq;
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// program counter
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reg [11:0] pc;
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wire pc_incr, pc_skip;
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// instruction register
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reg [2:0] ir;
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reg ir_z_flag;
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reg ir_i_flag;
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// extended memory - instruction field & data field
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reg [2:0] IF;
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reg [2:0] DF;
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reg [2:0] IB;
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reg [6:0] SF; // { UF, IF[2:0], DF[2:0] }
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reg IB_pending;
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// user mode
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reg UB; // user_buffer
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reg UF; // user_flag
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reg UI; // user_interrupt
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reg UB_pending;
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// processor state
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reg [3:0] state;
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wire [3:0] next_state;
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reg run;
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reg interrupt_enable;
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reg interrupt_cycle;
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reg [1:0] interrupt_inhibit_delay;
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reg interrupt_skip;
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reg interrupt;
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wire interrupt_inhibit;
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wire skip_condition;
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wire user_interrupt;
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wire fetch; // memory cycle to fetch instruction
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wire deferred;// memory cycle to get address of operand
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wire execute;// memory cycle to getch (store) operand and execute isn
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assign {fetch, deferred, execute} =
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(state[3:2] == 2'b00) ? 3'b100 :
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(state[3:2] == 2'b01) ? 3'b010 :
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(state[3:2] == 2'b10) ? 3'b001 :
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3'b000 ;
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// instruction op decode
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wire i_and,tad,isz,dca,jms,jmp,iot,opr;
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assign {i_and,tad,isz,dca,jms,jmp,iot,opr} =
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(ir == 3'b000) ? 8'b10000000 :
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(ir == 3'b001) ? 8'b01000000 :
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(ir == 3'b010) ? 8'b00100000 :
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(ir == 3'b011) ? 8'b00010000 :
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(ir == 3'b100) ? 8'b00001000 :
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(ir == 3'b101) ? 8'b00000100 :
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(ir == 3'b110) ? 8'b00000010 :
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8'b00000001 ;
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//-------------
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/*
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* note: bit numbering is opposite that used in "Computer Engineering"
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*
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* F1
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* if opr
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* if MB[8] and !MB[0]
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* begin
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* if skip.conditions ^ MB[3]
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* pc <= pc + 2
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* if skip.conditions == MB[3]
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* pc <= pc + 1 next
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* if MB[7]
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* ac <= 0
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*
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* skip conditions are only valid during F1
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*
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*/
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assign skip_condition = (mb[6] && ac[11]) ||
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(mb[5] && (ac == 12'b0)) ||
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(mb[4] && l);
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assign pc_incr =
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/* group 1 */
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(opr & !mb[8]) ||
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/* group 2 */
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(opr && (mb[8] && !mb[0]) && (skip_condition == mb[3])) ||
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/* group 3? */
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(opr && (mb[8] && mb[0])) ||
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iot ||
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(!(opr || iot) && !interrupt_cycle);
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assign pc_skip =
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(opr && (mb[8] && !mb[0]) && (skip_condition ^ mb[3])) ||
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(iot && (io_skip || interrupt_skip));
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assign user_interrupt =
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// i/o operation
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(UF && iot) ||
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// group 2 - user mode halt or osr
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(UF && opr && (mb[8] & !mb[0]) && (mb[2] | mb[1]));
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// cpu states
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parameter [3:0]
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F0 = 4'b0000,
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F1 = 4'b0001,
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F2 = 4'b0010,
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F3 = 4'b0011,
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D0 = 4'b0100,
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D1 = 4'b0101,
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D2 = 4'b0110,
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D3 = 4'b0111,
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E0 = 4'b1000,
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E1 = 4'b1001,
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E2 = 4'b1010,
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E3 = 4'b1011,
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H0 = 4'b1100;
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// for display
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assign pc_out = pc;
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assign ac_out = ac;
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//
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// cpu state state machine
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//
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// clock next cpu state at rising edge of clock
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//
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always @(posedge clk)
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if (reset)
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state <= 0;
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else
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state <= next_state;
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wire next_is_F0;
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wire next_is_E0;
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assign next_is_F0 = opr | iot | (!mb[8] & jmp);
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assign next_is_E0 = !mb[8] & !jmp;
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assign next_state = state == F0 ? F1 :
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state == F1 && (~iot | (iot & io_data_avail)) ? F2 :
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// state == F1 && (iot & ~io_data_avail) ? F1 :
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state == F2 ? F3 :
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state == F3 ? (~run ? H0 :
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next_is_F0 ? F0 :
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next_is_E0 ? E0 :
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D0) :
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state == D0 ? D1 :
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state == D1 ? D2 :
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state == D2 ? D3 :
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state == D3 ? (jmp ? F0 : E0) :
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state == E0 ? E1 :
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state == E1 ? E2 :
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state == E2 ? E3 :
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state == E3 ? F0 :
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state == H0 ? H0 :
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F0;
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//
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// pc
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//
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wire [11:0] pc_mux;
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always @(posedge clk)
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if (reset)
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pc <= initial_pc[11:0];
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else
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begin
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pc <= pc_mux;
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end
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assign pc_mux = (state == F1 && pc_skip) ? (pc + 12'd2) :
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(state == F1 && pc_incr) ? (pc + 12'd1) :
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(state == F3 && !(opr || iot) && (!mb[8] & jmp)) ? ma :
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(state == D3 && jmp) ? mb :
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(state == E3 && jms) ? ma :
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(state == E3 && isz && mb == 12'b0) ? (pc + 12'd1) :
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pc;
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//
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// ram
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//
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wire is_index_reg;
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assign ram_rd = (state == F0) ||
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(state == D0) ||
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(state == E0) ||
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(state == F2 && ext_ram_read_req);
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assign ram_wr = (state == D2 && is_index_reg) ||
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(state == E2 && (isz || dca || jms)) ||
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(state == F2 && ext_ram_write_req);
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/* peripherals get ram access during F2 */
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wire ext_ram_req;
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wire ext_ram_grant;
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assign ext_ram_req = ext_ram_read_req | ext_ram_write_req;
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assign ext_ram_done = state == F2 && ext_ram_req;
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assign ext_ram_grant = state == F2 && ext_ram_req;
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assign ext_ram_out = ext_ram_req ? ram_data_in : 12'b0;
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assign ram_addr = ext_ram_grant ? ext_ram_ma : ma;
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assign ram_data_out = ext_ram_grant ? ext_ram_in : mb;
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assign io_select = UF ? 6'b0 : mb[8:3];
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assign io_data_out = ac;
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//
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// ea calculation
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//
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reg [14:0] ea;
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always @(posedge clk)
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if (reset)
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ea <= 0;
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else
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if (state == F1)
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ea <= { IF, ir_z_flag ? pc[11:7] : 5'b0, mb[6:0] };
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else
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if (state == D3)
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ea <= { (ir_i_flag && (!jmp && !jms)) ? DF : IF, mb };
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assign is_index_reg = ea[11:3] == 9'o001;
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//
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// ma
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//
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assign ma = (state == F0) ? {IF,pc} :
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(state == F2 && (opr || iot)) ? {IF,pc} :
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((state == F3 || state == D0 || state == E0) &&
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(!opr && !iot)) ? ea :
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(state == D2) ? (is_index_reg ? ea : {DF,mb}) :
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(state == E2 ) ? ea :
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(state == E3 && jms) ? {ea[14:12], ea[11:0] + 12'b1} :
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15'b0;
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//
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// interrupt defer logic
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//
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reg interrupt_inhibit_clear;
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reg interrupt_inhibit_ib;
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reg interrupt_inhibit_ub;
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reg interrupt_inhibit_ion;
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assign interrupt_inhibit = interrupt_inhibit_delay[0] |
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interrupt_inhibit_delay[1] |
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interrupt_inhibit_ion;
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always @(posedge clk)
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if (reset)
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begin
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interrupt_inhibit_delay <= 2'b00;
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IB_pending <= 0;
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UB_pending <= 0;
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end
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else
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if (interrupt_inhibit_clear)
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begin
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interrupt_inhibit_delay <= 2'b00;
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IB_pending <= 1'b0;
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UB_pending <= 1'b0;
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end
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else
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if (interrupt_inhibit_ib || interrupt_inhibit_ub)
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begin
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interrupt_inhibit_delay <= 2'b10;
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if (interrupt_inhibit_ib)
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IB_pending <= 1;
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if (interrupt_inhibit_ub)
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UB_pending <= 1;
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end
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else
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if (~IB_pending && ~UB_pending)
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begin
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interrupt_inhibit_delay[1] <= interrupt_inhibit_delay[0];
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interrupt_inhibit_delay[0] <= interrupt_inhibit_ion;
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end
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//
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// combinatorial
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//
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always @(*)
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begin
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/* defaults - these should be comb logic */
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// interrupt_inhibit_clear = 1'b0;
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// interrupt_inhibit_ion = 1'b0;
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// interrupt_inhibit_ib = 1'b0;
|
|
// interrupt_inhibit_ub = 1'b0;
|
|
|
|
interrupt_skip = 0;
|
|
|
|
case (state)
|
|
F1:
|
|
begin
|
|
|
|
// if ((jmp || jms) && IB_pending)
|
|
// begin
|
|
// interrupt_inhibit_clear = 1'b1;
|
|
// end
|
|
|
|
// if ((jmp || jms) && UB_pending)
|
|
// begin
|
|
// interrupt_inhibit_clear = 1'b1;
|
|
// end
|
|
|
|
if (iot && ~UF)
|
|
begin
|
|
casex (io_select)
|
|
6'b000000: // ION, IOF
|
|
case (mb[2:0])
|
|
// 3'b001:
|
|
// interrupt_inhibit_ion = 1'b1;
|
|
3'b011:
|
|
if (interrupt_enable)
|
|
interrupt_skip = 1;
|
|
endcase
|
|
|
|
6'b010xxx: // CDF..RMF
|
|
begin
|
|
// if (mb[1])
|
|
// begin // CIF
|
|
// interrupt_inhibit_ib = 1'b1;
|
|
// end
|
|
|
|
if (mb[2:0] == 3'b100)
|
|
begin
|
|
case (io_select[2:0])
|
|
// 3'b100: begin // RMF
|
|
// interrupt_inhibit_ib = 1'b1;
|
|
// interrupt_inhibit_ub = 1'b1;
|
|
// end
|
|
|
|
3'b101: // SINT
|
|
begin
|
|
`ifdef debug
|
|
$display("SINT: UI %b, state %b",
|
|
UI, state);
|
|
`endif
|
|
if (UI)
|
|
interrupt_skip = 1;
|
|
end
|
|
|
|
// 3'b110: // CUF
|
|
// begin
|
|
// interrupt_inhibit_ub = 1'b1;
|
|
// end
|
|
|
|
// 3'b111: // SUF
|
|
// begin
|
|
// interrupt_inhibit_ub = 1'b1;
|
|
// end
|
|
endcase
|
|
end
|
|
|
|
end
|
|
endcase // casex(io_select)
|
|
|
|
end // if (iot && ~UF)
|
|
end
|
|
|
|
endcase
|
|
end
|
|
|
|
|
|
//
|
|
// registers
|
|
//
|
|
always @(posedge clk)
|
|
if (reset)
|
|
begin
|
|
mb <= 0;
|
|
ac <= 0;
|
|
mq <= 0;
|
|
l <= 0;
|
|
|
|
ir <= 3'b000;
|
|
ir_z_flag <= 1'b0;
|
|
ir_i_flag <= 1'b0;
|
|
|
|
run <= 1;
|
|
interrupt_enable <= 0;
|
|
interrupt_cycle <= 0;
|
|
interrupt <= 0;
|
|
UI <= 0;
|
|
IF <= initial_pc[14:12];
|
|
DF <= 0;
|
|
IB <= 0;
|
|
SF <= 0;
|
|
UF <= 0;
|
|
UB <= 0;
|
|
end
|
|
else
|
|
case (state)
|
|
//
|
|
// FETCH
|
|
//
|
|
F0:
|
|
begin
|
|
// interrupt_skip = 0;
|
|
interrupt_inhibit_ion = 1'b0;
|
|
|
|
if (interrupt && interrupt_enable &&
|
|
!interrupt_inhibit && !interrupt_cycle)
|
|
begin
|
|
if (0)
|
|
$display("xxx interrupt, pc %o; %b %b %b; %b %b",
|
|
pc,
|
|
interrupt, interrupt_enable, interrupt_cycle,
|
|
interrupt_inhibit, interrupt_inhibit_delay);
|
|
interrupt_cycle <= 1;
|
|
interrupt <= 0;
|
|
interrupt_enable <= 0;
|
|
|
|
// simulate a jsr to 0
|
|
mb <= 12'o4000;
|
|
ir <= 3'o4;
|
|
ir_i_flag <= 1'b0;
|
|
ir_z_flag <= 1'b0;
|
|
SF <= {UF,IF,DF};
|
|
IF <= 3'b000;
|
|
DF <= 3'b000;
|
|
UF <= 1'b0;
|
|
UB <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
interrupt_cycle <= 0;
|
|
|
|
if (0)
|
|
$display("read ram [%o] -> %o", ram_addr, ram_data_in);
|
|
|
|
mb <= ram_data_in;
|
|
ir <= ram_data_in[11:9];
|
|
ir_i_flag <= ram_data_in[8];
|
|
ir_z_flag <= ram_data_in[7];
|
|
end
|
|
end
|
|
|
|
F1:
|
|
begin
|
|
/* defaults - these should be comb logic */
|
|
interrupt_inhibit_clear = 1'b0;
|
|
interrupt_inhibit_ion = 1'b0;
|
|
interrupt_inhibit_ib = 1'b0;
|
|
interrupt_inhibit_ub = 1'b0;
|
|
|
|
// interrupt_skip = 0;
|
|
|
|
/* defered loading of IF from IB at next jmp/jms */
|
|
if ((jmp || jms) && IB_pending)
|
|
begin
|
|
//$display("loading IF %o", IB);
|
|
IF <= IB;
|
|
interrupt_inhibit_clear = 1'b1;
|
|
end
|
|
|
|
if ((jmp || jms) && UB_pending)
|
|
begin
|
|
UF <= UB;
|
|
interrupt_inhibit_clear = 1'b1;
|
|
end
|
|
|
|
if (opr)
|
|
casex ({mb[8],mb[0]})
|
|
2'b0x: // group 1
|
|
begin
|
|
case ({mb[7],mb[5]})
|
|
2'b01: ac <= ~ac;
|
|
2'b10: ac <= 12'o0;
|
|
2'b11: ac <= 12'o7777;
|
|
endcase
|
|
|
|
case ({mb[6],mb[4]})
|
|
2'b01: l <= ~l;
|
|
2'b10: l <= 1'b0;
|
|
2'b11: l <= 1'b1;
|
|
endcase
|
|
end
|
|
|
|
2'b10: // group 2
|
|
begin
|
|
if (mb[7])
|
|
ac <= 0;
|
|
end
|
|
|
|
2'b11: // group 3
|
|
begin
|
|
if (mb[7])
|
|
ac <= 0;
|
|
end
|
|
|
|
default:
|
|
;
|
|
endcase
|
|
|
|
if (iot && UF)
|
|
begin
|
|
UI <= 1;
|
|
$display("user iot: set UI");
|
|
end
|
|
|
|
if (iot && ~UF)
|
|
begin
|
|
casex (io_select)
|
|
6'b000000: // ION, IOF
|
|
case (mb[2:0])
|
|
3'b001:
|
|
begin
|
|
interrupt_enable <= 1;
|
|
interrupt_inhibit_ion = 1'b1;
|
|
end
|
|
3'b010: interrupt_enable <= 0;
|
|
// 3'b011: if (interrupt_enable)
|
|
// interrupt_skip = 1;
|
|
endcase
|
|
|
|
6'b010xxx: // CDF..RMF
|
|
begin
|
|
if (mb[0])
|
|
DF <= mb[5:3]; // CDF
|
|
|
|
if (mb[1])
|
|
begin // CIF
|
|
IB <= mb[5:3];
|
|
interrupt_inhibit_ib = 1'b1;
|
|
end
|
|
|
|
if (mb[2:0] == 3'b100)
|
|
begin
|
|
case (io_select[2:0])
|
|
3'b000: UI <= 0; // CINT
|
|
|
|
3'b001: ac <= ac | { 6'b0, DF, 3'b0 }; // RDF
|
|
3'b010: ac <= ac | { 6'b0, IF, 3'b0 }; // RIF
|
|
3'b011: ac <= ac | { 5'b0, SF }; // RIB
|
|
3'b100: begin // RMF
|
|
UB <= SF[6];
|
|
IB <= SF[5:3];
|
|
DF <= SF[2:0];
|
|
interrupt_inhibit_ib = 1'b1;
|
|
interrupt_inhibit_ub = 1'b1;
|
|
end
|
|
|
|
3'b101: // SINT
|
|
begin
|
|
`ifdef debug
|
|
$display("SINT: UI %b, state %b",
|
|
UI, state);
|
|
`endif
|
|
// if (UI)
|
|
// interrupt_skip = 1;
|
|
end
|
|
|
|
3'b110: // CUF
|
|
begin
|
|
UB <= 0;
|
|
interrupt_inhibit_ub = 1'b1;
|
|
end
|
|
|
|
3'b111: // SUF
|
|
begin
|
|
UB <= 1;
|
|
interrupt_inhibit_ub = 1'b1;
|
|
end
|
|
endcase
|
|
end // if (mb[2:0] == 3'b100)
|
|
end
|
|
endcase // case(io_select)
|
|
|
|
if (io_data_avail)
|
|
begin
|
|
`ifdef debug
|
|
if (0) $display("io_data clock %o", io_data_in);
|
|
`endif
|
|
ac <= io_data_in;
|
|
end
|
|
|
|
if (io_clear_ac)
|
|
begin
|
|
ac <= 0;
|
|
end
|
|
|
|
end // if (iot)
|
|
|
|
if (io_interrupt || user_interrupt)
|
|
begin
|
|
`ifdef debug
|
|
if (0)
|
|
$display("xxx F1 interrupt; (%b %b %b; %b %b; %b %b %b)",
|
|
interrupt_enable,
|
|
interrupt_inhibit,
|
|
interrupt_cycle,
|
|
io_interrupt, iot && UF,
|
|
IB_pending, UB_pending,
|
|
interrupt_inhibit_delay);
|
|
`endif
|
|
|
|
interrupt <= 1;
|
|
end
|
|
else
|
|
interrupt <= 0;
|
|
|
|
end // case: F1
|
|
|
|
F2:
|
|
begin
|
|
if (opr)
|
|
begin
|
|
// group 1
|
|
if (!mb[8] && mb[0]) /* IAC */
|
|
{l,ac} <= {l,ac} + 13'o00001;
|
|
|
|
// group 3
|
|
if (mb[8] & mb[0])
|
|
case ({mb[6:4]})
|
|
3'b001: /* MQL */
|
|
begin
|
|
mq <= ac;
|
|
ac <= 0;
|
|
end
|
|
3'b100: ac <= ac | mq; /* MQA */
|
|
3'b101: ac <= mq;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
F3:
|
|
begin
|
|
if (opr)
|
|
begin
|
|
// group 1
|
|
if (!mb[8])
|
|
begin
|
|
case (mb[3:1])
|
|
3'b001: // BSW
|
|
{l,ac} <= {l,ac[5:0],ac[11:6]};
|
|
3'b010: // RAL
|
|
{l,ac} <= {ac[11:0],l};
|
|
3'b011: // RTL
|
|
{l,ac} <= {ac[10:0],l,ac[11]};
|
|
3'b100: // RAR
|
|
{l,ac} <= {ac[0],l,ac[11:1]};
|
|
3'b101: // RTR
|
|
{l,ac} <= {ac[1:0],l,ac[11:2]};
|
|
endcase
|
|
end
|
|
|
|
if (!UF)
|
|
begin
|
|
// group 2
|
|
if (mb[8] & !mb[0])
|
|
begin
|
|
if (mb[2])
|
|
ac <= ac | switches;
|
|
if (mb[1])
|
|
begin
|
|
`ifdef debug
|
|
$display("HLT! %o", mb);
|
|
`endif
|
|
run <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
if (UF)
|
|
begin
|
|
// group 2 - user mode (halt & osr)
|
|
if (mb[8] & !mb[0])
|
|
begin
|
|
if (mb[2])
|
|
UI <= 1;
|
|
if (mb[1])
|
|
UI <= 1;
|
|
end
|
|
end
|
|
|
|
// group 3
|
|
if (mb[8] & mb[0])
|
|
begin
|
|
if (mb[7:4] == 4'b1101)
|
|
mq <= 0;
|
|
end
|
|
|
|
end // if (opr)
|
|
|
|
end // case: F3
|
|
|
|
//
|
|
// DEFER
|
|
//
|
|
D0:
|
|
begin
|
|
if (0) $display("read ram [%o] -> %o", ram_addr, ram_data_in);
|
|
mb <= ram_data_in;
|
|
end
|
|
|
|
D1:
|
|
begin
|
|
// auto increment locations
|
|
if (is_index_reg)
|
|
mb <= mb + 1;
|
|
end
|
|
|
|
D2:
|
|
begin
|
|
// write ram
|
|
if (ram_wr)
|
|
if (0) $display("write ram [%o] <- %o", ram_addr, ram_data_out);
|
|
end
|
|
|
|
D3:
|
|
begin
|
|
end
|
|
|
|
//
|
|
// EXECUTE
|
|
//
|
|
E0:
|
|
begin
|
|
if (0) $display("read ram [%o] -> %o", ram_addr, ram_data_in);
|
|
mb <= ram_data_in;
|
|
end
|
|
|
|
E1:
|
|
begin
|
|
if (i_and)
|
|
begin
|
|
end
|
|
|
|
if (isz)
|
|
mb <= mb + 1;
|
|
else
|
|
if (dca)
|
|
mb <= ac;
|
|
else
|
|
if (jms)
|
|
mb <= pc;
|
|
end
|
|
|
|
E2:
|
|
begin
|
|
// write ram
|
|
if (ram_wr)
|
|
if (0) $display("write ram [%o] <- %o (pc %o)",
|
|
ram_addr, ram_data_out, pc);
|
|
end
|
|
|
|
E3:
|
|
begin
|
|
if (i_and)
|
|
ac <= ac & mb;
|
|
else
|
|
if (tad)
|
|
{l,ac} <= {l,ac} + {1'b0,mb};
|
|
else
|
|
if (dca)
|
|
ac <= 0;
|
|
end
|
|
endcase // case(state)
|
|
|
|
endmodule
|
|
|