139 lines
2.5 KiB
Verilog
139 lines
2.5 KiB
Verilog
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module pdp8_tt(clk, reset, iot, state, mb,
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io_data_in, io_data_out, io_select,
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io_data_avail, io_interrupt, io_skip);
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input clk, reset, iot;
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input [11:0] io_data_in;
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input [11:0] mb;
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input [3:0] state;
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input [5:0] io_select;
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output reg [11:0] io_data_out;
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output reg io_data_avail;
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output reg io_interrupt;
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output reg io_skip;
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reg rx_int, tx_int;
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reg [12:0] rx_data, tx_data;
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reg tx_delaying;
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integer tx_delay;
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parameter F0 = 4'b0000;
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parameter F1 = 4'b0001;
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parameter F2 = 4'b0010;
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parameter F3 = 4'b0011;
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// combinatorial
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always @(state or
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rx_int or tx_int)
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begin
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// sampled during f1
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io_skip = 0;
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io_data_out = io_data_in;
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io_data_avail = 1;
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if (state == F1 && iot)
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case (io_select)
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6'o03:
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begin
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if (mb[0])
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io_skip = rx_int;
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if (mb[2])
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io_data_out = rx_data;
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end
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6'o04:
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if (mb[0])
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begin
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io_skip = tx_int;
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$display("xxx io_skip %b", tx_int);
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end
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endcase // case(io_select)
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end
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//
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// registers
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//
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always @(posedge clk)
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if (reset)
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begin
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end
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else
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case (state)
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F0:
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begin
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// sampled during f1
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io_data_avail <= 0;
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end
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F1:
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if (iot)
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begin
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$display("iot2 %t, state %b, mb %o, io_select %o",
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$time, state, mb, io_select);
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case (io_select)
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6'o03:
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begin
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if (mb[1])
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rx_int <= 0;
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end
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6'o04:
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begin
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if (mb[0])
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begin
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end
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if (mb[1])
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begin
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tx_int <= 0;
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$display("xxx reset tx_int");
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end
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if (mb[2])
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begin
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tx_data <= io_data_in;
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$display("xxx tx_data %o", io_data_in);
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tx_int <= 1;
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tx_delaying <= 1;
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tx_delay <= 98;
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$display("xxx set tx_int");
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end
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end // case: 6'o04
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endcase
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end // if (iot)
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F2:
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begin
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if (io_interrupt)
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$display("iot2 %t, reset io_interrupt", $time);
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// sampled during f0
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io_interrupt <= 0;
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end
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F3:
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begin
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if (tx_delaying)
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begin
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tx_delay <= tx_delay - 1;
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//$display("xxx delay %d", tx_delay);
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if (tx_delay == 0)
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begin
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$display("iot2 %t, xxx set io_interrupt", $time);
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tx_delaying <= 0;
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io_interrupt <= 1;
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end
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end
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end
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endcase // case(state)
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endmodule
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