24 lines
357 B
Verilog
24 lines
357 B
Verilog
// video_mem.v
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/* 1kx32 static ram */
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module video_ram(addr, data_in, data_out, ce_n, we_n);
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input [10:0] addr;
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input [7:0] data_in;
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input ce_n, we_n;
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output [7:0] data_out;
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reg [7:0] ram [0:2047];
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always @(negedge we_n)
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begin
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if (ce_n == 0)
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ram[addr] = data_in;
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end
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assign data_out = ram[addr];
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endmodule
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