30 lines
506 B
Verilog
30 lines
506 B
Verilog
/* 256x12 static ram */
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module ram_256x12(A, DI, DO, CE_N, WE_N);
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input [7:0] A;
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input [11:0] DI;
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input CE_N, WE_N;
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output [11:0] DO;
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reg [11:0] ram [0:255];
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integer i;
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initial
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begin
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for (i = 0; i < 256; i=i+1)
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ram[i] = 12'b0;
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end
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always @(WE_N or CE_N or A or DI)
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begin
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if (WE_N == 0 && CE_N == 0)
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begin
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ram[ A ] = DI;
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end
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end
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assign DO = ram[ A ];
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endmodule
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