102 lines
1.7 KiB
Verilog
102 lines
1.7 KiB
Verilog
// run.v
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`include "vga.v"
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`timescale 1ns / 1ns
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module test;
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reg clk, reset_n;
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wire [8:0] pixel;
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wire blank_n;
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wire hsync;
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wire vsync;
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reg ps2_clk;
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reg ps2_data;
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wire [7:0] led_data;
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vga vga(.reset_n(reset_n),
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.clock(clk25),
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.pixel(pixel),
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.blank_n(blank_n),
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.hsync(hsync),
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.vsync(vsync),
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.ps2_clk(ps2_clk),
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.ps2_data(ps2_data),
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.led_data(led_data));
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// clock divider by 4 to for a slower clock
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// uses grey code for minimized logic
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reg [1:0] gray_cnt;
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always @(posedge clk or negedge reset_n)
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if (~reset_n)
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gray_cnt <= 2'b00;
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else
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case (gray_cnt)
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2'b00: gray_cnt <= 2'b01;
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2'b01: gray_cnt <= 2'b11;
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2'b11: gray_cnt <= 2'b10;
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2'b10: gray_cnt <= 2'b00;
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default: gray_cnt <= 2'b00;
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endcase
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wire clk25;
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assign clk25 = gray_cnt[1];
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initial
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begin
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$timeformat(-9, 0, "ns", 7);
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$dumpfile("vga.vcd");
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// $dumpvars(0, test.vga);
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$dumpvars(0, test);
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end
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initial
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begin
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clk = 0;
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reset_n = 1;
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ps2_clk <= 0;
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ps2_data <= 0;
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#1 begin
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reset_n = 0;
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end
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#100 begin
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reset_n = 1;
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end
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#400000
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begin
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vga.scancode_convert.strobe_out = 1;
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vga.crt_data = 8'h41;
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vga.scancode_convert.ascii = 8'h41;
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end
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#200 vga.scancode_convert.strobe_out = 0;
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#400
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begin
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vga.scancode_convert.strobe_out = 1;
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vga.crt_data = 8'h42;
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vga.scancode_convert.ascii = 8'h42;
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end
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#200 vga.scancode_convert.strobe_out = 0;
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// #100000 $finish;
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// #500000 $finish;
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// #1000000 $finish;
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#20000000 $finish;
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end
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always
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begin
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#5 clk = 0;
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#5 clk = 1;
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end
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endmodule
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