48 lines
814 B
Verilog
48 lines
814 B
Verilog
/* 256x12 static ram */
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module ram_256x12(clk, reset, a, din, dout, ce, we);
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input clk;
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input reset;
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input [7:0] a;
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input [11:0] din;
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input ce, we;
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output [11:0] dout;
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reg [11:0] ram [0:255];
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// synthesis translate_off
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integer i;
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`ifdef debug
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integer ram_debug;
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`endif
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initial
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begin
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for (i = 0; i < 256; i=i+1)
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ram[i] = 12'b0;
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end
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// synthesis translate_on
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always @(posedge clk)
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begin
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if (we && ce)
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begin
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`ifdef debug
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if (ram_debug)
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$display("rf: buffer ram write [%o] <- %o", a, din);
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`endif
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ram[a] = din;
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end
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`ifdef debug
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if (ram_debug && we == 0 && ce == 1)
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$display("rf: buffer ram read [%o] -> %o", a, ram[a]);
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`endif
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end
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assign dout = ram[a];
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endmodule
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