36 lines
749 B
Makefile
36 lines
749 B
Makefile
#CVER_FLAGS = +loadvpi=../pli/ide/pli_ide.so:vpi_compat_bootstrap
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CVER_FLAGS =
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RTESTS = test_tt test_rf test_io
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#---------------------------------------------------------------------
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define runone_verilog_regression
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cver $(CVER_FLAGS) $(1) >$(2);
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@if grep -q ERROR $(2); then exit 1; fi;
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@if grep -q FAILURE $(2); then exit 1; fi;
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endef
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RTEST_LOGS = $(addsuffix .log,$(RTESTS))
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$(RTEST_LOGS) : %.log : %.v $(RTL)
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$(call runone_verilog_regression,$<,$@)
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# verilog testbench regression tests
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rgress: $(RTEST_LOGS)
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test_tt: test_tt.v
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$(call runone_verilog_regression,$<,$@)
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test_rf: test_rf.v
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$(call runone_verilog_regression,$<,$@)
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test_io: test_io.v
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$(call runone_verilog_regression,$<,$@)
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#
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clean:
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rm -f verilog.log
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rm -f *.vcd
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