21 lines
316 B
Verilog
21 lines
316 B
Verilog
//
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module pdp8_ram(clk, reset, addr, data_in, data_out, rd, wr);
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input clk;
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input reset;
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input [14:0] addr;
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input [11:0] data_in;
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output [11:0] data_out;
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input rd;
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input wr;
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ram_32kx12 ram(.A(addr),
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.DI(data_in),
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.DO(data_out),
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.CE_N(1'b0),
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.WE_N(~wr));
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endmodule
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