177 lines
4.2 KiB
Verilog
177 lines
4.2 KiB
Verilog
//
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// pdp-8/i in verilog - fpga top level
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// copyright Brad Parker <brad@heeltoe.com> 2009-2010
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//
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`timescale 1ns / 1ns
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module top(rs232_txd, rs232_rxd,
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button, led, sysclk,
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sevenseg, sevenseg_an,
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slideswitch,
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ram_a, ram_oe_n, ram_we_n,
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ram1_io, ram1_ce_n, ram1_ub_n, ram1_lb_n,
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ram2_io, ram2_ce_n, ram2_ub_n, ram2_lb_n,
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ide_data_bus, ide_dior, ide_diow, ide_cs, ide_da);
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output rs232_txd;
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input rs232_rxd;
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input [3:0] button;
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output [7:0] led;
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input sysclk;
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output [7:0] sevenseg;
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output [3:0] sevenseg_an;
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input [7:0] slideswitch;
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output [17:0] ram_a;
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output ram_oe_n;
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output ram_we_n;
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inout [15:0] ram1_io;
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output ram1_ce_n;
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output ram1_ub_n;
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output ram1_lb_n;
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inout [15:0] ram2_io;
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output ram2_ce_n;
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output ram2_ub_n;
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output ram2_lb_n;
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inout [15:0] ide_data_bus;
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output ide_dior, ide_diow;
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output [1:0] ide_cs;
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output [2:0] ide_da;
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// -----------------------------------------------------------------
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`define slower
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`ifdef slower
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reg clk;
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reg [24:0] clkdiv;
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wire [24:0] clkmax;
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assign clkmax = (slideswitch[3:0] == 4'd0) ? 25'h1 :
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(slideswitch[3:0] == 4'd1) ? 25'h2 :
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(slideswitch[3:0] == 4'd2) ? 25'h1ff :
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(slideswitch[3:0] == 4'd3) ? 25'h7ff :
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(slideswitch[3:0] == 4'd4) ? 25'h1fff :
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(slideswitch[3:0] == 4'd5) ? 25'h7fff :
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(slideswitch[3:0] == 4'd6) ? 25'h1ffff :
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(slideswitch[3:0] == 4'd7) ? 25'h7ffff :
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(slideswitch[3:0] == 4'd8) ? 25'h1fffff :
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(slideswitch[3:0] == 4'd9) ? 25'h3fffff :
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(slideswitch[3:0] == 4'd10) ? 25'h7fffff :
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(slideswitch[3:0] == 4'd11) ? 25'hffffff :
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25'h1ffffff;
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always @(posedge sysclk)
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begin
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if (clkdiv == clkmax)
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begin
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clk <= ~clk;
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clkdiv <= 0;
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end
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else
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clkdiv <= clkdiv + 25'b1;
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end
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`else
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wire clk;
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assign clk = sysclk;
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`endif
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// -------------------------------------------------------------
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reg [11:0] switches;
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wire reset;
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wire [11:0] ram_data_in;
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wire ram_rd;
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wire ram_wr;
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wire [11:0] ram_data_out;
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wire [14:0] ram_addr;
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wire [11:0] io_data_in;
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wire [11:0] io_data_out;
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wire [11:0] io_addr;
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wire io_data_avail;
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wire io_interrupt;
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wire io_skip;
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wire [5:0] io_select;
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wire iot;
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wire [3:0] state;
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wire [11:0] mb;
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wire ext_ram_read_req;
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wire ext_ram_write_req;
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wire [14:0] ext_ram_ma;
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wire [11:0] ext_ram_in;
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wire ext_ram_done;
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wire [11:0] ext_ram_out;
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debounce reset_sw(.clk(sysclk), .in(button[3]), .out(reset));
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// display show_pc(.clk(sysclk), .reset(reset),
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// .pc(pc), .dots(pc[15:12]),
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// .led(oled[3:0]),
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// .sevenseg(sevenseg), .sevenseg_an(sevenseg_an));
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// assign led = {rk_state, trapped, waited, halted};
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pdp8 cpu(.clk(clk),
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.reset(reset),
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.ram_addr(ram_addr),
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.ram_data_in(ram_data_out),
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.ram_data_out(ram_data_in),
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.ram_rd(ram_rd),
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.ram_wr(ram_wr),
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.state(state),
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.io_select(io_select),
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.io_data_in(io_data_in),
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.io_data_out(io_data_out),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.io_clear_ac(io_clear_ac),
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.iot(iot),
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.mb(mb),
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.switches(switches),
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.ext_ram_read_req(ext_ram_read_req),
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.ext_ram_write(ext_ram_write_req),
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.ext_ram_done(ext_ram_done),
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.ext_ram_ma(ext_ram_ma),
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.ext_ram_in(ext_ram_out),
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.ext_ram_out(ext_ram_in));
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pdp8_io io(.clk(clk),
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.reset(reset),
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.iot(iot),
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.state(state),
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.mb(mb),
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.io_data_in(io_data_out),
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.io_data_out(io_data_in),
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.io_select(io_select),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.io_clear_ac(io_clear_ac),
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.io_ram_read_req(ext_ram_read_req),
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.io_ram_write(ext_ram_write_req),
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.io_ram_done(ext_ram_done),
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.io_ram_ma(ext_ram_ma),
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.io_ram_in(ext_ram_in),
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.io_ram_out(ext_ram_out));
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pdp8_ram ram(.clk(clk),
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.reset(reset),
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.addr(ram_addr),
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.data_in(ram_data_in),
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.data_out(ram_data_out),
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.rd(ram_rd),
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.wr(ram_wr));
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endmodule
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