84 lines
1.7 KiB
Verilog
84 lines
1.7 KiB
Verilog
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module fake_ide(ide_dior, ide_diow, ide_cs, ide_da, ide_data_bus);
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input ide_dior;
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input ide_diow;
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input [1:0] ide_cs;
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input [2:0] ide_da;
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inout [15:0] ide_data_bus;
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reg [7:0] data_out;
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reg [7:0] cmd;
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reg [7:0] status;
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reg [7:0] drvhead;
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integer fifo;
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wire is_rd;
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wire is_wr;
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assign is_rd = ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
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assign is_wr = ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0);
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assign ide_data_bus = is_rd ? data_out : 12'bz;
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initial
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begin
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status = 8'h50;
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end
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always @(*)
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begin
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if (ide_dior == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
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begin
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if (ide_da != 0)
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#1 $display("ide r cs %b; da %b; bus %x",
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ide_cs, ide_da, ide_data_bus);
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case (ide_da)
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3'd0:
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begin
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if (fifo > 0)
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begin
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data_out = 0;
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fifo = fifo - 1;
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//$display("fifo %d", fifo);
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end
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if (fifo == 0)
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begin
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$display("ide empty!");
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status = 8'h50;
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cmd = 0;
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end
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end
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3'd7:
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data_out = status;
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endcase
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end
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if (ide_diow == 1'b0 && (ide_cs[0] == 1'b0 || ide_cs[1] == 1'b0))
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begin
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#1 $display("ide w cs %b; da %b; bus %x",
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ide_cs, ide_da, ide_data_bus);
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case (ide_da)
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3'd6:
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drvhead = ide_data_bus;
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3'd7:
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begin
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//release ide_data_bus;
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cmd = ide_data_bus;
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#1 $display("ide cmd %x", cmd);
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case (cmd)
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8'h20:
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begin
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status = 8'h58;
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fifo = 256;
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end
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endcase
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end
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endcase
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end
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end
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endmodule
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