181 lines
3.1 KiB
Verilog
181 lines
3.1 KiB
Verilog
// run_rf.v
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// testing top end for pdp8_rf.v
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//
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`include "../rtl/pdp8_rf.v"
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`include "../rtl/ide_disk.v"
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`include "../rtl/ide.v"
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`include "../rtl/ram_256x12.v"
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`include "../verif/fake_ide.v"
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`timescale 1ns / 1ns
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module test;
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reg clk, reset;
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wire [11:0] io_data_out;
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wire io_data_avail;
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wire io_interrupt;
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wire io_skip;
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wire ram_read_req;
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wire ram_write_req;
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reg ram_done;
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wire [14:0] ram_ma;
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wire [11:0] ram_out;
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reg [11:0] ram_in;
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reg [5:0] io_select;
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reg [11:0] io_data_in;
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reg iot;
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reg [3:0] state;
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reg [11:0] mb_in;
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wire ide_dior;
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wire ide_diow;
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wire [1:0] ide_cs;
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wire [2:0] ide_da;
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wire [15:0] ide_data_bus;
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fake_ide ide(.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da),
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.ide_data_bus(ide_data_bus));
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pdp8_rf rf(.clk(clk),
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.reset(reset),
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.iot(iot),
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.state(state),
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.mb(mb_in),
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.io_data_in(io_data_in),
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.io_data_out(io_data_out),
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.io_select(io_select),
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.io_data_avail(io_data_avail),
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.io_interrupt(io_interrupt),
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.io_skip(io_skip),
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.ram_read_req(ram_read_req),
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.ram_write_req(ram_write_req),
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.ram_done(ram_done),
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.ram_ma(ram_ma),
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.ram_in(ram_in),
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.ram_out(ram_out),
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.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da),
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.ide_data_bus(ide_data_bus));
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//
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task write_rf_reg;
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input [11:0] isn;
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input [11:0] data;
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begin
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@(posedge clk);
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begin
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state = 4'h0;
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mb_in = isn;
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io_select = isn[8:3];
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io_data_in = data;
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iot = 1;
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end
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#20 state = 4'h1;
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#20 state = 4'h2;
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#20 state = 4'h3;
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#20 begin
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state = 4'h0;
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iot = 0;
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end
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end
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endtask
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//
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task read_rf_reg;
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input [11:0] isn;
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output [11:0] data;
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begin
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@(posedge clk);
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begin
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state = 4'h0;
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mb_in = isn;
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io_select = isn[8:3];
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io_data_in = 0;
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iot = 1;
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end
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#20 state = 4'h1;
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#20 begin
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data = io_data_out;
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state = 4'h2;
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end
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#20 state = 4'h3;
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#20 begin
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state = 4'h0;
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iot = 0;
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end
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end
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endtask
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initial
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begin
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$timeformat(-9, 0, "ns", 7);
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$dumpfile("pdp8_rf.vcd");
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$dumpvars(0, test.rf);
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end
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reg [11:0] data;
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initial
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begin
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clk = 0;
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reset = 0;
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ram_done = 1;
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ram_in = 0;
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#1 begin
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reset = 1;
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end
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#50 begin
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reset = 0;
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end
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write_rf_reg(12'o6000, 12'o0000);
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write_rf_reg(12'o6601, 12'o0000);
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write_rf_reg(12'o6611, 12'o0000);
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write_rf_reg(12'o6615, 12'o0000);
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write_rf_reg(12'o6641, 12'o0000);
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write_rf_reg(12'o6643, 12'o0000);
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read_rf_reg(12'o6616, data);
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write_rf_reg(12'o6603, 12'o0000); // DMAR
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write_rf_reg(12'o6000, 12'o0000);
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write_rf_reg(12'o6000, 12'o0000);
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#40000 $finish;
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end
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always
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begin
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#10 clk = 0;
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#10 clk = 1;
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end
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//----
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integer cycle;
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initial
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cycle = 0;
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always @(posedge rf.clk)
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begin
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cycle = cycle + 1;
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end
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endmodule
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