119 lines
2.1 KiB
Verilog
119 lines
2.1 KiB
Verilog
// run_top.v
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// testing top end for pdp8.v
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//
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`include "../rtl/pdp8_tt.v"
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`include "../rtl/pdp8_rf.v"
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`include "../rtl/pdp8_io.v"
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`include "../rtl/pdp8_ram.v"
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`include "../rtl/pdp8.v"
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`include "../rtl/top.v"
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`include "../rtl/ram_32kx12.v"
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`include "../rtl/ram_256x12.v"
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`include "../rtl/debounce.v"
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`timescale 1ns / 1ns
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module test;
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wire rs232_txd;
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wire rs232_rxd;
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reg [3:0] button;
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wire [7:0] led;
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reg sysclk;
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wire [7:0] sevenseg;
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wire [3:0] sevenseg_an;
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reg [7:0] slideswitch;
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wire [17:0] ram_a;
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wire ram_oe_n;
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wire ram_we_n;
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wire [15:0] ram1_io;
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wire ram1_ce_n;
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wire ram1_ub_n;
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wire ram1_lb_n;
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wire [15:0] ram2_io;
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wire ram2_ce_n;
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wire ram2_ub_n;
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wire ram2_lb_n;
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wire [15:0] ide_data_bus;
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wire ide_dior, ide_diow;
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wire [1:0] ide_cs;
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wire [2:0] ide_da;
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top top(.rs232_txd(rs232_txd),
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.rs232_rxd(rs232_rxd),
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.button(button),
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.led(led),
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.sysclk(sysclk),
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.sevenseg(sevenseg),
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.sevenseg_an(sevenseg_an),
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.slideswitch(slideswitch),
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.ram_a(ram_a),
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.ram_oe_n(ram_oe_n),
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.ram_we_n(ram_we_n),
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.ram1_io(ram1_io),
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.ram1_ce_n(ram1_ce_n),
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.ram1_ub_n(ram1_ub_n),
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.ram1_lb_n(ram1_lb_n),
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.ram2_io(ram2_io),
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.ram2_ce_n(ram2_ce_n),
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.ram2_ub_n(ram2_ub_n),
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.ram2_lb_n(ram2_lb_n),
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.ide_data_bus(ide_data_bus),
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.ide_dior(ide_dior),
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.ide_diow(ide_diow),
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.ide_cs(ide_cs),
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.ide_da(ide_da));
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initial
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begin
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$timeformat(-9, 0, "ns", 7);
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$dumpfile("pdp8.vcd");
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$dumpvars(0, test.top);
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end
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initial
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begin
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sysclk = 0;
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#3000000 $finish;
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end
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always
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begin
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#10 sysclk = 0;
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#10 sysclk = 1;
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end
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//----
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integer cycle;
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initial
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cycle = 0;
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always @(posedge top.cpu.clk)
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if (top.cpu.state == 4'b0000)
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begin
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cycle = cycle + 1;
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#1 $display("pc %o ir %o l %b ac %o ion %o",
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top.cpu.pc, top.cpu.mb, top.cpu.l, top.cpu.ac,
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top.cpu.interrupt_enable);
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if (top.cpu.state == 4'b1100)
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$finish;
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end
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endmodule
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