mirror of
https://github.com/livingcomputermuseum/ContrAlto.git
synced 2026-05-04 23:16:24 +00:00
Ethernet implemented, fixed a bug in "mixed" double word stores (store followed by fetch rather than two stores). Fixed a few UI issues, fixed Reset behavior.
This commit is contained in:
Josh Dersch
258
Contralto/IO/EthernetController.cs
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258
Contralto/IO/EthernetController.cs
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using Contralto.CPU;
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using Contralto.Logging;
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using System;
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using System.Collections.Generic;
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using System.Linq;
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using System.Text;
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using System.Threading.Tasks;
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namespace Contralto.IO
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{
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public class EthernetController
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{
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public EthernetController(AltoSystem system)
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{
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_system = system;
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// TODO: make this configurable
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_ethernetAddress = 0x22;
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_fifo = new Queue<ushort>();
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Reset();
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_fifoWakeupEvent = new Event(_fifoTransmitDuration, null, FIFOCallback);
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}
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public void Reset()
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{
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ResetInterface();
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}
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public byte Address
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{
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get { return _ethernetAddress; }
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}
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/// <summary>
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/// The ICMD and OCMD flip-flops, combined into a single value
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/// as written by STARTF.
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/// (bit 15 = OCMD, bit 14 = ICMD)
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/// </summary>
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public int IOCMD
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{
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get { return _ioCmd; }
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}
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public bool FIFOEmpty
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{
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get { return _fifo.Count == 0; }
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}
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public bool OperationDone
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{
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get { return !_oBusy && !_iBusy; }
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}
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public bool Collision
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{
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get { return _collision; }
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}
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public bool DataLate
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{
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get { return _dataLate; }
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}
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public ushort Status
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{
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get
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{
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return _status;
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}
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}
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public bool CountdownWakeup
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{
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get { return _countdownWakeup; }
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set { _countdownWakeup = value; }
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}
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public void ResetInterface()
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{
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// Latch status before resetting
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_status = (ushort)(
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(0xffc0) | // bits always set
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(_dataLate ? 0x00 : 0x20) |
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(_collision ? 0x00 : 0x10) |
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(_crcBad ? 0x00 : 0x08) |
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((~_ioCmd & 0x3) << 1) |
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(_incomplete ? 0x00 : 0x01));
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_ioCmd = 0;
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_oBusy = false;
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_iBusy = false;
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_dataLate = false;
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_collision = false;
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_crcBad = false;
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_incomplete = false;
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_fifo.Clear();
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if (_system.CPU != null)
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{
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_system.CPU.BlockTask(TaskType.Ethernet);
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}
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Log.Write(LogComponent.EthernetController, "Interface reset.");
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}
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public ushort ReadInputFifo(bool lookOnly)
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{
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if (FIFOEmpty)
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{
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Log.Write(LogComponent.EthernetController, "Read from empty Ethernet FIFO, returning 0.");
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return 0;
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}
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if (lookOnly)
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{
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return _fifo.Peek();
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}
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else
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{
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return _fifo.Dequeue();
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}
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}
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public void WriteOutputFifo(ushort data)
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{
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if (_fifo.Count == 16)
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{
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Log.Write(LogComponent.EthernetController, "Write to full Ethernet FIFO, losing first entry.");
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_fifo.Dequeue();
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}
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_fifo.Enqueue(data);
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// If the FIFO is full, start transmitting and clear Wakeups
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if (_fifo.Count == 16)
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{
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if (_oBusy)
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{
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TransmitFIFO(false /* not end */);
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}
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_system.CPU.BlockTask(TaskType.Ethernet);
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}
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Log.Write(LogComponent.EthernetController, "FIFO written with {0}, length now {1}", data, _fifo.Count);
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}
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public void StartOutput()
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{
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// Sets the OBusy flip-flop in the interface
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_oBusy = true;
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// Enables wakeups to fill the FIFO
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_system.CPU.WakeupTask(TaskType.Ethernet);
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Log.Write(LogComponent.EthernetController, "Output started.");
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}
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public void StartInput()
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{
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InitializeReceiver();
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Log.Write(LogComponent.EthernetController, "Input started.");
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}
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public void EndTransmission()
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{
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// Clear FIFO wakeup and transmit the remainder of the data in the FIFO
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TransmitFIFO(true /* end */);
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_system.CPU.BlockTask(TaskType.Ethernet);
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Log.Write(LogComponent.EthernetController, "Transmission ended.");
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}
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public void STARTF(ushort busData)
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{
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Log.Write(LogComponent.EthernetController, "Ethernet STARTF {0}", Conversion.ToOctal(busData));
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//
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// HW Manual, p. 54:
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// "The emulator task sets [the ICMD and OCMD flip flops] from BUS[14 - 15] with
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// the STARTF function, causing the Ethernet task to wakeup, dispatch on them
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// and then reset them with EPFCT."
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//
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_ioCmd = busData & 0x3;
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_system.CPU.WakeupTask(TaskType.Ethernet);
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}
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private void TransmitFIFO(bool end)
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{
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// Schedule a callback to pick up the data and shuffle it out the host interface.
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_fifoWakeupEvent.Context = end;
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_fifoWakeupEvent.TimestampNsec = _fifoTransmitDuration;
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_system.Scheduler.Schedule(_fifoWakeupEvent);
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}
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private void FIFOCallback(ulong timeNsec, ulong skewNsec, object context)
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{
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bool end = (bool)context;
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if (!_oBusy)
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{
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// If OBUSY is no longer set then the interface was reset before
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// we got to run; abandon this operation.
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Log.Write(LogComponent.EthernetController, "FIFO callback after reset, abandoning.");
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return;
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}
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Log.Write(LogComponent.EthernetController, "Sending {0} words from fifo.", _fifo.Count);
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// TODO: actually transmit data in FIFO rather than bit-bucketing it.
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_fifo.Clear();
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if (!end)
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{
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// Enable FIFO microcode wakeups for next batch of data
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_system.CPU.WakeupTask(TaskType.Ethernet);
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}
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else
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{
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// This is the last of the data, clear the OBUSY flipflop, the transmitter is done.
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Log.Write(LogComponent.EthernetController, "Packet complete.");
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_oBusy = false;
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// Wakeup at end of transmission. ("OUTGONE Post wakeup.")
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_system.CPU.WakeupTask(TaskType.Ethernet);
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}
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}
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private void InitializeReceiver()
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{
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// TODO: pull next packet off host ethernet interface that's destined for the Alto, and start the
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// process of putting into the FIFO and generating wakeups for the microcode.
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}
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private Queue<ushort> _fifo;
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// Bits in Status register
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private int _ioCmd;
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private bool _dataLate;
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private bool _collision;
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private bool _crcBad;
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private bool _incomplete;
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private ushort _status;
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private byte _ethernetAddress;
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private bool _countdownWakeup;
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private bool _oBusy;
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private bool _iBusy;
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// FIFO scheduling
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private ulong _fifoTransmitDuration = 87075; // ~87000 nsec to transmit 16 words at 3mbit, assuming no collision
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private Event _fifoWakeupEvent;
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private AltoSystem _system;
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}
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}
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