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Improvements to Disk Word Task.
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@@ -1,5 +1,53 @@
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Current issue:
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9/15/15:
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Current issue:
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DCB @ 521 is set to 1 by emulator uCode; then clobbered once sector task runs (set to zero) so the disk controller never picks up a control
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block and never does anything.
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9/16:
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"solved" previous issue by issuing a Wake for the KS task on init; this causes the sector task to run first, the Emulator uCode then sets things up correctly.
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Not sure if this is how it's supposed to work.
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New issue: Emulator uCode sets up a DCB starting at 1 that looks like:
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DCB: 1 <next DCB, not really used here since it will be overwritten by the sector that gets read in -- ALSO a JMP 1 instruction the EMU task is running continuously!>
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DCB+1: 1 <status: meaningless, just a placeholder and will be overwritten by the KS/KW tasks>
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DCB+2: 44000 <command: read header, label, and data off of drive zero>
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DCB+3: 402 <header address: 402>
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DCB+4: 402 <label address: 402>
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DCB+5: 1 <data address: 1 -- overwrite this very data and the short jump that the CPU is executing at 1 (JMP 1) such that the emulator will start running a real program at 1 when loaded>
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.
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.
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.
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.
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.
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DCB+9: 0
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The sector task is noting when sector 0 comes around, and the word task is getting woken up -- at which point it seems to be miscalculating the memory address for disk data (in KNMAR/KNMARW, reg 33).
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This ends up being 177777 (-1) and this causes issues. KNMAR is shared between the sector and word tasks (it's KNMARW in the word task) and is set up by the sector task -- this setup code is not running,
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leaving R33 at 0; later 1 is subtracted and we hit our problem.
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KNMAR is loaded at KS 01153, this appears to be where we're going wrong (other places in the word task repurpose it for a counter, except for KW01746 which just decrements it)
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NO, the above is incorrect. See below...
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KNMARW is loaded at:
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KW 01665 (in prep to use as length register for record 0 (header))
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KW 01732 (same, for records 1 and 2)
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KW 01742 in prep for loading something...
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KW 01746 at the beginning of the transfer loop as an address, just decrementing it
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At KW1732 we load in the memory block for the record.
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KNMARW is used as a count
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at REC12A, we load L with the memory block address and load it into KWDCTW (R31) -- KWDX loads this into L, and then puts it into KNMARW.
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We are never reaching KW1732 -- why?
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10/19/15:
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Current issues are around how the "INIT" mode of RWC works (the mysterious fourth dispatch mode aside from Read/Write or Check).
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The logic is
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