Josh Dersch
|
6429c3ae7a
|
General code cleanup. Fixed debugger display of RAM banks for 3K systems, cleaned up logic for displaying ucode memory. Implemented memory timing for Alto I systems, incorporated Alto I uCode ROMs from Al K, which now boot. ST-74 runs better now.
|
2016-05-05 18:56:29 -07:00 |
|
Josh Dersch
|
a62ac823ed
|
Initial implementation of Alto I support. Still need proper Constants ROM for Alto I. Changed IDISP to use ACSOURCE ROM (small perf increase).
|
2016-04-13 15:45:33 -07:00 |
|
Josh Dersch
|
cbcfd2b47e
|
Minor bugfixes, introduced a new timing infrastructure and moved DiskController over to it. Minor performance improvements; now running at 110% speed. Display timing is still too slow.
|
2015-11-17 16:09:50 -08:00 |
|
Josh Dersch
|
c0f23685b1
|
Fixed instruction register decoding SFs for Emulator Task; first stab at handling (most) DNS<- operations including setting SKIP and CARRY flip flops. BLT now succeeds, Nova code in bootstrap is running.
|
2015-10-29 17:02:22 -07:00 |
|
Josh Dersch
|
2918ede7ce
|
Some fixes to emulator task dispatch functions, added Nova disassembler, nova instruction single-step and nova instruction breakpoint support. Penciled in DNS (Nova Shift) support in emulator task. Added skeleton for Logging.
|
2015-10-28 14:11:04 -07:00 |
|
Josh Dersch
|
ee7c7fb035
|
Implemented more Disk functionality, fixed bug in ACSOURCE dispatch in Emulator task.
|
2015-09-16 16:27:16 -07:00 |
|
Josh Dersch
|
59d98d1909
|
Refinement to CPU, implemented very rough diassembler and began annotation of official Xerox ucode sources with PROM addresses.
|
2015-08-28 18:07:59 -07:00 |
|
Josh Dersch
|
f1ffcb0547
|
Implemented ALU, most of Memory state machine.
|
2015-08-20 18:02:01 -07:00 |
|
Josh Dersch
|
3b77ba875d
|
Sketching in the rest of the CPU
|
2015-08-19 16:50:40 -07:00 |
|