mirror of
https://github.com/livingcomputermuseum/ContrAlto.git
synced 2026-01-17 00:23:24 +00:00
382 lines
13 KiB
C#
382 lines
13 KiB
C#
using Contralto.Logging;
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using System;
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using System.IO;
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namespace Contralto.CPU
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{
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public enum MicrocodeBank
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{
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ROM0 = 0,
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ROM1 = 1,
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RAM0 = 2,
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RAM1 = 3,
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RAM2 = 4
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}
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struct RomFile
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{
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public RomFile(string filename, ushort addr, int bitPosition)
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{
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Filename = filename;
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StartingAddress = addr;
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BitPosition = bitPosition;
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}
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public string Filename;
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public ushort StartingAddress;
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public int BitPosition;
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}
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static class UCodeMemory
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{
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static UCodeMemory()
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{
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Init();
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}
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public static void Reset()
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{
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Init();
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}
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private static void Init()
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{
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//
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// Max 3 banks of microcode RAM
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_uCodeRam = new UInt32[1024 * 3];
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LoadMicrocode(_uCodeRoms);
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//
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// Cache 5k of instructions: max 2K ROM, 3K RAM.
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_decodeCache = new MicroInstruction[1024 * 5];
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// Precache ROM
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CacheMicrocodeROM();
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// Precache (empty) RAM
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for(ushort i=0;i<_uCodeRam.Length;i++)
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{
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UpdateRAMCache(i);
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}
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// Start in ROM0
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_microcodeBank = new MicrocodeBank[16];
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_ramAddr = 0;
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_ramBank = 0;
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_ramSelect = true;
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_lowHalfsel = true;
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}
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public static void LoadBanksFromRMR(ushort rmr)
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{
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for(int i=0;i<16;i++)
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{
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_microcodeBank[i] = (rmr & (1 << i)) == 0 ? MicrocodeBank.RAM0 : MicrocodeBank.ROM0;
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}
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}
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/// <summary>
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/// Exposes the raw contents of the Microcode ROM
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/// </summary>
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public static UInt32[] UCodeROM
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{
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get { return _uCodeRom; }
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}
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/// <summary>
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/// Exposes the raw contents of the Microcode RAM
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/// </summary>
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public static UInt32[] UCodeRAM
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{
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get { return _uCodeRam; }
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}
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public static MicrocodeBank GetBank(TaskType task)
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{
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return _microcodeBank[(int)task];
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}
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public static void LoadControlRAMAddress(ushort address)
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{
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_ramBank = (address & 0x3000) >> 12;
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_ramSelect = (address & 0x0800) == 0;
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_lowHalfsel = (address & 0x0400) == 0;
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_ramAddr = (address & 0x3ff);
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// Clip RAM bank into range, it's always 0 unless we have a 3K uCode RAM system
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switch (Configuration.SystemType)
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{
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case SystemType.OneKRom:
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case SystemType.TwoKRom:
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_ramBank = 0;
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break;
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case SystemType.ThreeKRam:
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if (_ramBank > 2)
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{
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_ramBank = 2;
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}
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break;
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}
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}
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/// <summary>
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/// Implements the SWMODE F1 logic; selects the proper uCode bank (from
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/// RAM or ROM) based on the supplied NEXT value.
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/// Technically this is only supported for the Emulator task.
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/// </summary>
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/// <param name="nextAddress"></param>
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public static void SwitchMode(ushort nextAddress, TaskType task)
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{
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// Log.Write(Logging.LogComponent.Microcode, "SWMODE: Current Bank {0}", _microcodeBank[(int)task]);
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switch (Configuration.SystemType)
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{
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case SystemType.OneKRom:
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_microcodeBank[(int)task] = _microcodeBank[(int)task] == MicrocodeBank.ROM0 ? MicrocodeBank.RAM0 : MicrocodeBank.ROM0;
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break;
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case SystemType.TwoKRom:
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switch (_microcodeBank[(int)task])
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{
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case MicrocodeBank.ROM0:
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_microcodeBank[(int)task] = (nextAddress & 0x100) == 0 ? MicrocodeBank.RAM0 : MicrocodeBank.ROM1;
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break;
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case MicrocodeBank.ROM1:
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_microcodeBank[(int)task] = (nextAddress & 0x100) == 0 ? MicrocodeBank.ROM0 : MicrocodeBank.RAM0;
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break;
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case MicrocodeBank.RAM0:
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_microcodeBank[(int)task] = (nextAddress & 0x100) == 0 ? MicrocodeBank.ROM0 : MicrocodeBank.ROM1;
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break;
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}
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break;
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case SystemType.ThreeKRam:
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if ((nextAddress & 0x100) == 0)
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{
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switch(_microcodeBank[(int)task])
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{
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case MicrocodeBank.ROM0:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.RAM0 : MicrocodeBank.RAM2;
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break;
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case MicrocodeBank.RAM0:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.ROM0 : MicrocodeBank.RAM2;
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break;
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case MicrocodeBank.RAM1:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.ROM0 : MicrocodeBank.RAM2;
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break;
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case MicrocodeBank.RAM2:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.ROM0 : MicrocodeBank.RAM1;
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break;
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}
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}
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else
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{
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switch (_microcodeBank[(int)task])
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{
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case MicrocodeBank.ROM0:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.RAM1 : MicrocodeBank.RAM0;
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break;
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case MicrocodeBank.RAM0:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.RAM1 : MicrocodeBank.RAM1;
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break;
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case MicrocodeBank.RAM1:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.RAM0 : MicrocodeBank.RAM0;
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break;
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case MicrocodeBank.RAM2:
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_microcodeBank[(int)task] = (nextAddress & 0x80) == 0 ? MicrocodeBank.RAM0 : MicrocodeBank.RAM0;
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break;
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}
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}
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break;
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}
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// Log.Write(Logging.LogComponent.Microcode, "SWMODE: New Bank {0} for Task {1}", _microcodeBank[(int)task], task);
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}
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public static ushort ReadRAM()
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{
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if (!_ramSelect)
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{
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throw new NotImplementedException("Read from microcode ROM not implemented.");
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}
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Log.Write(Logging.LogComponent.Microcode, "CRAM address for read: Bank {0}, RAM {1}, lowhalf {2} addr {3}",
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_ramBank,
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_ramSelect,
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_lowHalfsel,
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Conversion.ToOctal(_ramAddr));
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UInt32 data = MapRAMWord(_uCodeRam[_ramAddr + (_ramBank * 1024)]);
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// Flip the necessary bits before returning them.
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// (See table in section 8.3 of HWRef.)
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ushort halfWord = (ushort)(_lowHalfsel ? data : (data >> 16));
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Log.Write(Logging.LogComponent.Microcode, "CRAM data read: {0}-{1}",
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_lowHalfsel ? "low" : "high",
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Conversion.ToOctal(halfWord));
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return halfWord;
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}
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public static void WriteRAM(ushort low, ushort high)
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{
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if (!_ramSelect)
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{
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// No-op, can't write to ROM.
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return;
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}
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/*
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Log.Write(Logging.LogComponent.Microcode, "CRAM address for write: Bank {0}, addr {1}",
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_ramBank,
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Conversion.ToOctal(_ramAddr));
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Log.Write(Logging.LogComponent.Microcode, "CRAM write of low {0}, high {1}",
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Conversion.ToOctal(low),
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Conversion.ToOctal(high));
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*/
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ushort address = (ushort)(_ramAddr + _ramBank * 1024);
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_uCodeRam[address] = MapRAMWord(((UInt32)(high) << 16) | low);
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UpdateRAMCache(address);
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}
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/// <summary>
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/// Retrieve the microinstruction for the given address using the currently
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/// selected memory bank.
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/// </summary>
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/// <param name="address"></param>
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/// <returns></returns>
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public static MicroInstruction GetInstruction(ushort address, TaskType task)
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{
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return _decodeCache[address + (int)_microcodeBank[(int)task] * 1024];
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}
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private static void LoadMicrocode(RomFile[] romInfo)
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{
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_uCodeRom = new UInt32[2048];
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foreach(RomFile file in romInfo)
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{
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//
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// Each file contains 1024 bytes, each byte containing one nybble in the low 4 bits.
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//
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using(FileStream fs = new FileStream(Path.Combine("ROM", file.Filename), FileMode.Open, FileAccess.Read))
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{
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int length = (int)fs.Length;
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if (length != 1024)
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{
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throw new InvalidOperationException("ROM file should be 1024 bytes in length");
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}
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byte[] data = new byte[fs.Length];
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fs.Read(data, 0, (int)fs.Length);
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// OR in the data
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for(int i=0;i<length;i++)
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{
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_uCodeRom[file.StartingAddress + i] |= (uint)((data[AddressMap(i)] & 0xf) << file.BitPosition);
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}
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}
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}
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for(int i=0;i<_uCodeRom.Length;i++)
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{
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_uCodeRom[i] = MapWord(_uCodeRom[i]);
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}
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}
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private static UInt32 MapWord(UInt32 word)
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{
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// Invert the requisite bits just to make things easier; the high bits of F1 and F2 and the Load L bit are inverted
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// already; we leave those alone.
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const UInt32 invertedBitMask = 0xfff77bff;
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UInt32 masked = word & ~invertedBitMask;
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word = ((~word) & invertedBitMask) | masked;
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return word;
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}
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private static UInt32 MapRAMWord(UInt32 word)
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{
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// Invert the requisite bits just to make things easier; the high bits of F1 and F2 and the Load L bit are inverted
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// already; we leave those alone.
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const UInt32 bitMask = 0x00088400;
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word ^= bitMask;
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return word;
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}
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private static int AddressMap(int address)
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{
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int mappedAddress = (~address) & 0x3ff;
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return mappedAddress;
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}
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private static void CacheMicrocodeROM()
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{
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for(int i=0;i<_uCodeRom.Length;i++)
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{
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_decodeCache[i] = new MicroInstruction(_uCodeRom[i]);
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}
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}
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private static void UpdateRAMCache(ushort address)
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{
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UInt32 instructionWord = _uCodeRam[address];
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_decodeCache[2048 + address] = new MicroInstruction(instructionWord);
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}
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private static RomFile[] _uCodeRoms =
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{
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// first K
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new RomFile("u55", 0x000, 28),
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new RomFile("u64", 0x000, 24),
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new RomFile("u65", 0x000, 20),
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new RomFile("u63", 0x000, 16),
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new RomFile("u53", 0x000, 12),
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new RomFile("u60", 0x000, 8),
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new RomFile("u61", 0x000, 4),
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new RomFile("u62", 0x000, 0),
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// second K
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new RomFile("u54", 0x400, 28),
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new RomFile("u74", 0x400, 24),
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new RomFile("u75", 0x400, 20),
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new RomFile("u73", 0x400, 16),
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new RomFile("u52", 0x400, 12),
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new RomFile("u70", 0x400, 8),
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new RomFile("u71", 0x400, 4),
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new RomFile("u72", 0x400, 0)
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};
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private static UInt32[] _uCodeRom;
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private static UInt32[] _uCodeRam;
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private static MicroInstruction[] _decodeCache;
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private static MicrocodeBank[] _microcodeBank;
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private static int _ramBank;
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private static bool _ramSelect;
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private static bool _lowHalfsel;
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private static int _ramAddr;
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}
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}
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