mirror of
https://github.com/livingcomputermuseum/ContrAlto.git
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394 lines
18 KiB
C#
394 lines
18 KiB
C#
using System;
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namespace Contralto.CPU
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{
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public partial class AltoCPU
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{
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/// <summary>
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/// EmulatorTask provides emulator (NOVA instruction set) specific operations.
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/// </summary>
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private sealed class EmulatorTask : Task
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{
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public EmulatorTask(AltoCPU cpu) : base(cpu)
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{
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_taskType = TaskType.Emulator;
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// The Wakeup signal is always true for the Emulator task.
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_wakeup = true;
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}
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public override void BlockTask()
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{
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throw new InvalidOperationException("The emulator task cannot be blocked.");
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}
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public override void WakeupTask()
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{
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throw new InvalidOperationException("The emulator task is always in wakeup state.");
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}
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protected override ushort GetBusSource(int bs)
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{
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EmulatorBusSource ebs = (EmulatorBusSource)bs;
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switch (ebs)
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{
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case EmulatorBusSource.ReadSLocation:
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if (_rSelect != 0)
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{
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return _cpu._s[_cpu._rb][_rSelect];
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}
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else
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{
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// "...when reading data from the S registers onto the processor bus,
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// the RSELECT value 0 causes the current value of the M register to
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// appear on the bus..."
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return _cpu._m;
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}
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case EmulatorBusSource.LoadSLocation:
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_loadS = true;
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return 0; // TODO: technically this is an "undefined value," not zero.
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default:
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throw new InvalidOperationException(String.Format("Unhandled bus source {0}", bs));
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}
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}
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protected override void ExecuteSpecialFunction1(MicroInstruction instruction)
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{
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EmulatorF1 ef1 = (EmulatorF1)instruction.F1;
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switch (ef1)
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{
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case EmulatorF1.RSNF:
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// TODO: make configurable
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// "...decoded by the Ethernet interface, which gates the host address wired on the
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// backplane onto BUS[8-15]. BUS[0-7] is not driven and will therefore be -1. If
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// no Ethernet interface is present, BUS will be -1.
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//
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_busData &= (0xff00 | 0x42);
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break;
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case EmulatorF1.STARTF:
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// Dispatch function to Ethernet I/O based on contents of AC0... (TBD: what are these?)
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// For now do nothing, since we have no Ethernet implemented
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//throw new NotImplementedException();
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break;
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case EmulatorF1.SWMODE:
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_swMode = true;
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break;
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case EmulatorF1.RDRAM:
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_rdRam = true;
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break;
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case EmulatorF1.WRTRAM:
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_wrtRam = true;
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break;
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default:
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throw new InvalidOperationException(String.Format("Unhandled emulator F1 {0}.", ef1));
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}
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}
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protected override void ExecuteSpecialFunction2Early(MicroInstruction instruction)
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{
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EmulatorF2 ef2 = (EmulatorF2)instruction.F2;
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switch (ef2)
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{
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case EmulatorF2.ACSOURCE:
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// Early: modify R select field:
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// "...it replaces the two-low order bits of the R select field with
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// the complement of the SrcAC field of IR, (IR[1-2] XOR 3), allowing the emulator
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// to address its accumulators (which are assigned to R0-R3)."
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_rSelect = (_rSelect & 0xfffc) | ((((uint)_cpu._ir & 0x6000) >> 13) ^ 3);
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break;
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case EmulatorF2.ACDEST:
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// "...causes (IR[3-4] XOR 3) to be used as the low-order two bits of the RSELECT field.
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// This address the accumulators from the destination field of the instruction. The selected
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// register may be loaded or read."
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_rSelect = (_rSelect & 0xfffc) | ((((uint)_cpu._ir & 0x1800) >> 11) ^ 3);
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break;
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case EmulatorF2.LoadDNS:
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//
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// "...DNS also addresses R from (3-IR[3 - 4])..."
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//
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_rSelect = (_rSelect & 0xfffc) | ((((uint)_cpu._ir & 0x1800) >> 11) ^ 3);
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break;
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}
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}
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protected override void ExecuteSpecialFunction2(MicroInstruction instruction)
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{
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EmulatorF2 ef2 = (EmulatorF2)instruction.F2;
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switch (ef2)
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{
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case EmulatorF2.LoadIR:
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// based on block diagram, this always comes from the bus
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_cpu._ir = _busData;
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// "IR<- also merges bus bits 0, 5, 6 and 7 into NEXT[6-9] which does a first level
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// instruction dispatch."
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// TODO: is this an AND or an OR operation? (how is the "merge" done?)
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// Assuming for now this is an OR operation like everything else that modifies NEXT.
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_nextModifier = (ushort)(((_busData & 0x8000) >> 12) | ((_busData & 0x0700) >> 8));
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// "IR<- clears SKIP"
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_skip = 0;
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break;
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case EmulatorF2.IDISP:
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// "The IDISP function (F2=15B) does a 16 way dispatch under control of a PROM and a
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// multiplexer. The values are tabulated below:
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// Conditions ORed onto NEXT Comment
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//
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// if IR[0] = 1 3-IR[8-9] complement of SH field of IR
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// elseif IR[1-2] = 0 IR[3-4] JMP, JSR, ISZ, DSZ ; dispatch selects register
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// elseif IR[1-2] = 1 4 LDA
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// elseif IR[1-2] = 2 5 STA
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// elseif IR[4-7] = 0 1
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// elseif IR[4-7] = 1 0
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// elseif IR[4-7] = 6 16B CONVERT
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// elseif IR[4-7] = 16B 6
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// else IR[4-7]
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// NB: as always, Xerox labels bits in the opposite order from modern convention;
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// (bit 0 is the msb...)
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if ((_cpu._ir & 0x8000) != 0)
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{
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_nextModifier = (ushort)(3 - ((_cpu._ir & 0xc0) >> 6));
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}
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else if ((_cpu._ir & 0x6000) == 0)
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{
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_nextModifier = (ushort)((_cpu._ir & 0x1800) >> 11);
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}
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else if ((_cpu._ir & 0x6000) == 0x2000)
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{
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_nextModifier = 4;
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}
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else if ((_cpu._ir & 0x6000) == 0x4000)
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{
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_nextModifier = 5;
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}
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else if ((_cpu._ir & 0x0f00) == 0)
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{
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_nextModifier = 1;
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}
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else if ((_cpu._ir & 0x0f00) == 0x0100)
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{
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_nextModifier = 0;
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}
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else if ((_cpu._ir & 0x0f00) == 0x0600)
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{
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_nextModifier = 0xe;
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}
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else if ((_cpu._ir & 0x0f00) == 0x0e00)
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{
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_nextModifier = 0x6;
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}
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else
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{
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_nextModifier = (ushort)((_cpu._ir & 0x0f00) >> 8);
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}
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break;
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case EmulatorF2.ACSOURCE:
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// Late:
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// "...a dispatch is performed:
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// Conditions ORed onto NEXT Comment
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//
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// if IR[0] = 1 3-IR[8-9] complement of SH field of IR
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// if IR[1-2] = 3 IR[5] the Indirect bit of R
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// if IR[3-7] = 0 2 CYCLE
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// if IR[3-7] = 1 5 RAMTRAP
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// if IR[3-7] = 2 3 NOPAR -- parameterless opcode group
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// if IR[3-7] = 3 6 RAMTRAP
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// if IR[3-7] = 4 7 RAMTRAP
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// if IR[3-7] = 11B 4 JSRII
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// if IR[3-7] = 12B 4 JSRIS
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// if IR[3-7] = 16B 1 CONVERT
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// if IR[3-7] = 37B 17B ROMTRAP -- used by Swat, the debugger
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// else 16B ROMTRAP
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//
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// NOTE: the above table from the Hardware Manual is incorrect (or at least incomplete / misleading).
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// There is considerably more that goes into determining the dispatch, which is controlled by a 256x8
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// PROM. We just use the PROM rather than implementing the above logic (because it works.)
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//
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if ((_cpu._ir & 0x8000) != 0)
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{
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// 3-IR[8-9] (shift field of arithmetic instruction)
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_nextModifier = (ushort)(3 - ((_cpu._ir & 0xc0) >> 6));
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}
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else
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{
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// Use the PROM.
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_nextModifier = ControlROM.ACSourceROM[((_cpu._ir & 0x7f00) >> 8)];
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}
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break;
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case EmulatorF2.ACDEST:
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// Handled in early handler, nothing to do here.
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break;
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case EmulatorF2.BUSODD:
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// "...merges BUS[15] into NEXT[9]."
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// TODO: is this an AND or an OR?
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_nextModifier |= (ushort)(_busData & 0x1);
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break;
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case EmulatorF2.MAGIC:
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Shifter.SetMagic(true);
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break;
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case EmulatorF2.LoadDNS:
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// DNS<- does the following:
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// - modifies the normal shift operations to perform Nova-style shifts (done here)
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// - addresses R from 3-IR[3-4] (destination AC) (see Early LoadDNS handler)
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// - stores into R unless IR[12] is set (done here)
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// - calculates Nova-style CARRY bit (done here)
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// - sets the SKIP and CARRY flip-flops appropriately (see Late LoadDNS handler)
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int carry = 0;
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// Also indicates modifying CARRY
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_loadR = (_cpu._ir & 0x0008) == 0;
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// At this point the ALU has already done its operation but the shifter has not yet run.
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// We need to set the CARRY bit that will be passed through the shifter appropriately.
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// Select carry input value based on carry control
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switch(_cpu._ir & 0x30)
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{
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case 0x00:
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// Nothing; CARRY unaffected.
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carry = _carry;
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break;
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case 0x10:
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carry = 0; // Z
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break;
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case 0x20:
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carry = 1; // O
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break;
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case 0x30:
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carry = (~_carry) & 0x1; // C
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break;
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}
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// Now modify the result based on the current ALU result
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switch (_cpu._ir & 0x700)
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{
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case 0x000:
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case 0x200:
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case 0x700:
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// COM, MOV, AND - Carry unaffected
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break;
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case 0x100:
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case 0x300:
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case 0x400:
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case 0x500:
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case 0x600:
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// NEG, INC, ADC, SUB, ADD - invert the carry bit
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if (_cpu._aluC0 != 0)
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{
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carry = (~carry) & 0x1;
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}
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break;
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}
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// Tell the Shifter to do a Nova-style shift with the
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// given carry bit.
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Shifter.SetDNS(true, carry);
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break;
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default:
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throw new InvalidOperationException(String.Format("Unhandled emulator F2 {0}.", ef2));
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}
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}
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protected override void ExecuteSpecialFunction2Late(MicroInstruction instruction)
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{
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EmulatorF2 ef2 = (EmulatorF2)instruction.F2;
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switch (ef2)
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{
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case EmulatorF2.LoadDNS:
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//
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// Set SKIP and CARRY flip-flops based on the final result of the operation after having
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// passed through the shifter.
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//
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ushort result = Shifter.Output;
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int carry = Shifter.DNSCarry;
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switch (_cpu._ir & 0x7)
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{
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case 0:
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// None, SKIP is reset
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_skip = 0;
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break;
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case 1: // SKP
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// Always skip
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_skip = 1;
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break;
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case 2: // SZC
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// Skip if carry result is zero
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_skip = (carry == 0) ? 1 : 0;
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break;
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case 3: // SNC
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// Skip if carry result is nonzero
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_skip = carry;
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break;
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case 4: // SZR
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_skip = (result == 0) ? 1 : 0;
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break;
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case 5: // SNR
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_skip = (result != 0) ? 1 : 0;
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break;
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case 6: // SEZ
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_skip = (result == 0 || carry == 0) ? 1 : 0;
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break;
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case 7: // SBN
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_skip = (result != 0 && carry != 0) ? 1 : 0;
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break;
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}
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if (_loadR)
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{
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// Write carry flag back.
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_carry = carry;
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}
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break;
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}
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}
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// From Section 3, Pg. 31:
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// "The emulator has two additional bits of state, the SKIP and CARRY flip flops. CARRY is distinct from the
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// microprocessor’s ALUC0 bit, tested by the ALUCY function. CARRY is set or cleared as a function of IR and
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// many other things(see section 3.1) when the DNS<-(do novel shifts, F2= 12B) function is executed. In
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// particular, if IR[12] is true, CARRY will not change. DNS also addresses R from (3-IR[3 - 4]), causes a store
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// into R unless IR[12] is set, and sets the SKIP flip flop if appropriate(see section 3.1). The emulator
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// microcode increments PC by 1 at the beginning of the next emulated instruction if SKIP is set, using
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// BUS+SKIP(ALUF= 13B). IR_ clears SKIP."
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//
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// NB: _skip is in the encapsulating AltoCPU class to make it easier to reference since the ALU needs to know about it.
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private int _carry;
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}
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}
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}
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