mirror of
https://github.com/livingcomputermuseum/ContrAlto.git
synced 2026-01-17 08:34:15 +00:00
538 lines
22 KiB
C#
538 lines
22 KiB
C#
using System;
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using Contralto.Memory;
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namespace Contralto.CPU
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{
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public partial class AltoCPU
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{
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// Task:
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// Base task class: provides implementation for non-task-specific microcode execution and
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// state. Task subclasses implement and execute Task-specific behavior and are called into
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// by the base class as necessary.
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public abstract class Task
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{
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public Task(AltoCPU cpu)
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{
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_wakeup = false;
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_mpc = 0xffff; // invalid, for sanity checking
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_taskType = TaskType.Invalid;
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_cpu = cpu;
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_block = false;
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}
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public int Priority
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{
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get { return (int)_taskType; }
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}
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public bool Wakeup
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{
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get { return _wakeup; }
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}
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public ushort MPC
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{
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get { return _mpc; }
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}
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/// <summary>
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/// Indicates whether the current uInstruction asserts BLOCK.
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/// Used by hardware for various tasks.
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/// </summary>
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public bool BLOCK
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{
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get { return _block; }
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}
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public virtual void Reset()
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{
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// From The Alto Hardware Manual (section 2, "Initialization"):
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// "...each task start[s] at the location which is its task number"
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//
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_mpc = (ushort)_taskType;
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_rdRam = false;
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}
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public virtual void BlockTask()
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{
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_wakeup = false;
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}
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public virtual void WakeupTask()
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{
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_wakeup = true;
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}
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public bool ExecuteNext()
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{
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// TODO: cache microinstructions (or pre-decode them) to save consing all these up every time.
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MicroInstruction instruction = UCodeMemory.GetInstruction(_mpc);
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// Grab BLOCK bit so that other tasks / hardware can look at it
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_block = instruction.F1 == SpecialFunction1.Block;
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//Console.WriteLine("R5:{0},R6:{1},IR:{2} - {3}:{4}", OctalHelpers.ToOctal(_cpu._r[5]), OctalHelpers.ToOctal(_cpu._r[6]), OctalHelpers.ToOctal(_cpu._ir), OctalHelpers.ToOctal(_mpc), UCodeDisassembler.DisassembleInstruction(instruction, _taskType));
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return ExecuteInstruction(instruction);
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}
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/// <summary>
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/// ExecuteInstruction causes the Task to execute the next instruction (the one
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/// _mpc is pointing to). The base implementation covers non-task specific logic; subclasses may
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/// provide their own overrides.
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/// </summary>
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/// <returns>True if a task switch has been requested by a TASK instruction, false otherwise.</returns>
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protected virtual bool ExecuteInstruction(MicroInstruction instruction)
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{
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bool nextTask = false;
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bool swMode = false;
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bool block = false;
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ushort aluData;
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ushort nextModifier;
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_loadR = false;
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_loadS = false;
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_rSelect = 0;
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_busData = 0;
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Shifter.SetMagic(false);
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Shifter.SetDNS(false, 0);
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//
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// Wait for memory state machine if a memory operation is requested by this instruction and
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// the memory isn't ready yet.
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// TODO: this needs to be seriously cleaned up.
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//
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bool constantAccess =
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instruction.F1 == SpecialFunction1.Constant ||
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instruction.F2 == SpecialFunction2.Constant;
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if ((instruction.BS == BusSource.ReadMD && !constantAccess) || // ReadMD only occurs if not reading from constant ROM.
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instruction.F1 == SpecialFunction1.LoadMAR ||
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instruction.F2 == SpecialFunction2.StoreMD)
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{
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MemoryOperation op;
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if (instruction.BS == BusSource.ReadMD)
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{
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op = MemoryOperation.Read;
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}
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else if (instruction.F1 == SpecialFunction1.LoadMAR)
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{
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op = MemoryOperation.LoadAddress;
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}
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else
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{
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op = MemoryOperation.Store;
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}
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if (!_cpu._system.MemoryBus.Ready(op))
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{
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// Suspend operation for this cycle.
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return false;
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}
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}
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// If we have a modified next field from the last instruction, make sure it gets applied to this one.
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nextModifier = _nextModifier;
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_nextModifier = 0;
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_rSelect = instruction.RSELECT;
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// Give tasks the chance to modify parameters early on (like RSELECT)
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ExecuteSpecialFunction2Early(instruction);
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// Select BUS data.
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if (!constantAccess)
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{
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// Normal BUS data (not constant ROM access).
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switch (instruction.BS)
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{
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case BusSource.ReadR:
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_busData = _cpu._r[_rSelect];
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break;
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case BusSource.LoadR:
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_busData = 0; // "Loading R forces the BUS to 0 so that an ALU function of 0 and T may be executed simultaneously"
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_loadR = true;
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break;
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case BusSource.None:
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_busData = 0xffff; // "Enables no source to the BUS, leaving it all ones"
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break;
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case BusSource.TaskSpecific1:
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case BusSource.TaskSpecific2:
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_busData = GetBusSource((int)instruction.BS); // task specific -- call into specific implementation
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break;
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case BusSource.ReadMD:
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_busData = _cpu._system.MemoryBus.ReadMD();
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break;
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case BusSource.ReadMouse:
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//throw new NotImplementedException("ReadMouse bus source not implemented.");
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_busData = 0; // TODO: implement;
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break;
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case BusSource.ReadDisp:
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// "The high-order bits of IR cannot be read directly, but the displacement field of IR (8 low order bits),
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// may be read with the <-DISP bus source. If the X field of the instruction is zero (i.e. it specifies page 0
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// addressing) then the DISP field of the instruction is put on BUS[8-15] and BUS[0-7] is zeroed. If the X
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// field of the instruction is nonzero (i.e. it specifies PC-relative or base-register addressing) then the DISP
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// field is sign-extended and put on the bus."
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// NB: the "X" field of the NOVA instruction is IR[6-7]
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_busData = (ushort)(_cpu._ir & 0xff);
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if ((_cpu._ir & 0x300) != 0)
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{
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// sign extend if necessary
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if ((_cpu._ir & 0x80) == 0x80)
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{
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_busData |= (0xff00);
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}
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}
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break;
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default:
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throw new InvalidOperationException(String.Format("Unhandled bus source {0}.", instruction.BS));
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}
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}
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else
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{
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// See also comments below.
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_busData = ControlROM.ConstantROM[(instruction.RSELECT << 3) | ((uint)instruction.BS)];
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}
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// Constant ROM access:
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// The constant memory is gated to the bus by F1=7, F2=7, or BS>4. The constant memory is addressed by the
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// (8 bit) concatenation of RSELECT and BS. The intent in enabling constants with BS>4 is to provide a masking
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// facility, particularly for the <-MOUSE and <-DISP bus sources. This works because the processor bus ANDs if
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// more than one source is gated to it. Up to 32 such mask contans can be provided for each of the four bus sources
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// > 4.
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// NOTE also:
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// "Note that the [emulator task F2] functions which replace the low bits of RSELECT with IR affect only the
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// selection of R; they do not affect the address supplied to the constant ROM."
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// Hence we use the unmodified RSELECT value here and above.
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if ((int)instruction.BS > 4 ||
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constantAccess)
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{
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_busData &= ControlROM.ConstantROM[(instruction.RSELECT << 3) | ((uint)instruction.BS)];
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}
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//
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// If there was a RDRAM operation last cycle, we AND in the uCode RAM data here.
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//
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if (_rdRam)
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{
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_busData &= UCodeMemory.ReadRAM();
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_rdRam = false;
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}
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// Do ALU operation
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aluData = ALU.Execute(instruction.ALUF, _busData, _cpu._t, _skip);
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//
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// If there was a WRTRAM operation last cycle, we write the uCode RAM here
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// using the results of this instruction's ALU operation.
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//
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if (_wrtRam)
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{
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UCodeMemory.WriteRAM(aluData, _cpu._m);
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_wrtRam = false;
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}
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//
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// If there was an SWMODE operation last cycle, we set the flag to ensure it
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// takes effect at the end of this cycle.
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//
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if (_swMode)
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{
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_swMode = false;
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swMode = true;
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}
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// Reset shifter op
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Shifter.SetOperation(ShifterOp.None, 0);
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//
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// Do Special Functions
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//
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switch (instruction.F1)
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{
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case SpecialFunction1.None:
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// Do nothing. Well, that was easy.
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break;
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case SpecialFunction1.LoadMAR:
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// Do MAR or XMAR reference based on whether F2 is MD<-, indicating an extended memory reference.
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_cpu._system.MemoryBus.LoadMAR(aluData, _taskType, instruction.F2 == SpecialFunction2.StoreMD);
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break;
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case SpecialFunction1.Task:
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nextTask = true; // Yield to other more important tasks
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break;
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case SpecialFunction1.Block:
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// Technically this is to be invoked by the hardware device associated with a task.
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// That logic would be circuituous and unless there's a good reason not to that is discovered
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// later, I'm just going to directly block the current task here.
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_cpu.BlockTask(this._taskType);
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// Let task-specific behavior take place at the end of this cycle.
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block = true;
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break;
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case SpecialFunction1.LLSH1:
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Shifter.SetOperation(ShifterOp.ShiftLeft, 1);
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break;
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case SpecialFunction1.LRSH1:
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Shifter.SetOperation(ShifterOp.ShiftRight, 1);
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break;
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case SpecialFunction1.LLCY8:
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Shifter.SetOperation(ShifterOp.RotateLeft, 8);
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break;
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case SpecialFunction1.Constant:
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// Ignored here; handled by Constant ROM access logic above.
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break;
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default:
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// Let the specific task implementation take a crack at this.
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ExecuteSpecialFunction1(instruction);
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break;
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}
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switch (instruction.F2)
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{
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case SpecialFunction2.None:
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// Nothing!
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break;
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case SpecialFunction2.BusEq0:
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if (_busData == 0)
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{
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_nextModifier = 1;
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}
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break;
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case SpecialFunction2.ShLt0:
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//
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// Note:
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// "the value of SHIFTER OUTPUT is determined by the value of L as the microinstruction
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// *begins* execution and the shifter function specified during the *current* microinstruction.
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//
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// Since we haven't modifed L yet, and we've selected the shifter function above, we're good to go here.
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//
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if ((short)Shifter.DoOperation(_cpu._l, _cpu._t) < 0)
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{
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_nextModifier = 1;
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}
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break;
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case SpecialFunction2.ShEq0:
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// See note above.
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if (Shifter.DoOperation(_cpu._l, _cpu._t) == 0)
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{
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_nextModifier = 1;
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}
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break;
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case SpecialFunction2.Bus:
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// Select bits 6-15 (bits 0-9 in modern parlance) of the bus
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_nextModifier = (ushort)(_busData & 0x3ff);
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break;
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case SpecialFunction2.ALUCY:
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// ALUC0 is the carry produced by the ALU during the most recent microinstruction
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// that loaded L. It is *not* the carry produced during the execution of the microinstruction
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// that contains the ALUCY function.
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_nextModifier = _cpu._aluC0;
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break;
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case SpecialFunction2.StoreMD:
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// Special case for XMAR; if F1 is a LoadMAR we do nothing here;
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// the handler for LoadMAR will load the correct bank.
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if (instruction.F1 != SpecialFunction1.LoadMAR)
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{
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_cpu._system.MemoryBus.LoadMD(_busData);
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}
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break;
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case SpecialFunction2.Constant:
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// Ignored here; handled by Constant ROM access logic above.
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break;
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default:
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// Let the specific task implementation take a crack at this.
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ExecuteSpecialFunction2(instruction);
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break;
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}
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// We always do the shifter operation; DNS may need its output.
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//
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Shifter.DoOperation(_cpu._l, _cpu._t);
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//
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// Write back to registers:
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//
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// Do writeback to selected R register from shifter output.
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//
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if (_loadR)
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{
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_cpu._r[_rSelect] = Shifter.Output;
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}
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// Do writeback to selected R register from M
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if (_loadS)
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{
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_cpu._s[_cpu._rb][_rSelect] = _cpu._m;
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}
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// Load T
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if (instruction.LoadT)
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{
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// Does this operation change the source for T?
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bool loadTFromALU = false;
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switch (instruction.ALUF)
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{
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case AluFunction.Bus:
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case AluFunction.BusOrT:
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case AluFunction.BusPlus1:
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case AluFunction.BusMinus1:
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case AluFunction.BusPlusTPlus1:
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case AluFunction.BusPlusSkip:
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case AluFunction.AluBusAndT:
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loadTFromALU = true;
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break;
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}
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_cpu._t = loadTFromALU ? aluData : _busData;
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//
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// Control RAM: "...the control RAM address is specified by the control RAM
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// address register... which is loaded from the ALU output whenver T is loaded
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// from its source."
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//
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UCodeMemory.LoadControlRAMAddress(aluData);
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}
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// Load L (and M) from ALU outputs.
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if (instruction.LoadL)
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{
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_cpu._l = aluData;
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_cpu._m = aluData;
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// Save ALUC0 for use in the next ALUCY special function.
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_cpu._aluC0 = (ushort)ALU.Carry;
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}
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//
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// Execute special functions that happen late in the cycle
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//
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ExecuteSpecialFunction2Late(instruction);
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//
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// Switch banks if the last instruction had an SWMODE F1;
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// this depends on the value of the NEXT field in this instruction
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//
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if (swMode)
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{
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Console.WriteLine("SWMODE NEXT {0} Modifier {1}", Conversion.ToOctal(instruction.NEXT), Conversion.ToOctal(nextModifier));
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UCodeMemory.SwitchMode((ushort)(instruction.NEXT | nextModifier));
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}
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//
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// Do task-specific BLOCK behavior if the last instruction had a BLOCK F1.
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//
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if (block)
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{
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ExecuteBlock();
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}
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//
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// Select next address, using the address modifier from the last instruction.
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//
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_mpc = (ushort)(instruction.NEXT | nextModifier);
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return nextTask;
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}
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protected virtual ushort GetBusSource(int bs)
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{
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// Nothing by default.
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return 0;
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}
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protected virtual void ExecuteSpecialFunction1(MicroInstruction instruction)
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{
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// Nothing by default
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}
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/// <summary>
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/// Used to allow Task-specific F2s that need to modify RSELECT to do so.
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/// </summary>
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/// <param name="f2"></param>
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protected virtual void ExecuteSpecialFunction2Early(MicroInstruction instruction)
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{
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// Nothing by default.
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}
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protected virtual void ExecuteSpecialFunction2(MicroInstruction instruction)
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{
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// Nothing by default.
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}
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protected virtual void ExecuteSpecialFunction2Late(MicroInstruction instruction)
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{
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// Nothing by default.
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}
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/// <summary>
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/// Allows task-specific handling for BLOCK microinstructions.
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/// (Disk and Display BLOCKs have side effects apart from removing Wakeup from the task, for example).
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/// </summary>
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protected virtual void ExecuteBlock()
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{
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// Nothing by default
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}
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//
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// Per uInstruction Task Data:
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// Modified by both the base Task implementation and any subclasses
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//
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// TODO: maybe instead of these being shared (which feels kinda bad)
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// these could be encapsulated in an object and passed to subclass implementations?
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protected ushort _busData; // Data placed onto the bus (ANDed from multiple sources)
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protected ushort _nextModifier; // Bits ORed onto the NEXT field of the current instruction
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protected uint _rSelect; // RSELECT field from current instruction, potentially modified by task
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protected bool _loadS; // Whether to load S from M at and of cycle
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protected bool _loadR; // Whether to load R from shifter at end of cycle.
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protected bool _rdRam; // Whether to load uCode RAM onto the bus during the next cycle.
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protected bool _wrtRam; // Whether to write uCode RAM from M and ALU outputs during the next cycle.
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protected bool _swMode; // Whether to switch uCode banks during the next cycle.
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//
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// Global Task Data
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//
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protected AltoCPU _cpu;
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protected ushort _mpc;
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protected TaskType _taskType;
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protected bool _wakeup;
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protected bool _block;
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// Emulator Task-specific data. This is placed here because it is used by the ALU and it's easier to reference in the
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// base class even if it does break encapsulation. See notes in the EmulatorTask class for meaning.
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protected int _skip;
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}
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}
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}
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