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39 lines
11 KiB
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39 lines
11 KiB
Plaintext
head 1.1;
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branch 1.1.1;
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access ;
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symbols start:1.1.1.1 Xerox:1.1.1;
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locks ; strict;
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comment @# @;
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1.1
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date 2001.08.12.22.22.24; author freier; state Exp;
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branches 1.1.1.1;
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next ;
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1.1.1.1
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date 2001.08.12.22.22.24; author freier; state Exp;
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branches ;
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next ;
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desc
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@@
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1.1
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log
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@Initial revision
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@
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text
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@{File name: Phase0.mc
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Description: PROM uCode used in starting booting sequence,
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Dennis DEG : 2-Sep-84 15:52:16, add copyright notice.
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Last Edited: Dan dD , February 17, 1982 10:23 AM: Clarify code, eliminate unmasked branches, fix recal code
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for Quantum drive (recal over 576 cylinders in, not 512).
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Last Edited: AeF AEF , January 21, 1982 3:57 PM: Change boot file numbers to 3-word quantity.
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Last Edited: AeF AEF , January 12, 1982 4:33 PM: Change uBootFileType values.
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Last Edited: AeF AEF , January 12, 1982 9:08 AM: Change comments to jive with new bootDevice values.
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Last Edited: Jozef JF , January 7, 1982 9:54 AM: Change register rE to RAdr in last click.
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Last Edited: AeF AEF , January 5, 1982 9:54 AM: Change BootDevice values.
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Last Edited: AeF AEF , January 5, 1982 9:06 AM: Change ordering.
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Last Edited: AeF AEF , December 21, 1981 4:00 PM: Add Task 4 to check for disk type.
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Last Edited: Jozef JF , December 18, 1981 2:56 PM: Trident power reset added.
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Last Edited: Jozef JF , December 11, 1981 11:55 AM: Trident2 & 3 added.
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Last Edited: Jozef JF , December 3, 1981 3:25 PM: Test for SAX000/Trident added.
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Last Edited: Jim JXF , November 24, 1981 5:14 PM: Change rD to rE for TridentBoot0.
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Last Edited: AeF AEF , November 24, 1981 9:57 AM: Add bootDevice = 7 code
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Last Edited: AeF AEF , November 16, 1981 10:15 AM: Delete setting of KCtl register
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Last Edited: AeF AEF , November 13, 1981 10:59 AM: Reduce code by 13 instructions
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Last Edited: AeF AEF , November 9, 1981 4:13 PM: Fix allocation error caused by addition of Trident
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Last Edited: Jozef JF , November 4, 1981 2:08 PM: Trident boot microcode added
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Last Edited: AeF AEF , September 14, 1981 12:19 PM: Change clock and retry count to R registers
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Last Edited: Jim JXF , September 10, 1981 1:28 PM: Add Ether booting
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Last Edited: RXO , July 10, 1981 12:55 PM
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Last Edited: PXJ , March 19, 1981 6:33 PM
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Author: PXJ ,
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Created: August 25, 1980,
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}
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{ Copyright (C) 1980, 1981, 1982 by Xerox Corporation. All rights reserved.}
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{IOP and CP use real memory locations 0 and 1 for communication during booting. Any boot microcode must first disable the IOP and clear those locations. The CP uses location 0 to indicate which devices for booting are present. Devices are coded one bit per device (0 indicates not initialized)
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1 SA4000
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2 SA1000
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4 Ethernet
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8 Trident
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After initializing location 0, the CP enables the IOP task and waits for the IOP to preload the necessary U registers. After the IOP loads U registers, the IOP task recieves the boot device from the IOP. The CP then enables the boot device and loads the boot file into main storage starting at location 100. If floppy booting is specified, the CP just loops in tèe protected area.
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After the CP loads the boot file, the location 1 gets non-zero to indicate the completion code (boot file loaded or error). If the high byte is non-zero, location 1 is the real address of the boot file. If the èigh byte is zero, the low byte contains an error code. The boot time error codes include
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1 device error
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2 null germ
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3 broken boot chain
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4 illegal command sent to IOP
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5 processor error trapped through control store location 0
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After completing the boot file loading the CP loops infinitely in the protected area.}
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{DEFINITIONS}
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Reserve[ProtectStart, ProtectFence], Reserve[0FE0, 0FFF]; {save room for boot kernel}
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{
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Phase0Protected (Protected.mc, IOPBoot.mc) resides in 0 - 00FF
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Phase0 (Phase0.mc, DiskBootDLion.mc, EtherBoot.mc) resides in 0100 - 0FDF
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The BootKernel resides in 0FE0 - 0FFF
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Part of the BootKernel that can be overlaid resides in 0FD8 - 0FDF
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}
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{Note the DiskBootDlion code for the Shugart disks uses Link registers 4 and 5.}
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SetTask[0], StartAddress[go];
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{The boot kernel resets the CP I/O registers and enables memory refresh}
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go: IOPCtl ¬ 0, rD ¬ 0, rDrh ¬ 0, CANCELBR[$, 0F], c1; {disable IOP port}
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dbUStatus ¬ 0, rE ¬ 0, c2; {clear disk status register}
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rErh ¬ 1, c3;
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{clear the first 128K of memory, includes the IO page, takes 54 msec}
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clear0: MAR ¬ [rDrh, rD+0], c1;
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MDR ¬ rE, rD ¬ rD + 1, ZeroBr, c2;
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passTraps ¬ rE, BRANCH[clear0, $], c3; {die on faults}
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MAR ¬ [rErh, rE + 0], GOTO[clear2], c1;
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clear1: MAR¬ [rErh, rE+0], c1;
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clear2: MDR¬ rD, rE¬ rE+1, ZeroBr, c2;
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bootDevice ¬ 0, BRANCH[clear1, Trident/SA], c3;
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{Test for controller type. NOTE: Any HSIO boards using this code must have the HSIO-e engineering change. If it is
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not present, the code may mistake a Shugart or Quantum drive for a Trident. This is because the WriteGate bit is
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the one tested and boards without the fix MAY come up with WriteGate active.}
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Trident/SA: Xbus ¬ KTest, XDisp, c1;
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uEtherBootDone ¬ 0, DISP4[diskType, 0E], c2;
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Trident: rE ¬ 0C, GOTO[enableIOP], c3, at[0F,10,diskType];
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SA: GOTO[pollDevices], c3, at[0E,10,diskType];
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pollDevices: Xbus ¬ KStatus, XwdDisp, c1; {SA4000 or SA1000?}
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rC ¬ 20, {set up for disk loop} BRANCH[SA1000, SA4000, 2], c2;
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SA4000: rE ¬ 5 {SA4000 = Ethernet}, GOTO[enableIOP], c3, at[3, 4, SA4000];
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SA1000: rE ¬ 6 {SA1000 = Ethernet}, GOTO[enableIOP], c3, at[2, 4, SA4000];
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enableIOP: MAR ¬ [rDrh, rD + 0], c1; {non-zero in zero=> ready}
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MDR ¬ CPBootDevice ¬ rE, c2;
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IOPCtl ¬ IOPInMode, c3;
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{ Wait for the IOP to inform the CP what the BootDevice is. U-register bootDevice will become nonzero.
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bootDevice = 0 (not valid yet), = 1 (SA4XXX), = 2 (SA100X), = 3 (Ethernet), = 4 (Floppy), = 5 (Alt. Ethernet), = 6 (Trident0), = 7 (Trident1), = 8 (Trident2), = 9 (Trident3).}
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here: rG ¬ 0FF, {so Protected won't timeout right away} c1, at[0, 10, here];
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Xbus ¬ bootDevice, XDisp, c2;
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uTimeout ¬ 0, DISP4[here], c3;
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{Set up the third word of the 3-word boot file number of the file being requested.}
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rE ¬ 0, GOTO[EtherBoot], c1, at[3, 10, here];
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rE ¬ 1, GOTO[EtherBoot], c1, at[5, 10, here];
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EtherBoot: rEtherBootRetries ¬ 0, uEtherBootStatus ¬ 0, c2;
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uFileNumber2 ¬ rE, c3;
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NotifyEtherBoot:
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{Notify EtherTask by sending Attention that it should start or restart}
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EICtl ¬ 2 {Notify the EtherTask}, CANCELBR[$,1], c1;
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TestTimeout: Ybus ¬ uTimeout, NZeroBr, CANCELBR[$,1], c2;
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Ybus ¬ uEtherBootDone, ZeroBr, BRANCH[$, NotifyEtherBoot], c3;
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Ybus ¬ uEtherBootStatus, NZeroBr, BRANCH[$, TestTimeout], c1;
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Noop, BRANCH[EtherBootSuccessful, EtherBootFailed], c2;
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EtherBootSuccessful:
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dbUStatus ¬ 0, GOTO[FileReady], c3;
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EtherBootFailed:
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acR ¬ bootDeviceError, GOTOABS[Maintenance1Loc], c3;
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floppyBoot: GOTOABS[IdleLoc], c1, at[4, 10, here];
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diskBoot4: rE ¬ faultClearCmd, {boot from SA4000}, c1, at[1, 10, here];
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KCtl ¬ rE LRot8, c2;
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KCtl ¬ 0, GOTO[diskBoot1], c3;
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diskBoot1: Xbus ¬ KStatus, XRefBr, c1, at[2, 10, here];
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rE ¬ driveSelectBit, BRANCH[$, recalibrate], c2; {check for drive ready}
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rE ¬ KCtl ¬ rE LRot8, GOTO[diskBoot1], c3;
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{disk is ready}
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recalibrate: rE ¬ driveSelectBit, c3; {step in first}
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rE ¬ rE LRot8, c1;
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rE ¬ rE or inBit, c2;
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KCtl ¬ rE LRot0, c3;
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{Step bit must be high for at least one microsecond and then low for at least one microsecond. Since a click is 411 ns, stepBit can change only once every third click.}
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WaitForSeekComplete:
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rD ¬ ~KStatus, CANCELBR[$, 1], c1, at[0B, 10, WaitForSeekComplete];
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rD ¬ rD LRot8, XDisp, c2; {check for seek complete}
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Ybus ¬ rD and 2, ZeroBr, DISP4[WaitForSeekComplete, 0B], c3; {check for Cylinder 0 flag, loop
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waiting for SeekComplete.}
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{Heads are now steady, if now at Cylinder 0, start disk microcode. Otherwise step the heads in or out.}
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seekComplete: rE ¬ rE or stepBit, BRANCH[at00, $], c1, at[0F, 10, WaitForSeekComplete];
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KCtl ¬ rE LRot0, c2;
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rD ¬ 3, c3;
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{Wait 3 clicks so Step pulse is active long enough.}
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stepWait: rE ¬ rE and ~stepBit, CANCELBR[$, 1], c1;
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rD ¬ rD - 1, ZeroBr, c2;
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Ybus ¬ rC, ZeroBr, BRANCH[stepWait, $], c3; {See if finished stepping in
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this direction (rC=0)}
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KCtl ¬ rE LRot0, BRANCH[$, countedIn], c1; {lower step line and continue
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only if there is more to go.}
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rC ¬ rC - 1, c2;
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GOTO[WaitForSeekComplete], c3;
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{At this point, we have gone as far as necessary in the current direction. If this is the first time through, we have moved the heads far enough towards the center of the disk that Cylinder 0 must be out from here. If this is the second time through, Cylinder 0 can't be found (we have gone 32 Cylinder inwards and 562 cylinders out) so give up.}
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countedIn: rD ¬ rE and inBit, c2; {select DirectionIn bit}
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Ybus ¬ rD, ZeroBr, c3; {did we just finish going in?}
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rE ¬ rE xor inBit, BRANCH[$, recalLost], c1; {flip direction, quit if we were
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going out}
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rC ¬ 0FF + 1, {max is 256 cylinders for SA1000} c2;
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rC ¬ LShift1 rC or 20, GOTO[WaitForSeekComplete], c3; {make sure we go far enough out
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for a 512 Cylinder Quantum drive.
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Use "or" instead of "+" for timing
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reasons.}
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recalLost: acR ¬ bootDeviceError, GOTOABS[Maintenance2Loc], c2;
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{Here recalibration has been successful. We turn on the disk microcode and wait for it to complete.}
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at00: rD ¬ firmwareEnable, c2;
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KCtl ¬ rD LRot0, c3;
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transferWait: rD ¬ ~KStatus, c1, at[0F, 10, transferWait];
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Xbus ¬ rD LRot8, XDisp, c2; {test firmware busy}
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rDrh ¬ 0, BRANCH[FileReady, transferWait, 0E], c3;
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{This section of the code is for Trident device 0 ,1, 2 and 3.}
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TridentBoot0: rE ¬ 0F8,GOTO[TridentCont], c1, at[6, 10, here];
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TridentBoot1: rE ¬ 0F4, GOTO[TridentCont], c1, at[7, 10, here];
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TridentBoot2: rE ¬ 0F2, GOTO[TridentCont], c1, at[8, 10, here];
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TridentBoot3: rE ¬ 0F1, c1, at[9, 10, here];
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TridentCont: KCtl ¬ rE ¬ rE LRot8, c2;
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KCmd ¬ bU0C00, c3;
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{Test for firmware busy. If not busy finish phase0 boot sequence.}
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TridentWait: rD ¬ ~KTest, c1, at[0F, 10, TridentWait];
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[] ¬ rD LRot4, XDisp, c2;
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bUBitSignAdr ¬ rE, BRANCH[TridentEnd, TridentWait, 0E], c3;
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TridentEnd: rE¬ dbUStatus, ZeroBr,GOTO[EtherBootCont] c1, at[0E, 10, TridentWait];
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FileReady: rE¬ dbUStatus, ZeroBr,GOTO[EtherBootCont] c1, at[0E,10,transferWait];
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EtherBootCont: rD ¬ 1, BRANCH[$, setReady], c2;
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acR ¬ bootDeviceError, GOTOABS[Maintenance1Loc], c3;
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setReady: acR ¬ 0FF+1, c3; {first location of boot file}
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MAR ¬ [rDrh, rD + 0], c1; {indicate boot file read}
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MDR ¬ acR, GOTOABS[IdleLoc], c2;
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{Determine the disk type and jump to the starting address of either DiskBootDLion or TridentBootDLion accordingly. We must test this here because we cannot have two different starting addresses for Task 4. When we arrive here, CPBootDevice is 5 or 6 for a Shugart disk and 0C for a Trident.}
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SetTask[4], StartAddress[FindDiskType];
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FindDiskType: RAdr ¬ CPBootDevice, CANCELBR[$, 0F], c1;
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Ybus ¬ RAdr, YDisp, c2;
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BRANCH[DiskStart, {SAx000} StartBoot, {Trident} 7], c3;
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@
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1.1.1.1
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log
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@first add
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@
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text
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@@
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