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39 lines
4.7 KiB
Plaintext
39 lines
4.7 KiB
Plaintext
head 1.1;
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branch 1.1.1;
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access ;
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symbols start:1.1.1.1 Xerox:1.1.1;
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locks ; strict;
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comment @;; @;
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1.1
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date 2001.08.12.22.22.23; author freier; state Exp;
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branches 1.1.1.1;
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next ;
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1.1.1.1
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date 2001.08.12.22.22.23; author freier; state Exp;
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branches ;
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next ;
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desc
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@@
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1.1
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log
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@Initial revision
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@
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text
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@{
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LoadExtraBanksX.asm
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(LoadExtraBanksX.asm does not provide the fake BootMain exports)
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last edited by :
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-- DEG 2-Sep-84 0:03:42 - added copyright notice
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-- JMM 24-Oct-83 11:22:14 - commented out calls to MP code and also
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made bank byte a variable.
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-- HXS : 16-Sep-83 16:16:39
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}
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{ Copyright (C) 1983 by Xerox Corporation. All rights reserved. }
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get "SysDefs.asm"
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get "BootDefs.asm"
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get "BootLinkDefs.asm"
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; LoadExtraBanksHandle will place a jmp to NewNextPhaseCodeProlog at 2000H
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; actually, for a first try this code will be loaded at 2000H, since this code will not be running when domino is loaded, so domino can load right on top of it.
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EXP NewNextPhaseCodeProlog
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; this module is expected to be loaded with BootSubs
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IMP CheckCPStopped, GetNextWord, IncrMP, PhaseToMP
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IMP StartCP, StartNextRead, TransferCSImage, TransferTPCImage
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; Boot subs needs the following, but will not actually use it
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; EXP StartIOPBoot, StartNextPhase
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; this definition is for Burdock
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StartIOPAddressHigh equ StartIOPAddress+1
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; this definition logically belongs in BootDefs, among CPKernelconstants
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CPSetBank equ 02H ; command to Kernel to Set the bank register
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CPKernelTest equ 03H ; command to Kernel to see if FakeKernel is present
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BankNo:
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db 0
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NewNextPhaseCodeProlog:
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; compute address of StartBootBlock in BootMain
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lhld DoBootPhaseExt+1
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lxi b, 3
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dad b
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prol1: shld StartBB+1
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; change StartIOPAddress
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prol2: lxi h, NewNextPhaseCode
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shld StartIOPAddress
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NewNextPhaseCode:
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;prol3: lxi h, Phase; Increment phase number
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; inr m
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; call PhaseToMP; Put Phase*50 + 99 in MP
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prol4: call CheckCPStopped; put it into Kernel if not already there
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call TestForMyKernel; see if all is well
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; call TestForMyKernel; see if all is well
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prol5: call StepBank;
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; call TestForMyKernel; see if all is well
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call TestForMyKernel; see if all is well
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call TransferCSImage; low CP memory, including idle loop
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call TestForMyKernel; see if all is well
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; call IncrMP
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call StartCP; safe now that idle loop in the new bank
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; call IncrMP;
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lxi h,1
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call StartNextRead
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lxi h,Header
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call GetNextWord; skip over check sum word of last .db
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; now we know that both my Kernal and the (cp) IOP (task 5) is working, lets try shutting down and starting up again
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call CheckCPStopped
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call TestForMyKernel
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call StartCP;
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call InitTPCsOnly; reset the TPCs, don't init the image
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; the address is loaded during prolog
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StartBB:
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jmp 0 ; jmp BootMain.StartBootBlock, don't init the image
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; init only the TPCs, do not change the low CP mem image
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; this code copied from BootSubs, extracted from InitCSTPCImage
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; Initialize the TPC array with all slots empty, i.e. high bit of word = 1.
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InitTPCsOnly:
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mvi c,8 ; Counter for 8 words
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mvi e,0 ; Initialize TPC slot to 8000H (empty)
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mvi d,80H
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lxi h,TPCBuffer ; Start of Buffer
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InitTPCImageLoop:
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mov m,e ; Store low byte
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inx h
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mov m,d ; Store high byte
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inx h
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dcr c ; More TPC's?
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jnz InitTPCImageLoop ; nz => More to do
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ret
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; request the Kernel to advance the bank register
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StepBank:
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mvi a, CPSetBank
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call WriteCPbyte
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lda BankNo
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call WriteCPbyte
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call ReadCPbyte
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sta LatestBank
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ret
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; see if my FakeKernel is really running
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TestForMyKernel:
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mvi a, CPKernelTest
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call WriteCPbyte
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call ReadCPbyte
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mvi b, 7
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cmp b
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rz ; Kernel Present
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KernelNotPresent:
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jmp KernelNotPresent
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; following exists in BootSubs, but not exported
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; Subroutine: WriteCPbyte.
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; Write CP byte.
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; Byte in A register written into port.
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WriteCPbyte:
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out CPOut ; Output data
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WaitCPOutAck:
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in CPStatus ; Read the port interrupt bits
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ani CPOutIntMask ; CPOut requesting an interrupt, i.e data read?
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jz WaitCPOutAck ; Zero means no interrupt
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ret
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; following exists in BootSubs, but not exported
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; Subroutine: ReadCPbyte.
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; Read CP byte.
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; Byte returned in A register.
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ReadCPbyte:
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in CPStatus ; Read the port interrupt bits
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ani CPInIntMask ; CPIn requesting an interrupt?
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jz ReadCPbyte ; Zero means no interrupt
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in CPIn ; get data
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ret
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;DATA section:
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; this is for debugging to see if correct bank was loaded.
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LatestBank:
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db 07FH
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; following code is to satisfy the imports of boot subs
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StartIOPBoot dw 0; this is only used during boot initialization, so not used
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StartNextPhase dw 0; also applies to this word
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;this is the bank to be loaded next.
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; ORG 5B00H ;Our assembler treats this as relocatable. jmm
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;BankNo:
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; db 0
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END LoadExtraBanksX@
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1.1.1.1
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log
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@first add
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@
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text
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@@
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