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https://github.com/livingcomputermuseum/Darkstar.git
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39 lines
11 KiB
Plaintext
39 lines
11 KiB
Plaintext
head 1.1;
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branch 1.1.1;
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access ;
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symbols start:1.1.1.1 Xerox:1.1.1;
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locks ; strict;
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comment @;; @;
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1.1
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date 2001.08.12.22.22.09; author freier; state Exp;
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branches 1.1.1.1;
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next ;
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1.1.1.1
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date 2001.08.12.22.22.09; author freier; state Exp;
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branches ;
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next ;
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desc
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@@
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1.1
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log
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@Initial revision
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@
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text
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@; Copyright (C) 1980 by Xerox Corporation. All rights reserved.
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; Test Programs for CP: TPC, control store,CPport, and INSTRUCTION Tests.
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; Last modification by
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; Modification History:
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; - Created (June 4, 1980 12:59 PM)
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get "SysDefs.asm" ; system defs (tests defs below)
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get "MOONBootDefs.asm" ; system defs (tests defs below)
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get "MOONBootLinkDefs.asm" ; system defs (tests defs below)
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get "MOONLinkDefs.asm" ; system links
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get "MOONSysDefs.asm" ; system defs
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;-----------------------------------------------------------------
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jmp CSTestS
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; Temporary data area.
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CSSeed:
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db 00H ; Seed for CS Data random number, or constant data
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OutCSData:
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db 0,0,0,0,0,0 ; Write control store data (6 bytes)
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Mode:
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db 0 ; Program mode for tests (default: , Constant data)
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CBank:
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db 0
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Save:
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db 0
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;---------------- START of Program -------------------------
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; Initialize.
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CSTestS:
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lda Conf
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ani 6
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jz Done1
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rrc
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ani 3
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sta CBank
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TestBank:
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call Loader
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call TestStart
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lda CBank
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cpi 0
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jz Done
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dcr a
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sta CBank
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jmp TestBank
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TestStart:
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lda TestN
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cpi EXTPCDT
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jz TPCTest
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cpi EXCSCDTO
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jz DoCSTest2
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cpi EXCSCDTZ
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jz DoCSTest1
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cpi EXCSADT
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jz DoCSTest3
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cpi EXCSRDT
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jz DoCSTest4
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Done:
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mvi a,0
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sta CBank
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call Loader
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Done1:
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mvi a,0
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sta ObservedData
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jmp ExtLogPError
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PortOut:
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lda ObservedData
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sta Save
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lda CBank
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call ExtWriteCPport
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mvi a,6
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sta ObservedData
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in CPStatus ; Check for error condition (CPAttn).
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ani CPAttnMask
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jz ExtLogPError
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lda Save
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sta ObservedData
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ret
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Loader:
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call ExtPhase1Entry
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call ExtStartCP
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call PortOut
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call ExtStartDelay
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call ExtStopCP
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call ExtTimeDelay
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ret
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; TPC test.
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; This test writes all the TPCs with a pattern and then reads and checks them.
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; All 12 bit patterns are tested.
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TPCTest:
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mvi a,0
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sta Mode
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TPCTest1:
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mvi a,MaxTPCAddr ; initialize TPC address
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sta Task
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call DcxMask
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WTPCTest2:
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lda Mode
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cpi 5
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jnz WTPCTest4
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lda Task
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mov d,a
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mov e,a
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WTPCTest4:
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call WriteTPC ; Write the data
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WTPCTest3:
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lda Task
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sui 10H
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sta Task
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jp WTPCTest2
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RTPCTest:
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mvi a,MaxTPCAddr ; initialize TPC address
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sta Task
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RTPCTest1:
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mov c,a
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call ReadTPC ; Read the data (returned in BC)
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lda Mode
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cpi 5
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jnz RTPCTest3
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lda Task
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mov d,a
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mov e,a
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RTPCTest3:
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call CheckTPC ; Check data (breakpoints if error)
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RTPCTest2:
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lda Task
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sui 10H
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sta Task
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jp RTPCTest1
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lda Mode
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cpi 5
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jnz TPCTest1
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RET
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ReadTPC:
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push d
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call ExtLeftAlignTPCAddr ; Left align 3 bits of address in C
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out TPCHigh
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in CS6 ; Separate TPCdata[0:3]
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cma ; complement
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mov d,a ; High part to D
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in CS7 ; separate TPCData[4:11]
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cma ; complement
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mov e,a ; low part to E
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xchg ; Move to HL for store
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shld ObservedCSlow ; Store returned data in TPC data area
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pop d
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ret
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DcxMask:
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lda Mode
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mvi d,0FFH
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cpi 1
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jz DcxMaskRet
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mvi d,0AAH
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cpi 2
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jz DcxMaskRet
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mvi d,55H
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cpi 3
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jz DcxMaskRet
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mvi d,0
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DcxMaskRet:
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inr a
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sta Mode
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mov a,d
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mov e,a
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ret
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; Write TPC.
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; On entry:
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; TPC address is in C (3 bits right-justified).
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; TPC data is in DE (12 bits right-justified).
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; Format of TPCHigh (write): TPCAddr[0:2],,TPCData[0:4]'
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; Format of TPCLow (write): don't care,,TPCData[5:11]'
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WriteTPC:
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push b ; Save B,C temporarily
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call ExtLeftAlignTPCAddr ; Left align 3 bits of address in C
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ori 0
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mov a,e ; Move TPC[4] into B for TPCHigh format
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ral ; TPC[4] into carry
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mov a,d ; get high part
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ral ; TPC[4] into B[7]
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cma ; complement for port
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ani 1FH ; Clear High 3 bits
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ora c ; OR in address
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out TPCHigh ; Set address, high data
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mov a,e ; Get low part (C[0] is don't care)
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cma ; complement for port
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out TPCLow ; send low data, Write TPC
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pop b
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ret
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; Subroutine to check TPC values read in.
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; Returned value is in ObservedCSlow, output value in DE.
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CheckTPC:
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mov a,d
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ani 0FH
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mov c,a
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lda CBank
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rlc
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rlc
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rlc
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rlc
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cma
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ani 0F0H
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ora c
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mov c,a
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lda ObservedCSlow ; Get low part of new data
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cmp e ; check it with Correct data
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jnz CheckTPCErr
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lda ObservedCSHigh ; Get high part of new data
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cmp c ; check it with Correct data
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rz
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CheckTPCErr:
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mov d,c
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xchg ; Move to HL for store
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shld ExpectedCSLow ; Store real data in TPC data area
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mvi a,0
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sta CBank
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call Loader
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jmp ExtLogTPCError
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DoCSTest1:
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mvi a,ConstantDataVal
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sta Mode
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jmp CSTest
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DoCSTest2:
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mvi a,ConstantDataVal
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sta Mode
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mvi a,0FFH
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jmp CSTest
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DoCSTest3:
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mvi a, AddressDataVal
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sta Mode
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jmp CSTest
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DoCSTest4:
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mvi a, RandomDataVal
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sta Mode
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jmp CSTest
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; Control Store Test.
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; This test writes control store with varying data, and then reads and checks the data.
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; The type of data written depends on flags in Mode.
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; Constant, Random: Each CS location has the same byte repeated 6 times.
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; Address in location: Each CS location has the its address repeated 3 times.
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; TPC register 6 is used to write/read the control store.
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; Conventions: C contains the TPC address (3 bits right-justified)
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; DE contains the TPC data (12 bits right-justified)
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CSTest:
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sta CSSeed
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CSTestStart:
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mvi a,60H ; Use TPC address 6
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NextTPCAddr:
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sta Task
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lhld BootIndexes+1 ; start with initial address
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xchg
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lda CSSeed ; Initialize seed for random number (or constant data)
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sta ExpectedData
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lda BootIndexes+5 ; get WriteOK
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cpi 0 ; Check forlower CSAddress
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jnz WriteDone
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NextCSWrite:
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call GetNextCSData ; Data stored in OutCSData array
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call WriteTPC ; Write the TPC slot with the control store address
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call WriteCS ; Write data in OutCSData
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lda mode
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cpi AddressDataVal
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jnz NextCSWrite1
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call InvertAddr ; Write the inversion address
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NextCSWrite1:
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lda BootIndexes+3 ; get ending address
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xra e ; Check forlower CSAddress
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jnz IncCSAddr
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call CheckKeyboard
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lda BootIndexes+4 ; get ending address
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xra d ; Check for CSAddress greater than 4095
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jz WriteDone; Go back to command loop
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IncCSAddr:
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inx d ; Increment CSAddress
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jmp NextCSWrite ; Do next CS address
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WriteDone:
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lda BootIndexes+6 ; Get Read OK
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cpi 0 ; Check forlower CSAddress
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rnz
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; Finished writing control store. Do read/checks.
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lhld BootIndexes+1 ; start with initial address
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xchg
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lda CSSeed ; Initialize seed for random number (or constant data)
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sta ExpectedData
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NextCSRead:
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call GetNextCSData ; Data stored in OutCSData array
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call WriteTPC ; Write the TPC slot with the control store address
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call ExtReadCS ; Read data into InCSData
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call CheckCS ; Check data (breakpoints if error)
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lda BootIndexes+3 ; get ending address
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xra e ; Check forlower CSAddress
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jnz IncCSAddr1
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call CheckKeyboard
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lda BootIndexes+4 ; get ending address
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xra d ; Check for CSAddress greater than 4095
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rz ; Go back to command loop
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IncCSAddr1:
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inx d ; Increment CSAddress
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jmp NextCSRead ; Do next CS address
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CheckKeyboard:
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push d
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push h
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call ExtMonitorKeyIn
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pop h
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pop d
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ret
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InvertAddr:
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push d
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mvi a,0FFH
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xra d
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ani 0FH ; Mask high part
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mov d,a
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mvi a,0FFH
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xra e
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mov e,a
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call GetNextCSData ; Data stored in OutCSData array
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call WriteTPC ; Write the TPC slot with the control store address
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call WriteCS ; Write data in OutCSData
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pop d
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ret
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; Subroutine to write a control store location.
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WriteCS:
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lda OutCSData+0 ; Get byte
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cma ; [4] Complement for CP LS240
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out CSa ; Write it
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lda OutCSData+1 ; Get byte
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cma ; [4] Complement for CP LS240
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out CSb
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lda OutCSData+2 ; Get byte
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cma ; [4] Complement for CP LS240
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out CSc
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lda OutCSData+3 ; Get byte
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cma ; [4] Complement for CP LS240
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out CSd
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lda OutCSData+4 ; Get byte
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cma ; [4] Complement for CP LS240
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out CSe
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lda OutCSData+5 ; Get byte
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cma ; [4] Complement for CP LS240
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out CSf
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ret
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; Subroutine to generate next CS data byte.
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; Check bits in Mode to determine whether constant, random, or address data.
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; If constant, next data is in Data.
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; If random, then next data is random.
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; If address, next data is CS address.
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; Random number generator simulates an 8-bit feedback shift register with
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; equation x8 (MSB) = x4 xor x3 xor x2 xor x0.
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GetNextCSData:
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push d
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lda Mode ; Check which data generation algorithm
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cpi RandomDataVal
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jz DoRandomCSData ; z => random data
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cpi AddressDataVal ;
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jz DoAddressCSData ; z => Address data
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;Constant data.
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lda ExpectedData ; Get constant data to be written
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mov d,a
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mov e,a
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jmp DoAddressCSData
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DoRandomCSData:
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lda ExpectedData ; Get last value
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add d ;[add d and e +11 sta inverse in e]
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add e
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adi 11H
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sta ExpectedData ; Save new value
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mov d,a
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cma
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mov e,a
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DoAddressCSData:
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mov a,d ; High part.
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sta OutCSData+0
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sta OutCSData+2
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sta OutCSData+4
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mov a,e ; Low part.
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sta OutCSData+1
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sta OutCSData+3
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sta OutCSData+5
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pop d
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ret ; RETURN
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; Subroutine to check the data in InCSData with OutCSData.
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; For CP Rev. B, IOP Rev E, we have to check the following:
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; In0 = Out0 (Checks rA, rB)
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; In1 = Out1 (Checks aS, aF, aD)
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; In2 = Out2 (Checks EP, CIn, EnSU, mem, fS)
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; In3 = Out3 (Checks fY, INIA[0:3])
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; In4 = Out4 (Checks fX, INIA[4:7])
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; In5 = Out5 (Checks fZ, INIA[8:11])
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CheckCS:
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push b ; Save B, C
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push d ; Save D, E
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mvi e,0 ;COUNT
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lxi h,OutCSData
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lxi b,InCSData+0
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CheckCS1:
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ldax b
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cmp m
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jz OkCSData
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sta ObservedData
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mov a,m
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sta ExpectedData
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mov a,e
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rlc
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rlc
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rlc
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rlc
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ani 070H
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mov e,a
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lda StopOnError
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ani 8FH
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ora e
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sta StopOnError
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pop d ; Restore D, E
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xchg ; Move to HL for store
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lda CBank
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rlc
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rlc
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rlc
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rlc
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ani 0F0H
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ora h
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mov h,a
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shld ExpectedCSLow
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shld ObservedCSlow
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mvi a,0
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sta CBank
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call Loader
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jmp ExtLogDError
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OkCSData:
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inx h
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inx b
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inr e
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mov a,e
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cpi 6
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jnz CheckCS1
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pop d ; Restore D, E
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pop b ; Restore B, C
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ret
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end
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@
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1.1.1.1
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log
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@first add
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@
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text
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@@
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