mirror of
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1270 lines
40 KiB
C#
1270 lines
40 KiB
C#
/*
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BSD 2-Clause License
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Copyright Vulcan Inc. 2017-2018 and Living Computer Museum + Labs 2018
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED.IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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using System;
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namespace D.CP
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{
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public enum AluSourcePair
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{
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AQ = 0,
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AB = 1,
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ZQ = 2,
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ZB = 3,
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ZA = 4,
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DA = 5,
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DQ = 6,
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D0 = 7,
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}
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public enum AluFunction
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{
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RplusS = 0,
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SminusR = 1,
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RminusS = 2,
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RorS = 3,
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RandS = 4,
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notRandS = 5,
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RxorS = 6,
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notRxorS = 7,
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}
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public enum FunctionSelectFY
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{
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DispBr = 0,
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fyNorm = 1,
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IOOut = 2,
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Byte = 3,
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}
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public enum FunctionSelectFZ
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{
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fzNorm = 0,
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Nibble = 1,
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Uaddr = 2,
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IOXIn = 3,
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}
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public enum XFunction
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{
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pCallRet0 = 0x0,
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pCallRet1 = 0x1,
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pCallRet2 = 0x2,
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pCallRet3 = 0x3,
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pCallRet4 = 0x4,
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pCallRet5 = 0x5,
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pCallRet6 = 0x6,
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pCallRet7 = 0x7,
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Noop = 0x8,
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LoadRH = 0x9,
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shift = 0xa,
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cycle = 0xb,
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LoadCinFrompc16 = 0xc,
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LoadMap = 0xd,
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pop = 0xe,
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push = 0xf,
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}
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public enum YNormFunction
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{
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ExitKern = 0x0,
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EnterKern = 0x1,
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ClrIntErr = 0x2,
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IBDisp = 0x3,
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MesaIntRq = 0x4,
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LoadstackP = 0x5,
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LoadIB = 0x6,
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cycle = 0x7,
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Noop = 0x8,
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LoadMap = 0x9,
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Refresh = 0xa,
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push = 0xb,
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ClrDPRq = 0xc,
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ClrIOPRq = 0xd,
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ClrRefRq = 0xe,
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ClrKFlags = 0xf,
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}
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public enum YDispBrFunction
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{
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NegBr = 0x0,
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ZeroBr = 0x1,
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NZeroBr = 0x2,
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MesaIntBr = 0x3,
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PgCarryBr = 0x4,
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CarryBr = 0x5,
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XRefBr = 0x6,
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NibCarryBr = 0x7,
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XDisp = 0x8,
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YDisp = 0x9,
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XC2npcDisp = 0xa,
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YIODisp = 0xb,
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XwdDisp = 0xc,
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XHDisp = 0xd,
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XLDisp = 0xe, // AKA XDirtyDisp
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PgCrOvDisp = 0xf,
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}
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public enum YIOOutFunction
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{
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IOPOData = 0x0,
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IOPCtl = 0x1,
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KOData = 0x2,
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KCtl = 0x3,
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EOData = 0x4,
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EICtl = 0x5,
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DCtlFifo = 0x6,
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DCtl = 0x7,
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DBorder = 0x8,
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PCtl = 0x9,
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MCtl = 0xa,
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Invalid0 = 0xb,
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EOCtl = 0xc,
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KCmd = 0xd,
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Invalid1 = 0xe,
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POData = 0xf,
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}
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public enum ZNormFunction
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{
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Refresh = 0x0,
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LoadIBPtr1 = 0x1,
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LoadIBPtr0 = 0x2,
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LoadCinFrompc16 = 0x3,
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LoadBank = 0x4,
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pop = 0x5,
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push = 0x6,
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AltUaddr = 0x7,
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Noop0 = 0x8,
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Noop1 = 0x9,
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Noop2 = 0xa,
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Noop3 = 0xb,
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LRot0 = 0xc,
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LRot12 = 0xd,
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LRot8 = 0xe,
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LRot4 = 0xf
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}
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// For Zap Rowsdower
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public enum ZIOXIn
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{
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ReadEIdata = 0x0,
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ReadEStatus = 0x1,
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ReadKIData = 0x2,
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ReadKStatus = 0x3,
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KStrobe = 0x4,
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ReadMStatus = 0x5,
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ReadKTest = 0x6,
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EStrobe = 0x7,
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ReadIOPIData = 0x8,
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ReadIOPStatus = 0x9,
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ReadErrnIBnStkp = 0xa,
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ReadRH = 0xb,
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ReadibNA = 0xc,
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Readib = 0xd,
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ReadibLow = 0xe,
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ReadibHigh = 0xf,
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}
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public enum StackTestType
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{
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None,
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Underflow,
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Overflow,
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Underflow2,
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}
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/// <summary>
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/// Decodes a single microcode word.
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/// </summary>
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public class Microinstruction
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{
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public Microinstruction(ulong word)
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{
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rA = (int)((word & 0xf00000000000) >> 44);
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rB = (int)((word & 0x0f0000000000) >> 40);
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aS = (AluSourcePair)((word & 0x00e000000000) >> 37);
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aF = (AluFunction)((word & 0x001c00000000) >> 34);
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aD = (int)((word & 0x000300000000) >> 32);
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ep = (word & 0x000080000000) != 0;
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Cin = (word & 0x000040000000) != 0;
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enSU = (word & 0x000020000000) != 0;
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mem = (word & 0x000010000000) != 0;
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fSfY = (FunctionSelectFY)((word & 0x00000c000000) >> 26);
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fSfZ = (FunctionSelectFZ)((word & 0x000003000000) >> 24);
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fX = (XFunction)((word & 0x000000f00000) >> 20);
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fY = (int)((word & 0x0000000f0000) >> 16);
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fZ = (int)((word & 0x00000000f000) >> 12);
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INIA = (int)((word & 0x000000000fff));
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//
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// Instruction metadata that can be precomputed and cached
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//
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Cycle = (fX == XFunction.cycle) ||
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(fSfY == FunctionSelectFY.fyNorm && ((YNormFunction)fY) == YNormFunction.cycle);
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Shift =
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((fX == XFunction.shift) ||
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Cycle);
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AluNeedsXBus = (aS == AluSourcePair.D0 || aS == AluSourcePair.DA || aS == AluSourcePair.DQ);
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AluDestination = aD | (Shift ? 0x4 : 0x0);
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SURead = enSU && !Cin;
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SUWrite = enSU && Cin;
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LoadMap = fX == XFunction.LoadMap ||
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(fSfY == FunctionSelectFY.fyNorm &&
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(YNormFunction)fY == YNormFunction.LoadMap);
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ABypass = AluDestination == 0x2;
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LoadStackP = (fSfY == FunctionSelectFY.fyNorm &&
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(YNormFunction)fY == YNormFunction.LoadstackP);
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LoadIBPtr1 = (fSfZ == FunctionSelectFZ.fzNorm && ((ZNormFunction)fZ) == ZNormFunction.LoadIBPtr1);
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AlwaysIBDisp = (fSfY == FunctionSelectFY.fyNorm &&
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(YNormFunction)fY == YNormFunction.IBDisp) &&
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LoadIBPtr1;
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LoadIB = fSfY == FunctionSelectFY.fyNorm &&
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(YNormFunction)fY == YNormFunction.LoadIB;
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UAddress = (rA << 4) | fZ;
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switch (fX)
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{
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case XFunction.pCallRet0:
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case XFunction.pCallRet1:
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case XFunction.pCallRet2:
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case XFunction.pCallRet3:
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case XFunction.pCallRet4:
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case XFunction.pCallRet5:
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case XFunction.pCallRet6:
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case XFunction.pCallRet7:
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LinkAddress = (int)fX;
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break;
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default:
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LinkAddress = -1;
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break;
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}
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MarMapMDR = mem || LoadMap;
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LateLRotN = !ABypass && fSfZ == FunctionSelectFZ.fzNorm;
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if (fSfY == FunctionSelectFY.Byte)
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{
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// Byte constant
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Byte = (byte)((fY << 4) | fZ);
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}
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else if (fSfZ == FunctionSelectFZ.Nibble)
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{
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// Nibble constant
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Byte = (byte)fZ;
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}
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else
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{
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// No constant value.
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Byte = 0;
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}
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bool fxPop = (fX == XFunction.pop);
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bool fzPop = (fSfZ == FunctionSelectFZ.fzNorm && ((ZNormFunction)fZ) == ZNormFunction.pop);
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Pop = fxPop || fzPop;
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//
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// There is a special case if both fxPop and fzPop are specified: stackP is still decremented by 1,
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// but a trap is invoked if stackP is 1 or 0 (rather than just 0).
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//
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DoublePop = fxPop && fzPop;
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Push = (fX == XFunction.push) ||
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(fSfY == FunctionSelectFY.fyNorm && ((YNormFunction)fY) == YNormFunction.push) ||
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(fSfZ == FunctionSelectFZ.fzNorm && ((ZNormFunction)fZ) == ZNormFunction.push);
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StackOperation = Pop || Push;
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//
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// From the HWref (p. 33):
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// "Multiple pop's and push's can be specified per microinstruction in order to ameliorate the detection
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// of Stack overflow or underflow. For instance, fXpop (i.e. the pop in the fX field), fZpop, and
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// push executed together leave the stackPointer unmodified, yet simulate two pop's with respect to
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// stack underflow detection..."
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// The actual overflow detection logic is controlled by a PROM, there's nothing too weird going on
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// here (other than overloading to provide only semi-related semantics, which is annoying.) At
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// any rate, we precompute the check that's being requested (if any) so we don't have to do it
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// at execution time.
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// TODO: might make sense to dump the PROM and use that.
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//
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if (fxPop && fzPop && Push)
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{
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StackTest = StackTestType.Underflow2;
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}
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else if (Push && fzPop)
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{
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StackTest = StackTestType.Overflow;
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}
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else if (fxPop && Push)
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{
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StackTest = StackTestType.Underflow;
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}
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else
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{
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// No non-modify test, just normal stack behavior.
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StackTest = StackTestType.None;
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}
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}
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/// <summary>
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/// 2901 A reg addr, U addr [0-3]
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/// </summary>
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public readonly int rA;
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/// <summary>
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/// 2901 B reg addr, RH addr
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/// </summary>
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public readonly int rB;
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/// <summary>
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/// 2901 alu Source operand pair
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/// </summary>
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public readonly AluSourcePair aS;
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/// <summary>
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/// 2901 alu Function
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/// </summary>
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public readonly AluFunction aF;
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/// <summary>
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/// 2901 alu Destination/shift control
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/// </summary>
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public readonly int aD;
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/// <summary>
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/// Even Parity
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/// </summary>
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public readonly bool ep;
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/// <summary>
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/// 2901 Carry In, Shift Ends, writeSU (if enSU = 1)
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/// </summary>
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public readonly bool Cin;
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/// <summary>
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/// enable SU reg file
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/// </summary>
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public readonly bool enSU;
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/// <summary>
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/// MAR<- (if c1), MDR<- (if c2), <-MD (if c3)
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/// </summary>
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public readonly bool mem;
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/// <summary>
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/// Function field selector for Y
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/// </summary>
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public readonly FunctionSelectFY fSfY;
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/// <summary>
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/// Function field selector for Z
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/// </summary>
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public readonly FunctionSelectFZ fSfZ;
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/// <summary>
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/// X Function
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/// </summary>
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public readonly XFunction fX;
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/// <summary>
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/// Y Function
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/// </summary>
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public readonly int fY;
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/// <summary>
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/// Z Function
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/// </summary>
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public readonly int fZ;
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/// <summary>
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/// Next Instruction Address
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/// </summary>
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public readonly int INIA;
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//
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// The following are metadata for this instruction, used to speed execution.
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//
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/// <summary>
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/// Instruction specifies a Cycle of ALU output when writing back to R/Q
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/// </summary>
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public readonly bool Cycle;
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/// <summary>
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/// Instruction specifies a Shift of ALU as above.
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/// </summary>
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public readonly bool Shift;
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/// <summary>
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/// Instruction requires XBus input to ALU.
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/// </summary>
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public readonly bool AluNeedsXBus;
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/// <summary>
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/// Destination control for the ALU
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/// </summary>
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public readonly int AluDestination;
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/// <summary>
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/// Instruction specifies an SU register read
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/// </summary>
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public readonly bool SURead;
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/// <summary>
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/// Instruction specifies an SU register write
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/// </summary>
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public readonly bool SUWrite;
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/// <summary>
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/// Instruction specifies a Map<- operation.
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/// </summary>
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public readonly bool LoadMap;
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/// <summary>
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/// Instruction uses the A-bypass mode for the ALU.
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/// </summary>
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public readonly bool ABypass;
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/// <summary>
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/// Instruction specifies a stackP<- operation.
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/// </summary>
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public readonly bool LoadStackP;
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/// <summary>
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/// Instruction specifies a push operation
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/// </summary>
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public readonly bool Push;
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/// <summary>
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/// Instruction specifies a pop operation
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/// </summary>
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public readonly bool Pop;
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/// <summary>
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/// Instruction specifies a double-pop operation.
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/// </summary>
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public readonly bool DoublePop;
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/// <summary>
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/// Whether any stack operations (pushes or pops) occur in this instruction.
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/// </summary>
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public readonly bool StackOperation;
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/// <summary>
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/// Specifies the kind of test specified by the various
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/// push/pop instruction fields.
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/// </summary>
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public readonly StackTestType StackTest;
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/// <summary>
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/// Causes an IBDisp branch even if IB is not full;
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/// specified by IBDisp + IBPtr<-1
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/// </summary>
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public readonly bool AlwaysIBDisp;
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/// <summary>
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/// Whether an IB<- is specified this instruction.
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/// </summary>
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public readonly bool LoadIB;
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/// <summary>
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/// Whether the instruction specifies an ibPtr<-1 operation,
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/// which can be used to modify other operations.
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/// </summary>
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public readonly bool LoadIBPtr1;
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/// <summary>
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/// Constant address used to address U register when loading/storing
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/// </summary>
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public readonly int UAddress;
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/// <summary>
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/// Constant byte value
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/// </summary>
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/// <returns></returns>
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public readonly byte Byte;
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/// <summary>
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/// Link address specified by instruction (or -1 if not specified)
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/// </summary>
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public readonly int LinkAddress;
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|
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/// <summary>
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/// Whether the instruction specifies an MAR<-, Map<-, or MDR<- operation.
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/// </summary>
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public readonly bool MarMapMDR;
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|
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/// <summary>
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/// Whether to do an LrotN operation after the ALU runs.
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/// </summary>
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public readonly bool LateLRotN;
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public override string ToString()
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{
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return String.Format("rA={0:x} rB={1:x} aS={2} aF={3} aD={4} ep={5} Cin={6} enSU={7} mem={8} fSY={9} fSZ={10} fX={11} fY={12:x} fZ={13:x} INIA={14:x3}",
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rA, rB, aS, aF, aD, ep, Cin, enSU, mem, fSfY, fSfZ, fX, fY, fZ, INIA);
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}
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|
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public string Disassemble(int cycle)
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{
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//
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// Build ALU op, start with the sources:
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//
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|
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string aluR;
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string aluS;
|
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bool Rzero = false;
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bool Szero = false;
|
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|
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string xBusValue = DisassembleXBusSource(cycle);
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|
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switch (aS)
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{
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case AluSourcePair.AB:
|
|
aluR = String.Format("R{0:x}", rA);
|
|
aluS = String.Format("R{0:x}", rB);
|
|
break;
|
|
|
|
case AluSourcePair.AQ:
|
|
aluR = String.Format("R{0:x}", rA);
|
|
aluS = "Q";
|
|
break;
|
|
|
|
case AluSourcePair.ZA:
|
|
aluR = "0";
|
|
Rzero = true;
|
|
aluS = String.Format("R{0:x}", rA);
|
|
break;
|
|
|
|
case AluSourcePair.ZB:
|
|
aluR = "0";
|
|
Rzero = true;
|
|
aluS = String.Format("R{0:x}", rB);
|
|
break;
|
|
|
|
case AluSourcePair.ZQ:
|
|
aluR = "0";
|
|
Rzero = true;
|
|
aluS = "Q";
|
|
break;
|
|
|
|
case AluSourcePair.D0:
|
|
aluR = xBusValue;
|
|
aluS = "0";
|
|
Szero = true;
|
|
break;
|
|
|
|
case AluSourcePair.DA:
|
|
aluR = xBusValue;
|
|
aluS = String.Format("R{0:x}", rA);
|
|
break;
|
|
|
|
case AluSourcePair.DQ:
|
|
aluR = xBusValue;
|
|
aluS = "Q";
|
|
break;
|
|
|
|
default:
|
|
throw new InvalidOperationException("Unexpected ALU source pair.");
|
|
}
|
|
|
|
//
|
|
// Select operation
|
|
//
|
|
string aluOp;
|
|
switch (aF)
|
|
{
|
|
case AluFunction.RplusS:
|
|
if (Rzero)
|
|
{
|
|
aluOp = aluS;
|
|
}
|
|
else if (Szero)
|
|
{
|
|
aluOp = aluR;
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("{0}+{1}", aluR, aluS);
|
|
}
|
|
break;
|
|
|
|
case AluFunction.SminusR:
|
|
if (Rzero)
|
|
{
|
|
aluOp = aluS;
|
|
}
|
|
else if (Szero)
|
|
{
|
|
aluOp = "-" + aluR;
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("{0}-{1}", aluS, aluR);
|
|
}
|
|
break;
|
|
|
|
case AluFunction.RminusS:
|
|
if (Rzero)
|
|
{
|
|
aluOp = "-" + aluS;
|
|
}
|
|
else if (Szero)
|
|
{
|
|
aluOp = aluR;
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("{0}-{1}", aluR, aluS);
|
|
}
|
|
break;
|
|
|
|
case AluFunction.RorS:
|
|
if (Rzero)
|
|
{
|
|
aluOp = aluS;
|
|
}
|
|
else if (Szero)
|
|
{
|
|
aluOp = aluR;
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("{0} or {1}", aluR, aluS);
|
|
}
|
|
break;
|
|
|
|
case AluFunction.RandS:
|
|
if (Rzero)
|
|
{
|
|
aluOp = "0";
|
|
}
|
|
else if (Szero)
|
|
{
|
|
aluOp = "0";
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("{0} and {1}", aluR, aluS);
|
|
}
|
|
break;
|
|
|
|
case AluFunction.notRandS:
|
|
if (Rzero)
|
|
{
|
|
aluOp = aluS;
|
|
}
|
|
else if (Szero)
|
|
{
|
|
aluOp = "0";
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("~{0} and {1}", aluR, aluS);
|
|
}
|
|
break;
|
|
|
|
case AluFunction.RxorS:
|
|
if (Rzero)
|
|
{
|
|
aluOp = aluS;
|
|
}
|
|
else if (Szero)
|
|
{
|
|
aluOp = aluR;
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("{0} xor {1}", aluR, aluS);
|
|
}
|
|
break;
|
|
|
|
case AluFunction.notRxorS:
|
|
if (Szero)
|
|
{
|
|
aluOp = "~" + aluR;
|
|
}
|
|
else
|
|
{
|
|
aluOp = String.Format("~{0} xor {1}", aluR, aluS);
|
|
}
|
|
break;
|
|
|
|
default:
|
|
throw new InvalidOperationException("Unexpected ALU operation");
|
|
}
|
|
|
|
//
|
|
// Select register writeback (to rB)
|
|
// Q writeback, and Y source (F, or A bypass)
|
|
//
|
|
int writeFn = aD | (Shift ? 0x4 : 0x0);
|
|
string regAssignment;
|
|
bool aBypass = false;
|
|
bool yBusIsSourceForDestination = false;
|
|
bool aluNoWriteBack = false;
|
|
switch(writeFn)
|
|
{
|
|
case 0:
|
|
// no write, Q<-F
|
|
regAssignment = String.Format("Q<- {0}{1}", aluOp, GetCarryMod());
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case 1:
|
|
// no write.
|
|
regAssignment = String.Format("{0}{1}", aluOp, GetCarryMod());
|
|
yBusIsSourceForDestination = false;
|
|
aluNoWriteBack = true;
|
|
break;
|
|
|
|
case 2:
|
|
// R[rB] <- F, no write to Q, A Bypass for YBus<-
|
|
regAssignment = String.Format("R{0:x}<- {1}{2}", rB, aluOp, GetCarryMod());
|
|
aBypass = true;
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case 3:
|
|
// R[rB] <- F, no write to Q
|
|
regAssignment = String.Format("R{0:x}<- {1}{2}", rB, aluOp, GetCarryMod());
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case 4:
|
|
if (Cycle)
|
|
{
|
|
// double-word right shift
|
|
regAssignment = String.Format("R{0:x}<- DRShift1 {1}{2}{3}", rB, aluOp, GetCarryMod(), Cin ? " SE<-1" : String.Empty);
|
|
}
|
|
else
|
|
{
|
|
// double-word arithmetic right shift.
|
|
regAssignment = String.Format("R{0:x}<- DARShift1 {1}{2}{3}", rB, aluOp, GetCarryMod(), Cin ? " SE<-1" : String.Empty);
|
|
}
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case 5:
|
|
if (Cycle)
|
|
{
|
|
// F: single-word right rotate:
|
|
regAssignment = String.Format("R{0:x}<- RRot1 {1}{2}", rB, aluOp, GetCarryMod());
|
|
}
|
|
else
|
|
{
|
|
// F: single-word right shift w/carryIn to MSB:
|
|
regAssignment = String.Format("R{0:x}<- RShift1 {1}{2}{3}", rB, aluOp, GetCarryMod(), Cin ? " SE<-1" : String.Empty);
|
|
}
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case 6:
|
|
if (Cycle)
|
|
{
|
|
// double-word left shift
|
|
regAssignment = String.Format("R{0:x}<- DLShift1 {1}{2}{3}", rB, aluOp, GetCarryMod(), Cin ? " SE<-1" : String.Empty);
|
|
}
|
|
else
|
|
{
|
|
// double-word arithmetic left shift
|
|
regAssignment = String.Format("R{0:x}<- DALShift1 {1}{2}{3}", rB, aluOp, GetCarryMod(), Cin ? " SE<-1" : String.Empty);
|
|
}
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case 7:
|
|
if (Cycle)
|
|
{
|
|
// single-word left rotate:
|
|
regAssignment = String.Format("R{0:x}<- LRot1 {1}{2}", rB, aluOp, GetCarryMod());
|
|
}
|
|
else
|
|
{
|
|
// single-word left shift w/carryIn to MSB:
|
|
regAssignment = String.Format("R{0:x}<- LShift1 {1}{2}{3}", rB, aluOp, GetCarryMod(), Cin ? " SE<-1" : String.Empty);
|
|
}
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
default:
|
|
throw new InvalidOperationException("Unexpected sh,,aD value.");
|
|
}
|
|
|
|
string yBusValue = aBypass ? String.Format("R{0:x}, {1}", rA, regAssignment) : String.Format("{0}", regAssignment);
|
|
|
|
string fxFunc = String.Empty;
|
|
bool xBusIsSourceForDestination = false;
|
|
|
|
bool yBusBranch = false;
|
|
bool xBusBranch = false;
|
|
|
|
// Handle fX functions that aren't implicitly handled elsewhere (shift, cycle)
|
|
switch (fX)
|
|
{
|
|
case XFunction.pCallRet0:
|
|
case XFunction.pCallRet1:
|
|
case XFunction.pCallRet2:
|
|
case XFunction.pCallRet3:
|
|
case XFunction.pCallRet4:
|
|
case XFunction.pCallRet5:
|
|
case XFunction.pCallRet6:
|
|
case XFunction.pCallRet7:
|
|
fxFunc = String.Format("pCall/Ret{0} ", (int)fX);
|
|
break;
|
|
|
|
case XFunction.LoadRH:
|
|
fxFunc = String.Format("RH{0:x}<-", rB);
|
|
xBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case XFunction.LoadCinFrompc16:
|
|
fxFunc = "SE<-pc16 ";
|
|
break;
|
|
|
|
case XFunction.LoadMap:
|
|
fxFunc = String.Format("Map<- RH{0:x},,", rB);
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case XFunction.pop:
|
|
fxFunc = "pop ";
|
|
break;
|
|
|
|
case XFunction.push:
|
|
fxFunc = "push ";
|
|
break;
|
|
}
|
|
|
|
string fyFunc = String.Empty;
|
|
|
|
// Handle fY functions that aren't implicitly handled elsewhere (cycle, Byte, etc.)
|
|
switch (fSfY)
|
|
{
|
|
case FunctionSelectFY.fyNorm:
|
|
switch ((YNormFunction)fY)
|
|
{
|
|
case YNormFunction.ExitKern:
|
|
fyFunc = "ExitKern ";
|
|
break;
|
|
|
|
case YNormFunction.EnterKern:
|
|
fyFunc = "EnterKern ";
|
|
break;
|
|
|
|
case YNormFunction.ClrIntErr:
|
|
fyFunc = "ClrIntErr ";
|
|
break;
|
|
|
|
case YNormFunction.IBDisp:
|
|
fyFunc = "IBDisp ";
|
|
break;
|
|
|
|
case YNormFunction.MesaIntRq:
|
|
fyFunc = "MesaIntRq ";
|
|
break;
|
|
|
|
case YNormFunction.LoadstackP:
|
|
fyFunc = "stackP<-";
|
|
yBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case YNormFunction.LoadIB:
|
|
fyFunc = "IB<-";
|
|
xBusIsSourceForDestination = true;
|
|
break;
|
|
|
|
case YNormFunction.LoadMap:
|
|
fyFunc = String.Format("Map<- RH{0:x},,", rB);
|
|
break;
|
|
|
|
case YNormFunction.Refresh:
|
|
fyFunc = "Refresh ";
|
|
break;
|
|
|
|
case YNormFunction.push:
|
|
fyFunc = "push ";
|
|
break;
|
|
|
|
case YNormFunction.ClrDPRq:
|
|
fyFunc = "ClrDPRq ";
|
|
break;
|
|
|
|
case YNormFunction.ClrIOPRq:
|
|
fyFunc = "ClrIOPRq ";
|
|
break;
|
|
|
|
case YNormFunction.ClrRefRq:
|
|
fyFunc = "ClrRefRq ";
|
|
break;
|
|
|
|
case YNormFunction.ClrKFlags:
|
|
fyFunc = "ClrKFlags ";
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case FunctionSelectFY.DispBr:
|
|
fyFunc = ((YDispBrFunction)fY).ToString() + " ";
|
|
|
|
switch ((YDispBrFunction)fY)
|
|
{
|
|
case YDispBrFunction.NegBr:
|
|
case YDispBrFunction.ZeroBr:
|
|
case YDispBrFunction.NibCarryBr:
|
|
case YDispBrFunction.PgCarryBr:
|
|
case YDispBrFunction.CarryBr:
|
|
case YDispBrFunction.PgCrOvDisp:
|
|
case YDispBrFunction.YDisp:
|
|
case YDispBrFunction.YIODisp:
|
|
yBusBranch = true;
|
|
break;
|
|
|
|
case YDispBrFunction.XRefBr:
|
|
case YDispBrFunction.XwdDisp:
|
|
case YDispBrFunction.XHDisp:
|
|
case YDispBrFunction.XLDisp:
|
|
case YDispBrFunction.XDisp:
|
|
case YDispBrFunction.XC2npcDisp:
|
|
xBusBranch = true;
|
|
break;
|
|
}
|
|
|
|
break;
|
|
|
|
case FunctionSelectFY.IOOut:
|
|
if (fY != 0xb && fY != 0xe)
|
|
{
|
|
YIOOutFunction yIOOut = ((YIOOutFunction)fY);
|
|
fyFunc = yIOOut.ToString() + "<-";
|
|
|
|
// IOOut functions are roughly split between taking data from the XBus or the YBus.
|
|
xBusIsSourceForDestination =
|
|
(yIOOut == YIOOutFunction.IOPOData ||
|
|
yIOOut == YIOOutFunction.IOPCtl ||
|
|
yIOOut == YIOOutFunction.KOData ||
|
|
yIOOut == YIOOutFunction.KCtl ||
|
|
yIOOut == YIOOutFunction.EOData ||
|
|
yIOOut == YIOOutFunction.EICtl ||
|
|
yIOOut == YIOOutFunction.DCtl ||
|
|
yIOOut == YIOOutFunction.PCtl ||
|
|
yIOOut == YIOOutFunction.EOCtl ||
|
|
yIOOut == YIOOutFunction.KCmd ||
|
|
yIOOut == YIOOutFunction.POData
|
|
);
|
|
|
|
yBusIsSourceForDestination = (!xBusIsSourceForDestination && (fY != 0xb && fY != 0xe));
|
|
|
|
}
|
|
break;
|
|
}
|
|
|
|
string fzFunc = String.Empty;
|
|
|
|
// Handle fZ functions that aren't implicitly handled elsewhere (IOXIn)
|
|
switch (fSfZ)
|
|
{
|
|
case FunctionSelectFZ.fzNorm:
|
|
switch((ZNormFunction)fZ)
|
|
{
|
|
case ZNormFunction.Refresh:
|
|
fzFunc = "Refresh ";
|
|
break;
|
|
|
|
case ZNormFunction.LoadIBPtr1:
|
|
fzFunc = "IBPtr<-1 ";
|
|
break;
|
|
|
|
case ZNormFunction.LoadIBPtr0:
|
|
fzFunc = "IBPtr<-0 ";
|
|
break;
|
|
|
|
case ZNormFunction.LoadCinFrompc16:
|
|
fzFunc = "SE<-pc16 ";
|
|
break;
|
|
|
|
case ZNormFunction.pop:
|
|
fzFunc = "pop ";
|
|
break;
|
|
|
|
case ZNormFunction.push:
|
|
fzFunc = "push ";
|
|
break;
|
|
|
|
case ZNormFunction.AltUaddr:
|
|
fzFunc = "AltUaddr ";
|
|
break;
|
|
|
|
case ZNormFunction.LRot0:
|
|
fzFunc = "LRot0 ";
|
|
break;
|
|
|
|
case ZNormFunction.LRot12:
|
|
fzFunc = "LRot12 ";
|
|
break;
|
|
|
|
case ZNormFunction.LRot8:
|
|
fzFunc = "LRot8 ";
|
|
break;
|
|
|
|
case ZNormFunction.LRot4:
|
|
fzFunc = "LRot4 ";
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
// SU reg write
|
|
string suWriteStr = String.Empty;
|
|
bool suWrite = enSU && Cin;
|
|
bool suRead = enSU && !Cin;
|
|
if (suWrite)
|
|
{
|
|
switch((int)fSfZ)
|
|
{
|
|
case 0:
|
|
case 1:
|
|
suWriteStr = "STK<-";
|
|
break;
|
|
|
|
case 2:
|
|
case 3:
|
|
suWriteStr = String.Format("U{0:x2}<-", (rA << 4) | fZ);
|
|
break;
|
|
}
|
|
|
|
yBusIsSourceForDestination = true;
|
|
}
|
|
|
|
if(!yBusIsSourceForDestination && !xBusIsSourceForDestination)
|
|
{
|
|
suWriteStr = "Xbus<- ";
|
|
|
|
// Y bus is implicitly used to provide an X bus value if nothing else is selected.
|
|
yBusIsSourceForDestination = string.IsNullOrEmpty(xBusValue);
|
|
}
|
|
|
|
// MAR or MDR writes:
|
|
string memWrite = String.Empty;
|
|
|
|
if (mem)
|
|
{
|
|
if (cycle == 1)
|
|
{
|
|
memWrite = "MAR<- ";
|
|
}
|
|
else if (cycle == 2)
|
|
{
|
|
memWrite = "MDR<- ";
|
|
}
|
|
else if (cycle == -1)
|
|
{
|
|
memWrite = "{MAR/MDR/MD} ";
|
|
}
|
|
|
|
yBusIsSourceForDestination = true;
|
|
}
|
|
|
|
//
|
|
// The below is kind of messy because of conflation of the ALU with the Y-Bus way up above, etc.
|
|
// Bear with me.
|
|
//
|
|
|
|
//
|
|
// The Y Bus value is important and needs to be included in the disassembly if one or more of the
|
|
// below are true:
|
|
// - A register assignment is taking place
|
|
// - The Y Bus is being used as a data source
|
|
// - A dispatch or branch involving the Y Bus or ALU is being invoked during this instruction.
|
|
//
|
|
bool showyBusValue = (yBusBranch || yBusIsSourceForDestination || !aluNoWriteBack);
|
|
|
|
//
|
|
// The X Bus value is important and needs to be included in the disassembly if one or more of the
|
|
// below are true:
|
|
// - The ALU isn't already using the X Bus as an input
|
|
// - The X Bus is being used as a data source
|
|
// - A dispatch or branch involving the X Bus is being invoked during this instruction.
|
|
//
|
|
bool showxBusValue = (xBusBranch || !AluNeedsXBus || xBusIsSourceForDestination);
|
|
|
|
string disassembly = String.Format("{0}{1}{2}{3}{4}{5}{6} [{7:x3}]",
|
|
fxFunc,
|
|
fyFunc,
|
|
fzFunc,
|
|
memWrite,
|
|
suWriteStr,
|
|
showxBusValue ? xBusValue : String.Empty,
|
|
showyBusValue ? yBusValue : String.Empty,
|
|
INIA);
|
|
|
|
|
|
return disassembly;
|
|
}
|
|
|
|
private string GetCarryMod()
|
|
{
|
|
string mod = String.Empty;
|
|
bool add = (aF == AluFunction.RplusS);
|
|
bool sub = (aF == AluFunction.RminusS || aF == AluFunction.SminusR);
|
|
|
|
if (Cin & add)
|
|
{
|
|
mod = "+1";
|
|
}
|
|
else if (!Cin & sub)
|
|
{
|
|
mod = "-1";
|
|
}
|
|
|
|
return mod;
|
|
}
|
|
|
|
private string DisassembleXBusSource(int cycle)
|
|
{
|
|
string xBus = String.Empty;
|
|
|
|
// Byte and/or Nibble. In theory these are mutually exclusive,
|
|
// but there's nothing that prevents them both from being coded at the same time.
|
|
// If this happens, Byte takes precedence.
|
|
if (fSfY == FunctionSelectFY.Byte)
|
|
{
|
|
xBus = String.Format("byte({0:x2})", ((fY << 4) | fZ));
|
|
}
|
|
|
|
if(fSfZ == FunctionSelectFZ.Nibble && fSfY != FunctionSelectFY.Byte)
|
|
{
|
|
xBus = String.Format("nibble({0:x1})", fZ);
|
|
}
|
|
else if (fSfZ == FunctionSelectFZ.IOXIn)
|
|
{
|
|
// IOXIn sources
|
|
switch((ZIOXIn)fZ)
|
|
{
|
|
case ZIOXIn.ReadEIdata:
|
|
xBus += "EIData";
|
|
break;
|
|
|
|
case ZIOXIn.ReadEStatus:
|
|
xBus += "EStatus";
|
|
break;
|
|
|
|
case ZIOXIn.ReadKIData:
|
|
xBus += "KIData";
|
|
break;
|
|
|
|
case ZIOXIn.ReadKStatus:
|
|
xBus += "KStatus";
|
|
break;
|
|
|
|
case ZIOXIn.ReadMStatus:
|
|
xBus += "MStatus";
|
|
break;
|
|
|
|
case ZIOXIn.ReadKTest:
|
|
xBus += "KTest";
|
|
break;
|
|
|
|
case ZIOXIn.ReadIOPIData:
|
|
xBus += "IOPIData";
|
|
break;
|
|
|
|
case ZIOXIn.ReadIOPStatus:
|
|
xBus += "IOPStatus";
|
|
break;
|
|
|
|
case ZIOXIn.ReadErrnIBnStkp:
|
|
xBus += "ErrnIBnStkP";
|
|
break;
|
|
|
|
case ZIOXIn.ReadRH:
|
|
xBus += String.Format("RH{0:x}", rB);
|
|
break;
|
|
|
|
case ZIOXIn.ReadibNA:
|
|
xBus += "ibNA";
|
|
break;
|
|
|
|
case ZIOXIn.ReadibLow:
|
|
xBus += "ibLow";
|
|
break;
|
|
|
|
case ZIOXIn.ReadibHigh:
|
|
xBus += "ibHigh";
|
|
break;
|
|
|
|
default:
|
|
xBus += ((ZIOXIn)fZ).ToString();
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (enSU && !Cin) // Cin is 0 for reads
|
|
{
|
|
// SU read operations
|
|
switch((int)fSfZ)
|
|
{
|
|
case 0:
|
|
case 1:
|
|
xBus += "STK";
|
|
break;
|
|
|
|
case 2:
|
|
case 3:
|
|
xBus += String.Format("U{0:x2}", (rA << 4) | fZ);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (mem && cycle == 3)
|
|
{
|
|
xBus += "<-MD";
|
|
}
|
|
|
|
return xBus;
|
|
}
|
|
}
|
|
}
|