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215 lines
7.2 KiB
Plaintext
215 lines
7.2 KiB
Plaintext
IOP notes. These are gleaned from various bits of documentation and source code.
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There is no official IOP documentation available.
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Hardware:
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- CPU: 8085
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- FDC: WD FD1797
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- i8253 programmable interval timer
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- i8251 UART
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- i8257 dma controller
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- Z80-SIO for RS232C/RS366 (?? not present on PCB...)
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Memory Map (see SysDefs.asm):
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$0000-$1FFF : PROM (8K)
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$2000-$5FFF : RAM (16K)
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$8000-$800F : Host Addr PROM
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$8010-$FFFF : Memory Mapped-I/O
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Map of PROM ICs to ROM Locations:
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3.1 :
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U129 - 537P03029 - $0000
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U130 - 537P03030 - $0800
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U131 - 537P03700 - $1000
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U132 - 537P03032 - $1800
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I/O addresses:
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$80-$83 - Alto PPI
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$84 - FDC Command (write)
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$84 - FDC Status (read)
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$85 - FDC Track register (write)
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$86 - FDC Sector register (write)
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$87 - FDC Data register (write, read?)
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$88 - Printer Data (read/write)
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$89 - Printer Commands (write)
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$89 - Printer Status (read)
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$8C - Timer Counter 0 (read/write)
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$8D - Timer Counter 1 (read/write)
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$8E - Timer Counter 2 (read/write)
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$8F - Timer Mode (commands) (write)
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$90 - LSEP Uart Data
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$91 - LSEP Uart Command
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$92 - LSEP Uart Status
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$94 - LSEP Timer Counter 0
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$95 - Counter for SIO
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$96 - Counter for Time Counter
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$97 - LSEP Timer Mode / Baud Rate Gen. Control Register (?)
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$98 - SIO Channel A Data Register
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$99 - " B "
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$9A - SIO Channel A Control Register
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$9B - " B "
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$9C - RS366 register
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$A0 - $A8 - DMA Controller
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$B0 - $BF - Host PROM data (read)
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$E0 - Keyset (read?)
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$E8 - FDC External State
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$E9 - KB, MP, TOD clocks (write)
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$E9 - Interrupt request bits (read)
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$EA - clear TOD interrupt (write)
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$EA - Keyboard data latch (read)
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$EB - CP data in (read)
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$EB - CP data out (write)
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$EC - CP (central processor) control register (write)
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$EC - CP status (read)
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$ED - Mouse X counter (read)
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$ED - Clear mouse X, Y counters (write)
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$EE - Mouse Y counter (read)
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$EE - Clear CP DMA Complete (write)
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$EF - Misc I/O devices (keyboard, clocks, etc.) input
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$EF - Misc control (write)
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$F8-$FF - Control Store read/write:
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; Format of TPCHigh (write): TPCAddr[0:2],,TPCData[0:4]'
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; Format of TPCLow (write): don't care,,TPCData[5:11]'
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$FE - TPC High (inverted)
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$FF - TPC Low (inverted)
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$F8-$FD - 48 bits of control store, MSB -> LSB, bits inverted.
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Memory-Mapped IO:
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-----------------
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$80ec - CPControl - CP control register : IOPWait',,SwTAddr',,IOPAttn,,CPDmaMode,,CPDmaIn (write)
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$80ec - CPStatus (read)
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$80eb - CP data in (read)
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$80eb - CP data out (write)
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CP <-> IOP comms
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----------------
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In WriteCPbyte (BootSubs.asm), addr $71b:
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WaitCPOutAck expects CPStatus to have the interrupt mask bit set after data is written, loops until this is so.
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CP interrupts from IOP:
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from Kernel.mc:
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"The Kernel can be entered by one of two ways: Either via a breakpoint or the IOP asynchronously interrupting the CP
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via the IOPWait line. If entry is via a breakpoint, the kernel can be entered in any cycle (and inter-cycle state
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information must be preserved). IOPWait caused entry always occurs between clicks (so all state information is already
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saved by the CP and there is no memory state across clicks which can be lost, saved or restored).
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Upon entering the kernel, it interrupts the IOP and waits for a command byte. There are 3 possible commands that the
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IOP can specify: Refresh, ExitKernel, and ExecuteBufffer. Refresh is used by the IOP when it is writing the CS,
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ExitKernel causes the CP to leave the kernel task, and ExecuteBuffer causes the instructions which the IOP wrote in
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the buffer area to be executed.
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When the kernel is entered via a breakpoint, an R register (rK) must be used to hold memory data or a breakpoint ID
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(or an RH reg for ID), and a Link register to hold condition bits (or a breakpoint ID).
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When being entered via an IOPWait, no R register state need be lost (currently rK is lost) (i.e. rK and RHrK can first
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be saved away, then later restored. There should also be a second kind of ExitKernel command which doesn't write Mem[0]).
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Currently, the kernel is written assuming it can always use rK, so this register is lost in the IOPWait caused entry
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also. (rK is used in the wait loop and in the overlay code which Burdock uses to read and write some registers.) "
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Status / Control registers:
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IOP Ports:
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CPControl: IOP -> CP (IOP write) ($EC)
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- IOP uses this to control the CP; IOPAttn is set if the IOP needs attention from the CP?
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- Bits are: (from IOP schematic, p 15):
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- CPDmaIn - 0x8
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- CPDmaMode - 0x10
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- IOPAttn - 0x20
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- SwTAddr' - 0x40
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- IOPWait' - 0x80
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CPStatus: CP -> IOP (IOP read) ($EC)
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- CP reports its status to the IOP, also includes IOP status
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- Bits are: (from IOP schematic, p 17):
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- CPDmaComplete' - 0x1
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- CPOutIntReq' - 0x2
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- CPInIntReq' - 0x4
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- CPDmaIn' - 0x8 - From CPControl
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- CPDmaMode' - 0x10 - "
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- IOPAttn' - 0x20 - "
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- EmuWake - 0x40 - From IOPCtl<-
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- CPAttn - 0x80 - "
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CP Ports:
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IOPCtl<-: CP-> IOP (CP write)
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- CP sets up communication between the IOP and the CP:
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- Bits are:
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- WakeMode.1 - 0x1
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- WakeMode.0 - 0x2
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- CPAttn - 0x4
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- EmuWake - 0x8 (is this actually used?)
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Per uCode and Schematic (IOP, p 15), the WakeMode bits are:
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- 00 = Disabled (no wakeups)
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- 01 = Input (wakeup when Input from IOP is available)
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- 10 = Output (wakeup when IOP is ready for data from CP)
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- 11 = Always wake up
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<-IOPStatus: IOP -> CP (CP read)
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- CP gets the IOP's status
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- Bits are (from IOP schematic, p 15):
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- IOPReq - 0x1 - set when data available from IOP?
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- WakeMode.1' - 0x2
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- WakeMode.0' - 0x4
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- CPAttn' - 0x8
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- EmuWake' = 0x10
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- IOPAttn - 0x20
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- Bits 0x40, 0x80 are always set low
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Communication register:
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- Appears to be a data register (8 bits + flow control) between the IOP and the CP; IOP gets status (interrupt?) when CP has written data to be read,
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CP can get woken up when the IOP has written data (see below).
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CP Wakeups for IOP:
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- If IOPInMode is set, the CP's IOP task will wake up if input is available from the IOP (in the data register)
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- If IOPOutMode is set, wakeups will occur if the output data register is empty (i.e. the IOP is ready to receive a word.)
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- If IOPAWmode is set (In and Out bits set) the IOP will always wake up regardless
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Interrupts:
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----------
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Three interrupt lines on the CPU are used as following:
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RST5.5 - CP Interrupt caused by CPAttn going high (also Burdock, the Alto debugging iface)
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RST6.5 - RS232 interrupt
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RST7.5 - Floppy Interrupt
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- Do no other devices actually cause interrupts?
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There is an interrupt status register that can be polled at i/o port 0xe9:
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- FloppyIntReq : 0x80
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- KBIntr : 0x40
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- PrinterTxRdy : 0x20
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- PrinterRxRdy : 0x10
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- MiscInt : 0x08
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- RS232Int' : 0x04
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- LSEP UART Tx' : 0x2
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- LSEP UART Rx' : 0x1
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DMA:
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---
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The Intel 8257 DMA controller deals with DMA transfers for the FDC (Ch 0) and CP (Ch 1). Channels 2 and 3 go unused.
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