mirror of
https://github.com/livingcomputermuseum/MDE2.git
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756 lines
43 KiB
VHDL
756 lines
43 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.std_logic_UNSIGNED.ALL;
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use IEEE.std_logic_ARITH.ALL;
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--
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-- Copyright (C) 2009, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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package IDROMConst is
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constant QCountRev : std_logic_vector(7 downto 0) := x"02";
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constant MQCRev: std_logic_vector(7 downto 0) := x"03";
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constant KUBStepGenRev : std_logic_vector(7 downto 0) := x"02";
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constant NullAddr : std_logic_vector(7 downto 0) := x"00";
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constant ReadIDAddr : std_logic_vector(7 downto 0) := x"01";
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constant LEDAddr : std_logic_vector(7 downto 0) := x"02";
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constant LEDNumRegs : std_logic_vector(7 downto 0) := x"01";
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constant LEDMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
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constant IDROMAddr : std_logic_vector(7 downto 0) := x"04";
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constant Cookie : std_logic_vector(31 downto 0) := x"55AACAFE";
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constant HostMotNameLow : std_logic_vector(31 downto 0) := x"54534F48"; -- HOST
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constant HostMotNameHigh : std_logic_vector(31 downto 0) := x"32544F4D"; -- MOT2
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constant BoardNameMesa : std_logic_vector(31 downto 0) := x"4153454D"; -- MESA
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constant BoardName4I65 : std_logic_vector(31 downto 0) := x"35364934"; -- 4I65
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constant BoardName4I68 : std_logic_vector(31 downto 0) := x"38364934"; -- 4I68
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constant BoardName4I69 : std_logic_vector(31 downto 0) := x"39364934"; -- 4I69
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constant BoardName4I74 : std_logic_vector(31 downto 0) := x"34374934"; -- 4I74
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constant BoardName5I20 : std_logic_vector(31 downto 0) := x"30324935"; -- 5I20
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constant BoardName5I21 : std_logic_vector(31 downto 0) := x"31324935"; -- 5I21
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constant BoardName5I22 : std_logic_vector(31 downto 0) := x"32324935"; -- 5I22
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constant BoardName5I23 : std_logic_vector(31 downto 0) := x"33324935"; -- 5I23
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constant BoardName5I25 : std_logic_vector(31 downto 0) := x"35324935"; -- 5I25
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constant BoardName6I25 : std_logic_vector(31 downto 0) := x"35324936"; -- 6I25
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constant BoardName7I43 : std_logic_vector(31 downto 0) := x"33344937"; -- 7I43
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constant BoardName7I60 : std_logic_vector(31 downto 0) := x"30364937"; -- 7I60
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constant BoardName7I61 : std_logic_vector(31 downto 0) := x"31364937"; -- 7I61
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constant BoardName7I62 : std_logic_vector(31 downto 0) := x"32364937"; -- 7I62
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constant BoardName7I80HD : std_logic_vector(31 downto 0) := x"30384937"; -- 7I80HD
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constant BoardName7I80DB : std_logic_vector(31 downto 0) := x"30384937"; -- 7I80DB
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constant BoardName7I77E : std_logic_vector(31 downto 0) := x"37374937"; -- 7I77E
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constant BoardName3X20 : std_logic_vector(31 downto 0) := x"30325833"; -- 3X20
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constant BoardName3X21 : std_logic_vector(31 downto 0) := x"30325833"; -- 3X21
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constant BoardName7I90 : std_logic_vector(31 downto 0) := x"30394937"; -- 7I90
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constant IDROMOffset : std_logic_vector(31 downto 0) := x"0000"&IDROMAddr&x"00"; -- note need to change if pitch changed
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constant IDROMWEnAddr : std_logic_vector(7 downto 0) := x"08";
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constant IRQDivAddr : std_logic_vector(7 downto 0) := x"09";
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constant IRQStatusAddr : std_logic_vector(7 downto 0) := x"0A";
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constant ClearIRQAddr : std_logic_vector(7 downto 0) := x"0B";
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constant IRQNumRegs : std_logic_vector(7 downto 0) := x"03";
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constant IRQMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
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constant WatchdogTimeAddr : std_logic_vector(7 downto 0) := x"0C";
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constant WatchDogStatusAddr : std_logic_vector(7 downto 0) := x"0D";
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constant WatchDogCookieAddr : std_logic_vector(7 downto 0) := x"0E";
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constant WatchDogNumRegs : std_logic_vector(7 downto 0) := x"03";
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constant WatchDogMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
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constant DMDMAModeAddr : std_logic_vector(7 downto 0) := x"0F"; -- demand mode DMA
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constant DMDMANumRegs : std_logic_vector(7 downto 0) := x"01";
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constant DMDMAMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
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constant PortAddr : std_logic_vector(7 downto 0) := x"10"; -- GPIO port
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constant DDRAddr : std_logic_vector(7 downto 0) := x"11"; -- GPIO/ALT DDR
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constant AltDataSrcAddr : std_logic_vector(7 downto 0) := x"12";
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constant OpenDrainModeAddr : std_logic_vector(7 downto 0) := x"13";
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constant OutputInvAddr : std_logic_vector(7 downto 0) := x"14";
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constant IOPortNumRegs : std_logic_vector(7 downto 0) := x"05";
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constant IOPortMPBitMask : std_logic_vector(31 downto 0) := x"0000001F";
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constant FAbsDataAddr0 : std_logic_vector(7 downto 0) := x"15";
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constant FAbsDataAddr1 : std_logic_vector(7 downto 0) := x"16";
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constant FAbsDataAddr2 : std_logic_vector(7 downto 0) := x"17";
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constant FAbsControlAddr0 : std_logic_vector(7 downto 0) := x"18";
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constant FAbsControlAddr1 : std_logic_vector(7 downto 0) := x"19";
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constant FAbsGlobalPStartAddr : std_logic_vector(7 downto 0) := x"1A";
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constant FAbsNumRegs : std_logic_vector(7 downto 0) := x"03";
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constant FAbsMPBitMask : std_logic_vector(31 downto 0) := x"0000001F";
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-- free 1B-1F
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constant StepGenRateAddr : std_logic_vector(7 downto 0) := x"20";
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constant StepGenAccumAddr : std_logic_vector(7 downto 0) := x"21";
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constant StepGenModeAddr : std_logic_vector(7 downto 0) := x"22";
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constant StepGenDSUTimeAddr : std_logic_vector(7 downto 0) := x"23";
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constant StepGenDHLDTimeAddr : std_logic_vector(7 downto 0) := x"24";
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constant StepGenPulseATimeAddr : std_logic_vector(7 downto 0) := x"25";
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constant StepGenPulseITimeAddr : std_logic_vector(7 downto 0) := x"26";
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constant StepGenTableAddr : std_logic_vector(7 downto 0) := x"27";
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constant StepGenTableMaxAddr : std_logic_vector(7 downto 0) := x"28";
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constant StepGenBasicRateAddr : std_logic_vector(7 downto 0) := x"29";
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constant StepGenNumRegs : std_logic_vector(7 downto 0) := x"0A";
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constant StepGenMPBitMask : std_logic_vector(31 downto 0) := x"000001FF";
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constant WaveGenRateAddr : std_logic_vector(7 downto 0) := x"2A";
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constant WaveGenPDMRateAddr : std_logic_vector(7 downto 0) := x"2B";
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constant WaveGenLengthAddr : std_logic_vector(7 downto 0) := x"2C";
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constant WaveGenTablePtrAddr : std_logic_vector(7 downto 0) := x"2D";
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constant WaveGenTableDataAddr : std_logic_vector(7 downto 0) := x"2E";
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constant WaveGenNumRegs : std_logic_vector(7 downto 0) := x"05";
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constant WaveGenMPBitMask : std_logic_vector(31 downto 0) := x"0000001F";
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-- free 2F
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constant QCounterAddr : std_logic_vector(7 downto 0) := x"30";
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constant QCounterCCRAddr : std_logic_vector(7 downto 0) := x"31";
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constant TSDivAddr : std_logic_vector(7 downto 0) := x"32";
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constant TSAddr : std_logic_vector(7 downto 0) := x"33";
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constant QCRateAddr : std_logic_vector(7 downto 0) := x"34";
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constant QCounterNumRegs : std_logic_vector(7 downto 0) := x"05";
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constant QCounterMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
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constant MuxedQCounterAddr : std_logic_vector(7 downto 0) := x"35";
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constant MuxedQCounterCCRAddr : std_logic_vector(7 downto 0) := x"36";
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constant MuxedTSDivAddr : std_logic_vector(7 downto 0) := x"37";
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constant MuxedTSAddr : std_logic_vector(7 downto 0) := x"38";
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constant MuxedQCRateAddr : std_logic_vector(7 downto 0) := x"39";
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constant MuxedQCounterNumRegs : std_logic_vector(7 downto 0) := x"05";
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constant MuxedQCounterMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
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constant ResModCommandAddr : std_logic_vector(7 downto 0) := x"3A"; -- peculiar addressing, one set of control regs per 6 channels
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constant ResModDataAddr : std_logic_vector(7 downto 0) := x"3B";
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constant ResModStatusAddr : std_logic_vector(7 downto 0) := x"3C";
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constant ResModVelRAMAddr : std_logic_vector(7 downto 0) := x"3D";
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constant ResModPosRAMAddr : std_logic_vector(7 downto 0) := x"3E";
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constant ResModNumRegs : std_logic_vector(7 downto 0) := x"05";
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constant ResModMPBitMask : std_logic_vector(31 downto 0) := x"0000001F";
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-- free 3F
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constant PWMValAddr : std_logic_vector(7 downto 0) := x"40";
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constant PWMCRAddr : std_logic_vector(7 downto 0) := x"41";
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constant PWMRateAddr : std_logic_vector(7 downto 0) := x"42";
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constant PDMRateAddr : std_logic_vector(7 downto 0) := x"43";
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constant PWMEnasAddr : std_logic_vector(7 downto 0) := x"44";
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constant PWMNumRegs : std_logic_vector(7 downto 0) := x"05";
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constant PWMMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
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constant TPPWMValAddr : std_logic_vector(7 downto 0) := x"45";
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constant TPPWMEnaAddr : std_logic_vector(7 downto 0) := x"46";
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constant TPPWMDZAddr : std_logic_vector(7 downto 0) := x"47";
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constant TPPWMRateAddr : std_logic_vector(7 downto 0) := x"48";
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constant TPPWMNumRegs : std_logic_vector(7 downto 0) := x"04";
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constant TPPWMMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
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constant BISSDataAddr : std_logic_vector(7 downto 0) := x"49";
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constant BISSControlAddr : std_logic_vector(7 downto 0) := x"4A";
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constant BISSGlobalPStartAddr : std_logic_vector(7 downto 0) := x"4B";
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constant BISSNumRegs : std_logic_vector(7 downto 0) := x"03";
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constant BISSMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
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constant TwiddlerCommandAddr : std_logic_vector(7 downto 0) := x"4C"; -- peculiar addressing, one set of control regs per 4-16 channels
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constant TwiddlerDataAddr : std_logic_vector(7 downto 0) := x"4D";
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constant TwiddlerRAMAddr : std_logic_vector(7 downto 0) := x"4E";
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constant TwiddlerNumRegs : std_logic_vector(7 downto 0) := x"03";
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constant TwiddlerMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
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-- free 4F
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constant SPIDataAddr : std_logic_vector(7 downto 0) := x"50";
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constant SPIBitCountAddr : std_logic_vector(7 downto 0) := x"51";
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constant SPIBitrateAddr : std_logic_vector(7 downto 0) := x"52";
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constant SPINumRegs : std_logic_vector(7 downto 0) := x"03";
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constant SPIMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
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constant BinOscEnaAddr : std_logic_vector(7 downto 0) := x"53";
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constant BinOscNumRegs : std_logic_vector(7 downto 0) := x"01";
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constant BinOscMPBitMask : std_logic_vector(31 downto 0) := x"00000001";
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constant BSPIDataAddr : std_logic_vector(7 downto 0) := x"54";
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constant BSPIDescriptorAddr : std_logic_vector(7 downto 0) := x"55";
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constant BSPIFIFOCountAddr : std_logic_vector(7 downto 0) := x"56";
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constant BSPINumRegs : std_logic_vector(7 downto 0) := x"03";
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constant BSPIMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
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constant DBSPIDataAddr : std_logic_vector(7 downto 0) := x"57"; -- should be same as BSPI
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constant DBSPIDescriptorAddr : std_logic_vector(7 downto 0) := x"58";
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constant DBSPIFIFOCountAddr : std_logic_vector(7 downto 0) := x"59";
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constant DBSPINumRegs : std_logic_vector(7 downto 0) := x"03";
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constant DBSPIMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
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constant SSerialCommandAddr : std_logic_vector(7 downto 0) := x"5A"; -- peculiar addressing, one set of control regs per 4-16 channels
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constant SSerialDataAddr : std_logic_vector(7 downto 0) := x"5B";
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constant SSerialRAMAddr0 : std_logic_vector(7 downto 0) := x"5C"; -- CSR
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constant SSerialRAMAddr1 : std_logic_vector(7 downto 0) := x"5D"; -- User0
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constant SSerialRAMAddr2 : std_logic_vector(7 downto 0) := x"5E"; -- User1
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constant SSerialRAMAddr3 : std_logic_vector(7 downto 0) := x"5F"; -- User2
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constant SSerialNumRegs : std_logic_vector(7 downto 0) := x"06";
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constant SSerialMPBitMask : std_logic_vector(31 downto 0) := x"0000003C";
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constant UARTTDataAddr : std_logic_vector(7 downto 0) := x"60";
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constant UARTTFIFOCountAddr : std_logic_vector(7 downto 0) := x"61";
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constant UARTTBitrateAddr: std_logic_vector(7 downto 0) := x"62";
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constant UARTTModeRegAddr : std_logic_vector(7 downto 0) := x"63";
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constant UARTTNumRegs : std_logic_vector(7 downto 0) := x"04";
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constant UARTTMPBitMask : std_logic_vector(31 downto 0) := x"0000000F";
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constant UARTRDataAddr : std_logic_vector(7 downto 0) := x"64";
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constant UARTRFIFOCountAddr : std_logic_vector(7 downto 0) := x"65";
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constant UARTRBitrateAddr : std_logic_vector(7 downto 0) := x"66";
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constant UARTRModeRegAddr : std_logic_vector(7 downto 0) := x"67";
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constant UARTRNumRegs : std_logic_vector(7 downto 0) := x"04";
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constant UARTRMPBitMask : std_logic_vector(31 downto 0) := x"0000000F";
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constant SSSIDataAddr : std_logic_vector(7 downto 0) := x"68";
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constant SSSIControlAddr : std_logic_vector(7 downto 0) := x"69";
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constant SSSIGlobalPStartAddr : std_logic_vector(7 downto 0) := x"6A";
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constant SSSINumRegs : std_logic_vector(7 downto 0) := x"03";
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constant SSSIMPBitMask : std_logic_vector(31 downto 0) := x"00000003";
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-- free 6B
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constant DAQFIFODataAddr : std_logic_vector(7 downto 0) := x"6C";
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constant DAQFIFOCountAddr : std_logic_vector(7 downto 0) := x"6D";
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constant DAQFIFOModeAddr : std_logic_vector(7 downto 0) := x"6E";
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constant DAQFIFONumRegs : std_logic_vector(7 downto 0) := x"03";
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constant DAQFIFOMPBitMask : std_logic_vector(31 downto 0) := x"00000007";
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-- free 6F
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constant DPLLFreqLowAddr : std_logic_vector(7 downto 0) := x"70"; -- note overlaps translate RAM!
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constant DPLLFreqHighAddr : std_logic_vector(7 downto 0) := x"71"; -- will fix in the great re-alignment
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constant DPLLPostScaleAddr : std_logic_vector(7 downto 0) := x"72";
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constant DPLLIRateAddr : std_logic_vector(7 downto 0) := x"73";
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constant DPLLILimitAddr : std_logic_vector(7 downto 0) := x"74";
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constant DPLLPTweakAddr : std_logic_vector(7 downto 0) := x"75";
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constant DPLLITweakAddr : std_logic_vector(7 downto 0) := x"76";
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constant DPLLCountAddr : std_logic_vector(7 downto 0) := x"77";
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constant DPLLPhaseErrAddr : std_logic_vector(7 downto 0) := x"78";
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constant DPLLPostErrAddr : std_logic_vector(7 downto 0) := x"79";
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constant DPLLPostCountAddr : std_logic_vector(7 downto 0) := x"7A";
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constant DPLLControlAddr : std_logic_vector(7 downto 0) := x"7B";
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constant DPLLNumRegs : std_logic_vector(7 downto 0) := x"0C";
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constant DPLLMPBitMask : std_logic_vector(31 downto 0) := x"000003FF";
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constant TranslateRamAddr : std_logic_vector(7 downto 0) := x"78";
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constant TranslateRegionAddr : std_logic_vector(7 downto 0) := x"7C";
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constant TranslateNumRegs : std_logic_vector(7 downto 0) := x"04";
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constant TranslateMPBitMask : std_logic_vector(31 downto 0) := x"00000000";
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constant ClockLow20: integer := 33333333; -- 5I20/4I65 low speed clock
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constant ClockLow22: integer := 48000000; -- 5I22/5I23 low speed clock
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constant ClockLow23: integer := 48000000; -- 5I22/5I23 low speed clock
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constant ClockLow25: integer := 33333333; -- 5I25 low speed clock
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constant ClockLow6I25: integer := 66666666; -- 6I25 low speed clock
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constant ClockLow21: integer := 48000000; -- 5I21 low speed clock
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constant ClockLow43: integer := 50000000; -- 7I43 low speed clock
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constant ClockLow43U: integer := 33333333; -- 7I43U low speed clock
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constant ClockLow61: integer := 50000000; -- 7I61 low speed clock
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constant ClockLow68: integer := 48000000; -- 4I68 low speed clock
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constant ClockLow69: integer := 50000000; -- 4I69 low speed clock
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constant ClockLowx20: integer := 50000000; -- 3X20 low speed clock
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constant ClockLow80: integer := 100000000; -- 7I80 low speed clock
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constant ClockLow90: integer := 100000000; -- 7I90 low speed clock
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constant ClockMed20: integer := 50000000; -- 5I20/4I65 medium speed clock
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constant ClockMed21: integer := 72000000; -- 5I21 medium speed clock
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constant ClockMed22: integer := 72000000; -- 5I22/5I23 medium speed clock
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constant ClockMed23: integer := 72000000; -- 5I22/5I23 medium speed clock
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constant ClockMed25: integer := 100000000; -- 5I25 medium speed clock
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constant ClockMed6I25: integer := 100000000; -- 6I25 medium speed clock
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constant ClockMed43: integer := 75000000; -- 7I43 medium speed clock
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constant ClockMed43U: integer := 75000000; -- 7I43U medium speed clock
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constant ClockMed61: integer := 100000000; -- 7I61 medium speed clock
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constant ClockMed68: integer := 72000000; -- 4I68 medium speed clock
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constant ClockMed69: integer := 100000000; -- 4I69 medium speed clock
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constant ClockMedx20: integer := 75000000; -- 3X20 medium speed clock
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constant ClockMed80: integer := 100000000; -- 7I80 medium speed clock
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constant ClockMed90: integer := 100000000; -- 7I90 medium speed clock
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constant ClockHigh20: integer := 100000000; -- 5I20/4I65 high speed clock
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constant ClockHigh21: integer := 96000000; -- 5I21 high speed clock
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constant ClockHigh22: integer := 96000000; -- 5I22/5I23 high speed clock
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constant ClockHigh23: integer := 96000000; -- 5I22/5I23 high speed clock
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constant ClockHigh25: integer := 200000000; -- 5I25 high speed clock
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constant ClockHigh6I25: integer := 200000000; -- 6I25 high speed clock
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constant ClockHigh43: integer := 100000000; -- 7I43 high speed clock
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constant ClockHigh43U: integer := 100000000; -- 7I43U high speed clock
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constant ClockHigh61: integer := 200000000; -- 7I61 high speed clock
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constant ClockHigh61u: integer := 200000000; -- 7I61U high speed clock
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constant ClockHigh68: integer := 96000000; -- 4I68 high speed clock
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constant ClockHigh69: integer := 100000000; -- 4I69 high speed clock
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constant ClockHighx20: integer := 100000000; -- 3X20 high speed clock
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constant ClockHigh80: integer := 200000000; -- 7I80 high speed clock
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constant ClockHigh90: integer := 200000000; -- 7I90 high speed clock
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constant ClockLowTag: std_logic_vector(7 downto 0) := x"01";
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constant ClockHighTag: std_logic_vector(7 downto 0) := x"02";
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constant NullTag : std_logic_vector(7 downto 0) := x"00";
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constant NullPin : std_logic_vector(7 downto 0) := x"00";
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constant IRQTag : std_logic_vector(7 downto 0) := x"01";
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constant WatchDogTag : std_logic_vector(7 downto 0) := x"02";
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constant IOPortTag : std_logic_vector(7 downto 0) := x"03";
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constant QCountTag : std_logic_vector(7 downto 0) := x"04";
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constant QCountQAPin : std_logic_vector(7 downto 0) := x"01";
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constant QCountQBPin : std_logic_vector(7 downto 0) := x"02";
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constant QCountIdxPin : std_logic_vector(7 downto 0) := x"03";
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constant QCountIdxMaskPin : std_logic_vector(7 downto 0) := x"04";
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constant QCountProbePin : std_logic_vector(7 downto 0) := x"05";
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constant StepGenTag : std_logic_vector(7 downto 0) := x"05";
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constant StepGenStepPin : std_logic_vector(7 downto 0) := x"81";
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constant StepGenDirPin : std_logic_vector(7 downto 0) := x"82";
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constant StepGenTable2Pin : std_logic_vector(7 downto 0) := x"83";
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constant StepGenTable3Pin : std_logic_vector(7 downto 0) := x"84";
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constant StepGenTable4Pin : std_logic_vector(7 downto 0) := x"85";
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constant StepGenTable5Pin : std_logic_vector(7 downto 0) := x"86";
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constant StepGenTable6Pin : std_logic_vector(7 downto 0) := x"87";
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constant StepGenTable7Pin : std_logic_vector(7 downto 0) := x"88";
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constant StepGenIndexPin : std_logic_vector(7 downto 0) := x"01";
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constant StepGenProbePin : std_logic_vector(7 downto 0) := x"02";
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constant PWMTag : std_logic_vector(7 downto 0) := x"06";
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constant PWMAOutPin : std_logic_vector(7 downto 0) := x"81";
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constant PWMBDirPin : std_logic_vector(7 downto 0) := x"82";
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constant PWMCEnaPin : std_logic_vector(7 downto 0) := x"83";
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constant SPITag : std_logic_vector(7 downto 0) := x"07";
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constant SPIFramePin : std_logic_vector(7 downto 0) := x"81";
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constant SPIOutPin : std_logic_vector(7 downto 0) := x"82";
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constant SPIClkPin : std_logic_vector(7 downto 0) := x"83";
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constant SPIInPin : std_logic_vector(7 downto 0) := x"04";
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constant SSSITag : std_logic_vector(7 downto 0) := x"08";
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constant SSSIClkPin : std_logic_vector(7 downto 0) := x"81";
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constant SSSIDataPin : std_logic_vector(7 downto 0) := x"02";
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constant UARTTTag : std_logic_vector(7 downto 0) := x"09";
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constant UTDataPin : std_logic_vector(7 downto 0) := x"81";
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constant UTDrvEnPin : std_logic_vector(7 downto 0) := x"82";
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constant UARTRTag : std_logic_vector(7 downto 0) := x"0A";
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constant URDataPin : std_logic_vector(7 downto 0) := x"01";
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constant AddrXTag : std_logic_vector(7 downto 0) := x"0B";
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constant MuxedQCountTag: std_logic_vector(7 downto 0) := x"0C";
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constant MuxedQCountQAPin : std_logic_vector(7 downto 0) := x"01";
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constant MuxedQCountQBPin : std_logic_vector(7 downto 0) := x"02";
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constant MuxedQCountIdxPin : std_logic_vector(7 downto 0) := x"03";
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constant MuxedQCountIdxMaskPin : std_logic_vector(7 downto 0) := x"04";
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constant MuxedQCountProbePin : std_logic_vector(7 downto 0) := x"05";
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constant MuxedQCountSelTag: std_logic_vector(7 downto 0) := x"0D";
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constant MuxedQCountSel0Pin : std_logic_vector(7 downto 0) := x"81";
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constant MuxedQCountSel1Pin : std_logic_vector(7 downto 0) := x"82";
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constant BSPITag : std_logic_vector(7 downto 0) := x"0E";
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constant BSPIFramePin : std_logic_vector(7 downto 0) := x"81";
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constant BSPIOutPin : std_logic_vector(7 downto 0) := x"82";
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constant BSPIClkPin : std_logic_vector(7 downto 0) := x"83";
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constant BSPIInPin : std_logic_vector(7 downto 0) := x"04";
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constant BSPICS0Pin : std_logic_vector(7 downto 0) := x"85";
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constant BSPICS1Pin : std_logic_vector(7 downto 0) := x"86";
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constant BSPICS2Pin : std_logic_vector(7 downto 0) := x"87";
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constant BSPICS3Pin : std_logic_vector(7 downto 0) := x"88";
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constant BSPICS4Pin : std_logic_vector(7 downto 0) := x"89";
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constant BSPICS5Pin : std_logic_vector(7 downto 0) := x"8A";
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constant BSPICS6Pin : std_logic_vector(7 downto 0) := x"8B";
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constant BSPICS7Pin : std_logic_vector(7 downto 0) := x"8C";
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constant DBSPITag : std_logic_vector(7 downto 0) := x"0F";
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constant DBSPIOutPin : std_logic_vector(7 downto 0) := x"82";
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constant DBSPIClkPin : std_logic_vector(7 downto 0) := x"83";
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constant DBSPIInPin : std_logic_vector(7 downto 0) := x"04";
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constant DBSPICS0Pin : std_logic_vector(7 downto 0) := x"85";
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constant DBSPICS1Pin : std_logic_vector(7 downto 0) := x"86";
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constant DBSPICS2Pin : std_logic_vector(7 downto 0) := x"87";
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constant DBSPICS3Pin : std_logic_vector(7 downto 0) := x"88";
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constant DBSPICS4Pin : std_logic_vector(7 downto 0) := x"89";
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constant DBSPICS5Pin : std_logic_vector(7 downto 0) := x"8A";
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constant DBSPICS6Pin : std_logic_vector(7 downto 0) := x"8B";
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constant DBSPICS7Pin : std_logic_vector(7 downto 0) := x"8C";
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constant DPLLTag: std_logic_vector(7 downto 0) := x"10";
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constant DPLLSyncInPin : std_logic_vector(7 downto 0) := x"01";
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constant DPLLMSBOutPin : std_logic_vector(7 downto 0) := x"82";
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constant DPLLFOutPin : std_logic_vector(7 downto 0) := x"83";
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constant DPLLPostOutPin : std_logic_vector(7 downto 0) := x"84";
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constant DPLLSyncTogPin : std_logic_vector(7 downto 0) := x"85";
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-- these are a muxed index mask varient of the muxed q counter
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-- since they will never co-exist with the non muxed index mask varient
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|
-- they share the same register decodes
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constant MuxedQCountMIMTag: std_logic_vector(7 downto 0) := x"11";
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constant MuxedQCountMIMQAPin : std_logic_vector(7 downto 0) := x"01";
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constant MuxedQCountMIMQBPin : std_logic_vector(7 downto 0) := x"02";
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constant MuxedQCountMIMIdxPin : std_logic_vector(7 downto 0) := x"03";
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constant MuxedQCountMIMIdxMaskPin : std_logic_vector(7 downto 0) := x"04";
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constant MuxedQCountSelMIMTag: std_logic_vector(7 downto 0) := x"12";
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constant MuxedQCountSelMIM0Pin : std_logic_vector(7 downto 0) := x"81";
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constant MuxedQCountSelMIM1Pin : std_logic_vector(7 downto 0) := x"82";
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constant TPPWMTag : std_logic_vector(7 downto 0) := x"13";
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constant TPPWMAOutPin : std_logic_vector(7 downto 0) := x"81";
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constant TPPWMBOutPin : std_logic_vector(7 downto 0) := x"82";
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constant TPPWMCOutPin : std_logic_vector(7 downto 0) := x"83";
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constant NTPPWMAOutPin : std_logic_vector(7 downto 0) := x"84";
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constant NTPPWMBOutPin : std_logic_vector(7 downto 0) := x"85";
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constant NTPPWMCOutPin : std_logic_vector(7 downto 0) := x"86";
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constant TPPWMEnaPin : std_logic_vector(7 downto 0) := x"87";
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|
constant TPPWMFaultPin : std_logic_vector(7 downto 0) := x"08";
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constant WavegenTag : std_logic_vector(7 downto 0) := x"14";
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|
constant PDMAOutPin : std_logic_vector(7 downto 0) := x"81";
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constant PDMBOutPin : std_logic_vector(7 downto 0) := x"82";
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constant Trigger0OutPin : std_logic_vector(7 downto 0) := x"83";
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constant Trigger1OutPin: std_logic_vector(7 downto 0) := x"84";
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constant Trigger2OutPin : std_logic_vector(7 downto 0) := x"85";
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constant Trigger3OutPin : std_logic_vector(7 downto 0) := x"86";
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constant DAQFIFOTag : std_logic_vector(7 downto 0) := x"15";
|
|
constant DAQFIFOStrobePin : std_logic_vector(7 downto 0) := x"41";
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|
constant DAQFIFOFullPin : std_logic_vector(7 downto 0) := x"81";
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|
constant DAQFIFOData0Pin : std_logic_vector(7 downto 0) := x"01";
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constant DAQFIFOData1Pin : std_logic_vector(7 downto 0) := x"02";
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constant DAQFIFOData2Pin : std_logic_vector(7 downto 0) := x"03";
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|
constant DAQFIFOData3Pin : std_logic_vector(7 downto 0) := x"04";
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constant DAQFIFOData4Pin : std_logic_vector(7 downto 0) := x"05";
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|
constant DAQFIFOData5Pin : std_logic_vector(7 downto 0) := x"06";
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constant DAQFIFOData6Pin : std_logic_vector(7 downto 0) := x"07";
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|
constant DAQFIFOData7Pin : std_logic_vector(7 downto 0) := x"08";
|
|
constant DAQFIFOData8Pin : std_logic_vector(7 downto 0) := x"09";
|
|
constant DAQFIFOData9Pin : std_logic_vector(7 downto 0) := x"0A";
|
|
constant DAQFIFODataAPin : std_logic_vector(7 downto 0) := x"0B";
|
|
constant DAQFIFODataBPin : std_logic_vector(7 downto 0) := x"0C";
|
|
constant DAQFIFODataCPin : std_logic_vector(7 downto 0) := x"0D";
|
|
constant DAQFIFODataDPin : std_logic_vector(7 downto 0) := x"0E";
|
|
constant DAQFIFODataEPin : std_logic_vector(7 downto 0) := x"0F";
|
|
constant DAQFIFODataFPin : std_logic_vector(7 downto 0) := x"10";
|
|
constant DAQFIFOData10Pin : std_logic_vector(7 downto 0) := x"11";
|
|
constant DAQFIFOData11Pin : std_logic_vector(7 downto 0) := x"12";
|
|
constant DAQFIFOData12Pin : std_logic_vector(7 downto 0) := x"13";
|
|
constant DAQFIFOData13Pin : std_logic_vector(7 downto 0) := x"14";
|
|
constant DAQFIFOData14Pin : std_logic_vector(7 downto 0) := x"15";
|
|
constant DAQFIFOData15Pin : std_logic_vector(7 downto 0) := x"16";
|
|
constant DAQFIFOData16Pin : std_logic_vector(7 downto 0) := x"17";
|
|
constant DAQFIFOData17Pin : std_logic_vector(7 downto 0) := x"18";
|
|
constant DAQFIFOData18Pin : std_logic_vector(7 downto 0) := x"19";
|
|
constant DAQFIFOData19Pin : std_logic_vector(7 downto 0) := x"1A";
|
|
constant DAQFIFOData1APin : std_logic_vector(7 downto 0) := x"1B";
|
|
constant DAQFIFOData1BPin : std_logic_vector(7 downto 0) := x"1C";
|
|
constant DAQFIFOData1CPin : std_logic_vector(7 downto 0) := x"1D";
|
|
constant DAQFIFOData1DPin : std_logic_vector(7 downto 0) := x"1E";
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|
|
|
constant BinOscTag : std_logic_vector(7 downto 0) := x"16";
|
|
constant BinOscOut0Pin : std_logic_vector(7 downto 0) := x"81";
|
|
constant BinOscOut1Pin : std_logic_vector(7 downto 0) := x"82";
|
|
constant BinOscOut2Pin : std_logic_vector(7 downto 0) := x"83";
|
|
constant BinOscOut3Pin : std_logic_vector(7 downto 0) := x"84";
|
|
constant BinOscOut4Pin : std_logic_vector(7 downto 0) := x"85";
|
|
constant BinOscOut5Pin : std_logic_vector(7 downto 0) := x"86";
|
|
constant BinOscOut6Pin : std_logic_vector(7 downto 0) := x"87";
|
|
constant BinOscOut7Pin : std_logic_vector(7 downto 0) := x"88";
|
|
constant BinOscOut8Pin : std_logic_vector(7 downto 0) := x"89";
|
|
constant BinOscOut9Pin : std_logic_vector(7 downto 0) := x"8A";
|
|
constant BinOscOutAPin : std_logic_vector(7 downto 0) := x"8B";
|
|
constant BinOscOutBPin : std_logic_vector(7 downto 0) := x"8C";
|
|
constant BinOscOutCPin : std_logic_vector(7 downto 0) := x"8D";
|
|
constant BinOscOutDPin : std_logic_vector(7 downto 0) := x"8E";
|
|
constant BinOscOutEPin : std_logic_vector(7 downto 0) := x"8F";
|
|
constant BinOscOutFPin : std_logic_vector(7 downto 0) := x"90";
|
|
constant BinOscOut10Pin : std_logic_vector(7 downto 0) := x"91";
|
|
constant BinOscOut11Pin : std_logic_vector(7 downto 0) := x"92";
|
|
constant BinOscOut12Pin : std_logic_vector(7 downto 0) := x"93";
|
|
constant BinOscOut13Pin : std_logic_vector(7 downto 0) := x"94";
|
|
constant BinOscOut14Pin : std_logic_vector(7 downto 0) := x"95";
|
|
constant BinOscOut15Pin : std_logic_vector(7 downto 0) := x"96";
|
|
constant BinOscOut16Pin : std_logic_vector(7 downto 0) := x"97";
|
|
constant BinOscOut17Pin : std_logic_vector(7 downto 0) := x"98";
|
|
constant BinOscOut18Pin : std_logic_vector(7 downto 0) := x"99";
|
|
constant BinOscOut19Pin : std_logic_vector(7 downto 0) := x"9A";
|
|
constant BinOscOut1APin : std_logic_vector(7 downto 0) := x"9B";
|
|
constant BinOscOut1BPin : std_logic_vector(7 downto 0) := x"9C";
|
|
constant BinOscOut1CPin : std_logic_vector(7 downto 0) := x"9D";
|
|
constant BinOscOut1DPin : std_logic_vector(7 downto 0) := x"9E";
|
|
constant BinOscOut1EPin : std_logic_vector(7 downto 0) := x"9F";
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|
|
|
constant DMDMATag : std_logic_vector(7 downto 0) := x"17";
|
|
|
|
constant BISSTag : std_logic_vector(7 downto 0) := x"18";
|
|
constant BISSClkPin : std_logic_vector(7 downto 0) := x"81";
|
|
constant BISSDataPin : std_logic_vector(7 downto 0) := x"02";
|
|
|
|
constant FAbsTag : std_logic_vector(7 downto 0) := x"19";
|
|
constant FAbsRQPin : std_logic_vector(7 downto 0) := x"81";
|
|
constant FAbsTestClkPin : std_logic_vector(7 downto 0) := x"82";
|
|
constant FAbsDataPin : std_logic_vector(7 downto 0) := x"03";
|
|
|
|
constant LIOPortTag : std_logic_vector(7 downto 0) := x"40";
|
|
|
|
constant ResModTag: std_logic_vector(7 downto 0) := x"C0";
|
|
constant ResModPwrEnPin : std_logic_vector(7 downto 0) := x"81";
|
|
constant ResModPDMPPin : std_logic_vector(7 downto 0) := x"82";
|
|
constant ResModPDMMPin : std_logic_vector(7 downto 0) := x"83";
|
|
constant ResModChan0Pin : std_logic_vector(7 downto 0) := x"84";
|
|
constant ResModChan1Pin : std_logic_vector(7 downto 0) := x"85";
|
|
constant ResModChan2Pin : std_logic_vector(7 downto 0) := x"86";
|
|
constant ResModSPICSPin : std_logic_vector(7 downto 0) := x"87";
|
|
constant ResModSPIClkPin : std_logic_vector(7 downto 0) := x"88";
|
|
constant ResModTestBitPin : std_logic_vector(7 downto 0) := x"89";
|
|
constant ResModSPIDI0Pin : std_logic_vector(7 downto 0) := x"09";
|
|
constant ResModSPIDI1Pin : std_logic_vector(7 downto 0) := x"0A";
|
|
|
|
constant SSerialTag: std_logic_vector(7 downto 0) := x"C1";
|
|
constant SSerialRX0Pin : std_logic_vector(7 downto 0) := x"01"; -- note, 15 ports max per SSerial module
|
|
constant SSerialRX1Pin : std_logic_vector(7 downto 0) := x"02";
|
|
constant SSerialRX2Pin : std_logic_vector(7 downto 0) := x"03";
|
|
constant SSerialRX3Pin : std_logic_vector(7 downto 0) := x"04";
|
|
constant SSerialRX4Pin : std_logic_vector(7 downto 0) := x"05";
|
|
constant SSerialRX5Pin : std_logic_vector(7 downto 0) := x"06";
|
|
constant SSerialRX6Pin : std_logic_vector(7 downto 0) := x"07";
|
|
constant SSerialRX7Pin : std_logic_vector(7 downto 0) := x"08";
|
|
constant SSerialRX8Pin : std_logic_vector(7 downto 0) := x"09"; -- note, 15 ports max per SSerial module
|
|
constant SSerialRX9Pin : std_logic_vector(7 downto 0) := x"0A";
|
|
constant SSerialRXAPin : std_logic_vector(7 downto 0) := x"0B";
|
|
constant SSerialRXBPin : std_logic_vector(7 downto 0) := x"0C";
|
|
constant SSerialRXCPin : std_logic_vector(7 downto 0) := x"0D";
|
|
constant SSerialRXDPin : std_logic_vector(7 downto 0) := x"0E";
|
|
constant SSerialRXEPin : std_logic_vector(7 downto 0) := x"0F";
|
|
constant SSerialTX0Pin : std_logic_vector(7 downto 0) := x"81";
|
|
constant SSerialTX1Pin : std_logic_vector(7 downto 0) := x"82";
|
|
constant SSerialTX2Pin : std_logic_vector(7 downto 0) := x"83";
|
|
constant SSerialTX3Pin : std_logic_vector(7 downto 0) := x"84";
|
|
constant SSerialTX4Pin : std_logic_vector(7 downto 0) := x"85";
|
|
constant SSerialTX5Pin : std_logic_vector(7 downto 0) := x"86";
|
|
constant SSerialTX6Pin : std_logic_vector(7 downto 0) := x"87";
|
|
constant SSerialTX7Pin : std_logic_vector(7 downto 0) := x"88";
|
|
constant SSerialTX8Pin : std_logic_vector(7 downto 0) := x"89";
|
|
constant SSerialTX9Pin : std_logic_vector(7 downto 0) := x"8A";
|
|
constant SSerialTXAPin : std_logic_vector(7 downto 0) := x"8B";
|
|
constant SSerialTXBPin : std_logic_vector(7 downto 0) := x"8C";
|
|
constant SSerialTXCPin : std_logic_vector(7 downto 0) := x"8D";
|
|
constant SSerialTXDPin : std_logic_vector(7 downto 0) := x"8E";
|
|
constant SSerialTXEPin : std_logic_vector(7 downto 0) := x"8F";
|
|
constant SSerialTXEn0Pin : std_logic_vector(7 downto 0) := x"91";
|
|
constant SSerialTXEn1Pin : std_logic_vector(7 downto 0) := x"92";
|
|
constant SSerialTXEn2Pin : std_logic_vector(7 downto 0) := x"93";
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constant SSerialTXEn3Pin : std_logic_vector(7 downto 0) := x"94";
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constant SSerialTXEn4Pin : std_logic_vector(7 downto 0) := x"95";
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constant SSerialTXEn5Pin : std_logic_vector(7 downto 0) := x"96";
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constant SSerialTXEn6Pin : std_logic_vector(7 downto 0) := x"97";
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constant SSerialTXEn7Pin : std_logic_vector(7 downto 0) := x"98";
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constant SSerialTXEn8Pin : std_logic_vector(7 downto 0) := x"99";
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constant SSerialTXEn9Pin : std_logic_vector(7 downto 0) := x"9A";
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constant SSerialTXEnAPin : std_logic_vector(7 downto 0) := x"9B";
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constant SSerialTXEnBPin : std_logic_vector(7 downto 0) := x"9C";
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constant SSerialTXEnCPin : std_logic_vector(7 downto 0) := x"9D";
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constant SSerialTXEnDPin : std_logic_vector(7 downto 0) := x"9E";
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constant SSerialTXEnEPin : std_logic_vector(7 downto 0) := x"9F";
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constant SSerialTestPin : std_logic_vector(7 downto 0) := x"A1";
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constant TwiddlerTag: std_logic_vector(7 downto 0) := x"C2";
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constant TwiddlerIn0Pin: std_logic_vector(7 downto 0) := x"01"; -- note 31 pins max
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constant TwiddlerIn1Pin: std_logic_vector(7 downto 0) := x"02";
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constant TwiddlerIn2Pin: std_logic_vector(7 downto 0) := x"03";
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constant TwiddlerIn3Pin: std_logic_vector(7 downto 0) := x"04";
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constant TwiddlerIn4Pin: std_logic_vector(7 downto 0) := x"05";
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constant TwiddlerIn5Pin: std_logic_vector(7 downto 0) := x"06";
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constant TwiddlerIn6Pin: std_logic_vector(7 downto 0) := x"07";
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constant TwiddlerIn7Pin: std_logic_vector(7 downto 0) := x"08";
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constant TwiddlerIn8Pin: std_logic_vector(7 downto 0) := x"09";
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constant TwiddlerIn9Pin: std_logic_vector(7 downto 0) := x"0A";
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constant TwiddlerInAPin: std_logic_vector(7 downto 0) := x"0B";
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constant TwiddlerInBPin: std_logic_vector(7 downto 0) := x"0C";
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constant TwiddlerInCPin: std_logic_vector(7 downto 0) := x"0D";
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constant TwiddlerInDPin: std_logic_vector(7 downto 0) := x"0E";
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constant TwiddlerInEPin: std_logic_vector(7 downto 0) := x"0F";
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constant TwiddlerInFPin: std_logic_vector(7 downto 0) := x"10";
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constant TwiddlerIn10Pin: std_logic_vector(7 downto 0) := x"11";
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constant TwiddlerIn11Pin: std_logic_vector(7 downto 0) := x"12";
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constant TwiddlerIn12Pin: std_logic_vector(7 downto 0) := x"13";
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constant TwiddlerIn13Pin: std_logic_vector(7 downto 0) := x"14";
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constant TwiddlerIn14Pin: std_logic_vector(7 downto 0) := x"15";
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constant TwiddlerIn15Pin: std_logic_vector(7 downto 0) := x"16";
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constant TwiddlerIn16Pin: std_logic_vector(7 downto 0) := x"17";
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constant TwiddlerIn17Pin: std_logic_vector(7 downto 0) := x"18";
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constant TwiddlerIn18Pin: std_logic_vector(7 downto 0) := x"19";
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constant TwiddlerIn19Pin: std_logic_vector(7 downto 0) := x"1A";
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constant TwiddlerIn1APin: std_logic_vector(7 downto 0) := x"1B";
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constant TwiddlerIn1BPin: std_logic_vector(7 downto 0) := x"1C";
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constant TwiddlerIn1CPin: std_logic_vector(7 downto 0) := x"1D";
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constant TwiddlerIn1DPin: std_logic_vector(7 downto 0) := x"1E";
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constant TwiddlerIn1EPin: std_logic_vector(7 downto 0) := x"1F";
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constant TwiddlerIO0Pin: std_logic_vector(7 downto 0) := x"C1";
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constant TwiddlerIO1Pin: std_logic_vector(7 downto 0) := x"C2";
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constant TwiddlerIO2Pin: std_logic_vector(7 downto 0) := x"C3";
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constant TwiddlerIO3Pin: std_logic_vector(7 downto 0) := x"C4";
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constant TwiddlerIO4Pin: std_logic_vector(7 downto 0) := x"C5";
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constant TwiddlerIO5Pin: std_logic_vector(7 downto 0) := x"C6";
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constant TwiddlerIO6Pin: std_logic_vector(7 downto 0) := x"C7";
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constant TwiddlerIO7Pin: std_logic_vector(7 downto 0) := x"C8";
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constant TwiddlerIO8Pin: std_logic_vector(7 downto 0) := x"C9";
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constant TwiddlerIO9Pin: std_logic_vector(7 downto 0) := x"CA";
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constant TwiddlerIOAPin: std_logic_vector(7 downto 0) := x"CB";
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constant TwiddlerIOBPin: std_logic_vector(7 downto 0) := x"CC";
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constant TwiddlerIOCPin: std_logic_vector(7 downto 0) := x"CD";
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constant TwiddlerIODPin: std_logic_vector(7 downto 0) := x"CE";
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constant TwiddlerIOEPin: std_logic_vector(7 downto 0) := x"CF";
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constant TwiddlerIOFPin: std_logic_vector(7 downto 0) := x"D0";
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constant TwiddlerIO10Pin: std_logic_vector(7 downto 0) := x"D1";
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constant TwiddlerIO11Pin: std_logic_vector(7 downto 0) := x"D2";
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constant TwiddlerIO12Pin: std_logic_vector(7 downto 0) := x"D3";
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constant TwiddlerIO13Pin: std_logic_vector(7 downto 0) := x"D4";
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constant TwiddlerIO14Pin: std_logic_vector(7 downto 0) := x"D5";
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constant TwiddlerIO15Pin: std_logic_vector(7 downto 0) := x"D6";
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constant TwiddlerIO16Pin: std_logic_vector(7 downto 0) := x"D7";
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constant TwiddlerIO17Pin: std_logic_vector(7 downto 0) := x"D8";
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constant TwiddlerIO18Pin: std_logic_vector(7 downto 0) := x"D9";
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constant TwiddlerIO19Pin: std_logic_vector(7 downto 0) := x"DA";
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constant TwiddlerIO1APin: std_logic_vector(7 downto 0) := x"DB";
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constant TwiddlerIO1BPin: std_logic_vector(7 downto 0) := x"DC";
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constant TwiddlerIO1CPin: std_logic_vector(7 downto 0) := x"DD";
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constant TwiddlerIO1DPin: std_logic_vector(7 downto 0) := x"DE";
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constant TwiddlerIO1EPin: std_logic_vector(7 downto 0) := x"DF";
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constant TwiddlerOut0Pin: std_logic_vector(7 downto 0) := x"81";
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constant TwiddlerOut1Pin: std_logic_vector(7 downto 0) := x"82";
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constant TwiddlerOut2Pin: std_logic_vector(7 downto 0) := x"83";
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constant TwiddlerOut3Pin: std_logic_vector(7 downto 0) := x"84";
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constant TwiddlerOut4Pin: std_logic_vector(7 downto 0) := x"85";
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constant TwiddlerOut5Pin: std_logic_vector(7 downto 0) := x"86";
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constant TwiddlerOut6Pin: std_logic_vector(7 downto 0) := x"87";
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constant TwiddlerOut7Pin: std_logic_vector(7 downto 0) := x"88";
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constant TwiddlerOut8Pin: std_logic_vector(7 downto 0) := x"89";
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constant TwiddlerOut9Pin: std_logic_vector(7 downto 0) := x"8A";
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constant TwiddlerOutAPin: std_logic_vector(7 downto 0) := x"8B";
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constant TwiddlerOutBPin: std_logic_vector(7 downto 0) := x"8C";
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constant TwiddlerOutCPin: std_logic_vector(7 downto 0) := x"8D";
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constant TwiddlerOutDPin: std_logic_vector(7 downto 0) := x"8E";
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constant TwiddlerOutEPin: std_logic_vector(7 downto 0) := x"8F";
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constant TwiddlerOutFPin: std_logic_vector(7 downto 0) := x"90";
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constant TwiddlerOut10Pin: std_logic_vector(7 downto 0) := x"91";
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constant TwiddlerOut11Pin: std_logic_vector(7 downto 0) := x"92";
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constant TwiddlerOut12Pin: std_logic_vector(7 downto 0) := x"93";
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constant TwiddlerOut13Pin: std_logic_vector(7 downto 0) := x"94";
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constant TwiddlerOut14Pin: std_logic_vector(7 downto 0) := x"95";
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constant TwiddlerOut15Pin: std_logic_vector(7 downto 0) := x"96";
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constant TwiddlerOut16Pin: std_logic_vector(7 downto 0) := x"97";
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constant TwiddlerOut17Pin: std_logic_vector(7 downto 0) := x"98";
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constant TwiddlerOut18Pin: std_logic_vector(7 downto 0) := x"99";
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constant TwiddlerOut19Pin: std_logic_vector(7 downto 0) := x"9A";
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constant TwiddlerOut1APin: std_logic_vector(7 downto 0) := x"9B";
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constant TwiddlerOut1BPin: std_logic_vector(7 downto 0) := x"9C";
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constant TwiddlerOut1CPin: std_logic_vector(7 downto 0) := x"9D";
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constant TwiddlerOut1DPin: std_logic_vector(7 downto 0) := x"9E";
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constant TwiddlerOut1EPin: std_logic_vector(7 downto 0) := x"9F";
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constant LEDTag : std_logic_vector(7 downto 0) := x"80";
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constant GlobalChan: std_logic_vector(7 downto 0) := x"80";
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constant emptypin : std_logic_vector(31 downto 0) := x"00000000";
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constant empty : std_logic_vector(31 downto 0) := x"00000000";
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constant PadT : std_logic_vector(7 downto 0) := x"00";
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constant MaxModules : integer := 32; -- maximum number of module types
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constant MaxPins : integer := 144; -- maximum number of I/O pins
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-- would be better to change all the pindescs to records
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-- but that requires reversing the byte order of the constant
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-- pindesc arrays, some other day...
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type PinDescRecord is -- not used yet!
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record
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SecPin : std_logic_vector(7 downto 0);
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SecFunc : std_logic_vector(7 downto 0);
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SecInst : std_logic_vector(7 downto 0);
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PriFunc : std_logic_vector(7 downto 0);
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end record;
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type PinDescType is array(0 to MaxPins -1) of std_logic_vector(31 downto 0);
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type ModuleRecord is -- probably need an alternate way for smart modules
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record
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GTag : std_logic_vector(7 downto 0);
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Version : std_logic_vector(7 downto 0);
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Clock : std_logic_vector(7 downto 0);
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NumInstances : std_logic_vector(7 downto 0);
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BaseAddr : std_logic_vector(15 downto 0);
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NumRegisters : std_logic_vector(7 downto 0);
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Strides : std_logic_vector(7 downto 0);
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MultRegs : std_logic_vector(31 downto 0);
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end record;
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type ModuleIDType is array(0 to MaxModules-1) of ModuleRecord;
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end package IDROMConst;
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