diff --git a/10.01_base/2_src/arm/memoryimage.cpp b/10.01_base/2_src/arm/memoryimage.cpp
index aef407e..0082f88 100644
--- a/10.01_base/2_src/arm/memoryimage.cpp
+++ b/10.01_base/2_src/arm/memoryimage.cpp
@@ -204,7 +204,7 @@ bool memoryimage_c::load_addr_value_text(const char *fname) {
 
 	fin = fopen(fname, "r");
 	if (!fin) {
-		printf("%s\n", fileErrorText("Error opening file %s for write", fname)) ;		
+		printf("%s\n", fileErrorText("Error opening file %s for write", fname)) ;
 		return false;
 	}
 	entry_address = MEMORY_ADDRESS_INVALID; // not known
@@ -538,6 +538,7 @@ bool memoryimage_c::load_papertape(const char *fname) {
 	entry_address = MEMORY_ADDRESS_INVALID; // not yet known
 
 	stream_byte_index = 0;
+    block_byte_size = addr = 0 ; // -Wmaybe-uninitialized
 	while (!feof(fin)) {
 		b = fgetc(fin);
 		// ERROR("[0x%04x] state=%d b=0x%02x sum=0x%02x block_byte_idx=%d",
diff --git a/10.01_base/2_src/arm/pru.cpp b/10.01_base/2_src/arm/pru.cpp
index 89efebc..e0b92db 100644
--- a/10.01_base/2_src/arm/pru.cpp
+++ b/10.01_base/2_src/arm/pru.cpp
@@ -134,6 +134,7 @@ int pru_c::start(enum prucode_enum prucode_id) {
 	// use stop() before restart()
 	assert(this->prucode_id == PRUCODE_NONE);
 
+
 	/* initialize PRU */
 	if ((rtn = prussdrv_init()) != 0) {
 		ERROR("prussdrv_init() failed");
@@ -152,6 +153,7 @@ int pru_c::start(enum prucode_enum prucode_id) {
 		goto error;
 	}
 
+
 	/*
 	 http://credentiality2.blogspot.com/2015/09/beaglebone-pru-ddr-memory-access.html
 	 * get pointer to shared DDR
@@ -165,6 +167,13 @@ int pru_c::start(enum prucode_enum prucode_id) {
 	ddrmem->base_physical = prussdrv_get_phys_addr((void *) (ddrmem->base_virtual));
 	ddrmem->info(); // may abort program
 
+	// get address of mail box struct in PRU
+	mailbox_connect();
+	// now all mailbox command fields initialized/cleared, PRUs can be started
+
+	// get address of device register descriptor struct in PRU
+	iopageregisters_connect();
+
 	// search code in dictionary
 	struct prucode_entry *pce;
 	for (pce = prucode; pce->id != prucode_id && pce->id != PRUCODE_EOD; pce++)
@@ -190,19 +199,20 @@ int pru_c::start(enum prucode_enum prucode_id) {
 			pce->pru1_entry)) != 0) {
 		FATAL("prussdrv_exec_program(PRU1) failed");
 	}
-	INFO("Loaded pru code with id = %d", prucode_id);
+	INFO("Loaded and started PRU code with id = %d", prucode_id);
 
 	timeout.wait_ms(100); // wait for PRU to come up, much too long
 
-	// get address of mail box struct in PRU
-	mailbox_connect();
-	// now all fields initialized/cleared
-
-	// get address of device register descriptor struct in PRU
-	iopageregisters_connect();
-
 	this->prucode_id = prucode_id;
 
+	// verify PRU1 is executing its command loop
+	mailbox->arm2pru_req = ARM2PRU_NOP;
+	timeout.wait_ms(1);
+	if (mailbox->arm2pru_req != ARM2PRU_NONE)  {
+		FATAL("PRU1 is not executing its command loop");
+		goto error;
+	}
+
 	return rtn;
 
 	error: //
diff --git a/10.01_base/2_src/arm/storagedrive.cpp b/10.01_base/2_src/arm/storagedrive.cpp
index 8ecad70..d006441 100644
--- a/10.01_base/2_src/arm/storagedrive.cpp
+++ b/10.01_base/2_src/arm/storagedrive.cpp
@@ -157,7 +157,7 @@ void storagedrive_c::file_write(uint8_t *buffer, uint64_t position, unsigned len
 	// 3. write data
 	f.write((const char*) buffer, len);
 	if (f.fail())
-		ERROR("file_write() failure on %s", name);
+		ERROR("file_write() failure on %s", name.value.c_str());
 	f.flush();
 }
 
@@ -177,7 +177,7 @@ void storagedrive_selftest_c::block_buffer_fill(unsigned block_number) {
 	assert((block_size % 4) == 0); // whole uint32
 	for (unsigned i = 0; i < block_size / 4; i++) {
 		// i counts dwords in buffer
-		// pattern: global incrementing uint32 
+		// pattern: global incrementing uint32
 		uint32_t pattern = i + (block_number * block_size / 4);
 		((uint32_t*) block_buffer)[i] = pattern;
 	}
@@ -188,7 +188,7 @@ void storagedrive_selftest_c::block_buffer_check(unsigned block_number) {
 	assert((block_size % 4) == 0);	// whole uint32
 	for (unsigned i = 0; i < block_size / 4; i++) {
 		// i counts dwords in buffer
-		// pattern: global incrementing uint32 
+		// pattern: global incrementing uint32
 		uint32_t pattern_expected = i + (block_number * block_size / 4);
 		uint32_t pattern_found = ((uint32_t*) block_buffer)[i];
 		if (pattern_expected != pattern_found) {
diff --git a/10.01_base/2_src/arm/unibus.cpp b/10.01_base/2_src/arm/unibus.cpp
index 6913628..ea7c5e1 100644
--- a/10.01_base/2_src/arm/unibus.cpp
+++ b/10.01_base/2_src/arm/unibus.cpp
@@ -140,7 +140,7 @@ void unibus_c::interrupt(uint8_t priority, uint16_t vector) {
 bool unibus_c::dma(enum unibus_c::arbitration_mode_enum arbitration_mode, uint8_t control,
 		uint32_t startaddr, unsigned blocksize) {
 	uint64_t dmatime_ns, totaltime_ns;
-	uint8_t dma_opcode;
+	uint8_t dma_opcode = ARBITRATION_MODE_NONE; // inihibit compiler warnings
 
 	// can access bus with DMA when there's a Bus Arbitrator
 	assert(pru->prucode_id == pru_c::PRUCODE_UNIBUS);
diff --git a/10.01_base/2_src/pru0/pru0_main_all.c b/10.01_base/2_src/pru0/pru0_main_all.c
new file mode 100644
index 0000000..cfdf3d3
--- /dev/null
+++ b/10.01_base/2_src/pru0/pru0_main_all.c
@@ -0,0 +1,56 @@
+/* pru0_main.c: endless loop, writes outputs on R30 from mailbox (C solution)
+
+   Copyright (c) 2018, Joerg Hoppe
+   j_hoppe@t-online.de, www.retrocmp.com
+
+   Permission is hereby granted, free of charge, to any person obtaining a
+   copy of this software and associated documentation files (the "Software"),
+   to deal in the Software without restriction, including without limitation
+   the rights to use, copy, modify, merge, publish, distribute, sublicense,
+   and/or sell copies of the Software, and to permit persons to whom the
+   Software is furnished to do so, subject to the following conditions:
+
+   The above copyright notice and this permission notice shall be included in
+   all copies or substantial portions of the Software.
+
+   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+   JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+   12-nov-2018  JH      entered beta phase
+
+  from d:\RetroCmp\dec\pdp11\UniBone\91_3rd_party\pru-c-compile\pru-software-support-package\examples\am335x\PRU_gpioToggle\
+
+
+ */
+
+#include <stdint.h>
+#include <pru_cfg.h>
+#include "resource_table_empty.h"
+
+#include "pru_pru_mailbox.h"
+
+volatile register uint32_t __R30;
+volatile register uint32_t __R31;
+
+void main(void) {
+
+	/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
+	CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
+
+	// loop forever
+	void pru0_dataout(void) ;
+	pru0_dataout() ;
+#ifdef USED
+	// old code using shared RAM mailbox,  not reached
+	while(1) {
+		__R30 = pru_pru_mailbox.pru0_r30 ;
+	}
+#endif
+
+}
+
diff --git a/10.01_base/2_src/pru1/pru1_main_test.c b/10.01_base/2_src/pru1/pru1_main_test.c
new file mode 100644
index 0000000..d3ae8cd
--- /dev/null
+++ b/10.01_base/2_src/pru1/pru1_main_test.c
@@ -0,0 +1,210 @@
+/* pru1_main.c: main loop with mailbox cmd interface. Test functions.
+
+ Copyright (c) 2018-2019, Joerg Hoppe
+ j_hoppe@t-online.de, www.retrocmp.com
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ 28-mar-2019  JH      split off from "all-function" main
+ 12-nov-2018  JH      entered beta phase
+
+ Functions to test GPIOs, shared memory and mailbox.
+ Separated from "all-function" main() because of PRU code size limits.
+ Application has to load this into PRU1 depending on system state.
+
+ from d:\RetroCmp\dec\pdp11\UniBone\91_3rd_party\pru-c-compile\pru-software-support-package\examples\am335x\PRU_gpioToggle
+ Test GPIO, shared mem and interrupt
+ a) waits until ARM writes a value to mailbox.arm2pru_req
+ b) ACKs the value in mailbox.arm2pru_resp, clears arm2pru_req
+ c) toggles 1 mio times GPIO, with delay as set by ARM
+ d) signal EVENT0
+ e) goto a
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <pru_cfg.h>
+#include "resource_table_empty.h"
+
+#include "pru1_utils.h"
+
+#include "pru_pru_mailbox.h"
+#include "mailbox.h"
+#include "ddrmem.h"
+#include "iopageregister.h"
+
+#include "pru1_buslatches.h"
+#include "pru1_statemachine_arbitration.h"
+#include "pru1_statemachine_dma.h"
+#include "pru1_statemachine_intr.h"
+#include "pru1_statemachine_slave.h"
+#include "pru1_statemachine_init.h"
+#include "pru1_statemachine_powercycle.h"
+
+
+void main(void) {
+
+	/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
+	CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
+
+	// clear all tables, as backup if ARM fails todo
+	iopageregisters_init();
+
+	buslatches_reset(); // all deasserted
+
+	// init mailbox
+	mailbox.arm2pru_req = ARM2PRU_NONE;
+	mailbox.events.eventmask = 0;
+	mailbox.events.initialization_signals_prev = 0;
+	mailbox.events.initialization_signals_cur = 0;
+
+	while (1) {
+		// display opcode (active for one cycle
+//		__R30 = (mailbox.arm2pru_req & 0xf) << 8;
+		/*
+		 mailbox.arm2pru_resp = mailbox.arm2pru_req ;
+		 __R30 = (mailbox.arm2pru_resp & 0xf) << 8;
+		 mailbox.arm2pru_resp = mailbox.arm2pru_req ;
+		 }
+		 */
+		/*** Attention: arm2pru_req (and all mailbox vars) change at ANY TIME
+		 * - ARM must set arm2pru_req as last operation on mailbox,
+		 *    memory barrier needed.
+		 * - ARM may not access mailbox until arm2pru_req is 0
+		 * - PRU only clears arm2pru_req after actual processing if mailbox
+		 * ***/
+		switch (mailbox.arm2pru_req) {
+		case ARM2PRU_NONE: // == 0
+			// reloop
+			break;
+		case ARM2PRU_NOP: // needed to probe PRU run state
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		case ARM2PRU_HALT:
+			__halt(); // that's it
+			break;
+#ifdef USED
+		case ARM2PRU_MAILBOXTEST1:
+			// simulate a register read access.
+#ifdef TEST_TIMEOUT
+			while (1) {
+				// toggle with REGSEL_0    = PRU1_8
+				__R30 |= (1 << 8);
+				// buslatches_setbits(1, BIT(6), BIT(6)) ;
+				TIMEOUT_SET(NANOSECS(1000));// 1 usec / level
+				while (!TIMEOUT_REACHED);
+				__R30 &= ~(1 << 8);
+				//buslatches_setbits(1, BIT(6), 0) ;
+				TIMEOUT_SET(NANOSECS(1000));
+				while (!TIMEOUT_REACHED);
+			}
+#endif
+
+			// show on REG_DATAOUT
+			buslatches_pru0_dataout(mailbox.mailbox_test.addr);
+			// pru_pru_mailbox.pru0_r30 = mailbox.mailbox_test.addr & 0xff;
+			// __R30 = (mailbox.mailbox_test.addr & 0xf) << 8;
+			mailbox.mailbox_test.val = mailbox.mailbox_test.addr;
+			__R30 = (mailbox.arm2pru_req & 0xf) << 8; // optical ACK
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+#endif
+		case ARM2PRU_BUSLATCH_INIT: // set all mux registers to "neutral"
+			buslatches_reset();
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+
+		case ARM2PRU_BUSLATCH_SET: { // set a mux register
+
+			// don't feed "volatile" vars into buslatch_macros !!!
+			uint8_t reg_sel = mailbox.buslatch.addr & 7;
+			uint8_t bitmask = mailbox.buslatch.bitmask;
+			uint8_t val = mailbox.buslatch.val;
+			//buslatches.cur_reg_sel = 0xff; // force new setting of reg_sel
+			if (BUSLATCHES_REG_IS_BYTE(reg_sel))
+				buslatches_setbyte(reg_sel, val);
+			else
+				buslatches_setbits(reg_sel, bitmask, val);
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		}
+		case ARM2PRU_BUSLATCH_GET: {
+			// don't feed "volatile" vars into buslatch_macros !!!
+			uint8_t reg_sel = mailbox.buslatch.addr & 7;
+			// buslatches.cur_reg_sel = 0xff; // force new setting of reg_sel
+			mailbox.buslatch.val = buslatches_getbyte(reg_sel);
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		}
+	case ARM2PRU_BUSLATCH_EXERCISER: 	// exercise 8 byte accesses to mux registers
+		buslatches_exerciser() ;
+		mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+		break ;
+
+		case ARM2PRU_BUSLATCH_TEST: {
+			buslatches_test(mailbox.buslatch_test.addr_0_7, mailbox.buslatch_test.addr_8_15,
+					mailbox.buslatch_test.data_0_7, mailbox.buslatch_test.data_8_15);
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		}
+		case ARM2PRU_INITPULSE: // generate a pulse on UNIBUS INIT
+		// INIT: latch[7], bit 3
+			buslatches_setbits(7, BIT(3), BIT(3)); // assert INIT
+			__delay_cycles(MILLISECS(250)); // INIT is 250ms
+			buslatches_setbits(7, BIT(3), 0); // deassert INIT
+				mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+
+		case ARM2PRU_POWERCYCLE: // do ACLO/DCLO power cycle
+			buslatches_powercycle();
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		case ARM2PRU_DMA_ARB_NONE:
+			sm_dma_start(); // without NPR/NPG arbitration
+			// simply call current state function, until stopped
+			// parallel the BUS-slave statemachine is triggered
+			// by master logic.
+			while (!sm_dma.state())
+				;
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		case ARM2PRU_DDR_FILL_PATTERN:
+			ddrmem_fill_pattern();
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		case ARM2PRU_DDR_SLAVE_MEMORY:
+			// respond to UNIBUS cycles as slave and
+			// access DDR as UNIBUS memory.
+
+			// only debugging: all signals deasserted
+			buslatches_reset();
+
+			// do UNIBUS slave cycles, until ARM abort this by
+			// writing into mailbox.arm2pru_req
+			while (mailbox.arm2pru_req == ARM2PRU_DDR_SLAVE_MEMORY) {
+				sm_slave_start();
+				// do all states of an access, start when MSYN found.
+				while (!sm_slave.state())
+					;
+			}
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		} // switch
+	} // while
+}
+
diff --git a/10.01_base/2_src/pru1/pru1_main_unibus.c b/10.01_base/2_src/pru1/pru1_main_unibus.c
new file mode 100644
index 0000000..1e486f8
--- /dev/null
+++ b/10.01_base/2_src/pru1/pru1_main_unibus.c
@@ -0,0 +1,209 @@
+/* pru1_main_unibus.c: main loop with mailbox cmd interface. UNIBUS devices with opt. phys. PDP-11 CPU.
+
+ Copyright (c) 2018-2019, Joerg Hoppe
+ j_hoppe@t-online.de, www.retrocmp.com
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+
+ 28-mar-2019  JH      split off from "all-function" main
+ 12-nov-2018  JH      entered beta phase
+
+ Master and slave functionality for UNIBUS devices.
+ Assumes a physical PDP-11 CPU is working as Arbitrator for
+ NPR/NG/SACK and BR/BG/SACK.
+ Needed if UniBone runs in a system running PDP-11 CPU
+ and simulated or physical devices do DMA or INTR.
+
+ Separated from "all-function" main() because of PRU code size limits.
+ Application has to load this into PRU1 depending on system state.
+
+ from d:\RetroCmp\dec\pdp11\UniBone\91_3rd_party\pru-c-compile\pru-software-support-package\examples\am335x\PRU_gpioToggle
+ Test GPIO, shared mem and interrupt
+ a) waits until ARM writes a value to mailbox.arm2pru_req
+ b) ACKs the value in mailbox.arm2pru_resp, clears arm2pru_req
+ c) toggles 1 mio times GPIO, with delay as set by ARM
+ d) signal EVENT0
+ e) goto a
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <pru_cfg.h>
+#include "resource_table_empty.h"
+
+#include "pru1_utils.h"
+
+#include "pru_pru_mailbox.h"
+#include "mailbox.h"
+#include "ddrmem.h"
+#include "iopageregister.h"
+
+#include "pru1_buslatches.h"
+#include "pru1_statemachine_arbitration.h"
+#include "pru1_statemachine_dma.h"
+#include "pru1_statemachine_intr.h"
+#include "pru1_statemachine_slave.h"
+#include "pru1_statemachine_init.h"
+#include "pru1_statemachine_powercycle.h"
+
+void main(void) {
+
+	/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */
+	CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;
+
+	// clear all tables, as backup if ARM fails todo
+	iopageregisters_init();
+
+	buslatches_reset(); // all deasserted, caches cleared
+
+	/* ARM must init mailbox, especially:
+	mailbox.arm2pru_req = ARM2PRU_NONE;
+	mailbox.events.eventmask = 0;
+	mailbox.events.initialization_signals_prev = 0;
+	mailbox.events.initialization_signals_cur = 0;
+	*/
+
+	/* start parallel emulation of all devices,
+	 * Process __DMA and _INTR bus master operations
+	 *
+	 * ! Several state machines (DMA, Powercycle, INIT,) use the same global timeout.
+	 * ! Never execute these in parallel !
+	 */
+	// Reset PDP-11 with power-cycle simulation.
+	// Necessary, as until now NPR/NPG/BG/BR/SACK lines were "unconnected"
+//	buslatches_powercycle();
+//	__delay_cycles(MILLISECS(100));
+	// execute 2x, because M9312 boot ROMs need this
+	//			__delay_cycles(MILLISECS(250));
+	//			buslatches_powercycle();
+
+	// buslatches_pulse_debug ;
+
+	// base operation: accept and execute slave cycles
+	sm_slave_start();
+
+	while (true) {
+		uint32_t arm2pru_req_cached;
+		// do all states of an access, start when MSYN found.
+
+		// slave cycles may trigger events to ARM, which changes "active" registers
+		// and issues interrupts
+		while (!sm_slave.state())
+			; // execute complete slave cycle, then check NPR/INTR
+
+		// update state of init lines
+		// INIT never asserted in the midst of a transaction, bit 3,4,5
+		do_event_initializationsignals();
+
+		// standard operation may be interrupt by other requests
+		arm2pru_req_cached = mailbox.arm2pru_req;
+		switch (arm2pru_req_cached) {
+		case ARM2PRU_NONE:
+			// pass BG[4-7] to next device, state machine "idle"
+			// pass all Arbitration GRANT IN to GRANT OUT for next device.
+			// This is not necessary while INTR or DMA is actiove:
+			// INTR is only 1 cycle, DMA has SACK set all the time, arbitration
+			// prohibited then.
+			sm_arb_state_idle();
+			// do only forward GRANT lines if not INTR is pending,
+			// else our GRANT would be passed too.
+			break; // fast case: only slave operation
+		case ARM2PRU_NOP: // needed to probe PRU run state
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		case ARM2PRU_DMA_ARB_NONE: // ignore SACK condition
+		case ARM2PRU_DMA_ARB_MASTER: // also without arbitration, TODO!
+			sm_dma_start();
+			while (!sm_dma.state())
+				;
+			// a dma cycle into a device register may trigger an interrupt
+			// do not delete that condition
+			if (mailbox.arm2pru_req == arm2pru_req_cached)
+				mailbox.arm2pru_req = ARM2PRU_NONE; // clear request
+			break;
+		case ARM2PRU_DMA_ARB_CLIENT:
+			// start DMA cycle
+			// can not run parallel with INTR levels
+			sm_arb_start(ARBITRATION_PRIORITY_BIT_NP);
+			while (!sm_arb.state()) {
+				// sm_slave is most time critical, as it must keep track with MSYN/SSYN bus traffic.
+				// so give it more cpu cycles
+				while (!sm_slave.state())
+					;
+			}
+			// now SACK held and BBSY set, slave state machine ended, since BBSY found inactive
+
+			// debug pin reset by bus access
+			//DEBUG_PIN_SET(1) ;
+			sm_dma_start();
+			//DEBUG_PIN_SET(1) ;
+			while (!sm_dma.state())
+				//DEBUG_PIN_SET(1) ;
+				;// execute dma master cycles
+			// a dma cycle into a device register may trigger an interrupt
+			// do not delete that condition
+			if (mailbox.arm2pru_req == arm2pru_req_cached)
+				mailbox.arm2pru_req = ARM2PRU_NONE; // clear request
+			break;
+		case ARM2PRU_INTR:
+			// start one INTR cycle. May be raised in midst of slave cycle
+			// by ARM, if access to "active" register triggers INTR.
+			// no multiple levels simultaneously allowed, not parallel with DMA !
+			sm_arb_start(mailbox.intr.priority_bit);
+			// wait while INTR is accepted. This may take long time,
+			// if system is at high processor priority (PSW register)
+			while (!sm_arb.state()) {
+				// sm_slave is most time critical, as it must keep track with MSYN/SSYN bus traffic.
+				// so give it more cpu cycles
+				while (!sm_slave.state())
+					;
+			}
+			// now SACK held and BBSY set, slave state machine ended, since BBSY found inactive
+			sm_intr_start();
+			while (!sm_intr.state())
+				; // execute intr cycle as bus master
+			mailbox.arm2pru_req = ARM2PRU_NONE; // clear request
+			break;
+		case ARM2PRU_INITPULSE: // generate a pulse on UNIBUS INIT
+			// only busmaster may assert INIT. violated here!
+			sm_slave_start();
+			sm_init_start();
+			while (!sm_slave.state() || !sm_init.state())
+				;
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+		case ARM2PRU_POWERCYCLE: // do ACLO/DCLO power cycle
+			// Runs for 4* POWERCYCLE_DELAY_MS millsecs, approx 1 sec.
+			// perform slave states in parallel, so emulated memory
+			// is existent for power fail trap and reboot
+			sm_slave_start();
+			sm_powercycle_start();
+			while (!sm_slave.state() || !sm_powercycle.state())
+				;
+			mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done
+			break;
+
+		default: // ignore all other requestes while executing emulation
+			;
+		} // switch
+	} // while (true)
+
+	// never reached
+}
+
diff --git a/10.02_devices/2_src/cpu.cpp b/10.02_devices/2_src/cpu.cpp
index 5b94582..d004ed0 100644
--- a/10.02_devices/2_src/cpu.cpp
+++ b/10.02_devices/2_src/cpu.cpp
@@ -69,7 +69,7 @@ extern "C" {
 int cpu_dato(unsigned addr, unsigned data) {
 	bool timeout;
 	mailbox->dma.words[0] = data;
-	timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_NONE, UNIBUS_CONTROL_DATO, addr, 1);
+	timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_MASTER , UNIBUS_CONTROL_DATO, addr, 1);
 	return !timeout;
 
 }
@@ -78,7 +78,7 @@ int cpu_datob(unsigned addr, unsigned data) {
 	// TODO DATOB als 1 byte-DMA !
 	bool timeout;
 	mailbox->dma.words[0] = data;
-	timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_NONE, UNIBUS_CONTROL_DATOB, addr, 1);
+	timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_MASTER, UNIBUS_CONTROL_DATOB, addr, 1);
 	return !timeout;
 
 }
@@ -86,7 +86,7 @@ int cpu_datob(unsigned addr, unsigned data) {
 int cpu_dati(unsigned addr, unsigned *data) {
 	bool timeout;
 
-	timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_NONE, UNIBUS_CONTROL_DATI, addr, 1);
+	timeout = !unibus->dma(unibus_c::ARBITRATION_MODE_MASTER, UNIBUS_CONTROL_DATI, addr, 1);
 	*data = mailbox->dma.words[0];
 	return !timeout;
 }
@@ -102,7 +102,10 @@ void cpu_c::worker(void) {
 	unsigned opcode = 0;
 	(void) opcode;
 	while (!worker_terminate) {
-		timeout.wait_ms(10);
+		// run full speed!
+		timeout.wait_us(1);
+
+		// timeout.wait_ms(10);
 
 		if (runmode.value != (ka11.state != 0))
 			ka11.state = runmode.value;
diff --git a/10.03_app_demo/2_src/makefile b/10.03_app_demo/2_src/makefile
index 27378dd..a566175 100644
--- a/10.03_app_demo/2_src/makefile
+++ b/10.03_app_demo/2_src/makefile
@@ -24,19 +24,18 @@ PRUSS_INCLUDE_DIR = $(PRU_PACKAGE_ROOT)/include
 PRUSS_DRV_LIB = $(PRU_PACKAGE_ROOT)/bin-bbb/libprussdrv.a
 
 # -static: do not used shared libs, include all coide into the binary
-# (big binary, but BBB neds no shared libs of certain verisons installed)
+# (big binary, but BBB neds no shared libs of certain versions installed)
 # Example: demo binary goes from 594K to 12.3MB !
 LDFLAGS+= -static -lstdc++ -lpthread $(PRUSS_DRV_LIB)
 
 # compiler flags and libraries
-#CC_DBG_FLAGS = -O3 -Wall -Wextra -DDBG
-CC_DBG_FLAGS = -ggdb3 -O0 -Wall -Wextra -DDBG
-
-#ifeq ($(DBG),1)
-#CC_DBG_FLAGS = -ggdb3 -O0 -Wall -Wextra -DDBG
-#else
-#CC_DBG_FLAGS = -O3 -Wall -Wextra -UDBG
-#endif
+ifeq ($(MAKE_CONFIGURATION),RELEASE)
+	CC_DBG_FLAGS = -O3 -Wall -Wextra -DDBG
+else ifeq ($(MAKE_CONFIGURATION),DBG)
+	CC_DBG_FLAGS = -ggdb3 -O0 -Wall -Wextra -DDBG
+else
+	$(error Set MAKE_CONFIGURATION to RELEASE or DBG!)
+endif
 
 ifeq ($(MAKE_TARGET_ARCH),BBB)
 	# cross compile on x64 for BBB
@@ -232,7 +231,7 @@ $(OBJDIR)/mscp_server.o :   $(DEVICE_SRC_DIR)/mscp_server.cpp $(DEVICE_SRC_DIR)/
 	$(CC) $(CCFLAGS) $< -o $@
 
 $(OBJDIR)/mscp_drive.o :   $(DEVICE_SRC_DIR)/mscp_drive.cpp $(DEVICE_SRC_DIR)/mscp_drive.hpp
-	$(CC) $(CCFLAGS) $< -o $@	
+	$(CC) $(CCFLAGS) $< -o $@
 
 $(OBJDIR)/storagedrive.o :  $(BASE_SRC_DIR)/storagedrive.cpp $(BASE_SRC_DIR)/storagedrive.hpp
 	$(CC) $(CCFLAGS) $< -o $@
diff --git a/10.03_app_demo/2_src/menu_devices.cpp b/10.03_app_demo/2_src/menu_devices.cpp
index 6b77ab9..c855121 100644
--- a/10.03_app_demo/2_src/menu_devices.cpp
+++ b/10.03_app_demo/2_src/menu_devices.cpp
@@ -102,7 +102,7 @@ void application_c::menu_devices(bool with_CPU) {
 	char *s_choice;
 	char s_opcode[256], s_param[2][256];
 
-	//CPU: MASTER!
+	// with_CPU: the emulated CPU is answering BR and NPR requests.
 	if (with_CPU)
 		arbitration_mode = unibus_c::ARBITRATION_MODE_MASTER;
 	else
@@ -123,11 +123,11 @@ void application_c::menu_devices(bool with_CPU) {
 	cur_device = NULL;
 	demo_io_c *demo_io = NULL;
 	//demo_regs_c demo_regs; // mem at 160000: RT11 crashes?
-	cpu_c *cpu;
-	RL11_c *RL11;
+	cpu_c *cpu = NULL;
+	RL11_c *RL11 = NULL;
 	paneldriver->reset(); // reset I2C, restart worker()
-	rk11_c *RK11;
-	uda_c *UDA50;
+	rk11_c *RK11 = NULL;
+	uda_c *UDA50 = NULL;
 
 	if (with_DEMOIO) {
 		demo_io = new demo_io_c();
@@ -217,8 +217,8 @@ void application_c::menu_devices(bool with_CPU) {
 				printf("d <regname> <val>    Deposit octal value into named device register\n");
 				printf("e <regname>          Examine single device register (regno decimal)\n");
 				printf("e                    Examine all device registers\n");
+				printf("e <addr>             Examine octal UNIBUS address.\n");
 				printf("d <addr> <val>       Deposit octal val into UNIBUS address.\n");
-				printf("e <addr>             Deposit octal val into UNIBUS address.\n");
 			}
 			printf("dl c|s|f             Debug log: Clear, Show on console, dump to File.\n");
 			printf("                       (file = %s)\n", logger->default_filepath.c_str());
@@ -383,7 +383,7 @@ void application_c::menu_devices(bool with_CPU) {
 					printf("Bus timeout at %06o.\n", mailbox->dma.cur_addr);
 			} else if (unibuscontroller && !strcasecmp(s_opcode, "e") && n_fields <= 2) {
 				unsigned blocksize = 0; // default: no EXAM
-				bool timeout;
+				bool timeout ;
 				uint32_t addr;
 				unibusdevice_register_t *reg;
 				if (n_fields == 2) { // single reg number given
@@ -399,14 +399,19 @@ void application_c::menu_devices(bool with_CPU) {
 				} else { // list all regs
 					addr = unibuscontroller->base_addr.value; // all device registers
 					blocksize = unibuscontroller->register_count;
-					unsigned i;
-					timeout = !unibus->dma(arbitration_mode, UNIBUS_CONTROL_DATI, addr,
-							blocksize);
-					for (i = 0; addr <= mailbox->dma.cur_addr; i++, addr += 2) {
-						reg = unibuscontroller->register_by_unibus_address(addr);
-						assert(reg);
-						printf("EXAM reg #%d %s %06o -> %06o\n", reg->index, reg->name,
-								reg->addr, mailbox->dma.words[i]);
+					if (blocksize) {
+						unsigned i;
+						timeout = !unibus->dma(arbitration_mode, UNIBUS_CONTROL_DATI, addr,
+								blocksize);
+						for (i = 0; addr <= mailbox->dma.cur_addr; i++, addr += 2) {
+							reg = unibuscontroller->register_by_unibus_address(addr);
+							assert(reg);
+							printf("EXAM reg #%d %s %06o -> %06o\n", reg->index, reg->name,
+									reg->addr, mailbox->dma.words[i]);
+						}
+					} else {
+						timeout = false ;
+						printf("Device has no UNIBUS registers.\n");
 					}
 				}
 				if (timeout)
@@ -444,7 +449,7 @@ void application_c::menu_devices(bool with_CPU) {
 	if (with_MSCP) {
 		UDA50->worker_stop();
 		UDA50->uninstall();
-		delete RK11;
+		delete UDA50;
 	}
 
 //	//demo_regs.worker_stop();
diff --git a/10.03_app_demo/2_src/menu_interrupts.cpp b/10.03_app_demo/2_src/menu_interrupts.cpp
index 9a9906a..acc078e 100644
--- a/10.03_app_demo/2_src/menu_interrupts.cpp
+++ b/10.03_app_demo/2_src/menu_interrupts.cpp
@@ -116,10 +116,6 @@ void application_c::menu_interrupts(void) {
 			unibus->powercycle();
 			timer.wait_ms(1000); // shpw prompt
 
-			SET_DEBUG_PIN0(0)
-			;
-			SET_DEBUG_PIN1(0)
-			;
 			printf("Loading memory content from MACRO-11 listing \"%s\".\n", testprogram_fname);
 			membuffer->init();
 			load_ok = membuffer->load_macro11_listing(testprogram_fname, "start");
diff --git a/10.03_app_demo/2_src/menus.cpp b/10.03_app_demo/2_src/menus.cpp
index dedc52c..20be42f 100644
--- a/10.03_app_demo/2_src/menus.cpp
+++ b/10.03_app_demo/2_src/menus.cpp
@@ -242,8 +242,7 @@ void application_c::menu_main(void) {
 		printf("ti          Test Interrupts (needs physical PDP-11 CPU)\n");
 		printf("d           Emulate devices, with PDP-11 CPU arbitration\n");
 		printf("dc          Emulate devices and CPU, PDP-11 must be disabled.\n");
-		printf(
-				"de          Device Exerciser: work with devices on the UNIBUS without PDP-11 CPU arbitration\n");
+		// printf("de          Device Exerciser: work with devices on the UNIBUS without PDP-11 CPU arbitration\n");
 		printf(
 				"m           Full memory slave emulation with DMA bus master functions by PDP-11 CPU.\n");
 		printf("i           Info, help\n");
diff --git a/10.03_app_demo/5_applications/211bsd.mscp/2.11BSD_du_44.cmd b/10.03_app_demo/5_applications/211bsd.mscp/2.11BSD_du_44.cmd
new file mode 100644
index 0000000..eb599a0
--- /dev/null
+++ b/10.03_app_demo/5_applications/211bsd.mscp/2.11BSD_du_44.cmd
@@ -0,0 +1,27 @@
+# inputfile for demo to select a rl1 device in the "device test" menu.
+# Read in with command line option  "demo --cmdfile ..."
+d			# device menu
+pwr			# reboot PDP-11
+.wait 3000		# wait for PDP-11 to reset
+m i			# install max UNIBUS memory
+
+# Deposit bootloader into memory
+m ll du.lst
+
+# mount 2.11bSD in drive #0 and start
+sd uda0			# select drive #0
+
+p type RA72
+p image 2.11BSD_44.ra72 # mount image file with test pattern
+
+.print MSCP drives ready.
+.print UDA50 boot loader installed.
+.print Start 10000 to boot from drive 0, 10010 for drive 1, ...
+.print Reload with "m ll"
+.print
+.print Set terminal to 9600 7O1
+.print At "44Boot" prompt, just hit RETURN.
+.print Login as "root", log out to enter multi user run level.
+
+
+
diff --git a/10.03_app_demo/5_applications/211bsd.mscp/211BSD_du0_44.sh b/10.03_app_demo/5_applications/211bsd.mscp/211BSD_du0_44.sh
new file mode 100644
index 0000000..9cbf61a
--- /dev/null
+++ b/10.03_app_demo/5_applications/211bsd.mscp/211BSD_du0_44.sh
@@ -0,0 +1,4 @@
+# start RT11 5.5 with "demo" application
+cd ~/10.03_app_demo/5_applications/211bsd.mscp
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose --debug  --cmdfile 2.11BSD_du_44.cmd
+
diff --git a/10.03_app_demo/5_applications/211bsd.mscp/211bsd_44.simh_pdp11 b/10.03_app_demo/5_applications/211bsd.mscp/211bsd_44.simh_pdp11
new file mode 100644
index 0000000..bebb821
--- /dev/null
+++ b/10.03_app_demo/5_applications/211bsd.mscp/211bsd_44.simh_pdp11
@@ -0,0 +1,51 @@
+; model a PDP-11/44 with maximum memory, fpu, no CIS
+set cpu 11/44 4096K fpp nocis
+
+; disable all extra devices by default, will enable later
+set ptr disabled
+set ptp disabled
+set lpt disabled
+set rha disabled
+set cr disabled
+set rp disabled
+set rk disabled
+set xu disabled
+set xq disabled
+set rl disabled
+set rx disabled
+set tm disabled
+set ts disabled
+set hk disabled
+set vh disabled
+
+; use 7b ascii terminal
+set tto 7b
+
+; set the boot disk as a 1GB RA72 on an MSCP UDA50
+set rq enabled
+set rq0 ra72
+attach rq0 2.11BSD_44.ra72
+
+; set one DZ11 8 line async mux
+; accessible via telnet to 127.0.0.1:4000...4007
+set dz enabled
+set dz lines=8
+set dz 7b
+set dz vector=310
+attach -am dz 4000
+
+; set one DELUA/DEUNA unibus enet controller
+; ==> must setup eth0/eth1 per your system config
+set xu enabled
+set xu type=deuna
+attach xu eth0
+
+; enable one tape device on a TMSCP controller
+set tq enabled
+
+; show our config
+show devices
+
+set cons telnet=23
+; boot it
+boot rq0
diff --git a/10.03_app_demo/5_applications/211bsd.mscp/du.lst b/10.03_app_demo/5_applications/211bsd.mscp/du.lst
new file mode 100644
index 0000000..615cee3
--- /dev/null
+++ b/10.03_app_demo/5_applications/211bsd.mscp/du.lst
@@ -0,0 +1,113 @@
+       1                                	.title	M9312 'DU' BOOT prom for MSCP compatible controller
+       2                                
+       3                                	; This source code is a mdified copy of the DEC M9312 23-767A9 boot PROM.
+       4                                	;
+       5                                	; This boot PROM is for any MSCP compatible controller (DEC UDA50, EMULEX UC17/UC18).
+       6                                	;
+       7                                	; Multiple units and/or CSR addresses are supported via different entry points.
+       8                                
+       9                                		;
+      10                                	; Revision history:
+      11                                	; May 2017: Joerg Hoppe
+      12                                	;
+      13                                	; 198?:  DEC
+      14                                	;      Original ROM 23-767A9 for M9312.
+      15                                	;
+      16                                
+      17                                
+      18                                
+      19 172150                         mscsr	=172150 			; std MSCP csrbase
+      20                                
+      21 000000                         msip	=+0				; IP register
+      22 000002                         mssa	=+2				; SA register
+      23                                
+      24                                	.asect
+      25 010000                         	.=10000 			;  arbitrary position > 3000
+      26                                
+      27                                	; --------------------------------------------------
+      28 001004                         rpkt	=1004	; rpkt structure
+      29 001070                         cpkt	=1070	; cpkt structure
+      30 001200                         comm	=1200	; comm structure
+      31                                ;comm	 =2404	 ; comm structure (at 'blt .+12')
+      32                                
+      33                                	; register usage:
+      34                                	; r0: unit number 0..3
+      35                                	; r1: MSCP csrbase
+      36                                	; r2: moving buffer pointer
+      37                                	; r3: moving buffer pointer
+      38                                	; r5: init mask
+      39                                
+      40                                	; 4 unit numbers => 4 entry addresses
+      41                                start0:
+      42 010000 012700  000000          	mov	#0,r0
+      43 010004 000413                  	br	duNr
+      44 010006 000240                  	nop
+      45                                start1:
+      46 010010 012700  000001          	mov	#1,r0
+      47 010014 000407                  	br	duNr
+      48 010016 000240                  	nop
+      49                                start2:
+      50 010020 012700  000002          	mov	#2,r0
+      51 010024 000403                  	br	duNr
+      52 010026 000240                  	nop
+      53                                start3:
+      54 010030 012700  000003          	mov	#3,r0
+      55                                
+      56                                	; retry entry
+      57 010034 012701  172150          duNr:	mov	#mscsr,r1		; boot std csr, unit <R0>
+      58                                
+      59 010040 010021                  go:	mov	r0,(r1)+		; init controller (write IP), bump ptr
+      60 010042 012705  004000          	mov	#4000,r5		; S1 state bitmask
+      61 010046 012703  010166          	mov	#mscpdt,r3		; point to data
+      62                                
+      63                                	; write 4 init words, with r5 mask from 4000 to 40000
+      64 010052 005711                  3$:	tst	(r1)			; error bit set ?
+      65 010054 100767                  	bmi	duNr			; yes, fail back to begin to retry
+      66 010056 031105                  	bit	(r1),r5 		; step bit set ?
+      67 010060 001774                  	beq	3$			; not yet, wait loop
+      68 010062 012311                  	mov	(r3)+,(r1)		; yes, send next init data
+      69 010064 006305                  	asl	r5			; next mask
+      70 010066 100371                  	bpl	3$			; s4 done? br if not yet
+      71                                
+      72 010070 005002                  4$:	clr	r2			; set bufptr to 0
+      73 010072 005022                  5$:	clr	(r2)+			; clear buffer [0..2403]
+      74 010074 020227  001200          	cmp	r2,#comm		; check for end of buffer
+      75 010100 001374                  	bne	5$			; loop if not done
+      76                                
+      77 010102 010237  001064          	mov	r2,@#cpkt-4		; set lnt -- R2=2404
+      78 010106 112337  001100          	movb	(r3)+,@#cpkt+10 	; set command
+      79 010112 111337  001105          	movb	(r3),@#cpkt+15		; set bytecnt(hi)
+      80 010116 010037  001074          	mov	r0,@#cpkt+4		; set unit
+      81 010122 012722  001004          	mov	#rpkt,(r2)+		; rq desc addr
+      82 010126 010522                  	mov	r5,(r2)+		; rq own bit15
+      83 010130 012722  001070          	mov	#cpkt,(r2)+		; cp desc addr
+      84 010134 010522                  	mov	r5,(r2)+		; cq own bit15
+      85 010136 016102  177776          	mov	-2(r1),r2		; wake controller (read IP)
+      86                                
+      87 010142 005737  001202          6$:	tst	@#comm+2		; rq own controller ?
+      88 010146 100775                  	bmi	6$			; loop if not done
+      89                                
+      90 010150 105737  001016          	tstb	@#rpkt+12		; check for error ?
+      91 010154 001327                  	bne	duNr			; yup, fail back to begin to retry
+      92                                
+      93 010156 105723                  	tstb	(r3)+			; check end of table ?
+      94 010160 001743                  	beq	4$			; br if not yet
+      95                                
+      96 010162 005041                  	clr	-(r1)			; init controller (write IP)
+      97 010164 005007                  	clr	pc			; jmp to bootstrap at zero
+      98                                
+      99                                	; MSCP init and command data
+     100                                	; pointed to by r3
+     101                                mscpdt:
+     102 010166 100000                  	.word	100000			; S1: 100000 = no int, ring size 1, no vector
+     103 010170 001200                  	.word	comm			; S2: 002404 = ringbase lo addr
+     104 010172 000000                  	.word	000000			; S3: 000000 = no purge/poll, ringbase hi addr
+     105 010174 000001                  	.word	000001			; S4: 000001 = go bit
+     106                                	;
+     107                                	; MSCP command data
+     108                                	;
+     109 010176    011     000          	.byte	011,000 		; cmd=011(online), bytecnt_hi=000(0)
+     110 010200    041     002          	.byte	041,002 		; cmd=041(read), bytecnt_hi=002(512)
+     111                                
+     112                                	.end
+     112                                
diff --git a/10.03_app_demo/5_applications/cpu/cpu20hello.cmd b/10.03_app_demo/5_applications/cpu/cpu20hello.cmd
new file mode 100644
index 0000000..c29b4fe
--- /dev/null
+++ b/10.03_app_demo/5_applications/cpu/cpu20hello.cmd
@@ -0,0 +1,27 @@
+# Inputfile for demo to execute "Hello world"
+# Uses emulated CPU and (physical or emulated) DL11
+# Read in with command line option  "demo --cmdfile ..."
+
+dc			# "device with cpu" menu
+
+m i   			# emulate missing memory
+
+sd cpu20		# selected emualted 11/20 CPU
+
+m ll serial.lst		# load test program
+
+p
+
+init
+
+.print Emulated PDP-11/20 CPU will now output "Hello world"
+.print and enter a serial echo loop on DL11 at 177650.
+.print Make sure physical CPU is disabled.
+
+.input
+
+p run 1
+
+.print CPU20 started
+
+
diff --git a/10.03_app_demo/5_applications/cpu/cpu20hello.sh b/10.03_app_demo/5_applications/cpu/cpu20hello.sh
new file mode 100644
index 0000000..fb6b303
--- /dev/null
+++ b/10.03_app_demo/5_applications/cpu/cpu20hello.sh
@@ -0,0 +1,6 @@
+# starts PDP11/20 emulation
+# and executes a "Hello world" on a physical DL11 card
+# Main PDP-1120 must be HALTed
+cd ~/10.03_app_demo/5_applications/cpu
+~/10.03_app_demo/4_deploy/demo --arb 0 --verbose --debug  --cmdfile cpu20hello.cmd
+
diff --git a/10.03_app_demo/5_applications/cpu/serial.lst b/10.03_app_demo/5_applications/cpu/serial.lst
new file mode 100644
index 0000000..08f0b11
--- /dev/null
+++ b/10.03_app_demo/5_applications/cpu/serial.lst
@@ -0,0 +1,115 @@
+       1                                
+       2                                	.title	Serial I/O test for console
+       3                                
+       4                                	; This program tests the DEC DL11 or Robotron AIS K8060 console interface.
+       5                                	; It run in 4 phases:
+       6                                	; 1. print a start message,
+       7                                	; 2. echoes chars typed to the output until ^C is hit
+       8                                	; 3. prints an end message and HALTs.
+       9                                	; 4. on CONT it repeats.
+      10                                	;
+      11                                	; Contact: Joerg Hoppe / j_hoppe@t-online.de / www.retromcp.com
+      12                                
+      13                                	.asect
+      14                                
+      15                                	; select one type of console at assembly time
+      16 177560                         	dladr = 177560	; base addr of DEC DL11 console
+      17                                	; dladr = 176500	 ; DL11 #0
+      18                                	; dladr = 176510	; DL11 #1
+      19                                	; dladr = 176520	; DL11 #2
+      20                                
+      21                                
+      22 000000                         	.=0
+      23 000000 000137  001000          	jmp	@#start 	  ; early emulation started code execution from 0
+      24                                
+      25 001000                         	.=1000
+      26                                
+      27 000776                         stack	=	. - 2		; stack growns down from start
+      28                                
+      29                                start:
+      30 001000 012706  000776          	mov	#stack,sp	; init stack
+      31                                
+      32                                	; 1. print "Hello" msg
+      33 001004 012701  001126          	mov	#shello,r1
+      34 001010 004737  001054          	call	@#puts
+      35                                
+      36                                	; 2. echo chars until ^C hit
+      37                                1$:
+      38 001014 004737  001110          	call	@#getc		; wait for char, return in r0
+      39 001020 042700  177600          	bic	#177600,r0	; make 7bit: clear bits <15:7>
+      40 001024 120027  000003          	cmpb	r0,#3		; break by ^C ?
+      41 001030 001403                  	beq	2$		; yes: leave loop
+      42 001032 004737  001070          	call	@#putc		; no: echo char in r0 and loop
+      43 001036 000766                  	br	1$
+      44                                
+      45                                2$:
+      46                                
+      47                                	; 3. print "Bye bye" msg and HALT
+      48 001040 012701  001211          	mov	#sbye,r1
+      49 001044 004737  001054          	call	@#puts
+      50 001050 000000                  	halt
+      51                                
+      52                                	; 4. loop on CONT
+      53 001052 000752                  	br	start
+      54                                
+      55                                
+      56                                	; ----------------------
+      57                                	; puts - print a string
+      58                                	; r1 = pointer, r0,r1 changed
+      59                                puts:
+      60 001054 112100                  	movb	(r1)+,r0	; load xmt char
+      61 001056 001403                  	beq	1$		; string ends with 0
+      62 001060 004737  001070          	call	@#putc
+      63 001064 000773                  	br	puts		; transmit nxt char of string
+      64 001066 000207                  1$:	return
+      65                                
+      66                                
+      67                                	; ----------------------
+      68                                	; putc - output a single char
+      69                                	; r0 = char, r4 changed
+      70                                putc:
+      71 001070 012704  177560          	mov	#dladr,r4	; set base addr
+      72 001074 110064  000006          	movb	r0,6(r4)	; char into transmit buffer
+      73 001100 105764  000004          1$:	tstb	4(r4)		; XMT RDY?
+      74 001104 100375                  	bpl	1$		; no, loop
+      75 001106 000207                  	return
+      76                                
+      77                                	; ----------------------
+      78                                	; getc - input a single char
+      79                                	; result in r0, r4 changed
+      80                                getc:
+      81 001110 012704  177560          	mov	#dladr,r4	; set base addr
+      82 001114 105714                  1$:	tstb	(r4)		; RCVR DONE?
+      83 001116 100376                  	bpl	1$		; no, loop
+      84 001120 016400  000002          	mov	2(r4),r0	; return data
+      85 001124 000207                  	return
+      86                                
+      87                                
+      88                                shello:
+      89 001126    110     145     154  	.ascii	/Hello, World!/
+         001131    154     157     054  
+         001134    040     127     157  
+         001137    162     154     144  
+         001142    041                  
+      90 001143    015     012          	.byte	15,12		; CR, LF,
+      91 001145    124     171     160  	.ascii	/Typed chars are echoed, ^C HALTs./
+         001150    145     144     040  
+         001153    143     150     141  
+         001156    162     163     040  
+         001161    141     162     145  
+         001164    040     145     143  
+         001167    150     157     145  
+         001172    144     054     040  
+         001175    136     103     040  
+         001200    110     101     114  
+         001203    124     163     056  
+      92 001206    015     012     000  	.byte	15,12,0 	; CR, LF, NUL=end marker
+      93                                sbye:
+      94 001211    015     012          	.byte	15,12
+      95 001213    107     157     157  	.ascii	/Good bye!/
+         001216    144     040     142  
+         001221    171     145     041  
+      96 001224    015     012     000  	.byte	15,12,0 	; CR, LF, NUL=end marker
+      97                                
+      98                                	.end
+      98                                
diff --git a/10.03_app_demo/5_applications/cpu/serial.mac b/10.03_app_demo/5_applications/cpu/serial.mac
new file mode 100644
index 0000000..b262fae
--- /dev/null
+++ b/10.03_app_demo/5_applications/cpu/serial.mac
@@ -0,0 +1,98 @@
+
+	.title	Serial I/O test for console
+
+	; This program tests the DEC DL11 or Robotron AIS K8060 console interface.
+	; It run in 4 phases:
+	; 1. print a start message,
+	; 2. echoes chars typed to the output until ^C is hit
+	; 3. prints an end message and HALTs.
+	; 4. on CONT it repeats.
+	;
+	; Contact: Joerg Hoppe / j_hoppe@t-online.de / www.retromcp.com
+
+	.asect
+
+	; select one type of console at assembly time
+	dladr = 177560	; base addr of DEC DL11 console
+	; dladr = 176500	 ; DL11 #0
+	; dladr = 176510	; DL11 #1
+	; dladr = 176520	; DL11 #2
+
+
+	.=0
+	jmp	@#start 	  ; early emulation started code execution from 0
+
+	.=1000
+
+stack	=	. - 2		; stack growns down from start
+
+start:
+	mov	#stack,sp	; init stack
+
+	; 1. print "Hello" msg
+	mov	#shello,r1
+	call	@#puts
+
+	; 2. echo chars until ^C hit
+1$:
+	call	@#getc		; wait for char, return in r0
+	bic	#177600,r0	; make 7bit: clear bits <15:7>
+	cmpb	r0,#3		; break by ^C ?
+	beq	2$		; yes: leave loop
+	call	@#putc		; no: echo char in r0 and loop
+	br	1$
+
+2$:
+
+	; 3. print "Bye bye" msg and HALT
+	mov	#sbye,r1
+	call	@#puts
+	halt
+
+	; 4. loop on CONT
+	br	start
+
+
+	; ----------------------
+	; puts - print a string
+	; r1 = pointer, r0,r1 changed
+puts:
+	movb	(r1)+,r0	; load xmt char
+	beq	1$		; string ends with 0
+	call	@#putc
+	br	puts		; transmit nxt char of string
+1$:	return
+
+
+	; ----------------------
+	; putc - output a single char
+	; r0 = char, r4 changed
+putc:
+	mov	#dladr,r4	; set base addr
+	movb	r0,6(r4)	; char into transmit buffer
+1$:	tstb	4(r4)		; XMT RDY?
+	bpl	1$		; no, loop
+	return
+
+	; ----------------------
+	; getc - input a single char
+	; result in r0, r4 changed
+getc:
+	mov	#dladr,r4	; set base addr
+1$:	tstb	(r4)		; RCVR DONE?
+	bpl	1$		; no, loop
+	mov	2(r4),r0	; return data
+	return
+
+
+shello:
+	.ascii	/Hello, World!/
+	.byte	15,12		; CR, LF,
+	.ascii	/Typed chars are echoed, ^C HALTs./
+	.byte	15,12,0 	; CR, LF, NUL=end marker
+sbye:
+	.byte	15,12
+	.ascii	/Good bye!/
+	.byte	15,12,0 	; CR, LF, NUL=end marker
+
+	.end
diff --git a/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape0.bin b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape0.bin
new file mode 100644
index 0000000..cefd118
Binary files /dev/null and b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape0.bin differ
diff --git a/10.03_app_demo/5_applications/mini-unix.rk05/tape1.bin b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape1.rk05
similarity index 83%
rename from 10.03_app_demo/5_applications/mini-unix.rk05/tape1.bin
rename to 10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape1.rk05
index 226547b..4c9eabd 100644
Binary files a/10.03_app_demo/5_applications/mini-unix.rk05/tape1.bin and b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape1.rk05 differ
diff --git a/10.03_app_demo/5_applications/mini-unix.rk05/tape2.bin b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape2.rk05
similarity index 100%
rename from 10.03_app_demo/5_applications/mini-unix.rk05/tape2.bin
rename to 10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape2.rk05
diff --git a/10.03_app_demo/5_applications/mini-unix.rk05/tape3.bin b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape3.rk05
similarity index 100%
rename from 10.03_app_demo/5_applications/mini-unix.rk05/tape3.bin
rename to 10.03_app_demo/5_applications/mini-unix.rk05/mini-unix-tape3.rk05
diff --git a/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix.sh b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix.sh
deleted file mode 100644
index adfe89f..0000000
--- a/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-# start Mini-UNix rom RK05 with "demo" application
-cd ~/10.03_app_demo/5_applications/mini-unix.rk05
-~/10.03_app_demo/4_deploy/demo --arbitration_active 1 --verbose --debug  --cmdfile mini-unix.cmd
-
diff --git a/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix_dk0_05.sh b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix_dk0_05.sh
new file mode 100644
index 0000000..812e90f
--- /dev/null
+++ b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix_dk0_05.sh
@@ -0,0 +1,4 @@
+# start Mini-Unix rom RK05 with "demo" application
+cd ~/10.03_app_demo/5_applications/mini-unix.rk05
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose --debug  --cmdfile mini-unix_dk_05.cmd
+
diff --git a/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix.cmd b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix_dk_05.cmd
similarity index 67%
rename from 10.03_app_demo/5_applications/mini-unix.rk05/mini-unix.cmd
rename to 10.03_app_demo/5_applications/mini-unix.rk05/mini-unix_dk_05.cmd
index 6188923..7edc2ff 100644
--- a/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix.cmd
+++ b/10.03_app_demo/5_applications/mini-unix.rk05/mini-unix_dk_05.cmd
@@ -1,30 +1,35 @@
 # inputfile for demo to select a rk05 device in the "device test" menu.
 # Read in with command line option  "demo --cmdfile ..."
 # mounts 4 "Mini.Unix" RK05 images
-td			# device test menu
+d			# device test menu
+pwr
 .wait 3000		# wait for PDP-11 to reset
+
 m i			# install max UNIBUS memory
 
+# Deposit bootloader into memory
+m ll dk.lst
+
 sd rk0			# select drive #0
-p image tape1.bin       # The BIN disk (RK05)
+p image mini-unix-tape1.rk05   # The BIN disk (RK05)
 
 sd rk1			# select drive #1
-p image tape2.bin       # The SRC disk (RK05)
+p image mini-unix-tape2.rk05 # The SRC disk (RK05)
 
 sd rk2			# select drive #2
-p image tape3.bin       # The MAN disk (RK05)
+p image mini-unix-tape3.rk05       # The MAN disk (RK05)
 
 .print Disk drive now on track after 5 secs
 .wait	6000		# wait until drive spins up
 p                       # show all params of RL1
 
 
-m ll dk.lst
+.print RK drives ready.
 .print RK11 boot loader installed.
 .print Start 10000 to boot from drive 0
 .print Reload with "m ll"
 .print
 .print Set terminal to 9600 7O1
-.print At @ prompt, select kernel file to boot with "rkmx"
+.print At @ prompt, select kernel to boot with "rkmx"
 .print Login with "root"
 
diff --git a/10.03_app_demo/5_applications/rsx11.rl02/rsx11.sh b/10.03_app_demo/5_applications/rsx11.rl02/rsx11.sh
deleted file mode 100644
index 8b22688..0000000
--- a/10.03_app_demo/5_applications/rsx11.rl02/rsx11.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-# start RSX4.1 with "demo" application
-cd ~/10.03_app_demo/5_applications/rsx11.rl02
-~/10.03_app_demo/4_deploy/demo --arbitration_active 1 --verbose --debug  --cmdfile rsx11.cmd
-
diff --git a/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_dl0_34.sh b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_dl0_34.sh
new file mode 100644
index 0000000..d0c7867
--- /dev/null
+++ b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_dl0_34.sh
@@ -0,0 +1,4 @@
+# start RSX4.1 with "demo" application
+cd ~/10.03_app_demo/5_applications/rsx11.rl02
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose --debug  --cmdfile rsx11m4.1_dl_34.cmd
+
diff --git a/10.03_app_demo/5_applications/rsx11.rl02/rsx11.cmd b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_dl_34.cmd
similarity index 85%
rename from 10.03_app_demo/5_applications/rsx11.rl02/rsx11.cmd
rename to 10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_dl_34.cmd
index 783060a..4358dc6 100644
--- a/10.03_app_demo/5_applications/rsx11.rl02/rsx11.cmd
+++ b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_dl_34.cmd
@@ -1,16 +1,20 @@
 # inputfile for demo to select a rl1 device in the "device test" menu.
 # Read in with command line option  "demo --cmdfile ..."
-td			# device test menu
+d			# device test menu
+pwr
 .wait 3000		# wait for PDP-11 to reset
 m i			# install max UNIBUS memory
 
+# Deposit bootloader into memory
+m ll dl.lst
+
 # mount RSX v4.1 in RL02 #0 and start
 sd rl0			# select drive #0
 p emulation_speed 10	# 10x speed. Load disk in 5 seconds
 p type rl02
 p runstopbutton 0	# released: "LOAD"
 p powerswitch 1		# power on, now in "load" state
-p image rsx11m.rl02     # mount image
+p image rsx11m4.1_sys_34.rl02  # mount image
 p runstopbutton 1	# press RUN/STOP, will start
 
         # mount disk #1 start
@@ -19,7 +23,7 @@ p emulation_speed 10	# 10x speed. Load disk in 5 seconds
 p type rl02
 p runstopbutton 0	# released: "LOAD"
 p powerswitch 1		# power on, now in "load" state
-p image rsx11user.rl02 	# mount image
+p image rsx11m4.1_user.rl02 	# mount image
 p runstopbutton 1	# press RUN/STOP, will start
 
 # mount scratch2 in RL02 #2 and start
@@ -28,7 +32,7 @@ p emulation_speed 10	# 10x speed. Load disk in 5 seconds
 p type rl02
 p runstopbutton 0	# released: "LOAD"
 p powerswitch 1		# power on, now in "load" state
-p image rsx11hlpdcl.rl02 	# mount image
+p image rsx11m4.1_hlpdcl.rl02 	# mount image
 p runstopbutton 1	# press RUN/STOP, will start
 
 # mount scratch3 in RL02 #3 and start
@@ -37,7 +41,7 @@ p emulation_speed 10	# 10x speed. Load disk in 5 seconds
 p type rl02
 p runstopbutton 0	# released: "LOAD"
 p powerswitch 1		# power on, now in "load" state
-p image rsx11excprv.rl02  # mount image
+p image rsx11m4.1_excprv.rl02  # mount image
 p runstopbutton 1	# press RUN/STOP, will start
 
 .print Disk drive now on track after 5 secs
@@ -45,7 +49,7 @@ p runstopbutton 1	# press RUN/STOP, will start
 
 p                       # show all params of RL1
 
-m ll dl.lst
+.print RL drives ready.
 .print RL11 boot loader installed.
 .print Start 10000 to boot from drive 0, 10010 for drive #1, ...
 .print Reload with "m ll"
diff --git a/10.03_app_demo/5_applications/rsx11.rl02/rsx11excprv.rl02 b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_excprv.rl02
similarity index 100%
rename from 10.03_app_demo/5_applications/rsx11.rl02/rsx11excprv.rl02
rename to 10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_excprv.rl02
diff --git a/10.03_app_demo/5_applications/rsx11.rl02/rsx11hlpdcl.rl02 b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_hlpdcl.rl02
similarity index 100%
rename from 10.03_app_demo/5_applications/rsx11.rl02/rsx11hlpdcl.rl02
rename to 10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_hlpdcl.rl02
diff --git a/10.03_app_demo/5_applications/rsx11.rl02/rsx11m.rl02 b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_sys_34.rl02
similarity index 100%
rename from 10.03_app_demo/5_applications/rsx11.rl02/rsx11m.rl02
rename to 10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_sys_34.rl02
diff --git a/10.03_app_demo/5_applications/rsx11.rl02/rsx11user.rl02 b/10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_user.rl02
similarity index 100%
rename from 10.03_app_demo/5_applications/rsx11.rl02/rsx11user.rl02
rename to 10.03_app_demo/5_applications/rsx11.rl02/rsx11m4.1_user.rl02
diff --git a/10.03_app_demo/5_applications/rt11.mscp/du.lst b/10.03_app_demo/5_applications/rt11.mscp/du.lst
new file mode 100644
index 0000000..615cee3
--- /dev/null
+++ b/10.03_app_demo/5_applications/rt11.mscp/du.lst
@@ -0,0 +1,113 @@
+       1                                	.title	M9312 'DU' BOOT prom for MSCP compatible controller
+       2                                
+       3                                	; This source code is a mdified copy of the DEC M9312 23-767A9 boot PROM.
+       4                                	;
+       5                                	; This boot PROM is for any MSCP compatible controller (DEC UDA50, EMULEX UC17/UC18).
+       6                                	;
+       7                                	; Multiple units and/or CSR addresses are supported via different entry points.
+       8                                
+       9                                		;
+      10                                	; Revision history:
+      11                                	; May 2017: Joerg Hoppe
+      12                                	;
+      13                                	; 198?:  DEC
+      14                                	;      Original ROM 23-767A9 for M9312.
+      15                                	;
+      16                                
+      17                                
+      18                                
+      19 172150                         mscsr	=172150 			; std MSCP csrbase
+      20                                
+      21 000000                         msip	=+0				; IP register
+      22 000002                         mssa	=+2				; SA register
+      23                                
+      24                                	.asect
+      25 010000                         	.=10000 			;  arbitrary position > 3000
+      26                                
+      27                                	; --------------------------------------------------
+      28 001004                         rpkt	=1004	; rpkt structure
+      29 001070                         cpkt	=1070	; cpkt structure
+      30 001200                         comm	=1200	; comm structure
+      31                                ;comm	 =2404	 ; comm structure (at 'blt .+12')
+      32                                
+      33                                	; register usage:
+      34                                	; r0: unit number 0..3
+      35                                	; r1: MSCP csrbase
+      36                                	; r2: moving buffer pointer
+      37                                	; r3: moving buffer pointer
+      38                                	; r5: init mask
+      39                                
+      40                                	; 4 unit numbers => 4 entry addresses
+      41                                start0:
+      42 010000 012700  000000          	mov	#0,r0
+      43 010004 000413                  	br	duNr
+      44 010006 000240                  	nop
+      45                                start1:
+      46 010010 012700  000001          	mov	#1,r0
+      47 010014 000407                  	br	duNr
+      48 010016 000240                  	nop
+      49                                start2:
+      50 010020 012700  000002          	mov	#2,r0
+      51 010024 000403                  	br	duNr
+      52 010026 000240                  	nop
+      53                                start3:
+      54 010030 012700  000003          	mov	#3,r0
+      55                                
+      56                                	; retry entry
+      57 010034 012701  172150          duNr:	mov	#mscsr,r1		; boot std csr, unit <R0>
+      58                                
+      59 010040 010021                  go:	mov	r0,(r1)+		; init controller (write IP), bump ptr
+      60 010042 012705  004000          	mov	#4000,r5		; S1 state bitmask
+      61 010046 012703  010166          	mov	#mscpdt,r3		; point to data
+      62                                
+      63                                	; write 4 init words, with r5 mask from 4000 to 40000
+      64 010052 005711                  3$:	tst	(r1)			; error bit set ?
+      65 010054 100767                  	bmi	duNr			; yes, fail back to begin to retry
+      66 010056 031105                  	bit	(r1),r5 		; step bit set ?
+      67 010060 001774                  	beq	3$			; not yet, wait loop
+      68 010062 012311                  	mov	(r3)+,(r1)		; yes, send next init data
+      69 010064 006305                  	asl	r5			; next mask
+      70 010066 100371                  	bpl	3$			; s4 done? br if not yet
+      71                                
+      72 010070 005002                  4$:	clr	r2			; set bufptr to 0
+      73 010072 005022                  5$:	clr	(r2)+			; clear buffer [0..2403]
+      74 010074 020227  001200          	cmp	r2,#comm		; check for end of buffer
+      75 010100 001374                  	bne	5$			; loop if not done
+      76                                
+      77 010102 010237  001064          	mov	r2,@#cpkt-4		; set lnt -- R2=2404
+      78 010106 112337  001100          	movb	(r3)+,@#cpkt+10 	; set command
+      79 010112 111337  001105          	movb	(r3),@#cpkt+15		; set bytecnt(hi)
+      80 010116 010037  001074          	mov	r0,@#cpkt+4		; set unit
+      81 010122 012722  001004          	mov	#rpkt,(r2)+		; rq desc addr
+      82 010126 010522                  	mov	r5,(r2)+		; rq own bit15
+      83 010130 012722  001070          	mov	#cpkt,(r2)+		; cp desc addr
+      84 010134 010522                  	mov	r5,(r2)+		; cq own bit15
+      85 010136 016102  177776          	mov	-2(r1),r2		; wake controller (read IP)
+      86                                
+      87 010142 005737  001202          6$:	tst	@#comm+2		; rq own controller ?
+      88 010146 100775                  	bmi	6$			; loop if not done
+      89                                
+      90 010150 105737  001016          	tstb	@#rpkt+12		; check for error ?
+      91 010154 001327                  	bne	duNr			; yup, fail back to begin to retry
+      92                                
+      93 010156 105723                  	tstb	(r3)+			; check end of table ?
+      94 010160 001743                  	beq	4$			; br if not yet
+      95                                
+      96 010162 005041                  	clr	-(r1)			; init controller (write IP)
+      97 010164 005007                  	clr	pc			; jmp to bootstrap at zero
+      98                                
+      99                                	; MSCP init and command data
+     100                                	; pointed to by r3
+     101                                mscpdt:
+     102 010166 100000                  	.word	100000			; S1: 100000 = no int, ring size 1, no vector
+     103 010170 001200                  	.word	comm			; S2: 002404 = ringbase lo addr
+     104 010172 000000                  	.word	000000			; S3: 000000 = no purge/poll, ringbase hi addr
+     105 010174 000001                  	.word	000001			; S4: 000001 = go bit
+     106                                	;
+     107                                	; MSCP command data
+     108                                	;
+     109 010176    011     000          	.byte	011,000 		; cmd=011(online), bytecnt_hi=000(0)
+     110 010200    041     002          	.byte	041,002 		; cmd=041(read), bytecnt_hi=002(512)
+     111                                
+     112                                	.end
+     112                                
diff --git a/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5.simh_pdp11 b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5.simh_pdp11
new file mode 100644
index 0000000..beba0fb
--- /dev/null
+++ b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5.simh_pdp11
@@ -0,0 +1,15 @@
+set cpu 11/34
+
+set rl disabled
+
+set rq enabled
+set rq0 ra80
+att rq0 rt11v5.5_du0.ra80
+
+; To make a bootable RA8= from RT11 running on RL02s:
+; . init du0:
+; . copy /sys *.* du0:
+; . copy/boot  du0:rt11fb.sys du0:
+; . boot du0:
+
+boot rq0
diff --git a/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5_34.ra80 b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5_34.ra80
new file mode 100644
index 0000000..7da10e3
Binary files /dev/null and b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5_34.ra80 differ
diff --git a/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5_du_34.cmd b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5_du_34.cmd
new file mode 100644
index 0000000..46e74ba
--- /dev/null
+++ b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5_du_34.cmd
@@ -0,0 +1,31 @@
+# inputfile for demo to select a rl1 device in the "device test" menu.
+# Read in with command line option  "demo --cmdfile ..."
+d			# device menu
+pwr			# reboot PDP-11
+.wait 3000		# wait for PDP-11 to reset
+m i			# install max UNIBUS memory
+
+# Deposit bootloader into memory
+m ll du.lst
+
+# mount RT11 v5.5 in drive #0 and start
+sd uda0			# select drive #0
+
+# set type to "RA80"
+p type RA80
+p image rt11v5.5_34.ra80 # mount image file with test pattern
+
+# empty scratch disk in uda1:
+sd uda1
+p type RA80
+p image scratch1.ra80
+
+
+
+.print MSCP drives ready.
+.print UDA50 boot loader installed.
+.print Start 10000 to boot from drive 0, 10010 for drive 1, ...
+.print Reload with "m ll"
+
+
+
diff --git a/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5fb_du0_34.sh b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5fb_du0_34.sh
new file mode 100644
index 0000000..6ab9cea
--- /dev/null
+++ b/10.03_app_demo/5_applications/rt11.mscp/rt11v5.5fb_du0_34.sh
@@ -0,0 +1,4 @@
+# start RT11 5.5 with "demo" application
+cd ~/10.03_app_demo/5_applications/rt11.mscp
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose --debug  --cmdfile rt11v5.5_du_34.cmd
+
diff --git a/10.03_app_demo/5_applications/rt11.rl02/rt11.sh b/10.03_app_demo/5_applications/rt11.rl02/rt11.sh
deleted file mode 100644
index f571c71..0000000
--- a/10.03_app_demo/5_applications/rt11.rl02/rt11.sh
+++ /dev/null
@@ -1,4 +0,0 @@
-# start RT11 5.5 with "demo" application
-cd ~/10.03_app_demo/5_applications/rt11.rl02
-~/10.03_app_demo/4_deploy/demo --arbitration_active 1 --verbose --debug  --cmdfile rt11.cmd
-
diff --git a/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5.simh_pdp11 b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5.simh_pdp11
new file mode 100644
index 0000000..af24e7c
--- /dev/null
+++ b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5.simh_pdp11
@@ -0,0 +1,18 @@
+set cpu 11/34
+
+set rl enabled
+
+att rl0 rt11v5.5_34.rl02
+att rl1 rt11v5.5_games_34.rl02
+
+set rq enabled
+set rq0 ra82
+att rq0 tmp.ra82
+
+; To make a bootable RA82:
+; . init du0:
+; . copy /sys *.* du0:
+; . copy/boot  du0:rt11fb.sys du0:
+; . boot du0:
+
+boot rl0
diff --git a/10.03_app_demo/5_applications/rt11.rl02/rt11v55.rl02 b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_34.rl02
similarity index 99%
rename from 10.03_app_demo/5_applications/rt11.rl02/rt11v55.rl02
rename to 10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_34.rl02
index 3f043af..f4c32e9 100644
Binary files a/10.03_app_demo/5_applications/rt11.rl02/rt11v55.rl02 and b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_34.rl02 differ
diff --git a/10.03_app_demo/5_applications/rt11.rl02/rt11.cmd b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_dl_34.cmd
similarity index 88%
rename from 10.03_app_demo/5_applications/rt11.rl02/rt11.cmd
rename to 10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_dl_34.cmd
index 148ade0..dea1b63 100644
--- a/10.03_app_demo/5_applications/rt11.rl02/rt11.cmd
+++ b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_dl_34.cmd
@@ -1,16 +1,20 @@
 # inputfile for demo to select a rl1 device in the "device test" menu.
 # Read in with command line option  "demo --cmdfile ..."
-td			# device test menu
+d			# device menu
+pwr			# reboot PDP-11
 .wait 3000		# wait for PDP-11 to reset
 m i			# install max UNIBUS memory
 
+# Deposit bootloader into memory
+m ll dl.lst
+
 # mount RT11 v5.5 in RL02 #0 and start
 sd rl0			# select drive #0
 p emulation_speed 10	# 10x speed. Load disk in 5 seconds
 # set type to "rl02"
 p runstopbutton 0	# released: "LOAD"
 p powerswitch 1		# power on, now in "load" state
-p image rt11v55.rl02 	# mount image file with test pattern
+p image rt11v5.5_34.rl02 # mount image file with test pattern
 p runstopbutton 1	# press RUN/STOP, will start
 
 # mount RT11 GAMES in RL02 #1 and start
@@ -19,7 +23,7 @@ p emulation_speed 10	# 10x speed. Load disk in 5 seconds
 # set type to "rl02"
 p runstopbutton 0	# released: "LOAD"
 p powerswitch 1		# power on, now in "load" state
-p image rt11games.rl02 	# mount image file with test pattern
+p image rt11v5.5_games_34.rl02	# mount image file with test pattern
 p runstopbutton 1	# press RUN/STOP, will start
 
 # mount scratch2 in RL02 #2 and start
@@ -44,7 +48,7 @@ p runstopbutton 1	# press RUN/STOP, will start
 .wait	6000		# wait until drive spins up
 p                       # show all params of RL1
 
-m ll dl.lst
+.print RL drives ready.
 .print RL11 boot loader installed.
 .print Start 10000 to boot from drive 0, 10010 for drive 1, ...
 .print Reload with "m ll"
diff --git a/10.03_app_demo/5_applications/rt11.rl02/rt11games.rl02 b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_games_34.rl02
similarity index 100%
rename from 10.03_app_demo/5_applications/rt11.rl02/rt11games.rl02
rename to 10.03_app_demo/5_applications/rt11.rl02/rt11v5.5_games_34.rl02
diff --git a/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5fb_dl0_34.sh b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5fb_dl0_34.sh
new file mode 100644
index 0000000..661cda3
--- /dev/null
+++ b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5fb_dl0_34.sh
@@ -0,0 +1,4 @@
+# start RT11 5.5 with "demo" application
+cd ~/10.03_app_demo/5_applications/rt11.rl02
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose --debug  --cmdfile rt11v5.5_dl_34.cmd
+
diff --git a/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5sj_dl1_34.sh b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5sj_dl1_34.sh
new file mode 100644
index 0000000..661cda3
--- /dev/null
+++ b/10.03_app_demo/5_applications/rt11.rl02/rt11v5.5sj_dl1_34.sh
@@ -0,0 +1,4 @@
+# start RT11 5.5 with "demo" application
+cd ~/10.03_app_demo/5_applications/rt11.rl02
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose --debug  --cmdfile rt11v5.5_dl_34.cmd
+
diff --git a/10.03_app_demo/5_applications/unixv6.rk05/unixv6.sh b/10.03_app_demo/5_applications/unixv6.rk05/unixv6_dk0_34.sh
similarity index 51%
rename from 10.03_app_demo/5_applications/unixv6.rk05/unixv6.sh
rename to 10.03_app_demo/5_applications/unixv6.rk05/unixv6_dk0_34.sh
index d000ded..7021f1d 100644
--- a/10.03_app_demo/5_applications/unixv6.rk05/unixv6.sh
+++ b/10.03_app_demo/5_applications/unixv6.rk05/unixv6_dk0_34.sh
@@ -1,4 +1,4 @@
 # start Mini-UNix rom RK05 with "demo" application
 cd ~/10.03_app_demo/5_applications/unixv6.rk05
-~/10.03_app_demo/4_deploy/demo --arbitration_active 1 --verbose --debug  --cmdfile unixv6.cmd
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose --debug  --cmdfile unixv6_dk_34.cmd
 
diff --git a/10.03_app_demo/5_applications/unixv6.rk05/unixv6.cmd b/10.03_app_demo/5_applications/unixv6.rk05/unixv6_dk_34.cmd
similarity index 83%
rename from 10.03_app_demo/5_applications/unixv6.rk05/unixv6.cmd
rename to 10.03_app_demo/5_applications/unixv6.rk05/unixv6_dk_34.cmd
index 0e0add3..7898412 100644
--- a/10.03_app_demo/5_applications/unixv6.rk05/unixv6.cmd
+++ b/10.03_app_demo/5_applications/unixv6.rk05/unixv6_dk_34.cmd
@@ -1,10 +1,14 @@
 # inputfile for demo to select a rk05 device in the "device test" menu.
 # Read in with command line option  "demo --cmdfile ..."
 # mounts 3 "Unixv6" RK05 images
-td			# device test menu
+d			# device test menu
+pwr
 .wait 3000		# wait for PDP-11 to reset
 m i			# install max UNIBUS memory
 
+# Deposit bootloader into memory
+m ll dk.lst
+
 sd rk0			# select drive #0
 p image v6bin.rk
 
@@ -19,12 +23,11 @@ p image v6src.rk
 p                       # show all params of RL1
 
 
-m ll dk.lst
+.print RK drives ready.
 .print RK11 boot loader installed.
 .print Start 10000 to boot from drive 0
 .print Reload boot loader with "m ll"
 .print Set terminal to 9600 7O1
-.print On @ prompt, select kernel filestty
- "rkunix"
+.print On @ prompt, select kernel to run: "rkunix"
 
 
diff --git a/10.03_app_demo/5_applications/xxdp.rl02/xxdp.cmd b/10.03_app_demo/5_applications/xxdp.rl02/xxdp.cmd
index 88e07ef..ca2481f 100644
--- a/10.03_app_demo/5_applications/xxdp.rl02/xxdp.cmd
+++ b/10.03_app_demo/5_applications/xxdp.rl02/xxdp.cmd
@@ -1,9 +1,13 @@
 # inputfile for demo to select a rl1 device in the "device test" menu.
 # Read in with command line option  "demo --cmdfile ..."
-td			# device test menu
+d			# device test menu
+pwr
 .wait 3000		# wait for PDP-11 to reset
 m i			# install max UNIBUS memory
 
+# Deposit bootloader into memory
+m ll dl.lst
+
 # mount XXDP22 in RL02 #0 and start
 sd rl0			# select drive #0
 p emulation_speed 10	# 10x speed. Load disk in 5 seconds
@@ -45,7 +49,7 @@ p runstopbutton 1	# press RUN/STOP, will start
 .wait	6000		# wait until drive spins up
 p                       # show all params of RL1
 
-m ll dl.lst
+.print RL drives ready.
 .print RL11 boot loader installed.
 .print Start 10000 to boot from drive 0, 10010 for drive 1, ...
 .print Reload with "m ll"
diff --git a/10.03_app_demo/5_applications/xxdp.rl02/xxdp.sh b/10.03_app_demo/5_applications/xxdp.rl02/xxdp.sh
deleted file mode 100644
index 271b2b1..0000000
--- a/10.03_app_demo/5_applications/xxdp.rl02/xxdp.sh
+++ /dev/null
@@ -1,3 +0,0 @@
-# start xxdp with "demo" application
-cd ~/10.03_app_demo/5_applications/xxdp.rl02
-~/10.03_app_demo/4_deploy/demo --arbitration_active 1 --verbose    --debug  --cmdfile xxdp.cmd
diff --git a/10.03_app_demo/5_applications/xxdp.rl02/xxdp2.2_dl0.sh b/10.03_app_demo/5_applications/xxdp.rl02/xxdp2.2_dl0.sh
new file mode 100644
index 0000000..04d75aa
--- /dev/null
+++ b/10.03_app_demo/5_applications/xxdp.rl02/xxdp2.2_dl0.sh
@@ -0,0 +1,3 @@
+# start xxdp with "demo" application
+cd ~/10.03_app_demo/5_applications/xxdp.rl02
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose    --debug  --cmdfile xxdp.cmd
diff --git a/10.03_app_demo/5_applications/xxdp.rl02/xxdp2.5_dl1.sh b/10.03_app_demo/5_applications/xxdp.rl02/xxdp2.5_dl1.sh
new file mode 100644
index 0000000..04d75aa
--- /dev/null
+++ b/10.03_app_demo/5_applications/xxdp.rl02/xxdp2.5_dl1.sh
@@ -0,0 +1,3 @@
+# start xxdp with "demo" application
+cd ~/10.03_app_demo/5_applications/xxdp.rl02
+~/10.03_app_demo/4_deploy/demo --arb 1 --verbose    --debug  --cmdfile xxdp.cmd
diff --git a/91_3rd_party/pru-c-compile/pru-software-support-package/lib/rpmsg_lib.lib b/91_3rd_party/pru-c-compile/pru-software-support-package/lib/rpmsg_lib.lib
new file mode 100644
index 0000000..dbd1cd0
Binary files /dev/null and b/91_3rd_party/pru-c-compile/pru-software-support-package/lib/rpmsg_lib.lib differ
diff --git a/compile-all.sh b/compile-all.sh
deleted file mode 100644
index 710db39..0000000
--- a/compile-all.sh
+++ /dev/null
@@ -1,7 +0,0 @@
-. compile-bbb.env
-cd 10.03_app_demo/2_src
-make clean
-make
-cd ~
-10.03_app_demo/4_deploy/demo
-
diff --git a/compile.sh b/compile.sh
new file mode 100644
index 0000000..a5576ef
--- /dev/null
+++ b/compile.sh
@@ -0,0 +1,17 @@
+. compile-bbb.env
+
+# Debugging: remote from Eclipse. Compile on BBB is release.
+export MAKE_CONFIGURATION=RELEASE
+
+cd 10.03_app_demo/2_src
+
+if [ "$1" == "-a" ] ; then
+make clean
+fi
+
+make
+cd ~
+
+echo "To run binary, call"
+echo "10.03_app_demo/4_deploy/demo"
+