From 1b90dd73f73f13f63469f883c8ca87902f933471 Mon Sep 17 00:00:00 2001 From: Joerg Hoppe Date: Sun, 8 Dec 2019 17:58:28 +0100 Subject: [PATCH] tuning for PCB 2019-12 CPU20 diags in comments --- .../pru1/pru1_statemachine_arbitration.c | 6 +++--- 10.01_base/2_src/pru1/pru1_timeouts.c | 8 ++++--- 10.01_base/2_src/shared/tuning.h | 21 ++++++++++++++++--- 3 files changed, 26 insertions(+), 9 deletions(-) diff --git a/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c b/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c index 392120e..ab6068f 100644 --- a/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c +++ b/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c @@ -189,8 +189,8 @@ uint8_t sm_arb_worker_device(uint8_t granted_requests_mask) { // "A device may not accept a grant (assert SACK) after it passes the grant" uint8_t device_grant_mask = granted_requests_mask & sm_arb.device_request_mask & ~sm_arb.device_forwarded_grant_mask; if (device_grant_mask) { - // one of our requests was granted: set SACK - // AND simultaneously clear granted requests BR*/NPR + // one of our requests was granted and not forwarded: + // set SACK AND simultaneously clear granted requests BR*/NPR // BIT(5): SACK mask and level buslatches_setbits(1, (PRIORITY_ARBITRATION_BIT_MASK & sm_arb.device_request_mask) | BIT(5), ~device_grant_mask | BIT(5)) @@ -207,7 +207,7 @@ uint8_t sm_arb_worker_device(uint8_t granted_requests_mask) { } return 0; // no REQUEST, or no GRANT for us, or wait for BG/BPG & BBSY && SSYN } else { - // State 2: wait for BG/NPG, BBSY and SSYN to clear + // State 2: got GRANT, wait for BG/NPG, BBSY and SSYN to clear // DMA and INTR: // "After receiving the negation of BBSY, SSYN and BGn, // the requesting device asserts BBSY" diff --git a/10.01_base/2_src/pru1/pru1_timeouts.c b/10.01_base/2_src/pru1/pru1_timeouts.c index 6150520..420354c 100644 --- a/10.01_base/2_src/pru1/pru1_timeouts.c +++ b/10.01_base/2_src/pru1/pru1_timeouts.c @@ -96,18 +96,20 @@ void timeout_cleanup(uint32_t *target_cycles_var) { // test a timeout, wether it reached its arg count nor or earlier bool timeout_reached(uint32_t *target_cycles_var) { + bool result = false ; // fast path: assume timeout_reached() is called // because timeout is active if (PRU1_CTRL.CYCLE < *target_cycles_var) - return false; + result = false; else if (*target_cycles_var == 0) - return true; // already "reached" if inactive + result =true; // already "reached" if inactive else { // switched from "running" to "timeout reached" *target_cycles_var = 0; timeouts_active--; - return true; + result = true; } + return result ; } void timeout_init(void) { diff --git a/10.01_base/2_src/shared/tuning.h b/10.01_base/2_src/shared/tuning.h index 6f6de3e..240b10f 100644 --- a/10.01_base/2_src/shared/tuning.h +++ b/10.01_base/2_src/shared/tuning.h @@ -26,6 +26,7 @@ #define TUNING_PCB_LEGACY_SECURE //#define TUNING_PCB_2018_12_OPTIMIZED +//#define TUNING_PCB_2019_12_OPTIMIZED //#define TUNING_PCB_TEST /*** Wait cycles for buslatch access. Depends on PCB, used chips and alofirth ***/ @@ -34,9 +35,9 @@ // #define BUSLATCHES_GETBYTE_DELAY 10 // Standard #if defined(TUNING_PCB_TEST) // experimental to test error rates -#define BUSLATCHES_GETBYTE_DELAY 10 -#define BUSLATCHES_SETBITS_DELAY 4 -#define BUSLATCHES_SETBYTE_DELAY 6 +#define BUSLATCHES_GETBYTE_DELAY 7 +#define BUSLATCHES_SETBITS_DELAY 0 +#define BUSLATCHES_SETBYTE_DELAY 0 #elif defined(TUNING_PCB_LEGACY_SECURE) /* Secure setting for PCBs <= 2018-12, delivered before June 2019. @@ -71,6 +72,20 @@ //#define BUSLATCHES_GETBYTE_DELAY 8 //#define BUSLATCHES_SETBITS_DELAY 3 //#define BUSLATCHES_SETBYTE_DELAY 5 +#elif defined(TUNING_PCB_2019_12_OPTIMIZED) +/* Setting for PCB v2018_12 with optimized timing (ticket 21, June 2019) + BeagleBone: BBB (no BBG) + U2 (REGSEL): 74AC138 -> 74AHC138 + RN8,9 (DATIN) : 47 -> 68 Ohm + RN10 <1:6>(REGADR): 33->0 Ohm + RN10 <7:8>(REGWRITE): 33->0 Ohm + R6,R7 (REGWRITE TERM): none + RN6,RN7 (DATOUT inline): 22 -> 27 + RN4,RN5 [[/DATOUT]] end) -> 180/- + */ +#define BUSLATCHES_GETBYTE_DELAY 7 +#define BUSLATCHES_SETBITS_DELAY 0 +#define BUSLATCHES_SETBYTE_DELAY 0 #endif // UNIBUS timing: Wait to stabilize DATA before MSYN asserted