diff --git a/10.01_base/2_src/pru1/pru1_main_unibus.c b/10.01_base/2_src/pru1/pru1_main_unibus.c index 18bd2c2..f25077b 100644 --- a/10.01_base/2_src/pru1/pru1_main_unibus.c +++ b/10.01_base/2_src/pru1/pru1_main_unibus.c @@ -94,7 +94,7 @@ void main(void) { statemachine_arb_worker_func sm_arb_worker = &sm_arb_worker_client; statemachine_state_func sm_data_slave_state = NULL; statemachine_state_func sm_data_master_state = NULL; - statemachine_state_func sm_intr_slave_state = NULL ; + statemachine_state_func sm_intr_slave_state = NULL; // these are function pointers: could be 16bit on PRU? bool emulate_cpu = false; @@ -125,24 +125,16 @@ void main(void) { // State 1 "SLAVE" // DATA or INTR for CPU? - + // fast: a complete slave data cycle if (!sm_data_slave_state) sm_data_slave_state = (statemachine_state_func) &sm_data_slave_start; while ((sm_data_slave_state = sm_data_slave_state()) - && EVENT_IS_ACKED(mailbox,deviceregister)) + && EVENT_IS_ACKED(mailbox, deviceregister)) // throws signals to ARM, // Acess to internal registers may may issue AMR2PRU opcode, so exit loop then ;// execute complete slave cycle, then check NPR/INTR - if (emulate_cpu) { - // same code loop as for DATA cycle - if (!sm_intr_slave_state) - sm_intr_slave_state = (statemachine_state_func) &sm_intr_slave_start; - while ((sm_intr_slave_state = sm_intr_slave_state()) - && EVENT_IS_ACKED(mailbox,intr_slave)) ; - } - // signal INT or PWR FAIL to ARM // before arb_worker(), so BR/NPR requests are canceled on INIT do_event_initializationsignals(); @@ -150,7 +142,7 @@ void main(void) { // Priority Arbitration // Delay INTR or DMA while BUS halted via SSYN. // ARM may start DMA within deviceregister event! - if (EVENT_IS_ACKED(mailbox,deviceregister)) { + if (EVENT_IS_ACKED(mailbox, deviceregister)) { // execute one of the arbitration workers uint8_t grant_mask = sm_arb_worker(); // sm_arb_worker()s include State 2 "BBSYWAIT". @@ -183,6 +175,16 @@ void main(void) { // throws signals to ARM, causes may issue mailbox.arm2pru_req } + if (emulate_cpu) { + // Receive INTR from physical or emulated devices, and signal ARM. + // Same code loop as for DATA cycle + if (!sm_intr_slave_state) + sm_intr_slave_state = (statemachine_state_func) &sm_intr_slave_start; + while ((sm_intr_slave_state = sm_intr_slave_state()) + && EVENT_IS_ACKED(mailbox, intr_slave)) + ; + } + // process ARM commands in master and slave mode // standard operation may be interrupt by other requests if (arm2pru_req_cached = mailbox.arm2pru_req) { @@ -275,16 +277,16 @@ void main(void) { } mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done break; - case ARM2PRU_CPU_ENABLE: + case ARM2PRU_CPU_ENABLE: // bool flag much faster to access then shared mailbox member. - emulate_cpu = mailbox.cpu_enable ; - if (emulate_cpu) + emulate_cpu = mailbox.cpu_enable; + if (emulate_cpu) sm_arb_worker = &sm_arb_worker_master; else sm_arb_worker = &sm_arb_worker_client; mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done - break ; - case ARM2PRU_HALT: + break; + case ARM2PRU_HALT: mailbox.arm2pru_req = ARM2PRU_NONE; // ACK: done __halt(); // LA: trigger on timeout of REG_WRITE break; diff --git a/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c b/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c index 52fd2fa..ee5a49c 100644 --- a/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c +++ b/10.01_base/2_src/pru1/pru1_statemachine_arbitration.c @@ -244,8 +244,8 @@ uint8_t sm_arb_worker_master() { sm_arb.arbitrator_grant_mask = 0; // CPU looses now access to UNIBUS after current cycle - mailbox.arbitrator.device_BBSY = true; // DATA section used by device now - //NONO: BBSY ! No SACK for parts of DMA cycle . + mailbox.arbitrator.device_BBSY = true; + // DATA section to be used by device now, for DMA or INTR timeout_cleanup(TIMEOUT_SACK); } else if (latch1val & PRIORITY_ARBITRATION_BIT_NP) { diff --git a/10.01_base/2_src/pru1/pru1_statemachine_intr_master.c b/10.01_base/2_src/pru1/pru1_statemachine_intr_master.c index 308de1a..d1e6743 100644 --- a/10.01_base/2_src/pru1/pru1_statemachine_intr_master.c +++ b/10.01_base/2_src/pru1/pru1_statemachine_intr_master.c @@ -110,6 +110,7 @@ static statemachine_state_func sm_intr_master_state_2() { // so no concurrent ARP+PRU access PRU2ARM_INTERRUPT ; + return NULL; // ready // master still drives SSYN diff --git a/10.01_base/2_src/pru1/pru1_statemachine_intr_slave.c b/10.01_base/2_src/pru1/pru1_statemachine_intr_slave.c index 7bae1d7..4a0a2d0 100644 --- a/10.01_base/2_src/pru1/pru1_statemachine_intr_slave.c +++ b/10.01_base/2_src/pru1/pru1_statemachine_intr_slave.c @@ -69,7 +69,6 @@ statemachine_state_func sm_intr_slave_start() { EVENT_SIGNAL(mailbox,intr_slave) ; // signal to ARM PRU2ARM_INTERRUPT ; - PRU_DEBUG_PIN0(1); // wait until ARM acked return (statemachine_state_func) &sm_intr_slave_state_1; } diff --git a/10.01_base/2_src/shared/mailbox.h b/10.01_base/2_src/shared/mailbox.h index c929f95..d88c989 100644 --- a/10.01_base/2_src/shared/mailbox.h +++ b/10.01_base/2_src/shared/mailbox.h @@ -124,7 +124,7 @@ typedef struct { // data for bus arbitrator typedef struct { // arbitrator.device_BBSY indicates a device wants or has acquired the UNIBUS. - // cpu DATA transfer must be delayed until device_BBSY == 0 + // CPU DATA transfer must be delayed until device_BBSY == 0 // set when arbitration logic detects SACK! uint8_t device_BBSY;