From 827515eb8cc7349ca572f1ce6a4dca0bdddef61f Mon Sep 17 00:00:00 2001 From: Joerg Hoppe Date: Mon, 26 Aug 2019 13:51:34 +0200 Subject: [PATCH] module rename for upcoming intr_slave --- 10.01_base/2_src/pru1/Makefile | 4 +-- 10.01_base/2_src/pru1/pru1_main_test.c | 2 +- 10.01_base/2_src/pru1/pru1_main_unibus.c | 10 +++--- ...slave.c => pru1_statemachine_data_slave.c} | 0 ...slave.h => pru1_statemachine_data_slave.h} | 0 ...intr.c => pru1_statemachine_intr_master.c} | 34 +++++++++---------- ...intr.h => pru1_statemachine_intr_master.h} | 14 ++++---- 7 files changed, 32 insertions(+), 32 deletions(-) rename 10.01_base/2_src/pru1/{pru1_statemachine_slave.c => pru1_statemachine_data_slave.c} (100%) rename 10.01_base/2_src/pru1/{pru1_statemachine_slave.h => pru1_statemachine_data_slave.h} (100%) rename 10.01_base/2_src/pru1/{pru1_statemachine_intr.c => pru1_statemachine_intr_master.c} (75%) rename 10.01_base/2_src/pru1/{pru1_statemachine_intr.h => pru1_statemachine_intr_master.h} (80%) diff --git a/10.01_base/2_src/pru1/Makefile b/10.01_base/2_src/pru1/Makefile index 1e66ac6..22788d5 100644 --- a/10.01_base/2_src/pru1/Makefile +++ b/10.01_base/2_src/pru1/Makefile @@ -71,8 +71,8 @@ OBJECTS_COMMON= \ $(OBJ_DIR)/pru1_pru_mailbox.object \ $(OBJ_DIR)/pru1_statemachine_arbitration.object \ $(OBJ_DIR)/pru1_statemachine_dma.object \ - $(OBJ_DIR)/pru1_statemachine_intr.object \ - $(OBJ_DIR)/pru1_statemachine_slave.object \ + $(OBJ_DIR)/pru1_statemachine_intr_master.object \ + $(OBJ_DIR)/pru1_statemachine_data_slave.object \ $(OBJ_DIR)/pru1_timeouts.object \ $(OBJ_DIR)/pru1_utils.object diff --git a/10.01_base/2_src/pru1/pru1_main_test.c b/10.01_base/2_src/pru1/pru1_main_test.c index f9119ff..e85cd26 100644 --- a/10.01_base/2_src/pru1/pru1_main_test.c +++ b/10.01_base/2_src/pru1/pru1_main_test.c @@ -53,7 +53,7 @@ #include "pru1_buslatches.h" #include "pru1_statemachine_arbitration.h" #include "pru1_statemachine_dma.h" -#include "pru1_statemachine_intr.h" +#include "pru1_statemachine_intr_master.h" #include "pru1_statemachine_slave.h" // Supress warnings about using void * as function pointers diff --git a/10.01_base/2_src/pru1/pru1_main_unibus.c b/10.01_base/2_src/pru1/pru1_main_unibus.c index 3436d80..bfc4251 100644 --- a/10.01_base/2_src/pru1/pru1_main_unibus.c +++ b/10.01_base/2_src/pru1/pru1_main_unibus.c @@ -58,7 +58,7 @@ #include "pru1_buslatches.h" #include "pru1_statemachine_arbitration.h" #include "pru1_statemachine_dma.h" -#include "pru1_statemachine_intr.h" +#include "pru1_statemachine_intr_master.h" #include "pru1_statemachine_slave.h" // supress warnigns about using void * as function pointers @@ -149,10 +149,10 @@ void main(void) { uint8_t idx = PRIORITY_ARBITRATION_INTR_BIT2IDX(grant_mask); // now transfer INTR vector for interupt of GRANted level. // vector and ARM context have been setup by ARM before ARM2PRU_INTR already - sm_intr.vector = mailbox.intr.vector[idx]; - sm_intr.level_index = idx; // to be returned to ARM on complete + sm_intr_master.vector = mailbox.intr.vector[idx]; + sm_intr_master.level_index = idx; // to be returned to ARM on complete - sm_data_master_state = (statemachine_state_func) &sm_intr_start; + sm_data_master_state = (statemachine_state_func) &sm_intr_master_start; } } } else { @@ -224,7 +224,7 @@ void main(void) { // by ARM, if access to "active" register triggers INTR. sm_arb.request_mask |= mailbox.intr.priority_arbitration_bit; // sm_arb_worker() evaluates this, extern Arbitrator raises Grant, - // vector of GRANted level is transfered with statemachine sm_intr + // vector of GRANted level is transfered with statemachine sm_intr_master // Atomically change state in a device's associates interrupt register. // The Interupt Register is set immediately. No wait for INTR GRANT, diff --git a/10.01_base/2_src/pru1/pru1_statemachine_slave.c b/10.01_base/2_src/pru1/pru1_statemachine_data_slave.c similarity index 100% rename from 10.01_base/2_src/pru1/pru1_statemachine_slave.c rename to 10.01_base/2_src/pru1/pru1_statemachine_data_slave.c diff --git a/10.01_base/2_src/pru1/pru1_statemachine_slave.h b/10.01_base/2_src/pru1/pru1_statemachine_data_slave.h similarity index 100% rename from 10.01_base/2_src/pru1/pru1_statemachine_slave.h rename to 10.01_base/2_src/pru1/pru1_statemachine_data_slave.h diff --git a/10.01_base/2_src/pru1/pru1_statemachine_intr.c b/10.01_base/2_src/pru1/pru1_statemachine_intr_master.c similarity index 75% rename from 10.01_base/2_src/pru1/pru1_statemachine_intr.c rename to 10.01_base/2_src/pru1/pru1_statemachine_intr_master.c index 55edfe6..92f9fd4 100644 --- a/10.01_base/2_src/pru1/pru1_statemachine_intr.c +++ b/10.01_base/2_src/pru1/pru1_statemachine_intr_master.c @@ -1,6 +1,6 @@ -/* pru1_statemachine_intr.c: state machine to transfer an interrupt vector +/* pru1_statemachine_intr_master.c: device transmits an interrupt vector after arb - Copyright (c) 2018, Joerg Hoppe + Copyright (c) 2018-2019, Joerg Hoppe j_hoppe@t-online.de, www.retrocmp.com Permission is hereby granted, free of charge, to any person obtaining a @@ -41,29 +41,29 @@ #include "pru1_utils.h" //#include "pru1_statemachine_arbitration.h" -#include "pru1_statemachine_intr.h" +#include "pru1_statemachine_intr_master.h" // states -statemachine_intr_t sm_intr; +statemachine_intr_master_t sm_intr_master; // forwards -static statemachine_state_func sm_intr_state_1(void); -static statemachine_state_func sm_intr_state_2(void); +static statemachine_state_func sm_intr_master_state_1(void); +static statemachine_state_func sm_intr_master_state_2(void); // Wait for BBSY deasserted, then assert, SACK already held asserted -statemachine_state_func sm_intr_start() { +statemachine_state_func sm_intr_master_start() { // Do not wait for BBSY here, this is part of Arbitration // if (buslatches_getbyte(1) & BIT(6)) - // return (statemachine_state_func) &sm_intr_start; // wait + // return (statemachine_state_func) &sm_intr_master_start; // wait buslatches_setbits(1, BIT(6), BIT(6)); // assert BBSY - return (statemachine_state_func) &sm_intr_state_1; + return (statemachine_state_func) &sm_intr_master_state_1; } // place vector onto data, then set INTR -static statemachine_state_func sm_intr_state_1() { +static statemachine_state_func sm_intr_master_state_1() { - buslatches_setbyte(5, sm_intr.vector & 0xff); // DATA[0..7] = latch[5] - buslatches_setbyte(6, sm_intr.vector >> 8); // DATA[8..15] = latch[6] + buslatches_setbyte(5, sm_intr_master.vector & 0xff); // DATA[0..7] = latch[5] + buslatches_setbyte(6, sm_intr_master.vector >> 8); // DATA[8..15] = latch[6] // set INTR buslatches_setbits(7, BIT(0), BIT(0)); // INTR = latch 7, bit 0 @@ -74,20 +74,20 @@ static statemachine_state_func sm_intr_state_1() { buslatches_setbits(1, BIT(5), 0); // SACK = latch[1], bit 5 // wait for processor to accept vector (no timeout?) - return (statemachine_state_func) &sm_intr_state_2; + return (statemachine_state_func) &sm_intr_master_state_2; } // wait for SSYN -static statemachine_state_func sm_intr_state_2() { +static statemachine_state_func sm_intr_master_state_2() { if (!(buslatches_getbyte(4) & BIT(5))) - return (statemachine_state_func) &sm_intr_state_2; // wait + return (statemachine_state_func) &sm_intr_master_state_2; // wait // received SSYN // Complete and signal this INTR transaction only after ARM has processed the previous event. // INTR may come faster than ARM Linux can process, // especially if Arbitrator grants INTRs of multiple levels almost simultaneaously in parallel. if (mailbox.events.event_intr) - return (statemachine_state_func) &sm_intr_state_2; // wait + return (statemachine_state_func) &sm_intr_master_state_2; // wait // remove vector buslatches_setbyte(5, 0); // DATA[0..7] = latch[5] @@ -105,7 +105,7 @@ static statemachine_state_func sm_intr_state_2() { // signal to ARM which INTR was completed // change mailbox only after ARM has ack'ed mailbox.events.event_intr - mailbox.events.event_intr_level_index = sm_intr.level_index; + mailbox.events.event_intr_level_index = sm_intr_master.level_index; mailbox.events.event_intr = 1; // ARM is clearing this, before requesting new interrupt of same level // so no concurrent ARP+PRU access diff --git a/10.01_base/2_src/pru1/pru1_statemachine_intr.h b/10.01_base/2_src/pru1/pru1_statemachine_intr_master.h similarity index 80% rename from 10.01_base/2_src/pru1/pru1_statemachine_intr.h rename to 10.01_base/2_src/pru1/pru1_statemachine_intr_master.h index 3361621..f3f107f 100644 --- a/10.01_base/2_src/pru1/pru1_statemachine_intr.h +++ b/10.01_base/2_src/pru1/pru1_statemachine_intr_master.h @@ -1,6 +1,6 @@ -/* pru1_statemachine_intr.h: state machine to transfer an interrupt vector +/* pru1_statemachine_intr_master.h: device transmits an interrupt vector after arb - Copyright (c) 2018, Joerg Hoppe + Copyright (c) 2018-2019, Joerg Hoppe j_hoppe@t-online.de, www.retrocmp.com Permission is hereby granted, free of charge, to any person obtaining a @@ -24,18 +24,18 @@ 29-jun-2019 JH rework: state returns ptr to next state func 12-nov-2018 JH entered beta phase */ -#ifndef _PRU1_STATEMACHINE_INTR_H_ -#define _PRU1_STATEMACHINE_INTR_H_ +#ifndef _PRU1_STATEMACHINE_INTR_MASTER_H_ +#define _PRU1_STATEMACHINE_INTR_MASTER_H_ #include "pru1_utils.h" // statemachine_state_func typedef struct { uint16_t vector; // interrupt vector to transfer uint8_t level_index; // 0..3 = BR..BR7. to be returned to ARM on complete -} statemachine_intr_t; +} statemachine_intr_master_t; -extern statemachine_intr_t sm_intr; +extern statemachine_intr_master_t sm_intr_master; -statemachine_state_func sm_intr_start(void); +statemachine_state_func sm_intr_master_start(void); #endif