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mirror of https://github.com/livingcomputermuseum/UniBone.git synced 2026-04-29 13:13:35 +00:00

Connected CPU20 to INTR,INIT,Power ON/OFF.

PRU INTR routing still do to.
This commit is contained in:
Joerg Hoppe
2019-08-25 09:17:28 +02:00
parent f938c8ba8a
commit ea91180f28
9 changed files with 137 additions and 59 deletions

View File

@@ -94,14 +94,14 @@ char *unibus_c::control2text(uint8_t control) {
return buffer;
}
/* pulse INIT cycle for 50 milliseconds ... source?
/* pulse INIT cycle for some milliseconds
*/
void unibus_c::init(void) {
void unibus_c::init(unsigned pulsewidth_ms) {
timeout_c timeout;
mailbox->initializationsignal.id = INITIALIZATIONSIGNAL_INIT;
mailbox->initializationsignal.val = 1;
mailbox_execute(ARM2PRU_INITALIZATIONSIGNAL_SET);
timeout.wait_ms(50);
timeout.wait_ms(pulsewidth_ms);
mailbox->initializationsignal.id = INITIALIZATIONSIGNAL_INIT;
mailbox->initializationsignal.val = 0;
mailbox_execute(ARM2PRU_INITALIZATIONSIGNAL_SET);

View File

@@ -85,7 +85,7 @@ public:
static char *control2text(uint8_t control);
static char *data2text(unsigned val);
void init(void);
void init(unsigned pulsewidth_ms);
static void set_arbitration_mode(enum arbitration_mode_enum arbitration_mode);
void powercycle(void);