mirror of
https://github.com/livingcomputermuseum/UniBone.git
synced 2026-01-28 20:51:08 +00:00
Connected CPU20 to INTR,INIT,Power ON/OFF.
PRU INTR routing still do to.
This commit is contained in:
@@ -84,33 +84,6 @@ bool cpu_c::on_param_changed(parameter_c *param) {
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return device_c::on_param_changed(param); // more actions (for enable)
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}
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extern "C" {
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// functions to be used by Angelos CPU emulator
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// Result: 1 = OK, 0 = bus timeout
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int cpu_dato(unsigned addr, unsigned data) {
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uint16_t wordbuffer = (uint16_t) data;
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unibusadapter->cpu_DATA_transfer(the_cpu->data_transfer_request, UNIBUS_CONTROL_DATO, addr, &wordbuffer);
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return the_cpu->data_transfer_request.success ;
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}
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int cpu_datob(unsigned addr, unsigned data) {
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uint16_t wordbuffer = (uint16_t) data;
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// TODO DATOB als 1 byte-DMA !
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unibusadapter->cpu_DATA_transfer(the_cpu->data_transfer_request, UNIBUS_CONTROL_DATOB, addr, &wordbuffer);
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return the_cpu->data_transfer_request.success ;
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}
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int cpu_dati(unsigned addr, unsigned *data) {
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uint16_t wordbuffer;
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unibusadapter->cpu_DATA_transfer(the_cpu->data_transfer_request, UNIBUS_CONTROL_DATI, addr, &wordbuffer);
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*data = wordbuffer;
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// printf("DATI; ba=%o, data=%o\n", addr, *data) ;
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return the_cpu->data_transfer_request.success ;
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}
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}
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// background worker.
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void cpu_c::worker(unsigned instance) {
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UNUSED(instance); // only one
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@@ -128,27 +101,27 @@ void cpu_c::worker(unsigned instance) {
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if (runmode.value != (ka11.state != 0))
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ka11.state = runmode.value;
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condstep(&ka11);
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ka11_condstep(&ka11);
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if (runmode.value != (ka11.state != 0))
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runmode.value = ka11.state != 0;
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if (init.value) {
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// user wants CPU reset
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reset(&ka11);
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ka11_reset(&ka11);
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init.value = 0;
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}
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#if 0
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if (runmode.value) {
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// simulate a fetch
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nxm = !cpu_dati(pc, &opcode);
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nxm = !unibone_dati(pc, &opcode);
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if (nxm) {
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printf("Bus timeout at PC = %06o. HALT.\n", pc);
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runmode.value = false;
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}
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pc = (pc + 2) % 0100; // loop around
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// set LEDS
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nxm = !cpu_dato(dr, pc & 0xf);
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nxm = !unibone_dato(dr, pc & 0xf);
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if (nxm) {
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printf("Bus timeout at DR = %06o. HALT.\n", dr);
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runmode.value = false;
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@@ -173,17 +146,76 @@ void cpu_c::on_after_register_access(unibusdevice_register_t *device_reg,
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UNUSED(unibus_control);
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}
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// TODO
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void cpu_c::on_power_changed(void) {
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if (power_down) { // power-on defaults
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INFO("CPU: ACLO failed");
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ka11_pwrdown(&the_cpu->ka11);
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// ACLO failed.
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// CPU traps to vector 24 and has 2ms time to execute code
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} else {
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INFO("CPU: DCLO restored");
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ka11_pwrup(&the_cpu->ka11);
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// DCLO restored
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// CPU loads PC and PSW from vector 24
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}
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}
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// UNIBUS INIT: clear all registers
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void cpu_c::on_init_changed(void) {
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// write all registers to "reset-values"
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if (init_asserted) {
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reset_unibus_registers();
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INFO("cpu::on_init()");
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}
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// a CPU does not react to INIT ... else its own RESET would reset it.
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}
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// TODO
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// CPU received interrupt vector from UNIBUS
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void cpu_c::on_interrupt(uint16_t vector) {
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// CPU sequence:
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// push PSW to stack
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// push PC to stack
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// PC := *vector
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// PSW := *(vector+2)
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ka11_setintr(&the_cpu->ka11, vector);
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}
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extern "C" {
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// functions to be used by Angelos CPU emulator
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// Result: 1 = OK, 0 = bus timeout
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int unibone_dato(unsigned addr, unsigned data) {
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uint16_t wordbuffer = (uint16_t) data;
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unibusadapter->cpu_DATA_transfer(the_cpu->data_transfer_request, UNIBUS_CONTROL_DATO, addr,
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&wordbuffer);
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return the_cpu->data_transfer_request.success;
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}
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int unibone_datob(unsigned addr, unsigned data) {
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uint16_t wordbuffer = (uint16_t) data;
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// TODO DATOB als 1 byte-DMA !
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unibusadapter->cpu_DATA_transfer(the_cpu->data_transfer_request, UNIBUS_CONTROL_DATOB, addr,
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&wordbuffer);
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return the_cpu->data_transfer_request.success;
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}
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int unibone_dati(unsigned addr, unsigned *data) {
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uint16_t wordbuffer;
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unibusadapter->cpu_DATA_transfer(the_cpu->data_transfer_request, UNIBUS_CONTROL_DATI, addr,
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&wordbuffer);
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*data = wordbuffer;
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// printf("DATI; ba=%o, data=%o\n", addr, *data) ;
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return the_cpu->data_transfer_request.success;
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}
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// CPU has changed the arbitration level, just forward
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void unibone_prioritylevelchange(uint8_t level) {
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mailbox->arbitrator.cpu_priority_level = level;
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}
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// TODO
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// CPU executes RESET opcode -> pulses INIT line
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void unibone_bus_init(unsigned pulsewidth_ms) {
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unibus->init(pulsewidth_ms);
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}
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}
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