DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP

10.01_base/2_src/shared/mailbox.h

@@ -43,14 +43,15 @@
 #define ARM2PRU_INITALIZATIONSIGNAL_SET		9 	// set an ACL=/DCLO/INIT signal
 #define ARM2PRU_ARB_MODE_NONE		11               // DMA without NPR/NPG/SACK arbitration
 #define ARM2PRU_ARB_MODE_CLIENT		12               // DMA with arbitration by external Arbitrator
-#define ARM2PRU_ARB_MODE_MASTER		13               // DMA as Arbitrator
 #define ARM2PRU_DMA		14               // DMA with selected arbitration
-#define PRU2ARM_DMA_CPU_TRANSFER_BLOCKED 15 // possible result of ARM2PRU_DMA
+//#define PRU2ARM_DMA_CPU_TRANSFER_BLOCKED 15 // possible result of ARM2PRU_DMA
 #define ARM2PRU_INTR		16               // INTR with arbitration by external Arbitrator
 #define ARM2PRU_INTR_CANCEL		17               // clear INTR which has been requested
 #define ARM2PRU_CPU_ENABLE		18	// siwtch CPU master side functions ON/OFF
 #define ARM2PRU_DDR_FILL_PATTERN	19	// fill DDR with test pattern
 #define ARM2PRU_DDR_SLAVE_MEMORY	20	// use DDR as UNIBUS slave memory
+#define ARM2PRU_ARB_GRANT_INTR_REQUESTS	21 // emulated CPU answers device requests
+
 
 // signal IDs for ARM2PRU_INITALIZATIONSIGNAL_* 
 // states of initialization section lines. Bitmask = latch[7]
@@ -123,17 +124,12 @@ typedef struct {
 
 // data for bus arbitrator 
 typedef struct {
-	// arbitrator.device_BBSY indicates a device wants or has acquired the UNIBUS.
-	// CPU DATA transfer must be delayed until device_BBSY == 0
-	// set when arbitration logic detects SACK!
-	uint8_t device_BBSY;
+	// ifs = Interrupt Fielding Processor
+	uint8_t ifs_priority_level; // Priority level of CPU, visible in PSW. 7,6,5,4 <4.
 
-	// Command by ARM on DMA start: DATA transfer as CPU, else as device	
-	uint8_t cpu_BBSY;
+	uint8_t	ifs_intr_arbitration_pending ; // produce GRANTS from requests
 
-	uint8_t cpu_priority_level; // Priority level of CPU, visible in PSW. 7,6,5,4 <4.
-
-	uint8_t _dummy1;	// keep 32 bit borders
+	uint8_t _dummy[2];	// keep 32 bit borders
 
 } mailbox_arbitrator_t;
 
@@ -141,11 +137,13 @@ typedef struct {
 typedef struct {
 	// take care of 32 bit word borders for struct members
 	uint8_t cur_status; // 0 = idle, 1 = DMA running, 2 = timeout error
-	// 0x80: set on start to indicate CPU access
 
 	uint8_t control; // cycle to perform: only DATO, DATI allowed
 	uint16_t wordcount; // # of remaining words transmit/receive, static
 	// ---dword---
+	uint8_t	cpu_access ; // 0 for device DMA, 1 for emulated CPU
+	uint8_t	dummy[3] ; 
+	// ---dword---
 	uint32_t cur_addr; // current address in transfer, if timeout: offending address.
 	// if complete: last address accessed.
 	uint32_t startaddr; // address of 1st word to transfer
@@ -213,8 +211,8 @@ typedef struct {
 	 */
 	uint8_t signaled; //  PRU->ARM
 	uint8_t acked; // ARM->PRU
-	uint8_t cpu_transfer; // 1: ARM must process DMA as completed cpu DATA transfer
-	uint8_t _dummy2;
+//int8_t cpu_transfer; // 1: ARM must process DMA as completed cpu DATA transfer
+	uint8_t _dummy2[2];
 } mailbox_event_dma_t;
 
 // INTR raised by device

10.01_base/2_src/shared/unibus.h

@@ -39,7 +39,8 @@
 #define UNIBUS_CONTROL_DATO	0x02 // 16 bit word from master to slave
 #define UNIBUS_CONTROL_DATOB	0x03 // 8 bit byte  from master to slave
 // data<15:8> for a00 = 1, data<7:0> for a00 = 0
-#define UNIBUS_CONTROL_ISDATO(c) (!!((c) & 0x02)) // check for DATO/B
+#define UNIBUS_CONTROL_IS_DATI(c) (!((c) & 0x02)) // check for DATI/P
+#define UNIBUS_CONTROL_IS_DATO(c) (!!((c) & 0x02)) // check for DATO/B
 
 #define UNIBUS_TIMEOUTVAL	0xffffffff // EXAM result for bus timeout
 
@@ -66,17 +67,16 @@ class intr_request_c;
 
 class unibus_c: public logsource_c {
 public:
-	enum arbitration_mode_enum {
-		ARBITRATION_MODE_NONE = 0,	// no BR*/BG*, NR/NPG SACK protocoll
-		ARBITRATION_MODE_CLIENT = 1,	// external Arbitrator (running PDP-11 CPU) required
-		ARBITRATION_MODE_MASTER = 2	// implmenet Arbitrator
-	// with or without physical CPU for arbitration
-	};
 
 private:
 
 	timeout_c timeout;
 
+	// false: no running CPU on UNIBUS (physical or emulated)
+	// 	devices do DMA without NPR/NPG protocol
+	// true:  active CPU. devcies pus perform Request/Grant/SACK protocoll
+	bool arbitrator_active;
+
 public:
 
 	unibus_c();
@@ -86,7 +86,10 @@ public:
 	static char *data2text(unsigned val);
 
 	void init(unsigned pulsewidth_ms);
-	static void set_arbitration_mode(enum arbitration_mode_enum arbitration_mode);
+
+	void set_arbitrator_active(bool active);
+
+	bool get_arbitrator_active(void);
 
 	void powercycle(void);
 
@@ -94,24 +97,23 @@ public:
 	dma_request_c *dma_request;
 	//intr_request_c *intr_request;
 
-	bool dma(enum unibus_c::arbitration_mode_enum arbitration_mode, bool blocking, uint8_t control,
-			uint32_t startaddr, uint16_t *buffer, unsigned wordcount);
+	bool dma(bool blocking,
+			uint8_t control, uint32_t startaddr, uint16_t *buffer, unsigned wordcount);
 
-	void mem_read(enum unibus_c::arbitration_mode_enum arbitration_mode, uint16_t *words,
+	void mem_read(uint16_t *words,
 			uint32_t unibus_start_addr, uint32_t unibus_end_addr, bool *timeout);
-	void mem_write(enum unibus_c::arbitration_mode_enum arbitration_mode, uint16_t *words,
+	void mem_write(uint16_t *words,
 			unsigned unibus_start_addr, unsigned unibus_end_addr, bool *timeout);
 
-	void mem_access_random(enum unibus_c::arbitration_mode_enum arbitration_mode,
+	void mem_access_random(
 			uint8_t unibus_control, uint16_t *words, uint32_t unibus_start_addr,
 			uint32_t unibus_end_addr, bool *timeout, uint32_t *block_counter);
 
-	uint32_t test_sizer(enum unibus_c::arbitration_mode_enum arbitration_mode);
+	uint32_t test_sizer(void);
 
 	uint16_t testwords[UNIBUS_WORDCOUNT];
 
-	void test_mem(enum unibus_c::arbitration_mode_enum arbitration_mode, uint32_t start_addr,
-			uint32_t end_addr, unsigned mode);
+	void test_mem(uint32_t start_addr,	uint32_t end_addr, unsigned mode);
 
 };