github.com/livingcomputermuseum.UniBone
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3 Commits

Author SHA1 Message Date
Joerg Hoppe
f314317e2a DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP 2019-10-04 12:45:26 +02:00
Josh Dersch
6f1b476716 Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait). 
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
 2019-08-16 02:23:32 +02:00
Joerg Hoppe
10cf1598f1 Big summer rework: 
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
 2019-08-02 20:10:48 +02:00