github.com/livingcomputermuseum.UniBone
1
0
Fork 0
mirror of https://github.com/livingcomputermuseum/UniBone.git synced 2026-01-31 05:42:56 +00:00
Code Issues Releases Wiki Activity
68 Commits 1 Branch 0 Tags
30df58f42c8e323b93abb8b4b66bd569a0a2ddbc
Commit Graph

3 Commits

Author SHA1 Message Date
Joerg Hoppe
3d1d9d3cf6 ACLO/DCLO/INIT moved from PRU to ARM 
INTR/DMA request params linked to device params on change
 2019-08-19 13:12:42 +02:00
Josh Dersch
6f1b476716 Cleaned up signaling of DMA/INTR completion (using pthread_cond_wait). 
Tweaked MSYN timeout value from 350ns to 400ns to compensate for timing changes
with latest PRU code -- MSCP works reliably on PDP-11/84 again.
 2019-08-16 02:23:32 +02:00
Joerg Hoppe
10cf1598f1 Big summer rework: 
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
 2019-08-02 20:10:48 +02:00