github.com/livingcomputermuseum.UniBone
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Commit Graph

9 Commits

Author SHA1 Message Date
Joerg Hoppe
f314317e2a DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP 2019-10-04 12:45:26 +02:00
Joerg Hoppe
b9d28d73c4 Start MSCP test, KW11 without "line monitor bit clear" 2019-09-19 12:58:38 +02:00
Joerg Hoppe
92714c1ebe Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11. 
Also MSCP IOX.
 2019-09-02 15:46:54 +02:00
Joerg Hoppe
cc42d60409 type in dir name 2019-09-02 15:37:29 +02:00
Joerg Hoppe
fa454f646c added listing for easy loading 2019-08-19 13:26:22 +02:00
Joerg Hoppe
e2229871de PDP-11 test program for concurrent INTR/DMA 
Serial, Clock, RL02, RK05, MSCP
 2019-08-19 12:57:18 +02:00
Joerg Hoppe
855f1a6cee GitHub usability 2019-08-05 09:28:07 +02:00
Joerg Hoppe
974aeed8eb Big summer rework: 
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
 2019-08-02 16:45:54 +02:00
Joerg Hoppe
2530d9cbb5 Initial 2019-04-05 11:30:26 +02:00