github.com/livingcomputermuseum.UniBone
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10 Commits

Author SHA1 Message Date
Joerg Hoppe
f314317e2a DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP 2019-10-04 12:45:26 +02:00
Joerg Hoppe
cef911f70b Better integration of CPU20 into UniBone framework 2019-09-26 07:42:59 +02:00
Joerg Hoppe
d058310e53 CPU20 power start/power fail 2019-08-27 19:05:41 +02:00
Joerg Hoppe
ea91180f28 Connected CPU20 to INTR,INIT,Power ON/OFF. 
PRU INTR routing still do to.
 2019-08-25 09:17:28 +02:00
Joerg Hoppe
8ff33a0be1 Infrastructure for emulated CPUs: Bus arbitrator, Interrupt fielding processor 2019-08-16 19:04:12 +02:00
Joerg Hoppe
974aeed8eb Big summer rework: 
Interrupt and DMA system now handles multiple levels and multiple devices in parallel
Interrupt Register changes synced with INTR transaction
DL11 and KW11 clock pass the ZDLDI0 diagnostic.
Devices can now be enabled and disabled individually.
 2019-08-02 16:45:54 +02:00
Joerg Hoppe
04869fb46f PRU statemachines easier to control from main thread 2019-07-02 07:09:01 +02:00
Joerg Hoppe
4062386b97 Multiple parallel instances of device::worker() possible 2019-06-23 12:00:13 +02:00
Joerg Hoppe
3952cb93b0 Enable devices individually over param "enabled" 
UNIBUS addr, intr vector, level setable
 2019-06-20 21:58:04 +02:00
Joerg Hoppe
2530d9cbb5 Initial 2019-04-05 11:30:26 +02:00