github.com/livingcomputermuseum.UniBone
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Commit Graph

9 Commits

Author SHA1 Message Date
Joerg Hoppe
10f0540c4a CPU20 WAIT 2019-10-08 15:05:37 +02:00
Joerg Hoppe
3f71d6f093 CPU20 UNIBUS Interrupt, Experiments to probe UNIBUS arbitrator 2019-10-08 12:36:36 +02:00
Joerg Hoppe
f314317e2a DMA/INTR arbitration rework, emulated CPU20 with DMA&INTR, runs XXDP 2019-10-04 12:45:26 +02:00
Joerg Hoppe
cef911f70b Better integration of CPU20 into UniBone framework 2019-09-26 07:42:59 +02:00
Joerg Hoppe
92714c1ebe Test "MultiArb": parallel INTR and DMA of DL11,RL11,RK11. 
Also MSCP IOX.
 2019-09-02 15:46:54 +02:00
Joerg Hoppe
6f2adbd216 levelchange(PSW) on RTI 2019-08-27 13:31:37 +02:00
Joerg Hoppe
ea91180f28 Connected CPU20 to INTR,INIT,Power ON/OFF. 
PRU INTR routing still do to.
 2019-08-25 09:17:28 +02:00
Joerg Hoppe
3952cb93b0 Enable devices individually over param "enabled" 
UNIBUS addr, intr vector, level setable
 2019-06-20 21:58:04 +02:00
Joerg Hoppe
2530d9cbb5 Initial 2019-04-05 11:30:26 +02:00