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974aeed8eb
Interrupt and DMA system now handles multiple levels and multiple devices in parallel Interrupt Register changes synced with INTR transaction DL11 and KW11 clock pass the ZDLDI0 diagnostic. Devices can now be enabled and disabled individually.
140 lines
4.4 KiB
C
140 lines
4.4 KiB
C
/* pru1_buslatches.h: PRU function to access to multiplex signal registers
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Copyright (c) 2018, Joerg Hoppe
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j_hoppe@t-online.de, www.retrocmp.com
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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12-nov-2018 JH entered beta phase
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*/
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#ifndef _BUSLATCH_H_
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#define _BUSLATCH_H_
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#include <stdint.h>
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#include "tuning.h"
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#include "pru_pru_mailbox.h"
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typedef struct {
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uint8_t cur_reg_val[8]; // content of output latches
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// # of bits in each register connected bidirectionally to UNIBUS
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// ( for example, LTC ignored)
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uint8_t bidi_bitwidth[8]; // # of bits in each
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// uint32_t bidi_bitmask[8] ; // mask with valid bits
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// uint8_t cur_reg_sel; // state of SEL A0,A1,A2 = PRU1_<8:10>
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// uint32_t cur_reg_write ; // state of REG_WRITE= PRU1_11>
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} buslatches_t;
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#ifndef _BUSLATCH_C_
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extern buslatches_t buslatches;
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#endif
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/*
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* Read timing:
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* 5ns on PRU to ouptput 0/1 level
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* 10ns until register select is stable (includes jitter on addr0:2)
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* 10 ns for 74LVTH to switch
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* 5ns for changing edge voltage level of DATIN signals
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* 5ns for PRU to sync with DATIN signals
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*
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* Timing verified with buslatches_test().
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*
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* With optimized circuitry (PCB 2018-12, adapted terminators, 74AHC138):
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* BBB can reach __delay_cycles(8)
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* BBG can reach *ALMOST* __delay_cycles(9)
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* */
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#define buslatches_getbyte(reg_sel) ( \
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( __R30 = ((reg_sel) << 8) | (1 << 11), \
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__delay_cycles(BUSLATCHES_GETBYTE_DELAY) \
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), \
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(__R31 & 0xff) \
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)
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// identify register which must be set byte-wise
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#define BUSLATCHES_REG_IS_BYTE(reg_sel) ( \
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((reg_sel) == 2) || ((reg_sel) == 3) || ((reg_sel) == 5) || ((reg_sel) == 6) \
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)
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/*******************************************************************************
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Timing write latches 74xx377
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1 char = 5ns
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lower letter = program event
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Upper letter = circuit event
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Circuit timing 74HCT377: (74LS a few percent faster)
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---------------------------------------------------
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Reference = Clock L->H = E
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A-E = Setup E* = 22 ns (typ. 12)
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C-E = Setup Data = 12 ns (typ. 4)
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D-E = pulsewidth = 20ns (typ. 8)
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E-B = setup E* = 22 ns (typ 12) deselect
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a A b B
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(A-B)Select E* ------______--
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c C
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(C) Data XXXXXXXX--XXXX
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dD eE
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(D+E) Strobe CP ---____---
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=> ac -> d = 10ns (minimal)
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d -> be = 15ns
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Delay program-circuit
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a-A: 5 + 10 ns (PRU + 3:8 74ac138)
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b-B = a-A
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c-D: 25ns (pru1_buslatches_pru0_datout.asmsrc)
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d-D: 5ns
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e-E: 5ns
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*******************************************************************************/
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#define buslatches_setbits(reg_sel,bitmask,val) do { \
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/* merge new value with existing latch content */\
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buslatches_setbits_helper( \
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/*val=*/(buslatches.cur_reg_val[reg_sel] & ~(bitmask)) | ((val) & (bitmask)), \
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reg_sel, &buslatches.cur_reg_val[reg_sel] ) ; \
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} while(0)
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void buslatches_setbits_helper(uint32_t val /*R14*/, uint32_t reg_sel /* R15 */,
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uint8_t *cur_reg_val /* R16 */);
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// set a register as byte.
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// no value caching, so register may never be accessed bitwise
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// only to be used for 2 (addr0..7), 3 (adr 8..15), 5 (data0..7), 6(data 8..15)
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#define buslatches_setbyte(reg_sel,val) do { \
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buslatches_setbyte_helper(val,reg_sel) ; \
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} while(0)
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void buslatches_setbyte_helper(uint32_t val /*R14*/, uint32_t reg_sel /* R15 */);
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void buslatches_reset(void);
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void buslatches_powercycle(void);
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void buslatches_exerciser(void);
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void buslatches_test(uint8_t a, uint8_t b, uint8_t c, uint8_t d);
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#endif
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