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97 lines
3.1 KiB
C
97 lines
3.1 KiB
C
/* pru1_statemachine_intr_slave.c: CPU receives interrupt vector
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Copyright (c) 2019, Joerg Hoppe
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j_hoppe@t-online.de, www.retrocmp.com
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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26-aug-2019 JH start
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State machines for CPU emulation to receive INTR vector placed onto bus by device.
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All references "PDP11BUS handbook 1979"
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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//#include "devices.h"
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#include "mailbox.h"
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#include "pru1_buslatches.h"
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#include "pru1_utils.h"
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#include "pru1_statemachine_intr_slave.h"
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// states
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statemachine_intr_slave_t sm_intr_slave;
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// forwards
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static statemachine_state_func sm_intr_slave_state_1(void);
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// WAIT for INTR.
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// Master holds BBSY and SACK
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statemachine_state_func sm_intr_slave_start() {
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if ((buslatches_getbyte(7) & BIT(0)) == 0)
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return NULL ; // INTR still deasserted
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// device has put vector onto DATA lines, fetch after 150ns
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__delay_cycles(NANOSECS(150));
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uint8_t latch5val = buslatches_getbyte(5) ;// DATA[0..7] = latch[5]
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uint8_t latch6val = buslatches_getbyte(6) ; // DATA[8..15] = latch[6]
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// set SSYN = latch[4], bit 5
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buslatches_setbits(4, BIT(5), BIT(5));
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// mark priority level as invalid, block more BG GRANTS until PSW fetched
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mailbox.arbitrator.ifs_priority_level = CPU_PRIORITY_LEVEL_FETCHING ;
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// signal ARM, wait for event to be processed
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mailbox.events.intr_slave.vector = (uint16_t) latch6val << 8 | latch5val ;
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EVENT_SIGNAL(mailbox,intr_slave) ; // signal to ARM
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PRU2ARM_INTERRUPT ;
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// wait until ARM acked
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return (statemachine_state_func) &sm_intr_slave_state_1;
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}
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static statemachine_state_func sm_intr_slave_state_1() {
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// wait until ARM acked the INTR vector
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// event_intr_slave ACK is delayed until the CPU
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// CPU has read the new PSW and new abritration level
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// event_intr_slave co solved by
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if (! EVENT_IS_ACKED(mailbox,intr_slave))
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return (statemachine_state_func) &sm_intr_slave_state_1;
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// wait if INTR still active
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if (buslatches_getbyte(7) & BIT(0)) // check INTR
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return (statemachine_state_func) &sm_intr_slave_state_1;
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// clear SSYN = latch[4], bit 5
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buslatches_setbits(4, BIT(5), 0);
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// now CPU may do DATI to fetch PC and PSW
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return NULL; // ready
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}
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