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livingcomputermuseum.UniBone/10.01_base/3_test/multiarb/ma_rl.mac
2019-09-02 15:37:29 +02:00

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.title ma_rl - RL11/RL01/2 test driver
; RL11 DMA is generated by reading cylinder 0, head0, sector 0
rlvect = 160 ; vector of RL11 controller
rlbase = 774400 ; base addr of RL11 controller
rllabl = 'L ; label char
; --- ISRs, increment Interrupt FLags
rliflg: .word 1 ; Interrupt flags
rlbuff: .blkw 2*400+1 ; data buffer: 2 sector = 256 words
rlecnt: .word 1 ; event counter
rlisr:
inc rliflg ; set ISR flag
rti
; --- Initialize device after RESET
rlinit:
clr rlecnt
return
; --- Restart new DMA transmission
rlgo:
mov #rlbase,r1 ; r1 = controller base address
; sequence from boot loader 23-751A9, lot of testing
; 1. get status
mov #013,4(r1) ; DA subcmd reset+getstatus
mov #4,(r1) ; CSR do "GET STATUS"
1$: tstb (r1) ; test for ready
bpl 1$ ; wait
; 2. read current track
mov #10,(r1) ; CSR read header cmd
2$: tstb (r1) ; test for ready
bpl 2$ ; wait
; 3. seek
mov 6(r1),r2 ; MP retrieve cyl/head/sector
bic #77,r2 ; set sector to zero
inc r2 ; set seek flag, head 0, seek to cyl 0
mov r2,4(r1) ; DA for seek
mov #6,(r1) ; CSR seek cmd
3$: tstb (r1) ; test for ready
bpl 3$ ; wait
; 4. read sector 0+1 and interrupt
mov #rlbuff,2(r1) ; BA bus address of DMA
clr 4(r1) ; DA select cyl0/head0/sector0
mov #-512.,6(r1) ; MP set word count
mov #100+14,(r1) ; CSR read data cmd with Interrupt Enable
inc rlecnt ; register as event
return