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2189e264c35084548c19fdeff886a659b3ddfc68
livingcomputermuseum.UniBone/10.01_base/4_deploy/pru1.map
Joerg Hoppe 2530d9cbb5 Initial
2019-04-05 11:30:26 +02:00

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******************************************************************************
PRU Linker Unix v2.3.1
******************************************************************************
>> Linked Sun Mar 31 20:55:40 2019
OUTPUT FILE NAME: </home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/pru1.out>
ENTRY POINT SYMBOL: "_c_int00_noinit_noargs" address: 00000000
MEMORY CONFIGURATION
name origin length used unused attr fill
---------------------- -------- --------- -------- -------- ---- --------
PAGE 0:
PRU_IMEM 00000000 00002000 00002000 00000000 RWIX
PAGE 1:
PRU_DMEM_0_1 00000000 00002000 0000013c 00001ec4 RWIX
PRU_DMEM_1_0 00002000 00002000 00001820 000007e0 RWIX
PAGE 2:
PRU_SHAREDMEM 00010000 00003000 00000424 00002bdc RWIX
PRU_INTC 00020000 00001504 00000000 00001504 RWIX
PRU_CFG 00026000 00000044 00000044 00000000 RWIX
PRU_UART 00028000 00000038 00000000 00000038 RWIX
PRU_IEP 0002e000 0000031c 00000000 0000031c RWIX
PRU_ECAP 00030000 00000060 00000000 00000060 RWIX
RSVD27 00032000 00000100 00000000 00000100 RWIX
RSVD21 00032400 00000100 00000000 00000100 RWIX
L3OCMC 40000000 00010000 00000000 00010000 RWIX
MCASP0_DMA 46000000 00000100 00000000 00000100 RWIX
UART1 48022000 00000088 00000000 00000088 RWIX
UART2 48024000 00000088 00000000 00000088 RWIX
I2C1 4802a000 000000d8 00000000 000000d8 RWIX
MCSPI0 48030000 000001a4 00000000 000001a4 RWIX
DMTIMER2 48040000 0000005c 00000000 0000005c RWIX
MMCHS0 48060000 00000300 00000000 00000300 RWIX
MBX0 480c8000 00000140 00000000 00000140 RWIX
SPINLOCK 480ca000 00000880 00000000 00000880 RWIX
I2C2 4819c000 000000d8 00000000 000000d8 RWIX
MCSPI1 481a0000 000001a4 00000000 000001a4 RWIX
DCAN0 481cc000 000001e8 00000000 000001e8 RWIX
DCAN1 481d0000 000001e8 00000000 000001e8 RWIX
PWMSS0 48300000 000002c4 00000000 000002c4 RWIX
PWMSS1 48302000 000002c4 00000000 000002c4 RWIX
PWMSS2 48304000 000002c4 00000000 000002c4 RWIX
RSVD13 48310000 00000100 00000000 00000100 RWIX
RSVD10 48318000 00000100 00000000 00000100 RWIX
TPCC 49000000 00001098 00000000 00001098 RWIX
GEMAC 4a100000 0000128c 00000000 0000128c RWIX
DDR 80000000 00000100 00000000 00000100 RWIX
SECTION ALLOCATION MAP
output attributes/
section page origin length input sections
-------- ---- ---------- ---------- ----------------
.text:_c_int00*
* 0 00000000 0000001c
00000000 0000001c rtspruv3_le.lib : boot.c.obj (.text:_c_int00_noinit_noargs)
.text 0 0000001c 00001fe4
0000001c 0000050c pru1_statemachine_dma.object (.text:sm_dma_state_1)
00000528 00000370 pru1_main.object (.text:main)
00000898 00000250 pru1_statemachine_slave.object (.text:sm_slave_state_1)
00000ae8 000001c8 pru1_statemachine_dma.object (.text:sm_dma_state_99)
00000cb0 0000015c pru1_statemachine_arbitration.object (.text:sm_arb_state_2)
00000e0c 00000130 pru1_buslatches.object (.text:buslatches_reset)
00000f3c 00000120 pru1_iopageregisters.object (.text:iopageregisters_write_b)
0000105c 0000011c pru1_statemachine_arbitration.object (.text:sm_arb_state_3)
00001178 00000100 pru1_buslatches.object (.text:buslatches_powercycle)
00001278 000000f4 pru1_statemachine_dma.object (.text:sm_dma_state_11)
0000136c 000000e8 pru1_iopageregisters.object (.text:iopageregisters_write_w)
00001454 000000e8 pru1_statemachine_dma.object (.text:sm_dma_state_21)
0000153c 000000e8 pru1_statemachine_intr.object (.text:sm_intr_state_2)
00001624 000000d8 pru1_statemachine_intr.object (.text:sm_intr_state_1)
000016fc 000000d4 pru1_iopageregisters.object (.text:iopageregisters_read)
000017d0 000000d4 pru1_statemachine_arbitration.object (.text:sm_arb_state_1)
000018a4 000000c4 pru1_statemachine_slave.object (.text:sm_slave_state_20)
00001968 000000ac pru1_statemachine_powercycle.object (.text:sm_powercycle_state_2)
00001a14 000000ac pru1_statemachine_powercycle.object (.text:sm_powercycle_state_3)
00001ac0 000000a8 pru1_statemachine_init.object (.text:sm_init_start)
00001b68 00000098 pru1_statemachine_powercycle.object (.text:sm_powercycle_state_1)
00001c00 0000008c pru1_statemachine_slave.object (.text:sm_slave_state_10)
00001c8c 00000080 pru1_statemachine_init.object (.text:sm_init_state_1)
00001d0c 00000080 pru1_statemachine_powercycle.object (.text:sm_powercycle_state_4)
00001d8c 00000074 pru1_statemachine_arbitration.object (.text:sm_arb_state_idle)
00001e00 00000060 pru1_statemachine_init.object (.text:do_event_initializationsignals)
00001e60 00000060 pru1_iopageregisters.object (.text:iopageregisters_init)
00001ec0 00000038 pru1_statemachine_dma.object (.text:sm_dma_start)
00001ef8 00000034 pru1_statemachine_slave.object (.text:sm_slave_state_99)
00001f2c 0000002c pru1_buslatches.object (.text:buslatches_test)
00001f58 0000002c pru1_ddrmem.object (.text:ddrmem_fill_pattern)
00001f84 00000014 pru1_statemachine_arbitration.object (.text:sm_arb_start)
00001f98 00000010 pru1_statemachine_intr.object (.text:sm_intr_start)
00001fa8 00000010 pru1_statemachine_powercycle.object (.text:sm_powercycle_start)
00001fb8 00000010 pru1_statemachine_slave.object (.text:sm_slave_start)
00001fc8 00000008 rtspruv3_le.lib : exit.c.obj (.text:abort)
00001fd0 00000008 : exit.c.obj (.text:loader_exit)
00001fd8 00000008 pru1_buslatches_pru0_datout.asmobject (.text)
00001fe0 00000008 pru1_statemachine_arbitration.object (.text:sm_arb_state_4)
00001fe8 00000008 pru1_statemachine_init.object (.text:sm_init_state_idle)
00001ff0 00000008 pru1_statemachine_intr.object (.text:sm_intr_state_idle)
00001ff8 00000008 pru1_statemachine_powercycle.object (.text:sm_powercycle_state_idle)
.stack 1 00000000 00000100 UNINITIALIZED
00000000 00000004 rtspruv3_le.lib : boot.c.obj (.stack)
00000004 000000fc --HOLE--
.bss 1 00000100 00000028 UNINITIALIZED
00000100 00000010 (.common:buslatches)
00000110 00000009 (.common:sm_dma)
00000119 00000004 (.common:timeout_target)
0000011d 00000003 (.common:sm_arb)
00000120 00000002 (.common:sm_init)
00000122 00000002 (.common:sm_intr)
00000124 00000002 (.common:sm_powercycle)
00000126 00000002 (.common:sm_slave)
.cinit 1 00000000 00000000 UNINITIALIZED
.resource_table
* 1 00000128 00000014
00000128 00000014 pru1_main.object (.resource_table:retain)
.deviceregisters_sec
* 1 00002000 00001820 UNINITIALIZED
00002000 00001820 pru1_iopageregisters.object (.deviceregisters_sec)
.mailbox_arm_sec
* 2 00010000 00000424 UNINITIALIZED
00010000 00000424 pru1_arm_mailbox.object (.mailbox_arm_sec)
.creg.PRU_CFG.noload.near
* 2 00026000 00000044 NOLOAD SECTION
00026000 00000044 pru1_buslatches.object (.creg.PRU_CFG.noload.near)
.creg.PRU_CFG.near
* 2 00026044 00000000 UNINITIALIZED
.creg.PRU_CFG.noload.far
* 2 00026044 00000000 NOLOAD SECTION
.creg.PRU_CFG.far
* 2 00026044 00000000 UNINITIALIZED
MODULE SUMMARY
Module code ro data rw data
------ ---- ------- -------
/home/joerg/retrocmp/dec/UniBone/10.01_base/4_deploy/
pru1_iopageregisters.object 828 0 6176
pru1_statemachine_dma.object 2280 0 9
pru1_arm_mailbox.object 0 0 1060
pru1_statemachine_slave.object 996 0 2
pru1_statemachine_arbitration.object 988 0 3
pru1_main.object 880 0 20
pru1_buslatches.object 604 0 84
pru1_statemachine_powercycle.object 648 0 2
pru1_statemachine_intr.object 472 0 2
pru1_statemachine_init.object 400 0 2
pru1_ddrmem.object 44 0 0
pru1_buslatches_pru0_datout.asmobject 8 0 0
pru1_utils.object 0 0 4
+--+---------------------------------------+------+---------+---------+
Total: 8148 0 7364
/home/joerg/retrocmp/dec/UniBone/91_3rd_party/pru-c-compile/ti-cgt-pru_2.3.1//lib/rtspruv3_le.lib
boot.c.obj 28 0 0
exit.c.obj 16 0 0
+--+---------------------------------------+------+---------+---------+
Total: 44 0 0
Stack: 0 0 256
+--+---------------------------------------+------+---------+---------+
Grand Total: 8192 0 7620
SEGMENT ATTRIBUTES
id tag seg value
-- --- --- -----
0 PHA_PAGE 1 1
1 PHA_PAGE 2 1
2 PHA_PAGE 3 1
3 PHA_PAGE 4 2
GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
page address name
---- ------- ----
0 00001fd0 C$$EXIT
2 00026000 CT_CFG
abs 481cc000 __PRU_CREG_BASE_DCAN0
abs 481d0000 __PRU_CREG_BASE_DCAN1
abs 80000000 __PRU_CREG_BASE_DDR
abs 48040000 __PRU_CREG_BASE_DMTIMER2
abs 4a100000 __PRU_CREG_BASE_GEMAC
abs 4802a000 __PRU_CREG_BASE_I2C1
abs 4819c000 __PRU_CREG_BASE_I2C2
abs 40000000 __PRU_CREG_BASE_L3OCMC
abs 480c8000 __PRU_CREG_BASE_MBX0
abs 46000000 __PRU_CREG_BASE_MCASP0_DMA
abs 48030000 __PRU_CREG_BASE_MCSPI0
abs 481a0000 __PRU_CREG_BASE_MCSPI1
abs 48060000 __PRU_CREG_BASE_MMCHS0
abs 00026000 __PRU_CREG_BASE_PRU_CFG
abs 00000000 __PRU_CREG_BASE_PRU_DMEM_0_1
abs 00002000 __PRU_CREG_BASE_PRU_DMEM_1_0
abs 00030000 __PRU_CREG_BASE_PRU_ECAP
abs 0002e000 __PRU_CREG_BASE_PRU_IEP
abs 00020000 __PRU_CREG_BASE_PRU_INTC
abs 00010000 __PRU_CREG_BASE_PRU_SHAREDMEM
abs 00028000 __PRU_CREG_BASE_PRU_UART
abs 48300000 __PRU_CREG_BASE_PWMSS0
abs 48302000 __PRU_CREG_BASE_PWMSS1
abs 48304000 __PRU_CREG_BASE_PWMSS2
abs 48318000 __PRU_CREG_BASE_RSVD10
abs 48310000 __PRU_CREG_BASE_RSVD13
abs 00032400 __PRU_CREG_BASE_RSVD21
abs 00032000 __PRU_CREG_BASE_RSVD27
abs 480ca000 __PRU_CREG_BASE_SPINLOCK
abs 49000000 __PRU_CREG_BASE_TPCC
abs 48022000 __PRU_CREG_BASE_UART1
abs 48024000 __PRU_CREG_BASE_UART2
abs 0000000e __PRU_CREG_DCAN0
abs 0000000f __PRU_CREG_DCAN1
abs 0000001f __PRU_CREG_DDR
abs 00000001 __PRU_CREG_DMTIMER2
abs 00000009 __PRU_CREG_GEMAC
abs 00000002 __PRU_CREG_I2C1
abs 00000011 __PRU_CREG_I2C2
abs 0000001e __PRU_CREG_L3OCMC
abs 00000016 __PRU_CREG_MBX0
abs 00000008 __PRU_CREG_MCASP0_DMA
abs 00000006 __PRU_CREG_MCSPI0
abs 00000010 __PRU_CREG_MCSPI1
abs 00000005 __PRU_CREG_MMCHS0
abs 00000004 __PRU_CREG_PRU_CFG
abs 00000018 __PRU_CREG_PRU_DMEM_0_1
abs 00000019 __PRU_CREG_PRU_DMEM_1_0
abs 00000003 __PRU_CREG_PRU_ECAP
abs 0000001a __PRU_CREG_PRU_IEP
abs 00000000 __PRU_CREG_PRU_INTC
abs 0000001c __PRU_CREG_PRU_SHAREDMEM
abs 00000007 __PRU_CREG_PRU_UART
abs 00000012 __PRU_CREG_PWMSS0
abs 00000013 __PRU_CREG_PWMSS1
abs 00000014 __PRU_CREG_PWMSS2
abs 0000000a __PRU_CREG_RSVD10
abs 0000000d __PRU_CREG_RSVD13
abs 00000015 __PRU_CREG_RSVD21
abs 0000001b __PRU_CREG_RSVD27
abs 00000017 __PRU_CREG_SPINLOCK
abs 0000001d __PRU_CREG_TPCC
abs 0000000b __PRU_CREG_UART1
abs 0000000c __PRU_CREG_UART2
1 00000100 __TI_STACK_END
abs 00000100 __TI_STACK_SIZE
abs ffffffff __c_args__
0 00000000 _c_int00_noinit_noargs
1 00000000 _stack
0 00001fc8 abort
1 00000100 buslatches
0 00001178 buslatches_powercycle
0 00001fd8 buslatches_pru0_dataout
0 00000e0c buslatches_reset
0 00001f2c buslatches_test
0 00001f58 ddrmem_fill_pattern
1 00002000 deviceregisters
0 00001e00 do_event_initializationsignals
0 00001e60 iopageregisters_init
0 000016fc iopageregisters_read
0 00000f3c iopageregisters_write_b
0 0000136c iopageregisters_write_w
2 00010000 mailbox
0 00000528 main
1 00000128 pru_remoteproc_ResourceTable
1 0000011d sm_arb
0 00001f84 sm_arb_start
0 00001d8c sm_arb_state_idle
1 00000110 sm_dma
0 00001ec0 sm_dma_start
1 00000120 sm_init
0 00001ac0 sm_init_start
0 00001fe8 sm_init_state_idle
1 00000122 sm_intr
0 00001f98 sm_intr_start
1 00000124 sm_powercycle
0 00001fa8 sm_powercycle_start
0 00001ff8 sm_powercycle_state_idle
1 00000126 sm_slave
0 00001fb8 sm_slave_start
1 00000119 timeout_target
GLOBAL SYMBOLS: SORTED BY Symbol Address
page address name
---- ------- ----
0 00000000 _c_int00_noinit_noargs
0 00000528 main
0 00000e0c buslatches_reset
0 00000f3c iopageregisters_write_b
0 00001178 buslatches_powercycle
0 0000136c iopageregisters_write_w
0 000016fc iopageregisters_read
0 00001ac0 sm_init_start
0 00001d8c sm_arb_state_idle
0 00001e00 do_event_initializationsignals
0 00001e60 iopageregisters_init
0 00001ec0 sm_dma_start
0 00001f2c buslatches_test
0 00001f58 ddrmem_fill_pattern
0 00001f84 sm_arb_start
0 00001f98 sm_intr_start
0 00001fa8 sm_powercycle_start
0 00001fb8 sm_slave_start
0 00001fc8 abort
0 00001fd0 C$$EXIT
0 00001fd8 buslatches_pru0_dataout
0 00001fe8 sm_init_state_idle
0 00001ff8 sm_powercycle_state_idle
1 00000000 _stack
1 00000100 __TI_STACK_END
1 00000100 buslatches
1 00000110 sm_dma
1 00000119 timeout_target
1 0000011d sm_arb
1 00000120 sm_init
1 00000122 sm_intr
1 00000124 sm_powercycle
1 00000126 sm_slave
1 00000128 pru_remoteproc_ResourceTable
1 00002000 deviceregisters
2 00010000 mailbox
2 00026000 CT_CFG
abs 00000000 __PRU_CREG_BASE_PRU_DMEM_0_1
abs 00000000 __PRU_CREG_PRU_INTC
abs 00000001 __PRU_CREG_DMTIMER2
abs 00000002 __PRU_CREG_I2C1
abs 00000003 __PRU_CREG_PRU_ECAP
abs 00000004 __PRU_CREG_PRU_CFG
abs 00000005 __PRU_CREG_MMCHS0
abs 00000006 __PRU_CREG_MCSPI0
abs 00000007 __PRU_CREG_PRU_UART
abs 00000008 __PRU_CREG_MCASP0_DMA
abs 00000009 __PRU_CREG_GEMAC
abs 0000000a __PRU_CREG_RSVD10
abs 0000000b __PRU_CREG_UART1
abs 0000000c __PRU_CREG_UART2
abs 0000000d __PRU_CREG_RSVD13
abs 0000000e __PRU_CREG_DCAN0
abs 0000000f __PRU_CREG_DCAN1
abs 00000010 __PRU_CREG_MCSPI1
abs 00000011 __PRU_CREG_I2C2
abs 00000012 __PRU_CREG_PWMSS0
abs 00000013 __PRU_CREG_PWMSS1
abs 00000014 __PRU_CREG_PWMSS2
abs 00000015 __PRU_CREG_RSVD21
abs 00000016 __PRU_CREG_MBX0
abs 00000017 __PRU_CREG_SPINLOCK
abs 00000018 __PRU_CREG_PRU_DMEM_0_1
abs 00000019 __PRU_CREG_PRU_DMEM_1_0
abs 0000001a __PRU_CREG_PRU_IEP
abs 0000001b __PRU_CREG_RSVD27
abs 0000001c __PRU_CREG_PRU_SHAREDMEM
abs 0000001d __PRU_CREG_TPCC
abs 0000001e __PRU_CREG_L3OCMC
abs 0000001f __PRU_CREG_DDR
abs 00000100 __TI_STACK_SIZE
abs 00002000 __PRU_CREG_BASE_PRU_DMEM_1_0
abs 00010000 __PRU_CREG_BASE_PRU_SHAREDMEM
abs 00020000 __PRU_CREG_BASE_PRU_INTC
abs 00026000 __PRU_CREG_BASE_PRU_CFG
abs 00028000 __PRU_CREG_BASE_PRU_UART
abs 0002e000 __PRU_CREG_BASE_PRU_IEP
abs 00030000 __PRU_CREG_BASE_PRU_ECAP
abs 00032000 __PRU_CREG_BASE_RSVD27
abs 00032400 __PRU_CREG_BASE_RSVD21
abs 40000000 __PRU_CREG_BASE_L3OCMC
abs 46000000 __PRU_CREG_BASE_MCASP0_DMA
abs 48022000 __PRU_CREG_BASE_UART1
abs 48024000 __PRU_CREG_BASE_UART2
abs 4802a000 __PRU_CREG_BASE_I2C1
abs 48030000 __PRU_CREG_BASE_MCSPI0
abs 48040000 __PRU_CREG_BASE_DMTIMER2
abs 48060000 __PRU_CREG_BASE_MMCHS0
abs 480c8000 __PRU_CREG_BASE_MBX0
abs 480ca000 __PRU_CREG_BASE_SPINLOCK
abs 4819c000 __PRU_CREG_BASE_I2C2
abs 481a0000 __PRU_CREG_BASE_MCSPI1
abs 481cc000 __PRU_CREG_BASE_DCAN0
abs 481d0000 __PRU_CREG_BASE_DCAN1
abs 48300000 __PRU_CREG_BASE_PWMSS0
abs 48302000 __PRU_CREG_BASE_PWMSS1
abs 48304000 __PRU_CREG_BASE_PWMSS2
abs 48310000 __PRU_CREG_BASE_RSVD13
abs 48318000 __PRU_CREG_BASE_RSVD10
abs 49000000 __PRU_CREG_BASE_TPCC
abs 4a100000 __PRU_CREG_BASE_GEMAC
abs 80000000 __PRU_CREG_BASE_DDR
abs ffffffff __c_args__
[103 symbols]
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