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79 lines
3.2 KiB
C
79 lines
3.2 KiB
C
/* priority_arbitration_requests.h: data struct to describe requests
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Datastructures common to ARM and PRU.
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Copyright (c) 2019, Joerg Hoppe
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j_hoppe@t-online.de, www.retrocmp.com
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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28-jun-2019 JH begin
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PRU handles all 5 requests in parlalel.
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4x INMTR BR4-BR7
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1x DMA NPR.
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Several ARM devcie may raise same BR|NPR level, ARM must serialize this to PRU.
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1. ARM sets a REQUEST by
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filling the RQUEST struct and perhaps DMA data
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doing AMR2PRO_PRIORITY_ARBITRATION_REQUEST,
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2. PRU sets BR4567|NPR lines according to open requests
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3. PRU monitors IN GRANT lines BG4567,NPG.
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IN state of idle requests is forwarded to BG|NPG OUT liens,
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to be processed by other UNIBUS cards.
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BG*|NPG IN state line of active request cleares BR*|NPR line,
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sets SACK, and starts INTR or DMA state machine.
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4. INTR or DMA sent a signal on compelte to PRU.
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PRU may then start next request on same (completed) BR*|NPR level.
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*/
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// bits BR*/NPR interrupts in buslatch 0 and 1
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// bit # is index into arbitration_request[] array.
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#define PRIORITY_ARBITRATION_BIT_B4 0x01
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#define PRIORITY_ARBITRATION_BIT_B5 0x02
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#define PRIORITY_ARBITRATION_BIT_B6 0x04
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#define PRIORITY_ARBITRATION_BIT_B7 0x08
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#define PRIORITY_ARBITRATION_BIT_NP 0x10
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#define PRIORITY_ARBITRATION_BIT_MASK 0x1f
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// info for one of 5 busrequests (BR4,5,6,7,NPR) generated by ARM
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typedef struct {
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// INTR BR* and DMA/NPR
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uint8_t priority_bit ; // PRIORITY_ARBITRATION_BIT_* for buslatch 0
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uint32_t data_transfer_complete_signal_tag ; // value returned with signal on complete
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// only INTR: interrupt register state to be set atomically with BR line
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uint8_t iopage_register_handle ;
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uint16_t iopage_register_value ;
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uint16_t vector; // interrupt vector to be transferred
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// DMA transaction data in mailbox_dma_t struct
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} priority_arbitration_request_t ;
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// list of all requests, some possible active
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typedef struct {
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// active BR/NPR signals, buslatch 0, PRIORITY_ARBITRATION_*
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uint8_t active_request_bits ;
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// index by bit # in "pirity b:it
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// BR4->[0], .. BR7 -> [3], NPR->[4]
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// Bit # in GRANT line is index here
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priority_arbitration_request_t priority_arbitration_request[5] ;
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} priority_arbitration_requests_t ;
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