mirror of
https://github.com/livingcomputermuseum/UniBone.git
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974aeed8eb
Interrupt and DMA system now handles multiple levels and multiple devices in parallel Interrupt Register changes synced with INTR transaction DL11 and KW11 clock pass the ZDLDI0 diagnostic. Devices can now be enabled and disabled individually.
258 lines
9.8 KiB
C++
258 lines
9.8 KiB
C++
/* menu_interrupts.cpp: user sub menu
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Copyright (c) 2018, Joerg Hoppe
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j_hoppe@t-online.de, www.retrocmp.com
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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JOERG HOPPE BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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16-Nov-2018 JH created
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <stdbool.h>
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#include "utils.hpp"
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#include "inputline.h"
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#include "mcout.h"
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#include "application.hpp" // own
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#include "pru.hpp"
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#include "gpios.hpp"
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#include "unibus.h"
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#include "memoryimage.hpp"
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#include "unibusadapter.hpp"
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#include "testcontroller.hpp"
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void application_c::menu_interrupts(void) {
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// needs physical CPU
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enum unibus_c::arbitration_mode_enum arbitration_mode = unibus_c::ARBITRATION_MODE_CLIENT;
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bool show_help = true; // show cmds on first screen, then only on error or request
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bool active = false; // 1 if PRU executes slave&master logic
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bool ready;
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bool test_loaded;
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char *s_choice;
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char s_opcode[256], s_param[5][256];
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int n_fields;
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testcontroller_c *test_controller = new testcontroller_c();
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test_controller->enabled.value = true;
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// These test need active PRUs
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// and an PDP-11 CPU as Arbitrator
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hardware_startup(pru_c::PRUCODE_UNIBUS, arbitration_mode);
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buslatches_output_enable(true);
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ready = false;
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test_loaded = false;
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while (!ready) {
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if (show_help) {
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show_help = false; // only once
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printf("\n");
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printf("*** Test of UNIBUS interrupts.\n");
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printf(
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" BR*/BG* Bus Arbitration needs a PDP-11 CPU acting as Bus Arbitrator.\n");
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if (emulated_memory_start_addr > emulated_memory_end_addr)
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printf(" UniBone does not emulate memory.\n");
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else
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printf(" UniBone emulates memory from %06o to %06o.\n",
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emulated_memory_start_addr, emulated_memory_end_addr);
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if (!active) {
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printf("***\n");
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printf("*** Starting full UNIBUS master/slave logic on PRU\n");
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printf("***\n");
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unibusadapter->enabled.set(true);
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active = true;
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}
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printf("m emulate all missing memory\n");
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printf("e <addr> EXAMINE the word at <addr>. [octal]\n");
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printf("d <addr> <val> DEPOSIT <val> into <addr> [octal]\n");
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printf("ll <filename> Load test program from MACRO-11 listing\n");
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if (test_loaded) {
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printf(
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"i <level> <vector> Issue interrupt at priority <level> to <<vector> [octal]\n");
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printf(" <level> = 0..7, <vector> = 0,4,10,...,374\n");
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printf(
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" Then interrupts cause print-out, and processor priority\n");
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printf(" can be set with keys 0..7.\n");
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printf(" Example:\n");
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printf(" \"i 5 164\" calls vector 164 at level 5.\n");
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printf(
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" If processor level < 5, INTR is accepted, a message is printed.\n");
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printf(" Else INTR is pending until level is lowered.\n");
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printf(" <level> = 0..7, <vector> = 0,4,10,...,374\n");
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printf(
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"i <level> <slot> <vector> Variant, additional a backplane slot for priority\n");
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printf(" within same level group is given\n");
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printf("dma <channel> <from> <to> <data> (addr & data word octal)\n");
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printf(
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" DEPOSIT memory range. Non-blocking, subsequent script commands\n");
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printf(
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" are executed in parallel. <slot> is backplane slot for priority\n");
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printf(" <channel> 0..%u possible.\n",
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(unsigned) test_controller->dma_channel_count);
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}
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printf("dl c|s|f Debug log: Clear, Show on console, dump to File.\n");
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printf("pwr Simulate UNIBUS power cycle (ACLO/DCLO)\n");
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printf("q Quit\n");
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}
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s_choice = getchoice();
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printf("\n");
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n_fields = sscanf(s_choice, "%s %s %s %s %s %s", s_opcode, s_param[0], s_param[1],
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s_param[2], s_param[3], s_param[4]);
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if (!strcasecmp(s_opcode, "q")) {
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ready = true;
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} else if (!strcasecmp(s_opcode, "pwr")) {
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unibus->powercycle();
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} else if (!strcasecmp(s_opcode, "m") && n_fields == 1) {
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emulate_memory(arbitration_mode);
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} else if (!strcasecmp(s_opcode, "e") && n_fields == 2) {
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uint32_t cur_addr;
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uint16_t wordbuffer;
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parse_addr18(s_param[0], &cur_addr);
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bool timeout = !unibus->dma(arbitration_mode, true, UNIBUS_CONTROL_DATI, cur_addr,
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&wordbuffer, 1);
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if (timeout)
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printf("Bus timeout at %06o.\n", cur_addr);
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else
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printf("EXAM %06o -> %06o\n", cur_addr, wordbuffer);
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} else if (!strcasecmp(s_opcode, "d") && n_fields == 3) {
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uint32_t cur_addr;
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uint16_t wordbuffer;
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parse_addr18(s_param[0], &cur_addr);
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parse_word(s_param[1], &wordbuffer);
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bool timeout = !unibus->dma(arbitration_mode, true, UNIBUS_CONTROL_DATO, cur_addr,
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&wordbuffer, 1);
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if (timeout)
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printf("Bus timeout at %06o.\n", cur_addr);
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else
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printf("DEPOSIT %06o <- %06o\n", cur_addr, wordbuffer);
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} else if (!strcasecmp(s_opcode, "ll") && n_fields == 2) {
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uint32_t start_addr, end_addr;
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bool timeout;
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test_loaded = false;
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printf("Loading memory content from MACRO-11 listing %s\n", s_param[0]);
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membuffer->init();
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bool load_ok = membuffer->load_macro11_listing(s_param[0], "start");
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if (!load_ok) {
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printf("File load failed, aborting.\n");
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continue;
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}
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membuffer->get_addr_range(&start_addr, &end_addr);
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printf("Loaded %u words, writing UNIBUS memory[%06o:%06o].\n",
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membuffer->get_word_count(), start_addr, end_addr);
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unibus->mem_write(arbitration_mode, membuffer->data.words, start_addr, end_addr,
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&timeout);
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if (timeout)
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printf("Memory write failed with UNIBUS timeout, aborting.\n");
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else {
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if (membuffer->entry_address == MEMORY_ADDRESS_INVALID)
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printf(
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"Start program manually on PDP-11 console (entry address not found).\n");
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else
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printf("Start program manually on PDP-11 console, entry address is %06o.\n",
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membuffer->entry_address);
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test_loaded = true;
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}
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} else if (test_loaded && !strcasecmp(s_opcode, "i") && n_fields >= 3
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&& n_fields <= 4) {
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uint8_t priority_slot = 16; // default
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uint8_t level;
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uint16_t vector;
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if (!parse_level(s_param[0], &level))
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continue;
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if (n_fields == 3) { // i <level> <vector>
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if (!parse_vector(s_param[1], 0374, &vector)) // artificial limit, still far to big
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continue;
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} else if (n_fields == 4) { // i <level> <slot> <vector>
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if (!parse_slot(s_param[1], &priority_slot))
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continue;
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if (!parse_vector(s_param[2], 0374, &vector)) // artificial limit, still far to big
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continue;
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}
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// use request from testcontroller
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unsigned level_idx = level - 4; // 4,5,6,7 -> 0,1,2,3
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intr_request_c *intr_request =
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test_controller->intr_request[priority_slot][level_idx];
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intr_request->set_vector(vector);
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unibusadapter->INTR(*intr_request, NULL, 0);
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printf("Interrupt with level=%d, priority slot=%d, vector=%03o generated.\n", level,
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priority_slot, vector);
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} else if (test_loaded && !strcasecmp(s_opcode, "dma") && n_fields == 5) {
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// dma <slot> <from> <to> <data>
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uint8_t dma_channel;
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uint32_t addr_from, addr_to;
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uint16_t fillword;
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dma_channel = strtol(s_param[0], NULL, 10);
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if (dma_channel >= test_controller->dma_channel_count) {
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printf("Only DMA channels 0..%u possible.\n",
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(unsigned) test_controller->dma_channel_count);
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continue;
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}
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parse_addr18(s_param[1], &addr_from);
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parse_addr18(s_param[2], &addr_to);
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parse_word(s_param[3], &fillword);
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if (addr_to < addr_from)
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addr_to = addr_from;
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unsigned wordcount = (addr_to - addr_from + 2) / 2;
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// do not use single global "membuffer": need independent buffer per concurrent DMA with different data
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memoryimage_c *dma_buffer = test_controller->dma_channel_buffer[dma_channel];
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dma_buffer->set_addr_range(addr_from, addr_to);
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dma_buffer->fill(fillword);
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// DMA running asynchronically parallel, no info on BUS timeout yet. User has to wait.
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dma_request_c *dma_request = test_controller->dma_channel_request[dma_channel];
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unibusadapter->DMA(*dma_request, false, UNIBUS_CONTROL_DATO, addr_from,
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&(dma_buffer->data.words[addr_from / 2]), wordcount);
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printf("DEPOSIT in slot %d started for %06o..%06o\n",
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dma_request->get_priority_slot(), addr_from, addr_to);
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} else if (!strcasecmp(s_opcode, "dl") && n_fields == 2) {
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if (!strcasecmp(s_param[0], "c")) {
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logger->clear();
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printf("Debug log cleared.\n");
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} else if (!strcasecmp(s_param[0], "s"))
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logger->dump();
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else if (!strcasecmp(s_param[0], "f"))
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logger->dump(logger->default_filepath);
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} else {
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printf("Unknown command \"%s\"!\n", s_choice);
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show_help = true;
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}
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} // while(!ready) ;
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if (active) {
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printf("***\n");
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printf("*** Stopping UNIBUS logic on PRU\n");
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printf("***\n");
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unibusadapter->enabled.set(false);
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active = false;
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}
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delete test_controller;
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// Switch off bus drivers
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buslatches_output_enable(false);
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hardware_shutdown();
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}
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